36582 lines
1.3 MiB
36582 lines
1.3 MiB
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SubGHz_Phy_Per.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000138 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000d3c8 08000138 08000138 00001138 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000630 0800d500 0800d500 0000e500 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800db30 0800db30 0000f024 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800db30 0800db30 0000eb30 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800db38 0800db38 0000f024 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800db38 0800db38 0000eb38 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 0800db3c 0800db3c 0000eb3c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000024 20000000 0800db40 0000f000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000cc4 20000024 0800db64 0000f024 2**2
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ALLOC
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10 ._user_heap_stack 00000a00 20000ce8 0800db64 0000fce8 2**0
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ALLOC
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11 .ARM.attributes 0000002a 00000000 00000000 0000f024 2**0
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CONTENTS, READONLY
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12 .debug_info 000233f6 00000000 00000000 0000f04e 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00005f69 00000000 00000000 00032444 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00002028 00000000 00000000 000383b0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 0000182b 00000000 00000000 0003a3d8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 000235c5 00000000 00000000 0003bc03 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00022287 00000000 00000000 0005f1c8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000c58b3 00000000 00000000 0008144f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 00146d02 2**0
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CONTENTS, READONLY
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20 .debug_frame 00008274 00000000 00000000 00146d48 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 0000005f 00000000 00000000 0014efbc 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000138 <__do_global_dtors_aux>:
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8000138: b510 push {r4, lr}
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800013a: 4c05 ldr r4, [pc, #20] @ (8000150 <__do_global_dtors_aux+0x18>)
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800013c: 7823 ldrb r3, [r4, #0]
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800013e: b933 cbnz r3, 800014e <__do_global_dtors_aux+0x16>
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8000140: 4b04 ldr r3, [pc, #16] @ (8000154 <__do_global_dtors_aux+0x1c>)
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8000142: b113 cbz r3, 800014a <__do_global_dtors_aux+0x12>
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8000144: 4804 ldr r0, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x20>)
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8000146: f3af 8000 nop.w
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800014a: 2301 movs r3, #1
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800014c: 7023 strb r3, [r4, #0]
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800014e: bd10 pop {r4, pc}
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8000150: 20000024 .word 0x20000024
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8000154: 00000000 .word 0x00000000
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8000158: 0800d4e8 .word 0x0800d4e8
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0800015c <frame_dummy>:
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800015c: b508 push {r3, lr}
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800015e: 4b03 ldr r3, [pc, #12] @ (800016c <frame_dummy+0x10>)
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8000160: b11b cbz r3, 800016a <frame_dummy+0xe>
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8000162: 4903 ldr r1, [pc, #12] @ (8000170 <frame_dummy+0x14>)
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8000164: 4803 ldr r0, [pc, #12] @ (8000174 <frame_dummy+0x18>)
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8000166: f3af 8000 nop.w
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800016a: bd08 pop {r3, pc}
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800016c: 00000000 .word 0x00000000
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8000170: 20000028 .word 0x20000028
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8000174: 0800d4e8 .word 0x0800d4e8
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08000178 <strlen>:
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8000178: 4603 mov r3, r0
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800017a: f813 2b01 ldrb.w r2, [r3], #1
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800017e: 2a00 cmp r2, #0
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8000180: d1fb bne.n 800017a <strlen+0x2>
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8000182: 1a18 subs r0, r3, r0
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8000184: 3801 subs r0, #1
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8000186: 4770 bx lr
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08000188 <__aeabi_uldivmod>:
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8000188: b953 cbnz r3, 80001a0 <__aeabi_uldivmod+0x18>
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800018a: b94a cbnz r2, 80001a0 <__aeabi_uldivmod+0x18>
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800018c: 2900 cmp r1, #0
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800018e: bf08 it eq
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8000190: 2800 cmpeq r0, #0
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8000192: bf1c itt ne
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8000194: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000198: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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800019c: f000 b988 b.w 80004b0 <__aeabi_idiv0>
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80001a0: f1ad 0c08 sub.w ip, sp, #8
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80001a4: e96d ce04 strd ip, lr, [sp, #-16]!
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80001a8: f000 f806 bl 80001b8 <__udivmoddi4>
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80001ac: f8dd e004 ldr.w lr, [sp, #4]
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80001b0: e9dd 2302 ldrd r2, r3, [sp, #8]
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80001b4: b004 add sp, #16
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80001b6: 4770 bx lr
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080001b8 <__udivmoddi4>:
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80001b8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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80001bc: 9d08 ldr r5, [sp, #32]
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80001be: 468e mov lr, r1
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80001c0: 4604 mov r4, r0
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80001c2: 4688 mov r8, r1
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80001c4: 2b00 cmp r3, #0
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80001c6: d14a bne.n 800025e <__udivmoddi4+0xa6>
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80001c8: 428a cmp r2, r1
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80001ca: 4617 mov r7, r2
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80001cc: d962 bls.n 8000294 <__udivmoddi4+0xdc>
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80001ce: fab2 f682 clz r6, r2
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80001d2: b14e cbz r6, 80001e8 <__udivmoddi4+0x30>
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80001d4: f1c6 0320 rsb r3, r6, #32
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80001d8: fa01 f806 lsl.w r8, r1, r6
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80001dc: fa20 f303 lsr.w r3, r0, r3
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80001e0: 40b7 lsls r7, r6
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80001e2: ea43 0808 orr.w r8, r3, r8
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80001e6: 40b4 lsls r4, r6
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80001e8: ea4f 4e17 mov.w lr, r7, lsr #16
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80001ec: fa1f fc87 uxth.w ip, r7
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80001f0: fbb8 f1fe udiv r1, r8, lr
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80001f4: 0c23 lsrs r3, r4, #16
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80001f6: fb0e 8811 mls r8, lr, r1, r8
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80001fa: ea43 4308 orr.w r3, r3, r8, lsl #16
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80001fe: fb01 f20c mul.w r2, r1, ip
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8000202: 429a cmp r2, r3
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8000204: d909 bls.n 800021a <__udivmoddi4+0x62>
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8000206: 18fb adds r3, r7, r3
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8000208: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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800020c: f080 80ea bcs.w 80003e4 <__udivmoddi4+0x22c>
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8000210: 429a cmp r2, r3
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8000212: f240 80e7 bls.w 80003e4 <__udivmoddi4+0x22c>
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8000216: 3902 subs r1, #2
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8000218: 443b add r3, r7
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800021a: 1a9a subs r2, r3, r2
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800021c: b2a3 uxth r3, r4
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800021e: fbb2 f0fe udiv r0, r2, lr
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8000222: fb0e 2210 mls r2, lr, r0, r2
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8000226: ea43 4302 orr.w r3, r3, r2, lsl #16
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800022a: fb00 fc0c mul.w ip, r0, ip
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800022e: 459c cmp ip, r3
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8000230: d909 bls.n 8000246 <__udivmoddi4+0x8e>
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8000232: 18fb adds r3, r7, r3
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8000234: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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8000238: f080 80d6 bcs.w 80003e8 <__udivmoddi4+0x230>
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800023c: 459c cmp ip, r3
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800023e: f240 80d3 bls.w 80003e8 <__udivmoddi4+0x230>
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8000242: 443b add r3, r7
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8000244: 3802 subs r0, #2
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8000246: ea40 4001 orr.w r0, r0, r1, lsl #16
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800024a: eba3 030c sub.w r3, r3, ip
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800024e: 2100 movs r1, #0
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8000250: b11d cbz r5, 800025a <__udivmoddi4+0xa2>
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8000252: 40f3 lsrs r3, r6
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8000254: 2200 movs r2, #0
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8000256: e9c5 3200 strd r3, r2, [r5]
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800025a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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800025e: 428b cmp r3, r1
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8000260: d905 bls.n 800026e <__udivmoddi4+0xb6>
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8000262: b10d cbz r5, 8000268 <__udivmoddi4+0xb0>
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8000264: e9c5 0100 strd r0, r1, [r5]
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8000268: 2100 movs r1, #0
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800026a: 4608 mov r0, r1
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800026c: e7f5 b.n 800025a <__udivmoddi4+0xa2>
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800026e: fab3 f183 clz r1, r3
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8000272: 2900 cmp r1, #0
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8000274: d146 bne.n 8000304 <__udivmoddi4+0x14c>
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8000276: 4573 cmp r3, lr
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8000278: d302 bcc.n 8000280 <__udivmoddi4+0xc8>
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800027a: 4282 cmp r2, r0
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800027c: f200 8105 bhi.w 800048a <__udivmoddi4+0x2d2>
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8000280: 1a84 subs r4, r0, r2
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8000282: eb6e 0203 sbc.w r2, lr, r3
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8000286: 2001 movs r0, #1
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8000288: 4690 mov r8, r2
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800028a: 2d00 cmp r5, #0
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800028c: d0e5 beq.n 800025a <__udivmoddi4+0xa2>
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800028e: e9c5 4800 strd r4, r8, [r5]
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8000292: e7e2 b.n 800025a <__udivmoddi4+0xa2>
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8000294: 2a00 cmp r2, #0
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8000296: f000 8090 beq.w 80003ba <__udivmoddi4+0x202>
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800029a: fab2 f682 clz r6, r2
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800029e: 2e00 cmp r6, #0
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80002a0: f040 80a4 bne.w 80003ec <__udivmoddi4+0x234>
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80002a4: 1a8a subs r2, r1, r2
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80002a6: 0c03 lsrs r3, r0, #16
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80002a8: ea4f 4e17 mov.w lr, r7, lsr #16
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80002ac: b280 uxth r0, r0
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80002ae: b2bc uxth r4, r7
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80002b0: 2101 movs r1, #1
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80002b2: fbb2 fcfe udiv ip, r2, lr
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80002b6: fb0e 221c mls r2, lr, ip, r2
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80002ba: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002be: fb04 f20c mul.w r2, r4, ip
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80002c2: 429a cmp r2, r3
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80002c4: d907 bls.n 80002d6 <__udivmoddi4+0x11e>
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80002c6: 18fb adds r3, r7, r3
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80002c8: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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80002cc: d202 bcs.n 80002d4 <__udivmoddi4+0x11c>
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80002ce: 429a cmp r2, r3
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80002d0: f200 80e0 bhi.w 8000494 <__udivmoddi4+0x2dc>
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80002d4: 46c4 mov ip, r8
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80002d6: 1a9b subs r3, r3, r2
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80002d8: fbb3 f2fe udiv r2, r3, lr
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80002dc: fb0e 3312 mls r3, lr, r2, r3
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80002e0: ea40 4303 orr.w r3, r0, r3, lsl #16
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80002e4: fb02 f404 mul.w r4, r2, r4
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80002e8: 429c cmp r4, r3
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80002ea: d907 bls.n 80002fc <__udivmoddi4+0x144>
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80002ec: 18fb adds r3, r7, r3
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80002ee: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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80002f2: d202 bcs.n 80002fa <__udivmoddi4+0x142>
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80002f4: 429c cmp r4, r3
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80002f6: f200 80ca bhi.w 800048e <__udivmoddi4+0x2d6>
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80002fa: 4602 mov r2, r0
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80002fc: 1b1b subs r3, r3, r4
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80002fe: ea42 400c orr.w r0, r2, ip, lsl #16
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8000302: e7a5 b.n 8000250 <__udivmoddi4+0x98>
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8000304: f1c1 0620 rsb r6, r1, #32
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8000308: 408b lsls r3, r1
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800030a: fa22 f706 lsr.w r7, r2, r6
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800030e: 431f orrs r7, r3
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8000310: fa0e f401 lsl.w r4, lr, r1
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8000314: fa20 f306 lsr.w r3, r0, r6
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8000318: fa2e fe06 lsr.w lr, lr, r6
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800031c: ea4f 4917 mov.w r9, r7, lsr #16
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8000320: 4323 orrs r3, r4
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8000322: fa00 f801 lsl.w r8, r0, r1
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8000326: fa1f fc87 uxth.w ip, r7
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800032a: fbbe f0f9 udiv r0, lr, r9
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800032e: 0c1c lsrs r4, r3, #16
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8000330: fb09 ee10 mls lr, r9, r0, lr
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8000334: ea44 440e orr.w r4, r4, lr, lsl #16
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8000338: fb00 fe0c mul.w lr, r0, ip
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800033c: 45a6 cmp lr, r4
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800033e: fa02 f201 lsl.w r2, r2, r1
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8000342: d909 bls.n 8000358 <__udivmoddi4+0x1a0>
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8000344: 193c adds r4, r7, r4
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8000346: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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800034a: f080 809c bcs.w 8000486 <__udivmoddi4+0x2ce>
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800034e: 45a6 cmp lr, r4
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8000350: f240 8099 bls.w 8000486 <__udivmoddi4+0x2ce>
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8000354: 3802 subs r0, #2
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8000356: 443c add r4, r7
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8000358: eba4 040e sub.w r4, r4, lr
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800035c: fa1f fe83 uxth.w lr, r3
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8000360: fbb4 f3f9 udiv r3, r4, r9
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8000364: fb09 4413 mls r4, r9, r3, r4
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8000368: ea4e 4404 orr.w r4, lr, r4, lsl #16
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800036c: fb03 fc0c mul.w ip, r3, ip
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8000370: 45a4 cmp ip, r4
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8000372: d908 bls.n 8000386 <__udivmoddi4+0x1ce>
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8000374: 193c adds r4, r7, r4
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8000376: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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800037a: f080 8082 bcs.w 8000482 <__udivmoddi4+0x2ca>
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800037e: 45a4 cmp ip, r4
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8000380: d97f bls.n 8000482 <__udivmoddi4+0x2ca>
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8000382: 3b02 subs r3, #2
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8000384: 443c add r4, r7
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8000386: ea43 4000 orr.w r0, r3, r0, lsl #16
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800038a: eba4 040c sub.w r4, r4, ip
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800038e: fba0 ec02 umull lr, ip, r0, r2
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8000392: 4564 cmp r4, ip
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8000394: 4673 mov r3, lr
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8000396: 46e1 mov r9, ip
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8000398: d362 bcc.n 8000460 <__udivmoddi4+0x2a8>
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800039a: d05f beq.n 800045c <__udivmoddi4+0x2a4>
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800039c: b15d cbz r5, 80003b6 <__udivmoddi4+0x1fe>
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800039e: ebb8 0203 subs.w r2, r8, r3
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80003a2: eb64 0409 sbc.w r4, r4, r9
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80003a6: fa04 f606 lsl.w r6, r4, r6
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80003aa: fa22 f301 lsr.w r3, r2, r1
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80003ae: 431e orrs r6, r3
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80003b0: 40cc lsrs r4, r1
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80003b2: e9c5 6400 strd r6, r4, [r5]
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80003b6: 2100 movs r1, #0
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80003b8: e74f b.n 800025a <__udivmoddi4+0xa2>
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80003ba: fbb1 fcf2 udiv ip, r1, r2
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80003be: 0c01 lsrs r1, r0, #16
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80003c0: ea41 410e orr.w r1, r1, lr, lsl #16
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80003c4: b280 uxth r0, r0
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80003c6: ea40 4201 orr.w r2, r0, r1, lsl #16
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80003ca: 463b mov r3, r7
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80003cc: 4638 mov r0, r7
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80003ce: 463c mov r4, r7
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80003d0: 46b8 mov r8, r7
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80003d2: 46be mov lr, r7
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80003d4: 2620 movs r6, #32
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80003d6: fbb1 f1f7 udiv r1, r1, r7
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80003da: eba2 0208 sub.w r2, r2, r8
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80003de: ea41 410c orr.w r1, r1, ip, lsl #16
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80003e2: e766 b.n 80002b2 <__udivmoddi4+0xfa>
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80003e4: 4601 mov r1, r0
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80003e6: e718 b.n 800021a <__udivmoddi4+0x62>
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80003e8: 4610 mov r0, r2
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80003ea: e72c b.n 8000246 <__udivmoddi4+0x8e>
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80003ec: f1c6 0220 rsb r2, r6, #32
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80003f0: fa2e f302 lsr.w r3, lr, r2
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80003f4: 40b7 lsls r7, r6
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80003f6: 40b1 lsls r1, r6
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80003f8: fa20 f202 lsr.w r2, r0, r2
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80003fc: ea4f 4e17 mov.w lr, r7, lsr #16
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8000400: 430a orrs r2, r1
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8000402: fbb3 f8fe udiv r8, r3, lr
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8000406: b2bc uxth r4, r7
|
|
8000408: fb0e 3318 mls r3, lr, r8, r3
|
|
800040c: 0c11 lsrs r1, r2, #16
|
|
800040e: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000412: fb08 f904 mul.w r9, r8, r4
|
|
8000416: 40b0 lsls r0, r6
|
|
8000418: 4589 cmp r9, r1
|
|
800041a: ea4f 4310 mov.w r3, r0, lsr #16
|
|
800041e: b280 uxth r0, r0
|
|
8000420: d93e bls.n 80004a0 <__udivmoddi4+0x2e8>
|
|
8000422: 1879 adds r1, r7, r1
|
|
8000424: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000428: d201 bcs.n 800042e <__udivmoddi4+0x276>
|
|
800042a: 4589 cmp r9, r1
|
|
800042c: d81f bhi.n 800046e <__udivmoddi4+0x2b6>
|
|
800042e: eba1 0109 sub.w r1, r1, r9
|
|
8000432: fbb1 f9fe udiv r9, r1, lr
|
|
8000436: fb09 f804 mul.w r8, r9, r4
|
|
800043a: fb0e 1119 mls r1, lr, r9, r1
|
|
800043e: b292 uxth r2, r2
|
|
8000440: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
8000444: 4542 cmp r2, r8
|
|
8000446: d229 bcs.n 800049c <__udivmoddi4+0x2e4>
|
|
8000448: 18ba adds r2, r7, r2
|
|
800044a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
800044e: d2c4 bcs.n 80003da <__udivmoddi4+0x222>
|
|
8000450: 4542 cmp r2, r8
|
|
8000452: d2c2 bcs.n 80003da <__udivmoddi4+0x222>
|
|
8000454: f1a9 0102 sub.w r1, r9, #2
|
|
8000458: 443a add r2, r7
|
|
800045a: e7be b.n 80003da <__udivmoddi4+0x222>
|
|
800045c: 45f0 cmp r8, lr
|
|
800045e: d29d bcs.n 800039c <__udivmoddi4+0x1e4>
|
|
8000460: ebbe 0302 subs.w r3, lr, r2
|
|
8000464: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000468: 3801 subs r0, #1
|
|
800046a: 46e1 mov r9, ip
|
|
800046c: e796 b.n 800039c <__udivmoddi4+0x1e4>
|
|
800046e: eba7 0909 sub.w r9, r7, r9
|
|
8000472: 4449 add r1, r9
|
|
8000474: f1a8 0c02 sub.w ip, r8, #2
|
|
8000478: fbb1 f9fe udiv r9, r1, lr
|
|
800047c: fb09 f804 mul.w r8, r9, r4
|
|
8000480: e7db b.n 800043a <__udivmoddi4+0x282>
|
|
8000482: 4673 mov r3, lr
|
|
8000484: e77f b.n 8000386 <__udivmoddi4+0x1ce>
|
|
8000486: 4650 mov r0, sl
|
|
8000488: e766 b.n 8000358 <__udivmoddi4+0x1a0>
|
|
800048a: 4608 mov r0, r1
|
|
800048c: e6fd b.n 800028a <__udivmoddi4+0xd2>
|
|
800048e: 443b add r3, r7
|
|
8000490: 3a02 subs r2, #2
|
|
8000492: e733 b.n 80002fc <__udivmoddi4+0x144>
|
|
8000494: f1ac 0c02 sub.w ip, ip, #2
|
|
8000498: 443b add r3, r7
|
|
800049a: e71c b.n 80002d6 <__udivmoddi4+0x11e>
|
|
800049c: 4649 mov r1, r9
|
|
800049e: e79c b.n 80003da <__udivmoddi4+0x222>
|
|
80004a0: eba1 0109 sub.w r1, r1, r9
|
|
80004a4: 46c4 mov ip, r8
|
|
80004a6: fbb1 f9fe udiv r9, r1, lr
|
|
80004aa: fb09 f804 mul.w r8, r9, r4
|
|
80004ae: e7c4 b.n 800043a <__udivmoddi4+0x282>
|
|
|
|
080004b0 <__aeabi_idiv0>:
|
|
80004b0: 4770 bx lr
|
|
80004b2: bf00 nop
|
|
|
|
080004b4 <LL_AHB1_GRP1_EnableClock>:
|
|
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
|
|
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80004b4: b480 push {r7}
|
|
80004b6: b085 sub sp, #20
|
|
80004b8: af00 add r7, sp, #0
|
|
80004ba: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB1ENR, Periphs);
|
|
80004bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80004c0: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80004c2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80004c6: 687b ldr r3, [r7, #4]
|
|
80004c8: 4313 orrs r3, r2
|
|
80004ca: 648b str r3, [r1, #72] @ 0x48
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
|
|
80004cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80004d0: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80004d2: 687b ldr r3, [r7, #4]
|
|
80004d4: 4013 ands r3, r2
|
|
80004d6: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
80004d8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80004da: bf00 nop
|
|
80004dc: 3714 adds r7, #20
|
|
80004de: 46bd mov sp, r7
|
|
80004e0: bc80 pop {r7}
|
|
80004e2: 4770 bx lr
|
|
|
|
080004e4 <MX_DMA_Init>:
|
|
|
|
/**
|
|
* Enable DMA controller clock
|
|
*/
|
|
void MX_DMA_Init(void)
|
|
{
|
|
80004e4: b580 push {r7, lr}
|
|
80004e6: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMAMUX1_CLK_ENABLE();
|
|
80004e8: 2004 movs r0, #4
|
|
80004ea: f7ff ffe3 bl 80004b4 <LL_AHB1_GRP1_EnableClock>
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
80004ee: 2001 movs r0, #1
|
|
80004f0: f7ff ffe0 bl 80004b4 <LL_AHB1_GRP1_EnableClock>
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Channel5_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0);
|
|
80004f4: 2200 movs r2, #0
|
|
80004f6: 2102 movs r1, #2
|
|
80004f8: 200f movs r0, #15
|
|
80004fa: f001 faa6 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
|
|
80004fe: 200f movs r0, #15
|
|
8000500: f001 fabd bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8000504: bf00 nop
|
|
8000506: bd80 pop {r7, pc}
|
|
|
|
08000508 <LL_AHB2_GRP1_EnableClock>:
|
|
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8000508: b480 push {r7}
|
|
800050a: b085 sub sp, #20
|
|
800050c: af00 add r7, sp, #0
|
|
800050e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
8000510: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000514: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8000516: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800051a: 687b ldr r3, [r7, #4]
|
|
800051c: 4313 orrs r3, r2
|
|
800051e: 64cb str r3, [r1, #76] @ 0x4c
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
8000520: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000524: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8000526: 687b ldr r3, [r7, #4]
|
|
8000528: 4013 ands r3, r2
|
|
800052a: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
800052c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800052e: bf00 nop
|
|
8000530: 3714 adds r7, #20
|
|
8000532: 46bd mov sp, r7
|
|
8000534: bc80 pop {r7}
|
|
8000536: 4770 bx lr
|
|
|
|
08000538 <MX_GPIO_Init>:
|
|
* Output
|
|
* EVENT_OUT
|
|
* EXTI
|
|
*/
|
|
void MX_GPIO_Init(void)
|
|
{
|
|
8000538: b580 push {r7, lr}
|
|
800053a: b086 sub sp, #24
|
|
800053c: af00 add r7, sp, #0
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800053e: 1d3b adds r3, r7, #4
|
|
8000540: 2200 movs r2, #0
|
|
8000542: 601a str r2, [r3, #0]
|
|
8000544: 605a str r2, [r3, #4]
|
|
8000546: 609a str r2, [r3, #8]
|
|
8000548: 60da str r2, [r3, #12]
|
|
800054a: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800054c: 2002 movs r0, #2
|
|
800054e: f7ff ffdb bl 8000508 <LL_AHB2_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000552: 2004 movs r0, #4
|
|
8000554: f7ff ffd8 bl 8000508 <LL_AHB2_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000558: 2001 movs r0, #1
|
|
800055a: f7ff ffd5 bl 8000508 <LL_AHB2_GRP1_EnableClock>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, LED1_Pin|LED2_Pin|PROB2_Pin|PROB1_Pin
|
|
800055e: 2200 movs r2, #0
|
|
8000560: f44f 413a mov.w r1, #47616 @ 0xba00
|
|
8000564: 4829 ldr r0, [pc, #164] @ (800060c <MX_GPIO_Init+0xd4>)
|
|
8000566: f002 f8ed bl 8002744 <HAL_GPIO_WritePin>
|
|
|LED3_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pins : LED1_Pin LED2_Pin LED3_Pin */
|
|
GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin;
|
|
800056a: f44f 430a mov.w r3, #35328 @ 0x8a00
|
|
800056e: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000570: 2301 movs r3, #1
|
|
8000572: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000574: 2300 movs r3, #0
|
|
8000576: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
8000578: 2302 movs r3, #2
|
|
800057a: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800057c: 1d3b adds r3, r7, #4
|
|
800057e: 4619 mov r1, r3
|
|
8000580: 4822 ldr r0, [pc, #136] @ (800060c <MX_GPIO_Init+0xd4>)
|
|
8000582: f001 feb1 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : BUT1_Pin BUT2_Pin */
|
|
GPIO_InitStruct.Pin = BUT1_Pin|BUT2_Pin;
|
|
8000586: 2303 movs r3, #3
|
|
8000588: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
800058a: f44f 1304 mov.w r3, #2162688 @ 0x210000
|
|
800058e: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8000590: 2301 movs r3, #1
|
|
8000592: 60fb str r3, [r7, #12]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000594: 1d3b adds r3, r7, #4
|
|
8000596: 4619 mov r1, r3
|
|
8000598: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800059c: f001 fea4 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PROB2_Pin PROB1_Pin */
|
|
GPIO_InitStruct.Pin = PROB2_Pin|PROB1_Pin;
|
|
80005a0: f44f 5340 mov.w r3, #12288 @ 0x3000
|
|
80005a4: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80005a6: 2301 movs r3, #1
|
|
80005a8: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80005aa: 2300 movs r3, #0
|
|
80005ac: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80005ae: 2303 movs r3, #3
|
|
80005b0: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80005b2: 1d3b adds r3, r7, #4
|
|
80005b4: 4619 mov r1, r3
|
|
80005b6: 4815 ldr r0, [pc, #84] @ (800060c <MX_GPIO_Init+0xd4>)
|
|
80005b8: f001 fe96 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : BUT3_Pin */
|
|
GPIO_InitStruct.Pin = BUT3_Pin;
|
|
80005bc: 2340 movs r3, #64 @ 0x40
|
|
80005be: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
80005c0: f44f 1304 mov.w r3, #2162688 @ 0x210000
|
|
80005c4: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80005c6: 2301 movs r3, #1
|
|
80005c8: 60fb str r3, [r7, #12]
|
|
HAL_GPIO_Init(BUT3_GPIO_Port, &GPIO_InitStruct);
|
|
80005ca: 1d3b adds r3, r7, #4
|
|
80005cc: 4619 mov r1, r3
|
|
80005ce: 4810 ldr r0, [pc, #64] @ (8000610 <MX_GPIO_Init+0xd8>)
|
|
80005d0: f001 fe8a bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/* EXTI interrupt init*/
|
|
HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0);
|
|
80005d4: 2200 movs r2, #0
|
|
80005d6: 2100 movs r1, #0
|
|
80005d8: 2006 movs r0, #6
|
|
80005da: f001 fa36 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI0_IRQn);
|
|
80005de: 2006 movs r0, #6
|
|
80005e0: f001 fa4d bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
|
|
HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0);
|
|
80005e4: 2200 movs r2, #0
|
|
80005e6: 2100 movs r1, #0
|
|
80005e8: 2007 movs r0, #7
|
|
80005ea: f001 fa2e bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
|
|
80005ee: 2007 movs r0, #7
|
|
80005f0: f001 fa45 bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
|
|
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
|
|
80005f4: 2200 movs r2, #0
|
|
80005f6: 2100 movs r1, #0
|
|
80005f8: 2016 movs r0, #22
|
|
80005fa: f001 fa26 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
|
|
80005fe: 2016 movs r0, #22
|
|
8000600: f001 fa3d bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8000604: bf00 nop
|
|
8000606: 3718 adds r7, #24
|
|
8000608: 46bd mov sp, r7
|
|
800060a: bd80 pop {r7, pc}
|
|
800060c: 48000400 .word 0x48000400
|
|
8000610: 48000800 .word 0x48000800
|
|
|
|
08000614 <LL_RCC_LSE_SetDriveCapability>:
|
|
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
|
|
* @arg @ref LL_RCC_LSEDRIVE_HIGH
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
|
|
{
|
|
8000614: b480 push {r7}
|
|
8000616: b083 sub sp, #12
|
|
8000618: af00 add r7, sp, #0
|
|
800061a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
|
|
800061c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000620: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8000624: f023 0218 bic.w r2, r3, #24
|
|
8000628: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800062c: 687b ldr r3, [r7, #4]
|
|
800062e: 4313 orrs r3, r2
|
|
8000630: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
8000634: bf00 nop
|
|
8000636: 370c adds r7, #12
|
|
8000638: 46bd mov sp, r7
|
|
800063a: bc80 pop {r7}
|
|
800063c: 4770 bx lr
|
|
|
|
0800063e <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
800063e: b580 push {r7, lr}
|
|
8000640: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000642: f001 f8db bl 80017fc <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000646: f000 f807 bl 8000658 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800064a: f7ff ff75 bl 8000538 <MX_GPIO_Init>
|
|
MX_SubGHz_Phy_Init();
|
|
800064e: f00b f9cf bl 800b9f0 <MX_SubGHz_Phy_Init>
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
/* USER CODE END WHILE */
|
|
MX_SubGHz_Phy_Process();
|
|
8000652: f00b f9d5 bl 800ba00 <MX_SubGHz_Phy_Process>
|
|
8000656: e7fc b.n 8000652 <main+0x14>
|
|
|
|
08000658 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000658: b580 push {r7, lr}
|
|
800065a: b09a sub sp, #104 @ 0x68
|
|
800065c: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800065e: f107 0320 add.w r3, r7, #32
|
|
8000662: 2248 movs r2, #72 @ 0x48
|
|
8000664: 2100 movs r1, #0
|
|
8000666: 4618 mov r0, r3
|
|
8000668: f00c ff04 bl 800d474 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
800066c: 1d3b adds r3, r7, #4
|
|
800066e: 2200 movs r2, #0
|
|
8000670: 601a str r2, [r3, #0]
|
|
8000672: 605a str r2, [r3, #4]
|
|
8000674: 609a str r2, [r3, #8]
|
|
8000676: 60da str r2, [r3, #12]
|
|
8000678: 611a str r2, [r3, #16]
|
|
800067a: 615a str r2, [r3, #20]
|
|
800067c: 619a str r2, [r3, #24]
|
|
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
800067e: f002 f891 bl 80027a4 <HAL_PWR_EnableBkUpAccess>
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
8000682: 2000 movs r0, #0
|
|
8000684: f7ff ffc6 bl 8000614 <LL_RCC_LSE_SetDriveCapability>
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8000688: 4b1e ldr r3, [pc, #120] @ (8000704 <SystemClock_Config+0xac>)
|
|
800068a: 681b ldr r3, [r3, #0]
|
|
800068c: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8000690: 4a1c ldr r2, [pc, #112] @ (8000704 <SystemClock_Config+0xac>)
|
|
8000692: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8000696: 6013 str r3, [r2, #0]
|
|
8000698: 4b1a ldr r3, [pc, #104] @ (8000704 <SystemClock_Config+0xac>)
|
|
800069a: 681b ldr r3, [r3, #0]
|
|
800069c: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
80006a0: 603b str r3, [r7, #0]
|
|
80006a2: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
|
|
80006a4: 2324 movs r3, #36 @ 0x24
|
|
80006a6: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
80006a8: 2381 movs r3, #129 @ 0x81
|
|
80006aa: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
80006ac: 2301 movs r3, #1
|
|
80006ae: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
|
80006b0: 2300 movs r3, #0
|
|
80006b2: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
|
|
80006b4: 23b0 movs r3, #176 @ 0xb0
|
|
80006b6: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
80006b8: 2300 movs r3, #0
|
|
80006ba: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80006bc: f107 0320 add.w r3, r7, #32
|
|
80006c0: 4618 mov r0, r3
|
|
80006c2: f002 fbe3 bl 8002e8c <HAL_RCC_OscConfig>
|
|
80006c6: 4603 mov r3, r0
|
|
80006c8: 2b00 cmp r3, #0
|
|
80006ca: d001 beq.n 80006d0 <SystemClock_Config+0x78>
|
|
{
|
|
Error_Handler();
|
|
80006cc: f000 f81c bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK
|
|
80006d0: 234f movs r3, #79 @ 0x4f
|
|
80006d2: 607b str r3, [r7, #4]
|
|
|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|
|
|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
|
80006d4: 2300 movs r3, #0
|
|
80006d6: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
80006d8: 2300 movs r3, #0
|
|
80006da: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
80006dc: 2300 movs r3, #0
|
|
80006de: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
80006e0: 2300 movs r3, #0
|
|
80006e2: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
|
|
80006e4: 2300 movs r3, #0
|
|
80006e6: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
|
80006e8: 1d3b adds r3, r7, #4
|
|
80006ea: 2102 movs r1, #2
|
|
80006ec: 4618 mov r0, r3
|
|
80006ee: f002 ff4f bl 8003590 <HAL_RCC_ClockConfig>
|
|
80006f2: 4603 mov r3, r0
|
|
80006f4: 2b00 cmp r3, #0
|
|
80006f6: d001 beq.n 80006fc <SystemClock_Config+0xa4>
|
|
{
|
|
Error_Handler();
|
|
80006f8: f000 f806 bl 8000708 <Error_Handler>
|
|
}
|
|
}
|
|
80006fc: bf00 nop
|
|
80006fe: 3768 adds r7, #104 @ 0x68
|
|
8000700: 46bd mov sp, r7
|
|
8000702: bd80 pop {r7, pc}
|
|
8000704: 58000400 .word 0x58000400
|
|
|
|
08000708 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000708: b480 push {r7}
|
|
800070a: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800070c: b672 cpsid i
|
|
}
|
|
800070e: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000710: bf00 nop
|
|
8000712: e7fd b.n 8000710 <Error_Handler+0x8>
|
|
|
|
08000714 <LL_RCC_EnableRTC>:
|
|
* @brief Enable RTC
|
|
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_EnableRTC(void)
|
|
{
|
|
8000714: b480 push {r7}
|
|
8000716: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
|
|
8000718: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800071c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8000720: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8000724: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8000728: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800072c: bf00 nop
|
|
800072e: 46bd mov sp, r7
|
|
8000730: bc80 pop {r7}
|
|
8000732: 4770 bx lr
|
|
|
|
08000734 <LL_APB1_GRP1_EnableClock>:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8000734: b480 push {r7}
|
|
8000736: b085 sub sp, #20
|
|
8000738: af00 add r7, sp, #0
|
|
800073a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
800073c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000740: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8000742: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8000746: 687b ldr r3, [r7, #4]
|
|
8000748: 4313 orrs r3, r2
|
|
800074a: 658b str r3, [r1, #88] @ 0x58
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
800074c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000750: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8000752: 687b ldr r3, [r7, #4]
|
|
8000754: 4013 ands r3, r2
|
|
8000756: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8000758: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800075a: bf00 nop
|
|
800075c: 3714 adds r7, #20
|
|
800075e: 46bd mov sp, r7
|
|
8000760: bc80 pop {r7}
|
|
8000762: 4770 bx lr
|
|
|
|
08000764 <MX_RTC_Init>:
|
|
|
|
RTC_HandleTypeDef hrtc;
|
|
|
|
/* RTC init function */
|
|
void MX_RTC_Init(void)
|
|
{
|
|
8000764: b580 push {r7, lr}
|
|
8000766: b08c sub sp, #48 @ 0x30
|
|
8000768: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN RTC_Init 0 */
|
|
|
|
/* USER CODE END RTC_Init 0 */
|
|
|
|
RTC_AlarmTypeDef sAlarm = {0};
|
|
800076a: 1d3b adds r3, r7, #4
|
|
800076c: 222c movs r2, #44 @ 0x2c
|
|
800076e: 2100 movs r1, #0
|
|
8000770: 4618 mov r0, r3
|
|
8000772: f00c fe7f bl 800d474 <memset>
|
|
|
|
/* USER CODE END RTC_Init 1 */
|
|
|
|
/** Initialize RTC Only
|
|
*/
|
|
hrtc.Instance = RTC;
|
|
8000776: 4b22 ldr r3, [pc, #136] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
8000778: 4a22 ldr r2, [pc, #136] @ (8000804 <MX_RTC_Init+0xa0>)
|
|
800077a: 601a str r2, [r3, #0]
|
|
hrtc.Init.AsynchPrediv = RTC_PREDIV_A;
|
|
800077c: 4b20 ldr r3, [pc, #128] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
800077e: 221f movs r2, #31
|
|
8000780: 609a str r2, [r3, #8]
|
|
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
|
|
8000782: 4b1f ldr r3, [pc, #124] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
8000784: 2200 movs r2, #0
|
|
8000786: 611a str r2, [r3, #16]
|
|
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
|
|
8000788: 4b1d ldr r3, [pc, #116] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
800078a: 2200 movs r2, #0
|
|
800078c: 615a str r2, [r3, #20]
|
|
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
|
800078e: 4b1c ldr r3, [pc, #112] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
8000790: 2200 movs r2, #0
|
|
8000792: 619a str r2, [r3, #24]
|
|
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
|
8000794: 4b1a ldr r3, [pc, #104] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
8000796: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
800079a: 61da str r2, [r3, #28]
|
|
hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE;
|
|
800079c: 4b18 ldr r3, [pc, #96] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
800079e: 2200 movs r2, #0
|
|
80007a0: 621a str r2, [r3, #32]
|
|
hrtc.Init.BinMode = RTC_BINARY_ONLY;
|
|
80007a2: 4b17 ldr r3, [pc, #92] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
80007a4: f44f 7280 mov.w r2, #256 @ 0x100
|
|
80007a8: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_RTC_Init(&hrtc) != HAL_OK)
|
|
80007aa: 4815 ldr r0, [pc, #84] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
80007ac: f003 fbca bl 8003f44 <HAL_RTC_Init>
|
|
80007b0: 4603 mov r3, r0
|
|
80007b2: 2b00 cmp r3, #0
|
|
80007b4: d001 beq.n 80007ba <MX_RTC_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
80007b6: f7ff ffa7 bl 8000708 <Error_Handler>
|
|
|
|
/* USER CODE END Check_RTC_BKUP */
|
|
|
|
/** Initialize RTC and set the Time and Date
|
|
*/
|
|
if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK)
|
|
80007ba: 4811 ldr r0, [pc, #68] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
80007bc: f003 feca bl 8004554 <HAL_RTCEx_SetSSRU_IT>
|
|
80007c0: 4603 mov r3, r0
|
|
80007c2: 2b00 cmp r3, #0
|
|
80007c4: d001 beq.n 80007ca <MX_RTC_Init+0x66>
|
|
{
|
|
Error_Handler();
|
|
80007c6: f7ff ff9f bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
/** Enable the Alarm A
|
|
*/
|
|
sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO;
|
|
80007ca: 2300 movs r3, #0
|
|
80007cc: 623b str r3, [r7, #32]
|
|
sAlarm.AlarmTime.SubSeconds = 0x0;
|
|
80007ce: 2300 movs r3, #0
|
|
80007d0: 60bb str r3, [r7, #8]
|
|
sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
|
|
80007d2: 2300 movs r3, #0
|
|
80007d4: 61bb str r3, [r7, #24]
|
|
sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE;
|
|
80007d6: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
80007da: 61fb str r3, [r7, #28]
|
|
sAlarm.Alarm = RTC_ALARM_A;
|
|
80007dc: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80007e0: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, 0) != HAL_OK)
|
|
80007e2: 1d3b adds r3, r7, #4
|
|
80007e4: 2200 movs r2, #0
|
|
80007e6: 4619 mov r1, r3
|
|
80007e8: 4805 ldr r0, [pc, #20] @ (8000800 <MX_RTC_Init+0x9c>)
|
|
80007ea: f003 fc37 bl 800405c <HAL_RTC_SetAlarm_IT>
|
|
80007ee: 4603 mov r3, r0
|
|
80007f0: 2b00 cmp r3, #0
|
|
80007f2: d001 beq.n 80007f8 <MX_RTC_Init+0x94>
|
|
{
|
|
Error_Handler();
|
|
80007f4: f7ff ff88 bl 8000708 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN RTC_Init 2 */
|
|
|
|
/* USER CODE END RTC_Init 2 */
|
|
|
|
}
|
|
80007f8: bf00 nop
|
|
80007fa: 3730 adds r7, #48 @ 0x30
|
|
80007fc: 46bd mov sp, r7
|
|
80007fe: bd80 pop {r7, pc}
|
|
8000800: 20000040 .word 0x20000040
|
|
8000804: 40002800 .word 0x40002800
|
|
|
|
08000808 <HAL_RTC_MspInit>:
|
|
|
|
void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
|
|
{
|
|
8000808: b580 push {r7, lr}
|
|
800080a: b090 sub sp, #64 @ 0x40
|
|
800080c: af00 add r7, sp, #0
|
|
800080e: 6078 str r0, [r7, #4]
|
|
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8000810: f107 0308 add.w r3, r7, #8
|
|
8000814: 2238 movs r2, #56 @ 0x38
|
|
8000816: 2100 movs r1, #0
|
|
8000818: 4618 mov r0, r3
|
|
800081a: f00c fe2b bl 800d474 <memset>
|
|
if(rtcHandle->Instance==RTC)
|
|
800081e: 687b ldr r3, [r7, #4]
|
|
8000820: 681b ldr r3, [r3, #0]
|
|
8000822: 4a16 ldr r2, [pc, #88] @ (800087c <HAL_RTC_MspInit+0x74>)
|
|
8000824: 4293 cmp r3, r2
|
|
8000826: d125 bne.n 8000874 <HAL_RTC_MspInit+0x6c>
|
|
|
|
/* USER CODE END RTC_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
|
8000828: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
800082c: 60bb str r3, [r7, #8]
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
800082e: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000832: 63fb str r3, [r7, #60] @ 0x3c
|
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8000834: f107 0308 add.w r3, r7, #8
|
|
8000838: 4618 mov r0, r3
|
|
800083a: f003 fa69 bl 8003d10 <HAL_RCCEx_PeriphCLKConfig>
|
|
800083e: 4603 mov r3, r0
|
|
8000840: 2b00 cmp r3, #0
|
|
8000842: d001 beq.n 8000848 <HAL_RTC_MspInit+0x40>
|
|
{
|
|
Error_Handler();
|
|
8000844: f7ff ff60 bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
/* RTC clock enable */
|
|
__HAL_RCC_RTC_ENABLE();
|
|
8000848: f7ff ff64 bl 8000714 <LL_RCC_EnableRTC>
|
|
__HAL_RCC_RTCAPB_CLK_ENABLE();
|
|
800084c: f44f 6080 mov.w r0, #1024 @ 0x400
|
|
8000850: f7ff ff70 bl 8000734 <LL_APB1_GRP1_EnableClock>
|
|
|
|
/* RTC interrupt Init */
|
|
HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0);
|
|
8000854: 2200 movs r2, #0
|
|
8000856: 2100 movs r1, #0
|
|
8000858: 2002 movs r0, #2
|
|
800085a: f001 f8f6 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn);
|
|
800085e: 2002 movs r0, #2
|
|
8000860: f001 f90d bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0);
|
|
8000864: 2200 movs r2, #0
|
|
8000866: 2100 movs r1, #0
|
|
8000868: 202a movs r0, #42 @ 0x2a
|
|
800086a: f001 f8ee bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
|
|
800086e: 202a movs r0, #42 @ 0x2a
|
|
8000870: f001 f905 bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN RTC_MspInit 1 */
|
|
|
|
/* USER CODE END RTC_MspInit 1 */
|
|
}
|
|
}
|
|
8000874: bf00 nop
|
|
8000876: 3740 adds r7, #64 @ 0x40
|
|
8000878: 46bd mov sp, r7
|
|
800087a: bd80 pop {r7, pc}
|
|
800087c: 40002800 .word 0x40002800
|
|
|
|
08000880 <LL_PWR_ClearFlag_C1STOP_C1STB>:
|
|
* @brief Clear standby and stop flags for CPU1
|
|
* @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void)
|
|
{
|
|
8000880: b480 push {r7}
|
|
8000882: af00 add r7, sp, #0
|
|
WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF);
|
|
8000884: 4b03 ldr r3, [pc, #12] @ (8000894 <LL_PWR_ClearFlag_C1STOP_C1STB+0x14>)
|
|
8000886: 2201 movs r2, #1
|
|
8000888: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
}
|
|
800088c: bf00 nop
|
|
800088e: 46bd mov sp, r7
|
|
8000890: bc80 pop {r7}
|
|
8000892: 4770 bx lr
|
|
8000894: 58000400 .word 0x58000400
|
|
|
|
08000898 <PWR_EnterOffMode>:
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
void PWR_EnterOffMode(void)
|
|
{
|
|
8000898: b480 push {r7}
|
|
800089a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EnterOffMode_1 */
|
|
|
|
/* USER CODE END EnterOffMode_1 */
|
|
}
|
|
800089c: bf00 nop
|
|
800089e: 46bd mov sp, r7
|
|
80008a0: bc80 pop {r7}
|
|
80008a2: 4770 bx lr
|
|
|
|
080008a4 <PWR_ExitOffMode>:
|
|
|
|
void PWR_ExitOffMode(void)
|
|
{
|
|
80008a4: b480 push {r7}
|
|
80008a6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN ExitOffMode_1 */
|
|
|
|
/* USER CODE END ExitOffMode_1 */
|
|
}
|
|
80008a8: bf00 nop
|
|
80008aa: 46bd mov sp, r7
|
|
80008ac: bc80 pop {r7}
|
|
80008ae: 4770 bx lr
|
|
|
|
080008b0 <PWR_EnterStopMode>:
|
|
|
|
void PWR_EnterStopMode(void)
|
|
{
|
|
80008b0: b580 push {r7, lr}
|
|
80008b2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EnterStopMode_1 */
|
|
|
|
/* USER CODE END EnterStopMode_1 */
|
|
HAL_SuspendTick();
|
|
80008b4: f000 ffc2 bl 800183c <HAL_SuspendTick>
|
|
/* Clear Status Flag before entering STOP/STANDBY Mode */
|
|
LL_PWR_ClearFlag_C1STOP_C1STB();
|
|
80008b8: f7ff ffe2 bl 8000880 <LL_PWR_ClearFlag_C1STOP_C1STB>
|
|
|
|
/* USER CODE BEGIN EnterStopMode_2 */
|
|
|
|
/* USER CODE END EnterStopMode_2 */
|
|
HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
|
|
80008bc: 2001 movs r0, #1
|
|
80008be: f002 f803 bl 80028c8 <HAL_PWREx_EnterSTOP2Mode>
|
|
/* USER CODE BEGIN EnterStopMode_3 */
|
|
|
|
/* USER CODE END EnterStopMode_3 */
|
|
}
|
|
80008c2: bf00 nop
|
|
80008c4: bd80 pop {r7, pc}
|
|
|
|
080008c6 <PWR_ExitStopMode>:
|
|
|
|
void PWR_ExitStopMode(void)
|
|
{
|
|
80008c6: b580 push {r7, lr}
|
|
80008c8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN ExitStopMode_1 */
|
|
|
|
/* USER CODE END ExitStopMode_1 */
|
|
/* Resume sysTick : work around for debugger problem in dual core */
|
|
HAL_ResumeTick();
|
|
80008ca: f000 ffc5 bl 8001858 <HAL_ResumeTick>
|
|
ADC interface
|
|
DAC interface USARTx, TIMx, i2Cx, SPIx
|
|
SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */
|
|
|
|
/* Resume not retained USARTx and DMA */
|
|
vcom_Resume();
|
|
80008ce: f000 fe11 bl 80014f4 <vcom_Resume>
|
|
/* USER CODE BEGIN ExitStopMode_2 */
|
|
|
|
/* USER CODE END ExitStopMode_2 */
|
|
}
|
|
80008d2: bf00 nop
|
|
80008d4: bd80 pop {r7, pc}
|
|
|
|
080008d6 <PWR_EnterSleepMode>:
|
|
|
|
void PWR_EnterSleepMode(void)
|
|
{
|
|
80008d6: b580 push {r7, lr}
|
|
80008d8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EnterSleepMode_1 */
|
|
|
|
/* USER CODE END EnterSleepMode_1 */
|
|
/* Suspend sysTick */
|
|
HAL_SuspendTick();
|
|
80008da: f000 ffaf bl 800183c <HAL_SuspendTick>
|
|
/* USER CODE BEGIN EnterSleepMode_2 */
|
|
|
|
/* USER CODE END EnterSleepMode_2 */
|
|
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
|
|
80008de: 2101 movs r1, #1
|
|
80008e0: 2000 movs r0, #0
|
|
80008e2: f001 ff6d bl 80027c0 <HAL_PWR_EnterSLEEPMode>
|
|
/* USER CODE BEGIN EnterSleepMode_3 */
|
|
|
|
/* USER CODE END EnterSleepMode_3 */
|
|
}
|
|
80008e6: bf00 nop
|
|
80008e8: bd80 pop {r7, pc}
|
|
|
|
080008ea <PWR_ExitSleepMode>:
|
|
|
|
void PWR_ExitSleepMode(void)
|
|
{
|
|
80008ea: b580 push {r7, lr}
|
|
80008ec: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN ExitSleepMode_1 */
|
|
|
|
/* USER CODE END ExitSleepMode_1 */
|
|
/* Resume sysTick */
|
|
HAL_ResumeTick();
|
|
80008ee: f000 ffb3 bl 8001858 <HAL_ResumeTick>
|
|
|
|
/* USER CODE BEGIN ExitSleepMode_2 */
|
|
|
|
/* USER CODE END ExitSleepMode_2 */
|
|
}
|
|
80008f2: bf00 nop
|
|
80008f4: bd80 pop {r7, pc}
|
|
|
|
080008f6 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80008f6: b480 push {r7}
|
|
80008f8: af00 add r7, sp, #0
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80008fa: bf00 nop
|
|
80008fc: 46bd mov sp, r7
|
|
80008fe: bc80 pop {r7}
|
|
8000900: 4770 bx lr
|
|
|
|
08000902 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000902: b480 push {r7}
|
|
8000904: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8000906: bf00 nop
|
|
8000908: e7fd b.n 8000906 <NMI_Handler+0x4>
|
|
|
|
0800090a <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800090a: b480 push {r7}
|
|
800090c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800090e: bf00 nop
|
|
8000910: e7fd b.n 800090e <HardFault_Handler+0x4>
|
|
|
|
08000912 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000912: b480 push {r7}
|
|
8000914: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000916: bf00 nop
|
|
8000918: e7fd b.n 8000916 <MemManage_Handler+0x4>
|
|
|
|
0800091a <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800091a: b480 push {r7}
|
|
800091c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800091e: bf00 nop
|
|
8000920: e7fd b.n 800091e <BusFault_Handler+0x4>
|
|
|
|
08000922 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000922: b480 push {r7}
|
|
8000924: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000926: bf00 nop
|
|
8000928: e7fd b.n 8000926 <UsageFault_Handler+0x4>
|
|
|
|
0800092a <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800092a: b480 push {r7}
|
|
800092c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
800092e: bf00 nop
|
|
8000930: 46bd mov sp, r7
|
|
8000932: bc80 pop {r7}
|
|
8000934: 4770 bx lr
|
|
|
|
08000936 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000936: b480 push {r7}
|
|
8000938: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800093a: bf00 nop
|
|
800093c: 46bd mov sp, r7
|
|
800093e: bc80 pop {r7}
|
|
8000940: 4770 bx lr
|
|
|
|
08000942 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000942: b480 push {r7}
|
|
8000944: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000946: bf00 nop
|
|
8000948: 46bd mov sp, r7
|
|
800094a: bc80 pop {r7}
|
|
800094c: 4770 bx lr
|
|
|
|
0800094e <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
800094e: b480 push {r7}
|
|
8000950: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000952: bf00 nop
|
|
8000954: 46bd mov sp, r7
|
|
8000956: bc80 pop {r7}
|
|
8000958: 4770 bx lr
|
|
...
|
|
|
|
0800095c <TAMP_STAMP_LSECSS_SSRU_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts.
|
|
*/
|
|
void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void)
|
|
{
|
|
800095c: b580 push {r7, lr}
|
|
800095e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */
|
|
|
|
/* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */
|
|
HAL_RTCEx_SSRUIRQHandler(&hrtc);
|
|
8000960: 4802 ldr r0, [pc, #8] @ (800096c <TAMP_STAMP_LSECSS_SSRU_IRQHandler+0x10>)
|
|
8000962: f003 fe33 bl 80045cc <HAL_RTCEx_SSRUIRQHandler>
|
|
/* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */
|
|
|
|
/* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */
|
|
}
|
|
8000966: bf00 nop
|
|
8000968: bd80 pop {r7, pc}
|
|
800096a: bf00 nop
|
|
800096c: 20000040 .word 0x20000040
|
|
|
|
08000970 <EXTI0_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI Line 0 Interrupt.
|
|
*/
|
|
void EXTI0_IRQHandler(void)
|
|
{
|
|
8000970: b580 push {r7, lr}
|
|
8000972: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI0_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI0_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(BUT1_Pin);
|
|
8000974: 2001 movs r0, #1
|
|
8000976: f001 fefd bl 8002774 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI0_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI0_IRQn 1 */
|
|
}
|
|
800097a: bf00 nop
|
|
800097c: bd80 pop {r7, pc}
|
|
|
|
0800097e <EXTI1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI Line 1 Interrupt.
|
|
*/
|
|
void EXTI1_IRQHandler(void)
|
|
{
|
|
800097e: b580 push {r7, lr}
|
|
8000980: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI1_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI1_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(BUT2_Pin);
|
|
8000982: 2002 movs r0, #2
|
|
8000984: f001 fef6 bl 8002774 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI1_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI1_IRQn 1 */
|
|
}
|
|
8000988: bf00 nop
|
|
800098a: bd80 pop {r7, pc}
|
|
|
|
0800098c <DMA1_Channel5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 Channel 5 Interrupt.
|
|
*/
|
|
void DMA1_Channel5_IRQHandler(void)
|
|
{
|
|
800098c: b580 push {r7, lr}
|
|
800098e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel5_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_tx);
|
|
8000990: 4802 ldr r0, [pc, #8] @ (800099c <DMA1_Channel5_IRQHandler+0x10>)
|
|
8000992: f001 fb0b bl 8001fac <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel5_IRQn 1 */
|
|
}
|
|
8000996: bf00 nop
|
|
8000998: bd80 pop {r7, pc}
|
|
800099a: bf00 nop
|
|
800099c: 20000120 .word 0x20000120
|
|
|
|
080009a0 <EXTI9_5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI Lines [9:5] Interrupt.
|
|
*/
|
|
void EXTI9_5_IRQHandler(void)
|
|
{
|
|
80009a0: b580 push {r7, lr}
|
|
80009a2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(BUT3_Pin);
|
|
80009a4: 2040 movs r0, #64 @ 0x40
|
|
80009a6: f001 fee5 bl 8002774 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 1 */
|
|
}
|
|
80009aa: bf00 nop
|
|
80009ac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080009b0 <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 Interrupt.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
80009b0: b580 push {r7, lr}
|
|
80009b2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
80009b4: 4802 ldr r0, [pc, #8] @ (80009c0 <USART2_IRQHandler+0x10>)
|
|
80009b6: f004 fc65 bl 8005284 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
80009ba: bf00 nop
|
|
80009bc: bd80 pop {r7, pc}
|
|
80009be: bf00 nop
|
|
80009c0: 2000008c .word 0x2000008c
|
|
|
|
080009c4 <RTC_Alarm_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles RTC Alarms (A and B) Interrupt.
|
|
*/
|
|
void RTC_Alarm_IRQHandler(void)
|
|
{
|
|
80009c4: b580 push {r7, lr}
|
|
80009c6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN RTC_Alarm_IRQn 0 */
|
|
|
|
/* USER CODE END RTC_Alarm_IRQn 0 */
|
|
HAL_RTC_AlarmIRQHandler(&hrtc);
|
|
80009c8: 4802 ldr r0, [pc, #8] @ (80009d4 <RTC_Alarm_IRQHandler+0x10>)
|
|
80009ca: f003 fcaf bl 800432c <HAL_RTC_AlarmIRQHandler>
|
|
/* USER CODE BEGIN RTC_Alarm_IRQn 1 */
|
|
|
|
/* USER CODE END RTC_Alarm_IRQn 1 */
|
|
}
|
|
80009ce: bf00 nop
|
|
80009d0: bd80 pop {r7, pc}
|
|
80009d2: bf00 nop
|
|
80009d4: 20000040 .word 0x20000040
|
|
|
|
080009d8 <SUBGHZ_Radio_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles SUBGHZ Radio Interrupt.
|
|
*/
|
|
void SUBGHZ_Radio_IRQHandler(void)
|
|
{
|
|
80009d8: b580 push {r7, lr}
|
|
80009da: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */
|
|
|
|
/* USER CODE END SUBGHZ_Radio_IRQn 0 */
|
|
HAL_SUBGHZ_IRQHandler(&hsubghz);
|
|
80009dc: 4802 ldr r0, [pc, #8] @ (80009e8 <SUBGHZ_Radio_IRQHandler+0x10>)
|
|
80009de: f004 f963 bl 8004ca8 <HAL_SUBGHZ_IRQHandler>
|
|
/* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */
|
|
|
|
/* USER CODE END SUBGHZ_Radio_IRQn 1 */
|
|
}
|
|
80009e2: bf00 nop
|
|
80009e4: bd80 pop {r7, pc}
|
|
80009e6: bf00 nop
|
|
80009e8: 20000078 .word 0x20000078
|
|
|
|
080009ec <LL_APB3_GRP1_EnableClock>:
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80009ec: b480 push {r7}
|
|
80009ee: b085 sub sp, #20
|
|
80009f0: af00 add r7, sp, #0
|
|
80009f2: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB3ENR, Periphs);
|
|
80009f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80009f8: 6e5a ldr r2, [r3, #100] @ 0x64
|
|
80009fa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80009fe: 687b ldr r3, [r7, #4]
|
|
8000a00: 4313 orrs r3, r2
|
|
8000a02: 664b str r3, [r1, #100] @ 0x64
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
|
|
8000a04: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000a08: 6e5a ldr r2, [r3, #100] @ 0x64
|
|
8000a0a: 687b ldr r3, [r7, #4]
|
|
8000a0c: 4013 ands r3, r2
|
|
8000a0e: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8000a10: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000a12: bf00 nop
|
|
8000a14: 3714 adds r7, #20
|
|
8000a16: 46bd mov sp, r7
|
|
8000a18: bc80 pop {r7}
|
|
8000a1a: 4770 bx lr
|
|
|
|
08000a1c <MX_SUBGHZ_Init>:
|
|
|
|
SUBGHZ_HandleTypeDef hsubghz;
|
|
|
|
/* SUBGHZ init function */
|
|
void MX_SUBGHZ_Init(void)
|
|
{
|
|
8000a1c: b580 push {r7, lr}
|
|
8000a1e: af00 add r7, sp, #0
|
|
/* USER CODE END SUBGHZ_Init 0 */
|
|
|
|
/* USER CODE BEGIN SUBGHZ_Init 1 */
|
|
|
|
/* USER CODE END SUBGHZ_Init 1 */
|
|
hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_4;
|
|
8000a20: 4b06 ldr r3, [pc, #24] @ (8000a3c <MX_SUBGHZ_Init+0x20>)
|
|
8000a22: 2208 movs r2, #8
|
|
8000a24: 601a str r2, [r3, #0]
|
|
if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK)
|
|
8000a26: 4805 ldr r0, [pc, #20] @ (8000a3c <MX_SUBGHZ_Init+0x20>)
|
|
8000a28: f003 febc bl 80047a4 <HAL_SUBGHZ_Init>
|
|
8000a2c: 4603 mov r3, r0
|
|
8000a2e: 2b00 cmp r3, #0
|
|
8000a30: d001 beq.n 8000a36 <MX_SUBGHZ_Init+0x1a>
|
|
{
|
|
Error_Handler();
|
|
8000a32: f7ff fe69 bl 8000708 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SUBGHZ_Init 2 */
|
|
|
|
/* USER CODE END SUBGHZ_Init 2 */
|
|
|
|
}
|
|
8000a36: bf00 nop
|
|
8000a38: bd80 pop {r7, pc}
|
|
8000a3a: bf00 nop
|
|
8000a3c: 20000078 .word 0x20000078
|
|
|
|
08000a40 <HAL_SUBGHZ_MspInit>:
|
|
|
|
void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle)
|
|
{
|
|
8000a40: b580 push {r7, lr}
|
|
8000a42: b082 sub sp, #8
|
|
8000a44: af00 add r7, sp, #0
|
|
8000a46: 6078 str r0, [r7, #4]
|
|
|
|
/* USER CODE BEGIN SUBGHZ_MspInit 0 */
|
|
|
|
/* USER CODE END SUBGHZ_MspInit 0 */
|
|
/* SUBGHZ clock enable */
|
|
__HAL_RCC_SUBGHZSPI_CLK_ENABLE();
|
|
8000a48: 2001 movs r0, #1
|
|
8000a4a: f7ff ffcf bl 80009ec <LL_APB3_GRP1_EnableClock>
|
|
|
|
/* SUBGHZ interrupt Init */
|
|
HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0);
|
|
8000a4e: 2200 movs r2, #0
|
|
8000a50: 2100 movs r1, #0
|
|
8000a52: 2032 movs r0, #50 @ 0x32
|
|
8000a54: f000 fff9 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn);
|
|
8000a58: 2032 movs r0, #50 @ 0x32
|
|
8000a5a: f001 f810 bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN SUBGHZ_MspInit 1 */
|
|
|
|
/* USER CODE END SUBGHZ_MspInit 1 */
|
|
}
|
|
8000a5e: bf00 nop
|
|
8000a60: 3708 adds r7, #8
|
|
8000a62: 46bd mov sp, r7
|
|
8000a64: bd80 pop {r7, pc}
|
|
|
|
08000a66 <LL_RCC_SetClkAfterWakeFromStop>:
|
|
{
|
|
8000a66: b480 push {r7}
|
|
8000a68: b083 sub sp, #12
|
|
8000a6a: af00 add r7, sp, #0
|
|
8000a6c: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
|
|
8000a6e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000a72: 689b ldr r3, [r3, #8]
|
|
8000a74: f423 4200 bic.w r2, r3, #32768 @ 0x8000
|
|
8000a78: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8000a7c: 687b ldr r3, [r7, #4]
|
|
8000a7e: 4313 orrs r3, r2
|
|
8000a80: 608b str r3, [r1, #8]
|
|
}
|
|
8000a82: bf00 nop
|
|
8000a84: 370c adds r7, #12
|
|
8000a86: 46bd mov sp, r7
|
|
8000a88: bc80 pop {r7}
|
|
8000a8a: 4770 bx lr
|
|
|
|
08000a8c <SystemApp_Init>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions ---------------------------------------------------------*/
|
|
void SystemApp_Init(void)
|
|
{
|
|
8000a8c: b580 push {r7, lr}
|
|
8000a8e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SystemApp_Init_1 */
|
|
|
|
/* USER CODE END SystemApp_Init_1 */
|
|
|
|
/* Ensure that MSI is wake-up system clock */
|
|
__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
|
|
8000a90: 2000 movs r0, #0
|
|
8000a92: f7ff ffe8 bl 8000a66 <LL_RCC_SetClkAfterWakeFromStop>
|
|
|
|
/*Initialize timer and RTC*/
|
|
UTIL_TIMER_Init();
|
|
8000a96: f00b ffc9 bl 800ca2c <UTIL_TIMER_Init>
|
|
SYS_TimerInitialisedFlag = 1;
|
|
8000a9a: 4b0c ldr r3, [pc, #48] @ (8000acc <SystemApp_Init+0x40>)
|
|
8000a9c: 2201 movs r2, #1
|
|
8000a9e: 701a strb r2, [r3, #0]
|
|
/* Initializes the SW probes pins and the monitor RF pins via Alternate Function */
|
|
DBG_Init();
|
|
8000aa0: f000 f8ba bl 8000c18 <DBG_Init>
|
|
|
|
/*Initialize the terminal */
|
|
UTIL_ADV_TRACE_Init();
|
|
8000aa4: f00c fa52 bl 800cf4c <UTIL_ADV_TRACE_Init>
|
|
UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow);
|
|
8000aa8: 4809 ldr r0, [pc, #36] @ (8000ad0 <SystemApp_Init+0x44>)
|
|
8000aaa: f00c faeb bl 800d084 <UTIL_ADV_TRACE_RegisterTimeStampFunction>
|
|
|
|
/*Set verbose LEVEL*/
|
|
UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL);
|
|
8000aae: 2002 movs r0, #2
|
|
8000ab0: f00c faf6 bl 800d0a0 <UTIL_ADV_TRACE_SetVerboseLevel>
|
|
|
|
/*Init low power manager*/
|
|
UTIL_LPM_Init();
|
|
8000ab4: f00b fa74 bl 800bfa0 <UTIL_LPM_Init>
|
|
/* Disable Stand-by mode */
|
|
UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE);
|
|
8000ab8: 2101 movs r1, #1
|
|
8000aba: 2001 movs r0, #1
|
|
8000abc: f00b fab0 bl 800c020 <UTIL_LPM_SetOffMode>
|
|
|
|
#if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1)
|
|
/* Disable Stop Mode */
|
|
UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE);
|
|
8000ac0: 2101 movs r1, #1
|
|
8000ac2: 2001 movs r0, #1
|
|
8000ac4: f00b fa7c bl 800bfc0 <UTIL_LPM_SetStopMode>
|
|
#endif /* LOW_POWER_DISABLE */
|
|
|
|
/* USER CODE BEGIN SystemApp_Init_2 */
|
|
|
|
/* USER CODE END SystemApp_Init_2 */
|
|
}
|
|
8000ac8: bf00 nop
|
|
8000aca: bd80 pop {r7, pc}
|
|
8000acc: 20000084 .word 0x20000084
|
|
8000ad0: 08000ae1 .word 0x08000ae1
|
|
|
|
08000ad4 <UTIL_SEQ_Idle>:
|
|
|
|
/**
|
|
* @brief redefines __weak function in stm32_seq.c such to enter low power
|
|
*/
|
|
void UTIL_SEQ_Idle(void)
|
|
{
|
|
8000ad4: b580 push {r7, lr}
|
|
8000ad6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UTIL_SEQ_Idle_1 */
|
|
|
|
/* USER CODE END UTIL_SEQ_Idle_1 */
|
|
UTIL_LPM_EnterLowPower();
|
|
8000ad8: f00b fad2 bl 800c080 <UTIL_LPM_EnterLowPower>
|
|
/* USER CODE BEGIN UTIL_SEQ_Idle_2 */
|
|
|
|
/* USER CODE END UTIL_SEQ_Idle_2 */
|
|
}
|
|
8000adc: bf00 nop
|
|
8000ade: bd80 pop {r7, pc}
|
|
|
|
08000ae0 <TimestampNow>:
|
|
/* USER CODE END EF */
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
|
|
static void TimestampNow(uint8_t *buff, uint16_t *size)
|
|
{
|
|
8000ae0: b580 push {r7, lr}
|
|
8000ae2: b086 sub sp, #24
|
|
8000ae4: af02 add r7, sp, #8
|
|
8000ae6: 6078 str r0, [r7, #4]
|
|
8000ae8: 6039 str r1, [r7, #0]
|
|
/* USER CODE BEGIN TimestampNow_1 */
|
|
|
|
/* USER CODE END TimestampNow_1 */
|
|
SysTime_t curtime = SysTimeGet();
|
|
8000aea: f107 0308 add.w r3, r7, #8
|
|
8000aee: 4618 mov r0, r3
|
|
8000af0: f00b fb70 bl 800c1d4 <SysTimeGet>
|
|
tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds);
|
|
8000af4: 68bb ldr r3, [r7, #8]
|
|
8000af6: f9b7 200c ldrsh.w r2, [r7, #12]
|
|
8000afa: 9200 str r2, [sp, #0]
|
|
8000afc: 4a07 ldr r2, [pc, #28] @ (8000b1c <TimestampNow+0x3c>)
|
|
8000afe: 2110 movs r1, #16
|
|
8000b00: 6878 ldr r0, [r7, #4]
|
|
8000b02: f000 f81d bl 8000b40 <tiny_snprintf_like>
|
|
*size = strlen((char *)buff);
|
|
8000b06: 6878 ldr r0, [r7, #4]
|
|
8000b08: f7ff fb36 bl 8000178 <strlen>
|
|
8000b0c: 4603 mov r3, r0
|
|
8000b0e: b29a uxth r2, r3
|
|
8000b10: 683b ldr r3, [r7, #0]
|
|
8000b12: 801a strh r2, [r3, #0]
|
|
/* USER CODE BEGIN TimestampNow_2 */
|
|
|
|
/* USER CODE END TimestampNow_2 */
|
|
}
|
|
8000b14: bf00 nop
|
|
8000b16: 3710 adds r7, #16
|
|
8000b18: 46bd mov sp, r7
|
|
8000b1a: bd80 pop {r7, pc}
|
|
8000b1c: 0800d500 .word 0x0800d500
|
|
|
|
08000b20 <UTIL_ADV_TRACE_PreSendHook>:
|
|
|
|
/* Disable StopMode when traces need to be printed */
|
|
void UTIL_ADV_TRACE_PreSendHook(void)
|
|
{
|
|
8000b20: b580 push {r7, lr}
|
|
8000b22: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */
|
|
|
|
/* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */
|
|
UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE);
|
|
8000b24: 2101 movs r1, #1
|
|
8000b26: 2002 movs r0, #2
|
|
8000b28: f00b fa4a bl 800bfc0 <UTIL_LPM_SetStopMode>
|
|
/* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */
|
|
|
|
/* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */
|
|
}
|
|
8000b2c: bf00 nop
|
|
8000b2e: bd80 pop {r7, pc}
|
|
|
|
08000b30 <UTIL_ADV_TRACE_PostSendHook>:
|
|
/* Re-enable StopMode when traces have been printed */
|
|
void UTIL_ADV_TRACE_PostSendHook(void)
|
|
{
|
|
8000b30: b580 push {r7, lr}
|
|
8000b32: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */
|
|
|
|
/* USER CODE END UTIL_LPM_SetStopMode_1 */
|
|
UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE);
|
|
8000b34: 2100 movs r1, #0
|
|
8000b36: 2002 movs r0, #2
|
|
8000b38: f00b fa42 bl 800bfc0 <UTIL_LPM_SetStopMode>
|
|
/* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */
|
|
|
|
/* USER CODE END UTIL_LPM_SetStopMode_2 */
|
|
}
|
|
8000b3c: bf00 nop
|
|
8000b3e: bd80 pop {r7, pc}
|
|
|
|
08000b40 <tiny_snprintf_like>:
|
|
|
|
static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...)
|
|
{
|
|
8000b40: b40c push {r2, r3}
|
|
8000b42: b580 push {r7, lr}
|
|
8000b44: b084 sub sp, #16
|
|
8000b46: af00 add r7, sp, #0
|
|
8000b48: 6078 str r0, [r7, #4]
|
|
8000b4a: 6039 str r1, [r7, #0]
|
|
/* USER CODE BEGIN tiny_snprintf_like_1 */
|
|
|
|
/* USER CODE END tiny_snprintf_like_1 */
|
|
va_list vaArgs;
|
|
va_start(vaArgs, strFormat);
|
|
8000b4c: f107 031c add.w r3, r7, #28
|
|
8000b50: 60fb str r3, [r7, #12]
|
|
UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs);
|
|
8000b52: 6839 ldr r1, [r7, #0]
|
|
8000b54: 68fb ldr r3, [r7, #12]
|
|
8000b56: 69ba ldr r2, [r7, #24]
|
|
8000b58: 6878 ldr r0, [r7, #4]
|
|
8000b5a: f00b fc87 bl 800c46c <tiny_vsnprintf_like>
|
|
va_end(vaArgs);
|
|
/* USER CODE BEGIN tiny_snprintf_like_2 */
|
|
|
|
/* USER CODE END tiny_snprintf_like_2 */
|
|
}
|
|
8000b5e: bf00 nop
|
|
8000b60: 3710 adds r7, #16
|
|
8000b62: 46bd mov sp, r7
|
|
8000b64: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8000b68: b002 add sp, #8
|
|
8000b6a: 4770 bx lr
|
|
|
|
08000b6c <HAL_InitTick>:
|
|
|
|
/**
|
|
* @note This function overwrites the __weak one from HAL
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000b6c: b480 push {r7}
|
|
8000b6e: b083 sub sp, #12
|
|
8000b70: af00 add r7, sp, #0
|
|
8000b72: 6078 str r0, [r7, #4]
|
|
/*Don't enable SysTick if TIMER_IF is based on other counters (e.g. RTC) */
|
|
/* USER CODE BEGIN HAL_InitTick_1 */
|
|
|
|
/* USER CODE END HAL_InitTick_1 */
|
|
return HAL_OK;
|
|
8000b74: 2300 movs r3, #0
|
|
/* USER CODE BEGIN HAL_InitTick_2 */
|
|
|
|
/* USER CODE END HAL_InitTick_2 */
|
|
}
|
|
8000b76: 4618 mov r0, r3
|
|
8000b78: 370c adds r7, #12
|
|
8000b7a: 46bd mov sp, r7
|
|
8000b7c: bc80 pop {r7}
|
|
8000b7e: 4770 bx lr
|
|
|
|
08000b80 <HAL_GetTick>:
|
|
|
|
/**
|
|
* @note This function overwrites the __weak one from HAL
|
|
*/
|
|
uint32_t HAL_GetTick(void)
|
|
{
|
|
8000b80: b580 push {r7, lr}
|
|
8000b82: b082 sub sp, #8
|
|
8000b84: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
8000b86: 2300 movs r3, #0
|
|
8000b88: 607b str r3, [r7, #4]
|
|
/* TIMER_IF can be based on other counter the SysTick e.g. RTC */
|
|
/* USER CODE BEGIN HAL_GetTick_1 */
|
|
|
|
/* USER CODE END HAL_GetTick_1 */
|
|
if (SYS_TimerInitialisedFlag == 0)
|
|
8000b8a: 4b06 ldr r3, [pc, #24] @ (8000ba4 <HAL_GetTick+0x24>)
|
|
8000b8c: 781b ldrb r3, [r3, #0]
|
|
8000b8e: 2b00 cmp r3, #0
|
|
8000b90: d002 beq.n 8000b98 <HAL_GetTick+0x18>
|
|
|
|
/* USER CODE END HAL_GetTick_EarlyCall */
|
|
}
|
|
else
|
|
{
|
|
ret = TIMER_IF_GetTimerValue();
|
|
8000b92: f000 f945 bl 8000e20 <TIMER_IF_GetTimerValue>
|
|
8000b96: 6078 str r0, [r7, #4]
|
|
}
|
|
/* USER CODE BEGIN HAL_GetTick_2 */
|
|
|
|
/* USER CODE END HAL_GetTick_2 */
|
|
return ret;
|
|
8000b98: 687b ldr r3, [r7, #4]
|
|
}
|
|
8000b9a: 4618 mov r0, r3
|
|
8000b9c: 3708 adds r7, #8
|
|
8000b9e: 46bd mov sp, r7
|
|
8000ba0: bd80 pop {r7, pc}
|
|
8000ba2: bf00 nop
|
|
8000ba4: 20000084 .word 0x20000084
|
|
|
|
08000ba8 <HAL_Delay>:
|
|
|
|
/**
|
|
* @note This function overwrites the __weak one from HAL
|
|
*/
|
|
void HAL_Delay(__IO uint32_t Delay)
|
|
{
|
|
8000ba8: b580 push {r7, lr}
|
|
8000baa: b082 sub sp, #8
|
|
8000bac: af00 add r7, sp, #0
|
|
8000bae: 6078 str r0, [r7, #4]
|
|
/* TIMER_IF can be based on other counter the SysTick e.g. RTC */
|
|
/* USER CODE BEGIN HAL_Delay_1 */
|
|
|
|
/* USER CODE END HAL_Delay_1 */
|
|
TIMER_IF_DelayMs(Delay);
|
|
8000bb0: 687b ldr r3, [r7, #4]
|
|
8000bb2: 4618 mov r0, r3
|
|
8000bb4: f000 f9bb bl 8000f2e <TIMER_IF_DelayMs>
|
|
/* USER CODE BEGIN HAL_Delay_2 */
|
|
|
|
/* USER CODE END HAL_Delay_2 */
|
|
}
|
|
8000bb8: bf00 nop
|
|
8000bba: 3708 adds r7, #8
|
|
8000bbc: 46bd mov sp, r7
|
|
8000bbe: bd80 pop {r7, pc}
|
|
|
|
08000bc0 <LL_AHB2_GRP1_EnableClock>:
|
|
{
|
|
8000bc0: b480 push {r7}
|
|
8000bc2: b085 sub sp, #20
|
|
8000bc4: af00 add r7, sp, #0
|
|
8000bc6: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
8000bc8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000bcc: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8000bce: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8000bd2: 687b ldr r3, [r7, #4]
|
|
8000bd4: 4313 orrs r3, r2
|
|
8000bd6: 64cb str r3, [r1, #76] @ 0x4c
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
8000bd8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8000bdc: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8000bde: 687b ldr r3, [r7, #4]
|
|
8000be0: 4013 ands r3, r2
|
|
8000be2: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8000be4: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000be6: bf00 nop
|
|
8000be8: 3714 adds r7, #20
|
|
8000bea: 46bd mov sp, r7
|
|
8000bec: bc80 pop {r7}
|
|
8000bee: 4770 bx lr
|
|
|
|
08000bf0 <LL_EXTI_EnableIT_32_63>:
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* (*) value not defined in all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
|
|
{
|
|
8000bf0: b480 push {r7}
|
|
8000bf2: b083 sub sp, #12
|
|
8000bf4: af00 add r7, sp, #0
|
|
8000bf6: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->IMR2, ExtiLine);
|
|
8000bf8: 4b06 ldr r3, [pc, #24] @ (8000c14 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
8000bfa: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90
|
|
8000bfe: 4905 ldr r1, [pc, #20] @ (8000c14 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
8000c00: 687b ldr r3, [r7, #4]
|
|
8000c02: 4313 orrs r3, r2
|
|
8000c04: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
8000c08: bf00 nop
|
|
8000c0a: 370c adds r7, #12
|
|
8000c0c: 46bd mov sp, r7
|
|
8000c0e: bc80 pop {r7}
|
|
8000c10: 4770 bx lr
|
|
8000c12: bf00 nop
|
|
8000c14: 58000800 .word 0x58000800
|
|
|
|
08000c18 <DBG_Init>:
|
|
|
|
/**
|
|
* @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function
|
|
*/
|
|
void DBG_Init(void)
|
|
{
|
|
8000c18: b580 push {r7, lr}
|
|
8000c1a: b086 sub sp, #24
|
|
8000c1c: af00 add r7, sp, #0
|
|
HAL_DBGMCU_DisableDBGSleepMode();
|
|
HAL_DBGMCU_DisableDBGStopMode();
|
|
HAL_DBGMCU_DisableDBGStandbyMode();
|
|
#elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 )
|
|
/*Debug power up request wakeup CBDGPWRUPREQ*/
|
|
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46);
|
|
8000c1e: f44f 4080 mov.w r0, #16384 @ 0x4000
|
|
8000c22: f7ff ffe5 bl 8000bf0 <LL_EXTI_EnableIT_32_63>
|
|
/* Disabled HAL_DBGMCU_ */
|
|
HAL_DBGMCU_EnableDBGSleepMode();
|
|
8000c26: f000 fe25 bl 8001874 <HAL_DBGMCU_EnableDBGSleepMode>
|
|
HAL_DBGMCU_EnableDBGStopMode();
|
|
8000c2a: f000 fe29 bl 8001880 <HAL_DBGMCU_EnableDBGStopMode>
|
|
HAL_DBGMCU_EnableDBGStandbyMode();
|
|
8000c2e: f000 fe2d bl 800188c <HAL_DBGMCU_EnableDBGStandbyMode>
|
|
#elif !defined (DEBUGGER_ENABLED)
|
|
#error "DEBUGGER_ENABLED not defined or out of range <0,1>"
|
|
#endif /* DEBUGGER_OFF */
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000c32: 1d3b adds r3, r7, #4
|
|
8000c34: 2200 movs r2, #0
|
|
8000c36: 601a str r2, [r3, #0]
|
|
8000c38: 605a str r2, [r3, #4]
|
|
8000c3a: 609a str r2, [r3, #8]
|
|
8000c3c: 60da str r2, [r3, #12]
|
|
8000c3e: 611a str r2, [r3, #16]
|
|
|
|
/* Configure the GPIO pin */
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c40: 2301 movs r3, #1
|
|
8000c42: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c44: 2300 movs r3, #0
|
|
8000c46: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000c48: 2303 movs r3, #3
|
|
8000c4a: 613b str r3, [r7, #16]
|
|
|
|
/* Enable the GPIO Clock */
|
|
PROBE_LINE1_CLK_ENABLE();
|
|
8000c4c: 2002 movs r0, #2
|
|
8000c4e: f7ff ffb7 bl 8000bc0 <LL_AHB2_GRP1_EnableClock>
|
|
PROBE_LINE2_CLK_ENABLE();
|
|
8000c52: 2002 movs r0, #2
|
|
8000c54: f7ff ffb4 bl 8000bc0 <LL_AHB2_GRP1_EnableClock>
|
|
|
|
GPIO_InitStruct.Pin = PROBE_LINE1_PIN;
|
|
8000c58: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000c5c: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(PROBE_LINE1_PORT, &GPIO_InitStruct);
|
|
8000c5e: 1d3b adds r3, r7, #4
|
|
8000c60: 4619 mov r1, r3
|
|
8000c62: 480d ldr r0, [pc, #52] @ (8000c98 <DBG_Init+0x80>)
|
|
8000c64: f001 fb40 bl 80022e8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = PROBE_LINE2_PIN;
|
|
8000c68: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8000c6c: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(PROBE_LINE2_PORT, &GPIO_InitStruct);
|
|
8000c6e: 1d3b adds r3, r7, #4
|
|
8000c70: 4619 mov r1, r3
|
|
8000c72: 4809 ldr r0, [pc, #36] @ (8000c98 <DBG_Init+0x80>)
|
|
8000c74: f001 fb38 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/* Reset probe Pins */
|
|
HAL_GPIO_WritePin(PROBE_LINE1_PORT, PROBE_LINE1_PIN, GPIO_PIN_RESET);
|
|
8000c78: 2200 movs r2, #0
|
|
8000c7a: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8000c7e: 4806 ldr r0, [pc, #24] @ (8000c98 <DBG_Init+0x80>)
|
|
8000c80: f001 fd60 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(PROBE_LINE2_PORT, PROBE_LINE2_PIN, GPIO_PIN_RESET);
|
|
8000c84: 2200 movs r2, #0
|
|
8000c86: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8000c8a: 4803 ldr r0, [pc, #12] @ (8000c98 <DBG_Init+0x80>)
|
|
8000c8c: f001 fd5a bl 8002744 <HAL_GPIO_WritePin>
|
|
#endif /* DEBUG_RF_BUSY_ENABLED */
|
|
|
|
/* USER CODE BEGIN DBG_Init_3 */
|
|
|
|
/* USER CODE END DBG_Init_3 */
|
|
}
|
|
8000c90: bf00 nop
|
|
8000c92: 3718 adds r7, #24
|
|
8000c94: 46bd mov sp, r7
|
|
8000c96: bd80 pop {r7, pc}
|
|
8000c98: 48000400 .word 0x48000400
|
|
|
|
08000c9c <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8000c9c: b480 push {r7}
|
|
8000c9e: af00 add r7, sp, #0
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */
|
|
#endif
|
|
}
|
|
8000ca0: bf00 nop
|
|
8000ca2: 46bd mov sp, r7
|
|
8000ca4: bc80 pop {r7}
|
|
8000ca6: 4770 bx lr
|
|
|
|
08000ca8 <LL_RTC_TIME_GetSubSecond>:
|
|
* @param RTCx RTC Instance
|
|
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
|
|
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx)
|
|
{
|
|
8000ca8: b480 push {r7}
|
|
8000caa: b083 sub sp, #12
|
|
8000cac: af00 add r7, sp, #0
|
|
8000cae: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
|
|
8000cb0: 687b ldr r3, [r7, #4]
|
|
8000cb2: 689b ldr r3, [r3, #8]
|
|
}
|
|
8000cb4: 4618 mov r0, r3
|
|
8000cb6: 370c adds r7, #12
|
|
8000cb8: 46bd mov sp, r7
|
|
8000cba: bc80 pop {r7}
|
|
8000cbc: 4770 bx lr
|
|
...
|
|
|
|
08000cc0 <TIMER_IF_Init>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions ---------------------------------------------------------*/
|
|
UTIL_TIMER_Status_t TIMER_IF_Init(void)
|
|
{
|
|
8000cc0: b580 push {r7, lr}
|
|
8000cc2: b082 sub sp, #8
|
|
8000cc4: af00 add r7, sp, #0
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
8000cc6: 2300 movs r3, #0
|
|
8000cc8: 71fb strb r3, [r7, #7]
|
|
/* USER CODE BEGIN TIMER_IF_Init */
|
|
|
|
/* USER CODE END TIMER_IF_Init */
|
|
if (RTC_Initialized == false)
|
|
8000cca: 4b14 ldr r3, [pc, #80] @ (8000d1c <TIMER_IF_Init+0x5c>)
|
|
8000ccc: 781b ldrb r3, [r3, #0]
|
|
8000cce: f083 0301 eor.w r3, r3, #1
|
|
8000cd2: b2db uxtb r3, r3
|
|
8000cd4: 2b00 cmp r3, #0
|
|
8000cd6: d01b beq.n 8000d10 <TIMER_IF_Init+0x50>
|
|
{
|
|
hrtc.IsEnabled.RtcFeatures = UINT32_MAX;
|
|
8000cd8: 4b11 ldr r3, [pc, #68] @ (8000d20 <TIMER_IF_Init+0x60>)
|
|
8000cda: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8000cde: 631a str r2, [r3, #48] @ 0x30
|
|
/*Init RTC*/
|
|
MX_RTC_Init();
|
|
8000ce0: f7ff fd40 bl 8000764 <MX_RTC_Init>
|
|
/*Stop Timer */
|
|
TIMER_IF_StopTimer();
|
|
8000ce4: f000 f856 bl 8000d94 <TIMER_IF_StopTimer>
|
|
/** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */
|
|
HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A);
|
|
8000ce8: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000cec: 480c ldr r0, [pc, #48] @ (8000d20 <TIMER_IF_Init+0x60>)
|
|
8000cee: f003 fac1 bl 8004274 <HAL_RTC_DeactivateAlarm>
|
|
/*overload RTC feature enable*/
|
|
hrtc.IsEnabled.RtcFeatures = UINT32_MAX;
|
|
8000cf2: 4b0b ldr r3, [pc, #44] @ (8000d20 <TIMER_IF_Init+0x60>)
|
|
8000cf4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8000cf8: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/*Enable Direct Read of the calendar registers (not through Shadow) */
|
|
HAL_RTCEx_EnableBypassShadow(&hrtc);
|
|
8000cfa: 4809 ldr r0, [pc, #36] @ (8000d20 <TIMER_IF_Init+0x60>)
|
|
8000cfc: f003 fbf8 bl 80044f0 <HAL_RTCEx_EnableBypassShadow>
|
|
/*Initialize MSB ticks*/
|
|
TIMER_IF_BkUp_Write_MSBticks(0);
|
|
8000d00: 2000 movs r0, #0
|
|
8000d02: f000 f9d3 bl 80010ac <TIMER_IF_BkUp_Write_MSBticks>
|
|
|
|
TIMER_IF_SetTimerContext();
|
|
8000d06: f000 f85f bl 8000dc8 <TIMER_IF_SetTimerContext>
|
|
|
|
/* Register a task to associate to UTIL_TIMER_Irq() interrupt */
|
|
UTIL_TIMER_IRQ_MAP_INIT();
|
|
|
|
RTC_Initialized = true;
|
|
8000d0a: 4b04 ldr r3, [pc, #16] @ (8000d1c <TIMER_IF_Init+0x5c>)
|
|
8000d0c: 2201 movs r2, #1
|
|
8000d0e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* USER CODE BEGIN TIMER_IF_Init_Last */
|
|
|
|
/* USER CODE END TIMER_IF_Init_Last */
|
|
return ret;
|
|
8000d10: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8000d12: 4618 mov r0, r3
|
|
8000d14: 3708 adds r7, #8
|
|
8000d16: 46bd mov sp, r7
|
|
8000d18: bd80 pop {r7, pc}
|
|
8000d1a: bf00 nop
|
|
8000d1c: 20000085 .word 0x20000085
|
|
8000d20: 20000040 .word 0x20000040
|
|
|
|
08000d24 <TIMER_IF_StartTimer>:
|
|
|
|
UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout)
|
|
{
|
|
8000d24: b580 push {r7, lr}
|
|
8000d26: b08e sub sp, #56 @ 0x38
|
|
8000d28: af00 add r7, sp, #0
|
|
8000d2a: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
8000d2c: 2300 movs r3, #0
|
|
8000d2e: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
/* USER CODE BEGIN TIMER_IF_StartTimer */
|
|
|
|
/* USER CODE END TIMER_IF_StartTimer */
|
|
RTC_AlarmTypeDef sAlarm = {0};
|
|
8000d32: f107 0308 add.w r3, r7, #8
|
|
8000d36: 222c movs r2, #44 @ 0x2c
|
|
8000d38: 2100 movs r1, #0
|
|
8000d3a: 4618 mov r0, r3
|
|
8000d3c: f00c fb9a bl 800d474 <memset>
|
|
/*Stop timer if one is already started*/
|
|
TIMER_IF_StopTimer();
|
|
8000d40: f000 f828 bl 8000d94 <TIMER_IF_StopTimer>
|
|
timeout += RtcTimerContext;
|
|
8000d44: 4b11 ldr r3, [pc, #68] @ (8000d8c <TIMER_IF_StartTimer+0x68>)
|
|
8000d46: 681b ldr r3, [r3, #0]
|
|
8000d48: 687a ldr r2, [r7, #4]
|
|
8000d4a: 4413 add r3, r2
|
|
8000d4c: 607b str r3, [r7, #4]
|
|
|
|
TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout);
|
|
/* starts timer*/
|
|
sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO;
|
|
8000d4e: 2300 movs r3, #0
|
|
8000d50: 627b str r3, [r7, #36] @ 0x24
|
|
sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout;
|
|
8000d52: 687b ldr r3, [r7, #4]
|
|
8000d54: 43db mvns r3, r3
|
|
8000d56: 60fb str r3, [r7, #12]
|
|
sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
|
|
8000d58: 2300 movs r3, #0
|
|
8000d5a: 61fb str r3, [r7, #28]
|
|
sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE;
|
|
8000d5c: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
8000d60: 623b str r3, [r7, #32]
|
|
sAlarm.Alarm = RTC_ALARM_A;
|
|
8000d62: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000d66: 633b str r3, [r7, #48] @ 0x30
|
|
if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
|
|
8000d68: f107 0308 add.w r3, r7, #8
|
|
8000d6c: 2201 movs r2, #1
|
|
8000d6e: 4619 mov r1, r3
|
|
8000d70: 4807 ldr r0, [pc, #28] @ (8000d90 <TIMER_IF_StartTimer+0x6c>)
|
|
8000d72: f003 f973 bl 800405c <HAL_RTC_SetAlarm_IT>
|
|
8000d76: 4603 mov r3, r0
|
|
8000d78: 2b00 cmp r3, #0
|
|
8000d7a: d001 beq.n 8000d80 <TIMER_IF_StartTimer+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8000d7c: f7ff fcc4 bl 8000708 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIMER_IF_StartTimer_Last */
|
|
|
|
/* USER CODE END TIMER_IF_StartTimer_Last */
|
|
return ret;
|
|
8000d80: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
}
|
|
8000d84: 4618 mov r0, r3
|
|
8000d86: 3738 adds r7, #56 @ 0x38
|
|
8000d88: 46bd mov sp, r7
|
|
8000d8a: bd80 pop {r7, pc}
|
|
8000d8c: 20000088 .word 0x20000088
|
|
8000d90: 20000040 .word 0x20000040
|
|
|
|
08000d94 <TIMER_IF_StopTimer>:
|
|
|
|
UTIL_TIMER_Status_t TIMER_IF_StopTimer(void)
|
|
{
|
|
8000d94: b580 push {r7, lr}
|
|
8000d96: b082 sub sp, #8
|
|
8000d98: af00 add r7, sp, #0
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
8000d9a: 2300 movs r3, #0
|
|
8000d9c: 71fb strb r3, [r7, #7]
|
|
/* USER CODE BEGIN TIMER_IF_StopTimer */
|
|
|
|
/* USER CODE END TIMER_IF_StopTimer */
|
|
/* Clear RTC Alarm Flag */
|
|
__HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF);
|
|
8000d9e: 4b08 ldr r3, [pc, #32] @ (8000dc0 <TIMER_IF_StopTimer+0x2c>)
|
|
8000da0: 2201 movs r2, #1
|
|
8000da2: 65da str r2, [r3, #92] @ 0x5c
|
|
/* Disable the Alarm A interrupt */
|
|
HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A);
|
|
8000da4: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000da8: 4806 ldr r0, [pc, #24] @ (8000dc4 <TIMER_IF_StopTimer+0x30>)
|
|
8000daa: f003 fa63 bl 8004274 <HAL_RTC_DeactivateAlarm>
|
|
/*overload RTC feature enable*/
|
|
hrtc.IsEnabled.RtcFeatures = UINT32_MAX;
|
|
8000dae: 4b05 ldr r3, [pc, #20] @ (8000dc4 <TIMER_IF_StopTimer+0x30>)
|
|
8000db0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8000db4: 631a str r2, [r3, #48] @ 0x30
|
|
/* USER CODE BEGIN TIMER_IF_StopTimer_Last */
|
|
|
|
/* USER CODE END TIMER_IF_StopTimer_Last */
|
|
return ret;
|
|
8000db6: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8000db8: 4618 mov r0, r3
|
|
8000dba: 3708 adds r7, #8
|
|
8000dbc: 46bd mov sp, r7
|
|
8000dbe: bd80 pop {r7, pc}
|
|
8000dc0: 40002800 .word 0x40002800
|
|
8000dc4: 20000040 .word 0x20000040
|
|
|
|
08000dc8 <TIMER_IF_SetTimerContext>:
|
|
|
|
uint32_t TIMER_IF_SetTimerContext(void)
|
|
{
|
|
8000dc8: b580 push {r7, lr}
|
|
8000dca: af00 add r7, sp, #0
|
|
/*store time context*/
|
|
RtcTimerContext = GetTimerTicks();
|
|
8000dcc: f000 f98e bl 80010ec <GetTimerTicks>
|
|
8000dd0: 4603 mov r3, r0
|
|
8000dd2: 4a03 ldr r2, [pc, #12] @ (8000de0 <TIMER_IF_SetTimerContext+0x18>)
|
|
8000dd4: 6013 str r3, [r2, #0]
|
|
|
|
/* USER CODE END TIMER_IF_SetTimerContext */
|
|
|
|
TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext);
|
|
/*return time context*/
|
|
return RtcTimerContext;
|
|
8000dd6: 4b02 ldr r3, [pc, #8] @ (8000de0 <TIMER_IF_SetTimerContext+0x18>)
|
|
8000dd8: 681b ldr r3, [r3, #0]
|
|
}
|
|
8000dda: 4618 mov r0, r3
|
|
8000ddc: bd80 pop {r7, pc}
|
|
8000dde: bf00 nop
|
|
8000de0: 20000088 .word 0x20000088
|
|
|
|
08000de4 <TIMER_IF_GetTimerContext>:
|
|
|
|
uint32_t TIMER_IF_GetTimerContext(void)
|
|
{
|
|
8000de4: b480 push {r7}
|
|
8000de6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END TIMER_IF_GetTimerContext */
|
|
|
|
TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext);
|
|
/*return time context*/
|
|
return RtcTimerContext;
|
|
8000de8: 4b02 ldr r3, [pc, #8] @ (8000df4 <TIMER_IF_GetTimerContext+0x10>)
|
|
8000dea: 681b ldr r3, [r3, #0]
|
|
}
|
|
8000dec: 4618 mov r0, r3
|
|
8000dee: 46bd mov sp, r7
|
|
8000df0: bc80 pop {r7}
|
|
8000df2: 4770 bx lr
|
|
8000df4: 20000088 .word 0x20000088
|
|
|
|
08000df8 <TIMER_IF_GetTimerElapsedTime>:
|
|
|
|
uint32_t TIMER_IF_GetTimerElapsedTime(void)
|
|
{
|
|
8000df8: b580 push {r7, lr}
|
|
8000dfa: b082 sub sp, #8
|
|
8000dfc: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
8000dfe: 2300 movs r3, #0
|
|
8000e00: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */
|
|
|
|
/* USER CODE END TIMER_IF_GetTimerElapsedTime */
|
|
ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext));
|
|
8000e02: f000 f973 bl 80010ec <GetTimerTicks>
|
|
8000e06: 4602 mov r2, r0
|
|
8000e08: 4b04 ldr r3, [pc, #16] @ (8000e1c <TIMER_IF_GetTimerElapsedTime+0x24>)
|
|
8000e0a: 681b ldr r3, [r3, #0]
|
|
8000e0c: 1ad3 subs r3, r2, r3
|
|
8000e0e: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */
|
|
|
|
/* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */
|
|
return ret;
|
|
8000e10: 687b ldr r3, [r7, #4]
|
|
}
|
|
8000e12: 4618 mov r0, r3
|
|
8000e14: 3708 adds r7, #8
|
|
8000e16: 46bd mov sp, r7
|
|
8000e18: bd80 pop {r7, pc}
|
|
8000e1a: bf00 nop
|
|
8000e1c: 20000088 .word 0x20000088
|
|
|
|
08000e20 <TIMER_IF_GetTimerValue>:
|
|
|
|
uint32_t TIMER_IF_GetTimerValue(void)
|
|
{
|
|
8000e20: b580 push {r7, lr}
|
|
8000e22: b082 sub sp, #8
|
|
8000e24: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
8000e26: 2300 movs r3, #0
|
|
8000e28: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_GetTimerValue */
|
|
|
|
/* USER CODE END TIMER_IF_GetTimerValue */
|
|
if (RTC_Initialized == true)
|
|
8000e2a: 4b06 ldr r3, [pc, #24] @ (8000e44 <TIMER_IF_GetTimerValue+0x24>)
|
|
8000e2c: 781b ldrb r3, [r3, #0]
|
|
8000e2e: 2b00 cmp r3, #0
|
|
8000e30: d002 beq.n 8000e38 <TIMER_IF_GetTimerValue+0x18>
|
|
{
|
|
ret = GetTimerTicks();
|
|
8000e32: f000 f95b bl 80010ec <GetTimerTicks>
|
|
8000e36: 6078 str r0, [r7, #4]
|
|
}
|
|
/* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */
|
|
|
|
/* USER CODE END TIMER_IF_GetTimerValue_Last */
|
|
return ret;
|
|
8000e38: 687b ldr r3, [r7, #4]
|
|
}
|
|
8000e3a: 4618 mov r0, r3
|
|
8000e3c: 3708 adds r7, #8
|
|
8000e3e: 46bd mov sp, r7
|
|
8000e40: bd80 pop {r7, pc}
|
|
8000e42: bf00 nop
|
|
8000e44: 20000085 .word 0x20000085
|
|
|
|
08000e48 <TIMER_IF_GetMinimumTimeout>:
|
|
|
|
uint32_t TIMER_IF_GetMinimumTimeout(void)
|
|
{
|
|
8000e48: b480 push {r7}
|
|
8000e4a: b083 sub sp, #12
|
|
8000e4c: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
8000e4e: 2300 movs r3, #0
|
|
8000e50: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */
|
|
|
|
/* USER CODE END TIMER_IF_GetMinimumTimeout */
|
|
ret = (MIN_ALARM_DELAY);
|
|
8000e52: 2303 movs r3, #3
|
|
8000e54: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */
|
|
|
|
/* USER CODE END TIMER_IF_GetMinimumTimeout_Last */
|
|
return ret;
|
|
8000e56: 687b ldr r3, [r7, #4]
|
|
}
|
|
8000e58: 4618 mov r0, r3
|
|
8000e5a: 370c adds r7, #12
|
|
8000e5c: 46bd mov sp, r7
|
|
8000e5e: bc80 pop {r7}
|
|
8000e60: 4770 bx lr
|
|
|
|
08000e62 <TIMER_IF_Convert_ms2Tick>:
|
|
|
|
uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec)
|
|
{
|
|
8000e62: b5b0 push {r4, r5, r7, lr}
|
|
8000e64: b084 sub sp, #16
|
|
8000e66: af00 add r7, sp, #0
|
|
8000e68: 6078 str r0, [r7, #4]
|
|
uint32_t ret = 0;
|
|
8000e6a: 2100 movs r1, #0
|
|
8000e6c: 60f9 str r1, [r7, #12]
|
|
/* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */
|
|
|
|
/* USER CODE END TIMER_IF_Convert_ms2Tick */
|
|
ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000));
|
|
8000e6e: 6879 ldr r1, [r7, #4]
|
|
8000e70: 2000 movs r0, #0
|
|
8000e72: 460a mov r2, r1
|
|
8000e74: 4603 mov r3, r0
|
|
8000e76: 0d95 lsrs r5, r2, #22
|
|
8000e78: 0294 lsls r4, r2, #10
|
|
8000e7a: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8000e7e: f04f 0300 mov.w r3, #0
|
|
8000e82: 4620 mov r0, r4
|
|
8000e84: 4629 mov r1, r5
|
|
8000e86: f7ff f97f bl 8000188 <__aeabi_uldivmod>
|
|
8000e8a: 4602 mov r2, r0
|
|
8000e8c: 460b mov r3, r1
|
|
8000e8e: 4613 mov r3, r2
|
|
8000e90: 60fb str r3, [r7, #12]
|
|
/* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */
|
|
|
|
/* USER CODE END TIMER_IF_Convert_ms2Tick_Last */
|
|
return ret;
|
|
8000e92: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000e94: 4618 mov r0, r3
|
|
8000e96: 3710 adds r7, #16
|
|
8000e98: 46bd mov sp, r7
|
|
8000e9a: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
08000e9c <TIMER_IF_Convert_Tick2ms>:
|
|
|
|
uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick)
|
|
{
|
|
8000e9c: e92d 0fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp}
|
|
8000ea0: b085 sub sp, #20
|
|
8000ea2: af00 add r7, sp, #0
|
|
8000ea4: 6078 str r0, [r7, #4]
|
|
uint32_t ret = 0;
|
|
8000ea6: 2100 movs r1, #0
|
|
8000ea8: 60f9 str r1, [r7, #12]
|
|
/* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */
|
|
|
|
/* USER CODE END TIMER_IF_Convert_Tick2ms */
|
|
ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S));
|
|
8000eaa: 6879 ldr r1, [r7, #4]
|
|
8000eac: 2000 movs r0, #0
|
|
8000eae: 460c mov r4, r1
|
|
8000eb0: 4605 mov r5, r0
|
|
8000eb2: 4620 mov r0, r4
|
|
8000eb4: 4629 mov r1, r5
|
|
8000eb6: f04f 0a00 mov.w sl, #0
|
|
8000eba: f04f 0b00 mov.w fp, #0
|
|
8000ebe: ea4f 1b41 mov.w fp, r1, lsl #5
|
|
8000ec2: ea4b 6bd0 orr.w fp, fp, r0, lsr #27
|
|
8000ec6: ea4f 1a40 mov.w sl, r0, lsl #5
|
|
8000eca: 4650 mov r0, sl
|
|
8000ecc: 4659 mov r1, fp
|
|
8000ece: 1b02 subs r2, r0, r4
|
|
8000ed0: eb61 0305 sbc.w r3, r1, r5
|
|
8000ed4: f04f 0000 mov.w r0, #0
|
|
8000ed8: f04f 0100 mov.w r1, #0
|
|
8000edc: 0099 lsls r1, r3, #2
|
|
8000ede: ea41 7192 orr.w r1, r1, r2, lsr #30
|
|
8000ee2: 0090 lsls r0, r2, #2
|
|
8000ee4: 4602 mov r2, r0
|
|
8000ee6: 460b mov r3, r1
|
|
8000ee8: eb12 0804 adds.w r8, r2, r4
|
|
8000eec: eb43 0905 adc.w r9, r3, r5
|
|
8000ef0: f04f 0200 mov.w r2, #0
|
|
8000ef4: f04f 0300 mov.w r3, #0
|
|
8000ef8: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8000efc: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8000f00: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8000f04: 4690 mov r8, r2
|
|
8000f06: 4699 mov r9, r3
|
|
8000f08: 4640 mov r0, r8
|
|
8000f0a: 4649 mov r1, r9
|
|
8000f0c: f04f 0200 mov.w r2, #0
|
|
8000f10: f04f 0300 mov.w r3, #0
|
|
8000f14: 0a82 lsrs r2, r0, #10
|
|
8000f16: ea42 5281 orr.w r2, r2, r1, lsl #22
|
|
8000f1a: 0a8b lsrs r3, r1, #10
|
|
8000f1c: 4613 mov r3, r2
|
|
8000f1e: 60fb str r3, [r7, #12]
|
|
/* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */
|
|
|
|
/* USER CODE END TIMER_IF_Convert_Tick2ms_Last */
|
|
return ret;
|
|
8000f20: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000f22: 4618 mov r0, r3
|
|
8000f24: 3714 adds r7, #20
|
|
8000f26: 46bd mov sp, r7
|
|
8000f28: e8bd 0fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp}
|
|
8000f2c: 4770 bx lr
|
|
|
|
08000f2e <TIMER_IF_DelayMs>:
|
|
|
|
void TIMER_IF_DelayMs(uint32_t delay)
|
|
{
|
|
8000f2e: b580 push {r7, lr}
|
|
8000f30: b084 sub sp, #16
|
|
8000f32: af00 add r7, sp, #0
|
|
8000f34: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_DelayMs */
|
|
|
|
/* USER CODE END TIMER_IF_DelayMs */
|
|
uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay);
|
|
8000f36: 6878 ldr r0, [r7, #4]
|
|
8000f38: f7ff ff93 bl 8000e62 <TIMER_IF_Convert_ms2Tick>
|
|
8000f3c: 60f8 str r0, [r7, #12]
|
|
uint32_t timeout = GetTimerTicks();
|
|
8000f3e: f000 f8d5 bl 80010ec <GetTimerTicks>
|
|
8000f42: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait delay ms */
|
|
while (((GetTimerTicks() - timeout)) < delayTicks)
|
|
8000f44: e000 b.n 8000f48 <TIMER_IF_DelayMs+0x1a>
|
|
{
|
|
__NOP();
|
|
8000f46: bf00 nop
|
|
while (((GetTimerTicks() - timeout)) < delayTicks)
|
|
8000f48: f000 f8d0 bl 80010ec <GetTimerTicks>
|
|
8000f4c: 4602 mov r2, r0
|
|
8000f4e: 68bb ldr r3, [r7, #8]
|
|
8000f50: 1ad3 subs r3, r2, r3
|
|
8000f52: 68fa ldr r2, [r7, #12]
|
|
8000f54: 429a cmp r2, r3
|
|
8000f56: d8f6 bhi.n 8000f46 <TIMER_IF_DelayMs+0x18>
|
|
}
|
|
/* USER CODE BEGIN TIMER_IF_DelayMs_Last */
|
|
|
|
/* USER CODE END TIMER_IF_DelayMs_Last */
|
|
}
|
|
8000f58: bf00 nop
|
|
8000f5a: bf00 nop
|
|
8000f5c: 3710 adds r7, #16
|
|
8000f5e: 46bd mov sp, r7
|
|
8000f60: bd80 pop {r7, pc}
|
|
|
|
08000f62 <HAL_RTC_AlarmAEventCallback>:
|
|
|
|
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8000f62: b580 push {r7, lr}
|
|
8000f64: b082 sub sp, #8
|
|
8000f66: af00 add r7, sp, #0
|
|
8000f68: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_RTC_AlarmAEventCallback */
|
|
|
|
/* USER CODE END HAL_RTC_AlarmAEventCallback */
|
|
UTIL_TIMER_IRQ_MAP_PROCESS();
|
|
8000f6a: f00b fead bl 800ccc8 <UTIL_TIMER_IRQ_Handler>
|
|
/* USER CODE BEGIN HAL_RTC_AlarmAEventCallback_Last */
|
|
|
|
/* USER CODE END HAL_RTC_AlarmAEventCallback_Last */
|
|
}
|
|
8000f6e: bf00 nop
|
|
8000f70: 3708 adds r7, #8
|
|
8000f72: 46bd mov sp, r7
|
|
8000f74: bd80 pop {r7, pc}
|
|
|
|
08000f76 <HAL_RTCEx_SSRUEventCallback>:
|
|
|
|
void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8000f76: b580 push {r7, lr}
|
|
8000f78: b084 sub sp, #16
|
|
8000f7a: af00 add r7, sp, #0
|
|
8000f7c: 6078 str r0, [r7, #4]
|
|
|
|
/* USER CODE END HAL_RTCEx_SSRUEventCallback */
|
|
/*called every 48 days with 1024 ticks per seconds*/
|
|
TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks());
|
|
/*Increment MSBticks*/
|
|
uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks();
|
|
8000f7e: f000 f8a5 bl 80010cc <TIMER_IF_BkUp_Read_MSBticks>
|
|
8000f82: 60f8 str r0, [r7, #12]
|
|
TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1);
|
|
8000f84: 68fb ldr r3, [r7, #12]
|
|
8000f86: 3301 adds r3, #1
|
|
8000f88: 4618 mov r0, r3
|
|
8000f8a: f000 f88f bl 80010ac <TIMER_IF_BkUp_Write_MSBticks>
|
|
/* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */
|
|
|
|
/* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */
|
|
}
|
|
8000f8e: bf00 nop
|
|
8000f90: 3710 adds r7, #16
|
|
8000f92: 46bd mov sp, r7
|
|
8000f94: bd80 pop {r7, pc}
|
|
|
|
08000f96 <TIMER_IF_GetTime>:
|
|
|
|
uint32_t TIMER_IF_GetTime(uint16_t *mSeconds)
|
|
{
|
|
8000f96: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8000f9a: b08c sub sp, #48 @ 0x30
|
|
8000f9c: af00 add r7, sp, #0
|
|
8000f9e: 6178 str r0, [r7, #20]
|
|
uint32_t seconds = 0;
|
|
8000fa0: 2300 movs r3, #0
|
|
8000fa2: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* USER CODE BEGIN TIMER_IF_GetTime */
|
|
|
|
/* USER CODE END TIMER_IF_GetTime */
|
|
uint64_t ticks;
|
|
uint32_t timerValueLsb = GetTimerTicks();
|
|
8000fa4: f000 f8a2 bl 80010ec <GetTimerTicks>
|
|
8000fa8: 62b8 str r0, [r7, #40] @ 0x28
|
|
uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks();
|
|
8000faa: f000 f88f bl 80010cc <TIMER_IF_BkUp_Read_MSBticks>
|
|
8000fae: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb;
|
|
8000fb0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000fb2: 2200 movs r2, #0
|
|
8000fb4: 60bb str r3, [r7, #8]
|
|
8000fb6: 60fa str r2, [r7, #12]
|
|
8000fb8: f04f 0200 mov.w r2, #0
|
|
8000fbc: f04f 0300 mov.w r3, #0
|
|
8000fc0: 68b9 ldr r1, [r7, #8]
|
|
8000fc2: 000b movs r3, r1
|
|
8000fc4: 2200 movs r2, #0
|
|
8000fc6: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8000fc8: 2000 movs r0, #0
|
|
8000fca: 460c mov r4, r1
|
|
8000fcc: 4605 mov r5, r0
|
|
8000fce: eb12 0804 adds.w r8, r2, r4
|
|
8000fd2: eb43 0905 adc.w r9, r3, r5
|
|
8000fd6: e9c7 8906 strd r8, r9, [r7, #24]
|
|
|
|
seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S);
|
|
8000fda: e9d7 0106 ldrd r0, r1, [r7, #24]
|
|
8000fde: f04f 0200 mov.w r2, #0
|
|
8000fe2: f04f 0300 mov.w r3, #0
|
|
8000fe6: 0a82 lsrs r2, r0, #10
|
|
8000fe8: ea42 5281 orr.w r2, r2, r1, lsl #22
|
|
8000fec: 0a8b lsrs r3, r1, #10
|
|
8000fee: 4613 mov r3, r2
|
|
8000ff0: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
ticks = (uint32_t) ticks & RTC_PREDIV_S;
|
|
8000ff2: 69bb ldr r3, [r7, #24]
|
|
8000ff4: 2200 movs r2, #0
|
|
8000ff6: 603b str r3, [r7, #0]
|
|
8000ff8: 607a str r2, [r7, #4]
|
|
8000ffa: 683b ldr r3, [r7, #0]
|
|
8000ffc: f3c3 0a09 ubfx sl, r3, #0, #10
|
|
8001000: f04f 0b00 mov.w fp, #0
|
|
8001004: e9c7 ab06 strd sl, fp, [r7, #24]
|
|
|
|
*mSeconds = TIMER_IF_Convert_Tick2ms(ticks);
|
|
8001008: 69bb ldr r3, [r7, #24]
|
|
800100a: 4618 mov r0, r3
|
|
800100c: f7ff ff46 bl 8000e9c <TIMER_IF_Convert_Tick2ms>
|
|
8001010: 4603 mov r3, r0
|
|
8001012: b29a uxth r2, r3
|
|
8001014: 697b ldr r3, [r7, #20]
|
|
8001016: 801a strh r2, [r3, #0]
|
|
|
|
/* USER CODE BEGIN TIMER_IF_GetTime_Last */
|
|
|
|
/* USER CODE END TIMER_IF_GetTime_Last */
|
|
return seconds;
|
|
8001018: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
800101a: 4618 mov r0, r3
|
|
800101c: 3730 adds r7, #48 @ 0x30
|
|
800101e: 46bd mov sp, r7
|
|
8001020: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
|
|
08001024 <TIMER_IF_BkUp_Write_Seconds>:
|
|
|
|
void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds)
|
|
{
|
|
8001024: b580 push {r7, lr}
|
|
8001026: b082 sub sp, #8
|
|
8001028: af00 add r7, sp, #0
|
|
800102a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_Seconds */
|
|
HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds);
|
|
800102c: 687a ldr r2, [r7, #4]
|
|
800102e: 2100 movs r1, #0
|
|
8001030: 4803 ldr r0, [pc, #12] @ (8001040 <TIMER_IF_BkUp_Write_Seconds+0x1c>)
|
|
8001032: f003 faef bl 8004614 <HAL_RTCEx_BKUPWrite>
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */
|
|
}
|
|
8001036: bf00 nop
|
|
8001038: 3708 adds r7, #8
|
|
800103a: 46bd mov sp, r7
|
|
800103c: bd80 pop {r7, pc}
|
|
800103e: bf00 nop
|
|
8001040: 20000040 .word 0x20000040
|
|
|
|
08001044 <TIMER_IF_BkUp_Write_SubSeconds>:
|
|
|
|
void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds)
|
|
{
|
|
8001044: b580 push {r7, lr}
|
|
8001046: b082 sub sp, #8
|
|
8001048: af00 add r7, sp, #0
|
|
800104a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */
|
|
HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds);
|
|
800104c: 687a ldr r2, [r7, #4]
|
|
800104e: 2101 movs r1, #1
|
|
8001050: 4803 ldr r0, [pc, #12] @ (8001060 <TIMER_IF_BkUp_Write_SubSeconds+0x1c>)
|
|
8001052: f003 fadf bl 8004614 <HAL_RTCEx_BKUPWrite>
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */
|
|
}
|
|
8001056: bf00 nop
|
|
8001058: 3708 adds r7, #8
|
|
800105a: 46bd mov sp, r7
|
|
800105c: bd80 pop {r7, pc}
|
|
800105e: bf00 nop
|
|
8001060: 20000040 .word 0x20000040
|
|
|
|
08001064 <TIMER_IF_BkUp_Read_Seconds>:
|
|
|
|
uint32_t TIMER_IF_BkUp_Read_Seconds(void)
|
|
{
|
|
8001064: b580 push {r7, lr}
|
|
8001066: b082 sub sp, #8
|
|
8001068: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
800106a: 2300 movs r3, #0
|
|
800106c: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_Seconds */
|
|
ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS);
|
|
800106e: 2100 movs r1, #0
|
|
8001070: 4804 ldr r0, [pc, #16] @ (8001084 <TIMER_IF_BkUp_Read_Seconds+0x20>)
|
|
8001072: f003 fae7 bl 8004644 <HAL_RTCEx_BKUPRead>
|
|
8001076: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */
|
|
return ret;
|
|
8001078: 687b ldr r3, [r7, #4]
|
|
}
|
|
800107a: 4618 mov r0, r3
|
|
800107c: 3708 adds r7, #8
|
|
800107e: 46bd mov sp, r7
|
|
8001080: bd80 pop {r7, pc}
|
|
8001082: bf00 nop
|
|
8001084: 20000040 .word 0x20000040
|
|
|
|
08001088 <TIMER_IF_BkUp_Read_SubSeconds>:
|
|
|
|
uint32_t TIMER_IF_BkUp_Read_SubSeconds(void)
|
|
{
|
|
8001088: b580 push {r7, lr}
|
|
800108a: b082 sub sp, #8
|
|
800108c: af00 add r7, sp, #0
|
|
uint32_t ret = 0;
|
|
800108e: 2300 movs r3, #0
|
|
8001090: 607b str r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */
|
|
ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS);
|
|
8001092: 2101 movs r1, #1
|
|
8001094: 4804 ldr r0, [pc, #16] @ (80010a8 <TIMER_IF_BkUp_Read_SubSeconds+0x20>)
|
|
8001096: f003 fad5 bl 8004644 <HAL_RTCEx_BKUPRead>
|
|
800109a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */
|
|
return ret;
|
|
800109c: 687b ldr r3, [r7, #4]
|
|
}
|
|
800109e: 4618 mov r0, r3
|
|
80010a0: 3708 adds r7, #8
|
|
80010a2: 46bd mov sp, r7
|
|
80010a4: bd80 pop {r7, pc}
|
|
80010a6: bf00 nop
|
|
80010a8: 20000040 .word 0x20000040
|
|
|
|
080010ac <TIMER_IF_BkUp_Write_MSBticks>:
|
|
|
|
/* USER CODE END EF */
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks)
|
|
{
|
|
80010ac: b580 push {r7, lr}
|
|
80010ae: b082 sub sp, #8
|
|
80010b0: af00 add r7, sp, #0
|
|
80010b2: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_MSBticks */
|
|
HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks);
|
|
80010b4: 687a ldr r2, [r7, #4]
|
|
80010b6: 2102 movs r1, #2
|
|
80010b8: 4803 ldr r0, [pc, #12] @ (80010c8 <TIMER_IF_BkUp_Write_MSBticks+0x1c>)
|
|
80010ba: f003 faab bl 8004614 <HAL_RTCEx_BKUPWrite>
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */
|
|
}
|
|
80010be: bf00 nop
|
|
80010c0: 3708 adds r7, #8
|
|
80010c2: 46bd mov sp, r7
|
|
80010c4: bd80 pop {r7, pc}
|
|
80010c6: bf00 nop
|
|
80010c8: 20000040 .word 0x20000040
|
|
|
|
080010cc <TIMER_IF_BkUp_Read_MSBticks>:
|
|
|
|
static uint32_t TIMER_IF_BkUp_Read_MSBticks(void)
|
|
{
|
|
80010cc: b580 push {r7, lr}
|
|
80010ce: b082 sub sp, #8
|
|
80010d0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_MSBticks */
|
|
uint32_t MSBticks;
|
|
MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS);
|
|
80010d2: 2102 movs r1, #2
|
|
80010d4: 4804 ldr r0, [pc, #16] @ (80010e8 <TIMER_IF_BkUp_Read_MSBticks+0x1c>)
|
|
80010d6: f003 fab5 bl 8004644 <HAL_RTCEx_BKUPRead>
|
|
80010da: 6078 str r0, [r7, #4]
|
|
return MSBticks;
|
|
80010dc: 687b ldr r3, [r7, #4]
|
|
/* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */
|
|
|
|
/* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */
|
|
}
|
|
80010de: 4618 mov r0, r3
|
|
80010e0: 3708 adds r7, #8
|
|
80010e2: 46bd mov sp, r7
|
|
80010e4: bd80 pop {r7, pc}
|
|
80010e6: bf00 nop
|
|
80010e8: 20000040 .word 0x20000040
|
|
|
|
080010ec <GetTimerTicks>:
|
|
|
|
static inline uint32_t GetTimerTicks(void)
|
|
{
|
|
80010ec: b580 push {r7, lr}
|
|
80010ee: b082 sub sp, #8
|
|
80010f0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN GetTimerTicks */
|
|
|
|
/* USER CODE END GetTimerTicks */
|
|
uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC);
|
|
80010f2: 480b ldr r0, [pc, #44] @ (8001120 <GetTimerTicks+0x34>)
|
|
80010f4: f7ff fdd8 bl 8000ca8 <LL_RTC_TIME_GetSubSecond>
|
|
80010f8: 6078 str r0, [r7, #4]
|
|
/* read twice to make sure value it valid*/
|
|
while (ssr != LL_RTC_TIME_GetSubSecond(RTC))
|
|
80010fa: e003 b.n 8001104 <GetTimerTicks+0x18>
|
|
{
|
|
ssr = LL_RTC_TIME_GetSubSecond(RTC);
|
|
80010fc: 4808 ldr r0, [pc, #32] @ (8001120 <GetTimerTicks+0x34>)
|
|
80010fe: f7ff fdd3 bl 8000ca8 <LL_RTC_TIME_GetSubSecond>
|
|
8001102: 6078 str r0, [r7, #4]
|
|
while (ssr != LL_RTC_TIME_GetSubSecond(RTC))
|
|
8001104: 4806 ldr r0, [pc, #24] @ (8001120 <GetTimerTicks+0x34>)
|
|
8001106: f7ff fdcf bl 8000ca8 <LL_RTC_TIME_GetSubSecond>
|
|
800110a: 4602 mov r2, r0
|
|
800110c: 687b ldr r3, [r7, #4]
|
|
800110e: 4293 cmp r3, r2
|
|
8001110: d1f4 bne.n 80010fc <GetTimerTicks+0x10>
|
|
}
|
|
return UINT32_MAX - ssr;
|
|
8001112: 687b ldr r3, [r7, #4]
|
|
8001114: 43db mvns r3, r3
|
|
/* USER CODE BEGIN GetTimerTicks_Last */
|
|
|
|
/* USER CODE END GetTimerTicks_Last */
|
|
}
|
|
8001116: 4618 mov r0, r3
|
|
8001118: 3708 adds r7, #8
|
|
800111a: 46bd mov sp, r7
|
|
800111c: bd80 pop {r7, pc}
|
|
800111e: bf00 nop
|
|
8001120: 40002800 .word 0x40002800
|
|
|
|
08001124 <LL_AHB2_GRP1_EnableClock>:
|
|
{
|
|
8001124: b480 push {r7}
|
|
8001126: b085 sub sp, #20
|
|
8001128: af00 add r7, sp, #0
|
|
800112a: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
800112c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001130: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8001132: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8001136: 687b ldr r3, [r7, #4]
|
|
8001138: 4313 orrs r3, r2
|
|
800113a: 64cb str r3, [r1, #76] @ 0x4c
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
800113c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001140: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8001142: 687b ldr r3, [r7, #4]
|
|
8001144: 4013 ands r3, r2
|
|
8001146: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8001148: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800114a: bf00 nop
|
|
800114c: 3714 adds r7, #20
|
|
800114e: 46bd mov sp, r7
|
|
8001150: bc80 pop {r7}
|
|
8001152: 4770 bx lr
|
|
|
|
08001154 <LL_APB1_GRP1_EnableClock>:
|
|
{
|
|
8001154: b480 push {r7}
|
|
8001156: b085 sub sp, #20
|
|
8001158: af00 add r7, sp, #0
|
|
800115a: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
800115c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001160: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8001162: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8001166: 687b ldr r3, [r7, #4]
|
|
8001168: 4313 orrs r3, r2
|
|
800116a: 658b str r3, [r1, #88] @ 0x58
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
800116c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001170: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8001172: 687b ldr r3, [r7, #4]
|
|
8001174: 4013 ands r3, r2
|
|
8001176: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8001178: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800117a: bf00 nop
|
|
800117c: 3714 adds r7, #20
|
|
800117e: 46bd mov sp, r7
|
|
8001180: bc80 pop {r7}
|
|
8001182: 4770 bx lr
|
|
|
|
08001184 <LL_APB1_GRP1_DisableClock>:
|
|
{
|
|
8001184: b480 push {r7}
|
|
8001186: b083 sub sp, #12
|
|
8001188: af00 add r7, sp, #0
|
|
800118a: 6078 str r0, [r7, #4]
|
|
CLEAR_BIT(RCC->APB1ENR1, Periphs);
|
|
800118c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001190: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8001192: 687b ldr r3, [r7, #4]
|
|
8001194: 43db mvns r3, r3
|
|
8001196: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800119a: 4013 ands r3, r2
|
|
800119c: 658b str r3, [r1, #88] @ 0x58
|
|
}
|
|
800119e: bf00 nop
|
|
80011a0: 370c adds r7, #12
|
|
80011a2: 46bd mov sp, r7
|
|
80011a4: bc80 pop {r7}
|
|
80011a6: 4770 bx lr
|
|
|
|
080011a8 <MX_USART2_UART_Init>:
|
|
DMA_HandleTypeDef hdma_usart2_tx;
|
|
|
|
/* USART2 init function */
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
{
|
|
80011a8: b580 push {r7, lr}
|
|
80011aa: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80011ac: 4b22 ldr r3, [pc, #136] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011ae: 4a23 ldr r2, [pc, #140] @ (800123c <MX_USART2_UART_Init+0x94>)
|
|
80011b0: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80011b2: 4b21 ldr r3, [pc, #132] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011b4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80011b8: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80011ba: 4b1f ldr r3, [pc, #124] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011bc: 2200 movs r2, #0
|
|
80011be: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
80011c0: 4b1d ldr r3, [pc, #116] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011c2: 2200 movs r2, #0
|
|
80011c4: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
80011c6: 4b1c ldr r3, [pc, #112] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011c8: 2200 movs r2, #0
|
|
80011ca: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
80011cc: 4b1a ldr r3, [pc, #104] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011ce: 220c movs r2, #12
|
|
80011d0: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80011d2: 4b19 ldr r3, [pc, #100] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011d4: 2200 movs r2, #0
|
|
80011d6: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80011d8: 4b17 ldr r3, [pc, #92] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011da: 2200 movs r2, #0
|
|
80011dc: 61da str r2, [r3, #28]
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
80011de: 4b16 ldr r3, [pc, #88] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011e0: 2200 movs r2, #0
|
|
80011e2: 621a str r2, [r3, #32]
|
|
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
|
80011e4: 4b14 ldr r3, [pc, #80] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011e6: 2200 movs r2, #0
|
|
80011e8: 625a str r2, [r3, #36] @ 0x24
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
80011ea: 4b13 ldr r3, [pc, #76] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011ec: 2200 movs r2, #0
|
|
80011ee: 629a str r2, [r3, #40] @ 0x28
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
80011f0: 4811 ldr r0, [pc, #68] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
80011f2: f003 ff2a bl 800504a <HAL_UART_Init>
|
|
80011f6: 4603 mov r3, r0
|
|
80011f8: 2b00 cmp r3, #0
|
|
80011fa: d001 beq.n 8001200 <MX_USART2_UART_Init+0x58>
|
|
{
|
|
Error_Handler();
|
|
80011fc: f7ff fa84 bl 8000708 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8001200: 2100 movs r1, #0
|
|
8001202: 480d ldr r0, [pc, #52] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
8001204: f006 f85b bl 80072be <HAL_UARTEx_SetTxFifoThreshold>
|
|
8001208: 4603 mov r3, r0
|
|
800120a: 2b00 cmp r3, #0
|
|
800120c: d001 beq.n 8001212 <MX_USART2_UART_Init+0x6a>
|
|
{
|
|
Error_Handler();
|
|
800120e: f7ff fa7b bl 8000708 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8001212: 2100 movs r1, #0
|
|
8001214: 4808 ldr r0, [pc, #32] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
8001216: f006 f890 bl 800733a <HAL_UARTEx_SetRxFifoThreshold>
|
|
800121a: 4603 mov r3, r0
|
|
800121c: 2b00 cmp r3, #0
|
|
800121e: d001 beq.n 8001224 <MX_USART2_UART_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8001220: f7ff fa72 bl 8000708 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK)
|
|
8001224: 4804 ldr r0, [pc, #16] @ (8001238 <MX_USART2_UART_Init+0x90>)
|
|
8001226: f006 f80f bl 8007248 <HAL_UARTEx_EnableFifoMode>
|
|
800122a: 4603 mov r3, r0
|
|
800122c: 2b00 cmp r3, #0
|
|
800122e: d001 beq.n 8001234 <MX_USART2_UART_Init+0x8c>
|
|
{
|
|
Error_Handler();
|
|
8001230: f7ff fa6a bl 8000708 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8001234: bf00 nop
|
|
8001236: bd80 pop {r7, pc}
|
|
8001238: 2000008c .word 0x2000008c
|
|
800123c: 40004400 .word 0x40004400
|
|
|
|
08001240 <HAL_UART_MspInit>:
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8001240: b580 push {r7, lr}
|
|
8001242: b096 sub sp, #88 @ 0x58
|
|
8001244: af00 add r7, sp, #0
|
|
8001246: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001248: f107 0344 add.w r3, r7, #68 @ 0x44
|
|
800124c: 2200 movs r2, #0
|
|
800124e: 601a str r2, [r3, #0]
|
|
8001250: 605a str r2, [r3, #4]
|
|
8001252: 609a str r2, [r3, #8]
|
|
8001254: 60da str r2, [r3, #12]
|
|
8001256: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8001258: f107 030c add.w r3, r7, #12
|
|
800125c: 2238 movs r2, #56 @ 0x38
|
|
800125e: 2100 movs r1, #0
|
|
8001260: 4618 mov r0, r3
|
|
8001262: f00c f907 bl 800d474 <memset>
|
|
if(uartHandle->Instance==USART2)
|
|
8001266: 687b ldr r3, [r7, #4]
|
|
8001268: 681b ldr r3, [r3, #0]
|
|
800126a: 4a33 ldr r2, [pc, #204] @ (8001338 <HAL_UART_MspInit+0xf8>)
|
|
800126c: 4293 cmp r3, r2
|
|
800126e: d15f bne.n 8001330 <HAL_UART_MspInit+0xf0>
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
|
8001270: 2302 movs r3, #2
|
|
8001272: 60fb str r3, [r7, #12]
|
|
PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK;
|
|
8001274: 4b31 ldr r3, [pc, #196] @ (800133c <HAL_UART_MspInit+0xfc>)
|
|
8001276: 617b str r3, [r7, #20]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8001278: f107 030c add.w r3, r7, #12
|
|
800127c: 4618 mov r0, r3
|
|
800127e: f002 fd47 bl 8003d10 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001282: 4603 mov r3, r0
|
|
8001284: 2b00 cmp r3, #0
|
|
8001286: d001 beq.n 800128c <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001288: f7ff fa3e bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
/* USART2 clock enable */
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
800128c: f44f 3000 mov.w r0, #131072 @ 0x20000
|
|
8001290: f7ff ff60 bl 8001154 <LL_APB1_GRP1_EnableClock>
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001294: 2001 movs r0, #1
|
|
8001296: f7ff ff45 bl 8001124 <LL_AHB2_GRP1_EnableClock>
|
|
/**USART2 GPIO Configuration
|
|
PA3 ------> USART2_RX
|
|
PA2 ------> USART2_TX
|
|
*/
|
|
GPIO_InitStruct.Pin = USARTx_RX_Pin|USARTx_TX_Pin;
|
|
800129a: 230c movs r3, #12
|
|
800129c: 647b str r3, [r7, #68] @ 0x44
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800129e: 2302 movs r3, #2
|
|
80012a0: 64bb str r3, [r7, #72] @ 0x48
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012a2: 2300 movs r3, #0
|
|
80012a4: 64fb str r3, [r7, #76] @ 0x4c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012a6: 2303 movs r3, #3
|
|
80012a8: 653b str r3, [r7, #80] @ 0x50
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80012aa: 2307 movs r3, #7
|
|
80012ac: 657b str r3, [r7, #84] @ 0x54
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80012ae: f107 0344 add.w r3, r7, #68 @ 0x44
|
|
80012b2: 4619 mov r1, r3
|
|
80012b4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80012b8: f001 f816 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
/* USART2 DMA Init */
|
|
/* USART2_TX Init */
|
|
hdma_usart2_tx.Instance = DMA1_Channel5;
|
|
80012bc: 4b20 ldr r3, [pc, #128] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012be: 4a21 ldr r2, [pc, #132] @ (8001344 <HAL_UART_MspInit+0x104>)
|
|
80012c0: 601a str r2, [r3, #0]
|
|
hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
|
|
80012c2: 4b1f ldr r3, [pc, #124] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012c4: 2214 movs r2, #20
|
|
80012c6: 605a str r2, [r3, #4]
|
|
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
80012c8: 4b1d ldr r3, [pc, #116] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012ca: 2210 movs r2, #16
|
|
80012cc: 609a str r2, [r3, #8]
|
|
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80012ce: 4b1c ldr r3, [pc, #112] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012d0: 2200 movs r2, #0
|
|
80012d2: 60da str r2, [r3, #12]
|
|
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80012d4: 4b1a ldr r3, [pc, #104] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012d6: 2280 movs r2, #128 @ 0x80
|
|
80012d8: 611a str r2, [r3, #16]
|
|
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80012da: 4b19 ldr r3, [pc, #100] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012dc: 2200 movs r2, #0
|
|
80012de: 615a str r2, [r3, #20]
|
|
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80012e0: 4b17 ldr r3, [pc, #92] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012e2: 2200 movs r2, #0
|
|
80012e4: 619a str r2, [r3, #24]
|
|
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
|
|
80012e6: 4b16 ldr r3, [pc, #88] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012e8: 2200 movs r2, #0
|
|
80012ea: 61da str r2, [r3, #28]
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
80012ec: 4b14 ldr r3, [pc, #80] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012ee: 2200 movs r2, #0
|
|
80012f0: 621a str r2, [r3, #32]
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
80012f2: 4813 ldr r0, [pc, #76] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
80012f4: f000 fbe0 bl 8001ab8 <HAL_DMA_Init>
|
|
80012f8: 4603 mov r3, r0
|
|
80012fa: 2b00 cmp r3, #0
|
|
80012fc: d001 beq.n 8001302 <HAL_UART_MspInit+0xc2>
|
|
{
|
|
Error_Handler();
|
|
80012fe: f7ff fa03 bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
if (HAL_DMA_ConfigChannelAttributes(&hdma_usart2_tx, DMA_CHANNEL_NPRIV) != HAL_OK)
|
|
8001302: 2110 movs r1, #16
|
|
8001304: 480e ldr r0, [pc, #56] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
8001306: f000 ff17 bl 8002138 <HAL_DMA_ConfigChannelAttributes>
|
|
800130a: 4603 mov r3, r0
|
|
800130c: 2b00 cmp r3, #0
|
|
800130e: d001 beq.n 8001314 <HAL_UART_MspInit+0xd4>
|
|
{
|
|
Error_Handler();
|
|
8001310: f7ff f9fa bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
|
|
8001314: 687b ldr r3, [r7, #4]
|
|
8001316: 4a0a ldr r2, [pc, #40] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
8001318: 67da str r2, [r3, #124] @ 0x7c
|
|
800131a: 4a09 ldr r2, [pc, #36] @ (8001340 <HAL_UART_MspInit+0x100>)
|
|
800131c: 687b ldr r3, [r7, #4]
|
|
800131e: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
/* USART2 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 2, 0);
|
|
8001320: 2200 movs r2, #0
|
|
8001322: 2102 movs r1, #2
|
|
8001324: 2025 movs r0, #37 @ 0x25
|
|
8001326: f000 fb90 bl 8001a4a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
800132a: 2025 movs r0, #37 @ 0x25
|
|
800132c: f000 fba7 bl 8001a7e <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
}
|
|
8001330: bf00 nop
|
|
8001332: 3758 adds r7, #88 @ 0x58
|
|
8001334: 46bd mov sp, r7
|
|
8001336: bd80 pop {r7, pc}
|
|
8001338: 40004400 .word 0x40004400
|
|
800133c: 000c0004 .word 0x000c0004
|
|
8001340: 20000120 .word 0x20000120
|
|
8001344: 40020058 .word 0x40020058
|
|
|
|
08001348 <HAL_UART_MspDeInit>:
|
|
|
|
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8001348: b580 push {r7, lr}
|
|
800134a: b082 sub sp, #8
|
|
800134c: af00 add r7, sp, #0
|
|
800134e: 6078 str r0, [r7, #4]
|
|
|
|
if(uartHandle->Instance==USART2)
|
|
8001350: 687b ldr r3, [r7, #4]
|
|
8001352: 681b ldr r3, [r3, #0]
|
|
8001354: 4a0b ldr r2, [pc, #44] @ (8001384 <HAL_UART_MspDeInit+0x3c>)
|
|
8001356: 4293 cmp r3, r2
|
|
8001358: d110 bne.n 800137c <HAL_UART_MspDeInit+0x34>
|
|
{
|
|
/* USER CODE BEGIN USART2_MspDeInit 0 */
|
|
|
|
/* USER CODE END USART2_MspDeInit 0 */
|
|
/* Peripheral clock disable */
|
|
__HAL_RCC_USART2_CLK_DISABLE();
|
|
800135a: f44f 3000 mov.w r0, #131072 @ 0x20000
|
|
800135e: f7ff ff11 bl 8001184 <LL_APB1_GRP1_DisableClock>
|
|
|
|
/**USART2 GPIO Configuration
|
|
PA3 ------> USART2_RX
|
|
PA2 ------> USART2_TX
|
|
*/
|
|
HAL_GPIO_DeInit(GPIOA, USARTx_RX_Pin|USARTx_TX_Pin);
|
|
8001362: 210c movs r1, #12
|
|
8001364: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001368: f001 f91e bl 80025a8 <HAL_GPIO_DeInit>
|
|
|
|
/* USART2 DMA DeInit */
|
|
HAL_DMA_DeInit(uartHandle->hdmatx);
|
|
800136c: 687b ldr r3, [r7, #4]
|
|
800136e: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8001370: 4618 mov r0, r3
|
|
8001372: f000 fc49 bl 8001c08 <HAL_DMA_DeInit>
|
|
|
|
/* USART2 interrupt Deinit */
|
|
HAL_NVIC_DisableIRQ(USART2_IRQn);
|
|
8001376: 2025 movs r0, #37 @ 0x25
|
|
8001378: f000 fb8f bl 8001a9a <HAL_NVIC_DisableIRQ>
|
|
/* USER CODE BEGIN USART2_MspDeInit 1 */
|
|
|
|
/* USER CODE END USART2_MspDeInit 1 */
|
|
}
|
|
}
|
|
800137c: bf00 nop
|
|
800137e: 3708 adds r7, #8
|
|
8001380: 46bd mov sp, r7
|
|
8001382: bd80 pop {r7, pc}
|
|
8001384: 40004400 .word 0x40004400
|
|
|
|
08001388 <LL_APB1_GRP1_ForceReset>:
|
|
{
|
|
8001388: b480 push {r7}
|
|
800138a: b083 sub sp, #12
|
|
800138c: af00 add r7, sp, #0
|
|
800138e: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->APB1RSTR1, Periphs);
|
|
8001390: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8001394: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8001396: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800139a: 687b ldr r3, [r7, #4]
|
|
800139c: 4313 orrs r3, r2
|
|
800139e: 638b str r3, [r1, #56] @ 0x38
|
|
}
|
|
80013a0: bf00 nop
|
|
80013a2: 370c adds r7, #12
|
|
80013a4: 46bd mov sp, r7
|
|
80013a6: bc80 pop {r7}
|
|
80013a8: 4770 bx lr
|
|
|
|
080013aa <LL_APB1_GRP1_ReleaseReset>:
|
|
{
|
|
80013aa: b480 push {r7}
|
|
80013ac: b083 sub sp, #12
|
|
80013ae: af00 add r7, sp, #0
|
|
80013b0: 6078 str r0, [r7, #4]
|
|
CLEAR_BIT(RCC->APB1RSTR1, Periphs);
|
|
80013b2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80013b6: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80013b8: 687b ldr r3, [r7, #4]
|
|
80013ba: 43db mvns r3, r3
|
|
80013bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80013c0: 4013 ands r3, r2
|
|
80013c2: 638b str r3, [r1, #56] @ 0x38
|
|
}
|
|
80013c4: bf00 nop
|
|
80013c6: 370c adds r7, #12
|
|
80013c8: 46bd mov sp, r7
|
|
80013ca: bc80 pop {r7}
|
|
80013cc: 4770 bx lr
|
|
...
|
|
|
|
080013d0 <LL_EXTI_EnableIT_0_31>:
|
|
{
|
|
80013d0: b480 push {r7}
|
|
80013d2: b083 sub sp, #12
|
|
80013d4: af00 add r7, sp, #0
|
|
80013d6: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->IMR1, ExtiLine);
|
|
80013d8: 4b06 ldr r3, [pc, #24] @ (80013f4 <LL_EXTI_EnableIT_0_31+0x24>)
|
|
80013da: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
|
|
80013de: 4905 ldr r1, [pc, #20] @ (80013f4 <LL_EXTI_EnableIT_0_31+0x24>)
|
|
80013e0: 687b ldr r3, [r7, #4]
|
|
80013e2: 4313 orrs r3, r2
|
|
80013e4: f8c1 3080 str.w r3, [r1, #128] @ 0x80
|
|
}
|
|
80013e8: bf00 nop
|
|
80013ea: 370c adds r7, #12
|
|
80013ec: 46bd mov sp, r7
|
|
80013ee: bc80 pop {r7}
|
|
80013f0: 4770 bx lr
|
|
80013f2: bf00 nop
|
|
80013f4: 58000800 .word 0x58000800
|
|
|
|
080013f8 <vcom_Init>:
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *))
|
|
{
|
|
80013f8: b580 push {r7, lr}
|
|
80013fa: b082 sub sp, #8
|
|
80013fc: af00 add r7, sp, #0
|
|
80013fe: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN vcom_Init_1 */
|
|
|
|
/* USER CODE END vcom_Init_1 */
|
|
TxCpltCallback = cb;
|
|
8001400: 4a07 ldr r2, [pc, #28] @ (8001420 <vcom_Init+0x28>)
|
|
8001402: 687b ldr r3, [r7, #4]
|
|
8001404: 6013 str r3, [r2, #0]
|
|
MX_DMA_Init();
|
|
8001406: f7ff f86d bl 80004e4 <MX_DMA_Init>
|
|
MX_USART2_UART_Init();
|
|
800140a: f7ff fecd bl 80011a8 <MX_USART2_UART_Init>
|
|
LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_27);
|
|
800140e: f04f 6000 mov.w r0, #134217728 @ 0x8000000
|
|
8001412: f7ff ffdd bl 80013d0 <LL_EXTI_EnableIT_0_31>
|
|
return UTIL_ADV_TRACE_OK;
|
|
8001416: 2300 movs r3, #0
|
|
/* USER CODE BEGIN vcom_Init_2 */
|
|
|
|
/* USER CODE END vcom_Init_2 */
|
|
}
|
|
8001418: 4618 mov r0, r3
|
|
800141a: 3708 adds r7, #8
|
|
800141c: 46bd mov sp, r7
|
|
800141e: bd80 pop {r7, pc}
|
|
8001420: 20000184 .word 0x20000184
|
|
|
|
08001424 <vcom_DeInit>:
|
|
|
|
UTIL_ADV_TRACE_Status_t vcom_DeInit(void)
|
|
{
|
|
8001424: b580 push {r7, lr}
|
|
8001426: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN vcom_DeInit_1 */
|
|
|
|
/* USER CODE END vcom_DeInit_1 */
|
|
/* ##-1- Reset peripherals ################################################## */
|
|
__HAL_RCC_USART2_FORCE_RESET();
|
|
8001428: f44f 3000 mov.w r0, #131072 @ 0x20000
|
|
800142c: f7ff ffac bl 8001388 <LL_APB1_GRP1_ForceReset>
|
|
__HAL_RCC_USART2_RELEASE_RESET();
|
|
8001430: f44f 3000 mov.w r0, #131072 @ 0x20000
|
|
8001434: f7ff ffb9 bl 80013aa <LL_APB1_GRP1_ReleaseReset>
|
|
|
|
/* ##-2- MspDeInit ################################################## */
|
|
HAL_UART_MspDeInit(&huart2);
|
|
8001438: 4804 ldr r0, [pc, #16] @ (800144c <vcom_DeInit+0x28>)
|
|
800143a: f7ff ff85 bl 8001348 <HAL_UART_MspDeInit>
|
|
|
|
/* ##-3- Disable the NVIC for DMA ########################################### */
|
|
/* USER CODE BEGIN 1 */
|
|
HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn);
|
|
800143e: 200f movs r0, #15
|
|
8001440: f000 fb2b bl 8001a9a <HAL_NVIC_DisableIRQ>
|
|
|
|
return UTIL_ADV_TRACE_OK;
|
|
8001444: 2300 movs r3, #0
|
|
/* USER CODE END 1 */
|
|
/* USER CODE BEGIN vcom_DeInit_2 */
|
|
|
|
/* USER CODE END vcom_DeInit_2 */
|
|
}
|
|
8001446: 4618 mov r0, r3
|
|
8001448: bd80 pop {r7, pc}
|
|
800144a: bf00 nop
|
|
800144c: 2000008c .word 0x2000008c
|
|
|
|
08001450 <vcom_Trace_DMA>:
|
|
|
|
/* USER CODE END vcom_Trace_2 */
|
|
}
|
|
|
|
UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size)
|
|
{
|
|
8001450: b580 push {r7, lr}
|
|
8001452: b082 sub sp, #8
|
|
8001454: af00 add r7, sp, #0
|
|
8001456: 6078 str r0, [r7, #4]
|
|
8001458: 460b mov r3, r1
|
|
800145a: 807b strh r3, [r7, #2]
|
|
/* USER CODE BEGIN vcom_Trace_DMA_1 */
|
|
|
|
/* USER CODE END vcom_Trace_DMA_1 */
|
|
HAL_UART_Transmit_DMA(&huart2, p_data, size);
|
|
800145c: 887b ldrh r3, [r7, #2]
|
|
800145e: 461a mov r2, r3
|
|
8001460: 6879 ldr r1, [r7, #4]
|
|
8001462: 4804 ldr r0, [pc, #16] @ (8001474 <vcom_Trace_DMA+0x24>)
|
|
8001464: f003 fe8e bl 8005184 <HAL_UART_Transmit_DMA>
|
|
return UTIL_ADV_TRACE_OK;
|
|
8001468: 2300 movs r3, #0
|
|
/* USER CODE BEGIN vcom_Trace_DMA_2 */
|
|
|
|
/* USER CODE END vcom_Trace_DMA_2 */
|
|
}
|
|
800146a: 4618 mov r0, r3
|
|
800146c: 3708 adds r7, #8
|
|
800146e: 46bd mov sp, r7
|
|
8001470: bd80 pop {r7, pc}
|
|
8001472: bf00 nop
|
|
8001474: 2000008c .word 0x2000008c
|
|
|
|
08001478 <vcom_ReceiveInit>:
|
|
|
|
UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error))
|
|
{
|
|
8001478: b580 push {r7, lr}
|
|
800147a: b084 sub sp, #16
|
|
800147c: af00 add r7, sp, #0
|
|
800147e: 6078 str r0, [r7, #4]
|
|
|
|
/* USER CODE END vcom_ReceiveInit_1 */
|
|
UART_WakeUpTypeDef WakeUpSelection;
|
|
|
|
/*record call back*/
|
|
RxCpltCallback = RxCb;
|
|
8001480: 4a19 ldr r2, [pc, #100] @ (80014e8 <vcom_ReceiveInit+0x70>)
|
|
8001482: 687b ldr r3, [r7, #4]
|
|
8001484: 6013 str r3, [r2, #0]
|
|
|
|
/*Set wakeUp event on start bit*/
|
|
WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT;
|
|
8001486: f44f 1300 mov.w r3, #2097152 @ 0x200000
|
|
800148a: 60bb str r3, [r7, #8]
|
|
|
|
HAL_UARTEx_StopModeWakeUpSourceConfig(&huart2, WakeUpSelection);
|
|
800148c: f107 0308 add.w r3, r7, #8
|
|
8001490: e893 0006 ldmia.w r3, {r1, r2}
|
|
8001494: 4815 ldr r0, [pc, #84] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
8001496: f005 fe4a bl 800712e <HAL_UARTEx_StopModeWakeUpSourceConfig>
|
|
|
|
/* Make sure that no UART transfer is on-going */
|
|
while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_BUSY) == SET);
|
|
800149a: bf00 nop
|
|
800149c: 4b13 ldr r3, [pc, #76] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
800149e: 681b ldr r3, [r3, #0]
|
|
80014a0: 69db ldr r3, [r3, #28]
|
|
80014a2: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
80014a6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80014aa: d0f7 beq.n 800149c <vcom_ReceiveInit+0x24>
|
|
|
|
/* Make sure that UART is ready to receive) */
|
|
while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_REACK) == RESET);
|
|
80014ac: bf00 nop
|
|
80014ae: 4b0f ldr r3, [pc, #60] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
80014b0: 681b ldr r3, [r3, #0]
|
|
80014b2: 69db ldr r3, [r3, #28]
|
|
80014b4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80014b8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80014bc: d1f7 bne.n 80014ae <vcom_ReceiveInit+0x36>
|
|
|
|
/* Enable USART interrupt */
|
|
__HAL_UART_ENABLE_IT(&huart2, UART_IT_WUF);
|
|
80014be: 4b0b ldr r3, [pc, #44] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
80014c0: 681b ldr r3, [r3, #0]
|
|
80014c2: 689a ldr r2, [r3, #8]
|
|
80014c4: 4b09 ldr r3, [pc, #36] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
80014c6: 681b ldr r3, [r3, #0]
|
|
80014c8: f442 0280 orr.w r2, r2, #4194304 @ 0x400000
|
|
80014cc: 609a str r2, [r3, #8]
|
|
|
|
/*Enable wakeup from stop mode*/
|
|
HAL_UARTEx_EnableStopMode(&huart2);
|
|
80014ce: 4807 ldr r0, [pc, #28] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
80014d0: f005 fe88 bl 80071e4 <HAL_UARTEx_EnableStopMode>
|
|
|
|
/*Start LPUART receive on IT*/
|
|
HAL_UART_Receive_IT(&huart2, &charRx, 1);
|
|
80014d4: 2201 movs r2, #1
|
|
80014d6: 4906 ldr r1, [pc, #24] @ (80014f0 <vcom_ReceiveInit+0x78>)
|
|
80014d8: 4804 ldr r0, [pc, #16] @ (80014ec <vcom_ReceiveInit+0x74>)
|
|
80014da: f003 fe07 bl 80050ec <HAL_UART_Receive_IT>
|
|
|
|
return UTIL_ADV_TRACE_OK;
|
|
80014de: 2300 movs r3, #0
|
|
/* USER CODE BEGIN vcom_ReceiveInit_2 */
|
|
|
|
/* USER CODE END vcom_ReceiveInit_2 */
|
|
}
|
|
80014e0: 4618 mov r0, r3
|
|
80014e2: 3710 adds r7, #16
|
|
80014e4: 46bd mov sp, r7
|
|
80014e6: bd80 pop {r7, pc}
|
|
80014e8: 20000188 .word 0x20000188
|
|
80014ec: 2000008c .word 0x2000008c
|
|
80014f0: 20000180 .word 0x20000180
|
|
|
|
080014f4 <vcom_Resume>:
|
|
|
|
void vcom_Resume(void)
|
|
{
|
|
80014f4: b580 push {r7, lr}
|
|
80014f6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN vcom_Resume_1 */
|
|
|
|
/* USER CODE END vcom_Resume_1 */
|
|
/*to re-enable lost UART settings*/
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
80014f8: 4808 ldr r0, [pc, #32] @ (800151c <vcom_Resume+0x28>)
|
|
80014fa: f003 fda6 bl 800504a <HAL_UART_Init>
|
|
80014fe: 4603 mov r3, r0
|
|
8001500: 2b00 cmp r3, #0
|
|
8001502: d001 beq.n 8001508 <vcom_Resume+0x14>
|
|
{
|
|
Error_Handler();
|
|
8001504: f7ff f900 bl 8000708 <Error_Handler>
|
|
}
|
|
|
|
/*to re-enable lost DMA settings*/
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
8001508: 4805 ldr r0, [pc, #20] @ (8001520 <vcom_Resume+0x2c>)
|
|
800150a: f000 fad5 bl 8001ab8 <HAL_DMA_Init>
|
|
800150e: 4603 mov r3, r0
|
|
8001510: 2b00 cmp r3, #0
|
|
8001512: d001 beq.n 8001518 <vcom_Resume+0x24>
|
|
{
|
|
Error_Handler();
|
|
8001514: f7ff f8f8 bl 8000708 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN vcom_Resume_2 */
|
|
|
|
/* USER CODE END vcom_Resume_2 */
|
|
}
|
|
8001518: bf00 nop
|
|
800151a: bd80 pop {r7, pc}
|
|
800151c: 2000008c .word 0x2000008c
|
|
8001520: 20000120 .word 0x20000120
|
|
|
|
08001524 <HAL_UART_TxCpltCallback>:
|
|
|
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8001524: b580 push {r7, lr}
|
|
8001526: b082 sub sp, #8
|
|
8001528: af00 add r7, sp, #0
|
|
800152a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */
|
|
|
|
/* USER CODE END HAL_UART_TxCpltCallback_1 */
|
|
/* buffer transmission complete*/
|
|
if (huart->Instance == USART2)
|
|
800152c: 687b ldr r3, [r7, #4]
|
|
800152e: 681b ldr r3, [r3, #0]
|
|
8001530: 4a05 ldr r2, [pc, #20] @ (8001548 <HAL_UART_TxCpltCallback+0x24>)
|
|
8001532: 4293 cmp r3, r2
|
|
8001534: d103 bne.n 800153e <HAL_UART_TxCpltCallback+0x1a>
|
|
{
|
|
TxCpltCallback(NULL);
|
|
8001536: 4b05 ldr r3, [pc, #20] @ (800154c <HAL_UART_TxCpltCallback+0x28>)
|
|
8001538: 681b ldr r3, [r3, #0]
|
|
800153a: 2000 movs r0, #0
|
|
800153c: 4798 blx r3
|
|
}
|
|
/* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */
|
|
|
|
/* USER CODE END HAL_UART_TxCpltCallback_2 */
|
|
}
|
|
800153e: bf00 nop
|
|
8001540: 3708 adds r7, #8
|
|
8001542: 46bd mov sp, r7
|
|
8001544: bd80 pop {r7, pc}
|
|
8001546: bf00 nop
|
|
8001548: 40004400 .word 0x40004400
|
|
800154c: 20000184 .word 0x20000184
|
|
|
|
08001550 <HAL_UART_RxCpltCallback>:
|
|
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8001550: b580 push {r7, lr}
|
|
8001552: b082 sub sp, #8
|
|
8001554: af00 add r7, sp, #0
|
|
8001556: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */
|
|
|
|
/* USER CODE END HAL_UART_RxCpltCallback_1 */
|
|
if (huart->Instance == USART2)
|
|
8001558: 687b ldr r3, [r7, #4]
|
|
800155a: 681b ldr r3, [r3, #0]
|
|
800155c: 4a0d ldr r2, [pc, #52] @ (8001594 <HAL_UART_RxCpltCallback+0x44>)
|
|
800155e: 4293 cmp r3, r2
|
|
8001560: d113 bne.n 800158a <HAL_UART_RxCpltCallback+0x3a>
|
|
{
|
|
if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode))
|
|
8001562: 4b0d ldr r3, [pc, #52] @ (8001598 <HAL_UART_RxCpltCallback+0x48>)
|
|
8001564: 681b ldr r3, [r3, #0]
|
|
8001566: 2b00 cmp r3, #0
|
|
8001568: d00a beq.n 8001580 <HAL_UART_RxCpltCallback+0x30>
|
|
800156a: 687b ldr r3, [r7, #4]
|
|
800156c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8001570: 2b00 cmp r3, #0
|
|
8001572: d105 bne.n 8001580 <HAL_UART_RxCpltCallback+0x30>
|
|
{
|
|
RxCpltCallback(&charRx, 1, 0);
|
|
8001574: 4b08 ldr r3, [pc, #32] @ (8001598 <HAL_UART_RxCpltCallback+0x48>)
|
|
8001576: 681b ldr r3, [r3, #0]
|
|
8001578: 2200 movs r2, #0
|
|
800157a: 2101 movs r1, #1
|
|
800157c: 4807 ldr r0, [pc, #28] @ (800159c <HAL_UART_RxCpltCallback+0x4c>)
|
|
800157e: 4798 blx r3
|
|
}
|
|
HAL_UART_Receive_IT(huart, &charRx, 1);
|
|
8001580: 2201 movs r2, #1
|
|
8001582: 4906 ldr r1, [pc, #24] @ (800159c <HAL_UART_RxCpltCallback+0x4c>)
|
|
8001584: 6878 ldr r0, [r7, #4]
|
|
8001586: f003 fdb1 bl 80050ec <HAL_UART_Receive_IT>
|
|
}
|
|
/* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */
|
|
|
|
/* USER CODE END HAL_UART_RxCpltCallback_2 */
|
|
}
|
|
800158a: bf00 nop
|
|
800158c: 3708 adds r7, #8
|
|
800158e: 46bd mov sp, r7
|
|
8001590: bd80 pop {r7, pc}
|
|
8001592: bf00 nop
|
|
8001594: 40004400 .word 0x40004400
|
|
8001598: 20000188 .word 0x20000188
|
|
800159c: 20000180 .word 0x20000180
|
|
|
|
080015a0 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
80015a0: 480d ldr r0, [pc, #52] @ (80015d8 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
80015a2: 4685 mov sp, r0
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80015a4: f7ff fb7a bl 8000c9c <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80015a8: 480c ldr r0, [pc, #48] @ (80015dc <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
80015aa: 490d ldr r1, [pc, #52] @ (80015e0 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
80015ac: 4a0d ldr r2, [pc, #52] @ (80015e4 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
80015ae: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
80015b0: e002 b.n 80015b8 <LoopCopyDataInit>
|
|
|
|
080015b2 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
80015b2: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80015b4: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80015b6: 3304 adds r3, #4
|
|
|
|
080015b8 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80015b8: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80015ba: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80015bc: d3f9 bcc.n 80015b2 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80015be: 4a0a ldr r2, [pc, #40] @ (80015e8 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
80015c0: 4c0a ldr r4, [pc, #40] @ (80015ec <LoopForever+0x16>)
|
|
movs r3, #0
|
|
80015c2: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80015c4: e001 b.n 80015ca <LoopFillZerobss>
|
|
|
|
080015c6 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80015c6: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80015c8: 3204 adds r2, #4
|
|
|
|
080015ca <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80015ca: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80015cc: d3fb bcc.n 80015c6 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80015ce: f00b ff59 bl 800d484 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
80015d2: f7ff f834 bl 800063e <main>
|
|
|
|
080015d6 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80015d6: e7fe b.n 80015d6 <LoopForever>
|
|
ldr r0, =_estack
|
|
80015d8: 20010000 .word 0x20010000
|
|
ldr r0, =_sdata
|
|
80015dc: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80015e0: 20000024 .word 0x20000024
|
|
ldr r2, =_sidata
|
|
80015e4: 0800db40 .word 0x0800db40
|
|
ldr r2, =_sbss
|
|
80015e8: 20000024 .word 0x20000024
|
|
ldr r4, =_ebss
|
|
80015ec: 20000ce8 .word 0x20000ce8
|
|
|
|
080015f0 <ADC_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80015f0: e7fe b.n 80015f0 <ADC_IRQHandler>
|
|
|
|
080015f2 <LL_AHB2_GRP1_EnableClock>:
|
|
{
|
|
80015f2: b480 push {r7}
|
|
80015f4: b085 sub sp, #20
|
|
80015f6: af00 add r7, sp, #0
|
|
80015f8: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
80015fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80015fe: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8001600: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8001604: 687b ldr r3, [r7, #4]
|
|
8001606: 4313 orrs r3, r2
|
|
8001608: 64cb str r3, [r1, #76] @ 0x4c
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
800160a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800160e: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8001610: 687b ldr r3, [r7, #4]
|
|
8001612: 4013 ands r3, r2
|
|
8001614: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8001616: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8001618: bf00 nop
|
|
800161a: 3714 adds r7, #20
|
|
800161c: 46bd mov sp, r7
|
|
800161e: bc80 pop {r7}
|
|
8001620: 4770 bx lr
|
|
...
|
|
|
|
08001624 <BSP_RADIO_Init>:
|
|
/**
|
|
* @brief Init Radio Switch
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_RADIO_Init(void)
|
|
{
|
|
8001624: b580 push {r7, lr}
|
|
8001626: b086 sub sp, #24
|
|
8001628: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef gpio_init_structure = {0};
|
|
800162a: 1d3b adds r3, r7, #4
|
|
800162c: 2200 movs r2, #0
|
|
800162e: 601a str r2, [r3, #0]
|
|
8001630: 605a str r2, [r3, #4]
|
|
8001632: 609a str r2, [r3, #8]
|
|
8001634: 60da str r2, [r3, #12]
|
|
8001636: 611a str r2, [r3, #16]
|
|
|
|
/* Enable the Radio Switch Clock */
|
|
RF_SW_CTRL3_GPIO_CLK_ENABLE();
|
|
8001638: 2004 movs r0, #4
|
|
800163a: f7ff ffda bl 80015f2 <LL_AHB2_GRP1_EnableClock>
|
|
|
|
/* Configure the Radio Switch pin */
|
|
gpio_init_structure.Pin = RF_SW_CTRL1_PIN;
|
|
800163e: 2310 movs r3, #16
|
|
8001640: 607b str r3, [r7, #4]
|
|
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001642: 2301 movs r3, #1
|
|
8001644: 60bb str r3, [r7, #8]
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
8001646: 2300 movs r3, #0
|
|
8001648: 60fb str r3, [r7, #12]
|
|
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800164a: 2303 movs r3, #3
|
|
800164c: 613b str r3, [r7, #16]
|
|
|
|
HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure);
|
|
800164e: 1d3b adds r3, r7, #4
|
|
8001650: 4619 mov r1, r3
|
|
8001652: 4812 ldr r0, [pc, #72] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
8001654: f000 fe48 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
gpio_init_structure.Pin = RF_SW_CTRL2_PIN;
|
|
8001658: 2320 movs r3, #32
|
|
800165a: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure);
|
|
800165c: 1d3b adds r3, r7, #4
|
|
800165e: 4619 mov r1, r3
|
|
8001660: 480e ldr r0, [pc, #56] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
8001662: f000 fe41 bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
gpio_init_structure.Pin = RF_SW_CTRL3_PIN;
|
|
8001666: 2308 movs r3, #8
|
|
8001668: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure);
|
|
800166a: 1d3b adds r3, r7, #4
|
|
800166c: 4619 mov r1, r3
|
|
800166e: 480b ldr r0, [pc, #44] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
8001670: f000 fe3a bl 80022e8 <HAL_GPIO_Init>
|
|
|
|
HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET);
|
|
8001674: 2200 movs r2, #0
|
|
8001676: 2120 movs r1, #32
|
|
8001678: 4808 ldr r0, [pc, #32] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
800167a: f001 f863 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET);
|
|
800167e: 2200 movs r2, #0
|
|
8001680: 2110 movs r1, #16
|
|
8001682: 4806 ldr r0, [pc, #24] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
8001684: f001 f85e bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET);
|
|
8001688: 2200 movs r2, #0
|
|
800168a: 2108 movs r1, #8
|
|
800168c: 4803 ldr r0, [pc, #12] @ (800169c <BSP_RADIO_Init+0x78>)
|
|
800168e: f001 f859 bl 8002744 <HAL_GPIO_WritePin>
|
|
|
|
return BSP_ERROR_NONE;
|
|
8001692: 2300 movs r3, #0
|
|
}
|
|
8001694: 4618 mov r0, r3
|
|
8001696: 3718 adds r7, #24
|
|
8001698: 46bd mov sp, r7
|
|
800169a: bd80 pop {r7, pc}
|
|
800169c: 48000800 .word 0x48000800
|
|
|
|
080016a0 <BSP_RADIO_ConfigRFSwitch>:
|
|
* @arg RADIO_SWITCH_RFO_LP
|
|
* @arg RADIO_SWITCH_RFO_HP
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config)
|
|
{
|
|
80016a0: b580 push {r7, lr}
|
|
80016a2: b082 sub sp, #8
|
|
80016a4: af00 add r7, sp, #0
|
|
80016a6: 4603 mov r3, r0
|
|
80016a8: 71fb strb r3, [r7, #7]
|
|
switch (Config)
|
|
80016aa: 79fb ldrb r3, [r7, #7]
|
|
80016ac: 2b03 cmp r3, #3
|
|
80016ae: d84b bhi.n 8001748 <BSP_RADIO_ConfigRFSwitch+0xa8>
|
|
80016b0: a201 add r2, pc, #4 @ (adr r2, 80016b8 <BSP_RADIO_ConfigRFSwitch+0x18>)
|
|
80016b2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80016b6: bf00 nop
|
|
80016b8: 080016c9 .word 0x080016c9
|
|
80016bc: 080016e9 .word 0x080016e9
|
|
80016c0: 08001709 .word 0x08001709
|
|
80016c4: 08001729 .word 0x08001729
|
|
{
|
|
case RADIO_SWITCH_OFF:
|
|
{
|
|
/* Turn off switch */
|
|
HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET);
|
|
80016c8: 2200 movs r2, #0
|
|
80016ca: 2108 movs r1, #8
|
|
80016cc: 4821 ldr r0, [pc, #132] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
80016ce: f001 f839 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET);
|
|
80016d2: 2200 movs r2, #0
|
|
80016d4: 2110 movs r1, #16
|
|
80016d6: 481f ldr r0, [pc, #124] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
80016d8: f001 f834 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET);
|
|
80016dc: 2200 movs r2, #0
|
|
80016de: 2120 movs r1, #32
|
|
80016e0: 481c ldr r0, [pc, #112] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
80016e2: f001 f82f bl 8002744 <HAL_GPIO_WritePin>
|
|
break;
|
|
80016e6: e030 b.n 800174a <BSP_RADIO_ConfigRFSwitch+0xaa>
|
|
}
|
|
case RADIO_SWITCH_RX:
|
|
{
|
|
/*Turns On in Rx Mode the RF Switch */
|
|
HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET);
|
|
80016e8: 2201 movs r2, #1
|
|
80016ea: 2108 movs r1, #8
|
|
80016ec: 4819 ldr r0, [pc, #100] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
80016ee: f001 f829 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET);
|
|
80016f2: 2201 movs r2, #1
|
|
80016f4: 2110 movs r1, #16
|
|
80016f6: 4817 ldr r0, [pc, #92] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
80016f8: f001 f824 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET);
|
|
80016fc: 2200 movs r2, #0
|
|
80016fe: 2120 movs r1, #32
|
|
8001700: 4814 ldr r0, [pc, #80] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
8001702: f001 f81f bl 8002744 <HAL_GPIO_WritePin>
|
|
break;
|
|
8001706: e020 b.n 800174a <BSP_RADIO_ConfigRFSwitch+0xaa>
|
|
}
|
|
case RADIO_SWITCH_RFO_LP:
|
|
{
|
|
/*Turns On in Tx Low Power the RF Switch */
|
|
HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET);
|
|
8001708: 2201 movs r2, #1
|
|
800170a: 2108 movs r1, #8
|
|
800170c: 4811 ldr r0, [pc, #68] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
800170e: f001 f819 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET);
|
|
8001712: 2201 movs r2, #1
|
|
8001714: 2110 movs r1, #16
|
|
8001716: 480f ldr r0, [pc, #60] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
8001718: f001 f814 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET);
|
|
800171c: 2201 movs r2, #1
|
|
800171e: 2120 movs r1, #32
|
|
8001720: 480c ldr r0, [pc, #48] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
8001722: f001 f80f bl 8002744 <HAL_GPIO_WritePin>
|
|
break;
|
|
8001726: e010 b.n 800174a <BSP_RADIO_ConfigRFSwitch+0xaa>
|
|
}
|
|
case RADIO_SWITCH_RFO_HP:
|
|
{
|
|
/*Turns On in Tx High Power the RF Switch */
|
|
HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET);
|
|
8001728: 2201 movs r2, #1
|
|
800172a: 2108 movs r1, #8
|
|
800172c: 4809 ldr r0, [pc, #36] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
800172e: f001 f809 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET);
|
|
8001732: 2200 movs r2, #0
|
|
8001734: 2110 movs r1, #16
|
|
8001736: 4807 ldr r0, [pc, #28] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
8001738: f001 f804 bl 8002744 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET);
|
|
800173c: 2201 movs r2, #1
|
|
800173e: 2120 movs r1, #32
|
|
8001740: 4804 ldr r0, [pc, #16] @ (8001754 <BSP_RADIO_ConfigRFSwitch+0xb4>)
|
|
8001742: f000 ffff bl 8002744 <HAL_GPIO_WritePin>
|
|
break;
|
|
8001746: e000 b.n 800174a <BSP_RADIO_ConfigRFSwitch+0xaa>
|
|
}
|
|
default:
|
|
break;
|
|
8001748: bf00 nop
|
|
}
|
|
|
|
return BSP_ERROR_NONE;
|
|
800174a: 2300 movs r3, #0
|
|
}
|
|
800174c: 4618 mov r0, r3
|
|
800174e: 3708 adds r7, #8
|
|
8001750: 46bd mov sp, r7
|
|
8001752: bd80 pop {r7, pc}
|
|
8001754: 48000800 .word 0x48000800
|
|
|
|
08001758 <BSP_RADIO_GetTxConfig>:
|
|
* RADIO_CONF_RFO_LP_HP
|
|
* RADIO_CONF_RFO_LP
|
|
* RADIO_CONF_RFO_HP
|
|
*/
|
|
int32_t BSP_RADIO_GetTxConfig(void)
|
|
{
|
|
8001758: b480 push {r7}
|
|
800175a: af00 add r7, sp, #0
|
|
return RADIO_CONF_RFO_LP_HP;
|
|
800175c: 2300 movs r3, #0
|
|
}
|
|
800175e: 4618 mov r0, r3
|
|
8001760: 46bd mov sp, r7
|
|
8001762: bc80 pop {r7}
|
|
8001764: 4770 bx lr
|
|
|
|
08001766 <BSP_RADIO_IsTCXO>:
|
|
* @retval
|
|
* RADIO_CONF_TCXO_NOT_SUPPORTED
|
|
* RADIO_CONF_TCXO_SUPPORTED
|
|
*/
|
|
int32_t BSP_RADIO_IsTCXO(void)
|
|
{
|
|
8001766: b480 push {r7}
|
|
8001768: af00 add r7, sp, #0
|
|
return RADIO_CONF_TCXO_SUPPORTED;
|
|
800176a: 2301 movs r3, #1
|
|
}
|
|
800176c: 4618 mov r0, r3
|
|
800176e: 46bd mov sp, r7
|
|
8001770: bc80 pop {r7}
|
|
8001772: 4770 bx lr
|
|
|
|
08001774 <BSP_RADIO_IsDCDC>:
|
|
* @retval
|
|
* RADIO_CONF_DCDC_NOT_SUPPORTED
|
|
* RADIO_CONF_DCDC_SUPPORTED
|
|
*/
|
|
int32_t BSP_RADIO_IsDCDC(void)
|
|
{
|
|
8001774: b480 push {r7}
|
|
8001776: af00 add r7, sp, #0
|
|
return RADIO_CONF_DCDC_SUPPORTED;
|
|
8001778: 2301 movs r3, #1
|
|
}
|
|
800177a: 4618 mov r0, r3
|
|
800177c: 46bd mov sp, r7
|
|
800177e: bc80 pop {r7}
|
|
8001780: 4770 bx lr
|
|
|
|
08001782 <BSP_RADIO_GetRFOMaxPowerConfig>:
|
|
* @retval
|
|
* RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode
|
|
* RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode
|
|
*/
|
|
int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config)
|
|
{
|
|
8001782: b480 push {r7}
|
|
8001784: b085 sub sp, #20
|
|
8001786: af00 add r7, sp, #0
|
|
8001788: 4603 mov r3, r0
|
|
800178a: 71fb strb r3, [r7, #7]
|
|
int32_t ret;
|
|
|
|
if(Config == RADIO_RFO_LP_MAXPOWER)
|
|
800178c: 79fb ldrb r3, [r7, #7]
|
|
800178e: 2b00 cmp r3, #0
|
|
8001790: d102 bne.n 8001798 <BSP_RADIO_GetRFOMaxPowerConfig+0x16>
|
|
{
|
|
ret = RADIO_CONF_RFO_LP_MAX_15_dBm;
|
|
8001792: 230f movs r3, #15
|
|
8001794: 60fb str r3, [r7, #12]
|
|
8001796: e001 b.n 800179c <BSP_RADIO_GetRFOMaxPowerConfig+0x1a>
|
|
}
|
|
else
|
|
{
|
|
ret = RADIO_CONF_RFO_HP_MAX_22_dBm;
|
|
8001798: 2316 movs r3, #22
|
|
800179a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return ret;
|
|
800179c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800179e: 4618 mov r0, r3
|
|
80017a0: 3714 adds r7, #20
|
|
80017a2: 46bd mov sp, r7
|
|
80017a4: bc80 pop {r7}
|
|
80017a6: 4770 bx lr
|
|
|
|
080017a8 <LL_DBGMCU_EnableDBGSleepMode>:
|
|
* @brief Enable the CPU1 Debug Module during SLEEP mode
|
|
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
|
|
{
|
|
80017a8: b480 push {r7}
|
|
80017aa: af00 add r7, sp, #0
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
|
80017ac: 4b04 ldr r3, [pc, #16] @ (80017c0 <LL_DBGMCU_EnableDBGSleepMode+0x18>)
|
|
80017ae: 685b ldr r3, [r3, #4]
|
|
80017b0: 4a03 ldr r2, [pc, #12] @ (80017c0 <LL_DBGMCU_EnableDBGSleepMode+0x18>)
|
|
80017b2: f043 0301 orr.w r3, r3, #1
|
|
80017b6: 6053 str r3, [r2, #4]
|
|
}
|
|
80017b8: bf00 nop
|
|
80017ba: 46bd mov sp, r7
|
|
80017bc: bc80 pop {r7}
|
|
80017be: 4770 bx lr
|
|
80017c0: e0042000 .word 0xe0042000
|
|
|
|
080017c4 <LL_DBGMCU_EnableDBGStopMode>:
|
|
* in Stop mode even when this bit is enabled
|
|
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
|
|
{
|
|
80017c4: b480 push {r7}
|
|
80017c6: af00 add r7, sp, #0
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
|
80017c8: 4b04 ldr r3, [pc, #16] @ (80017dc <LL_DBGMCU_EnableDBGStopMode+0x18>)
|
|
80017ca: 685b ldr r3, [r3, #4]
|
|
80017cc: 4a03 ldr r2, [pc, #12] @ (80017dc <LL_DBGMCU_EnableDBGStopMode+0x18>)
|
|
80017ce: f043 0302 orr.w r3, r3, #2
|
|
80017d2: 6053 str r3, [r2, #4]
|
|
}
|
|
80017d4: bf00 nop
|
|
80017d6: 46bd mov sp, r7
|
|
80017d8: bc80 pop {r7}
|
|
80017da: 4770 bx lr
|
|
80017dc: e0042000 .word 0xe0042000
|
|
|
|
080017e0 <LL_DBGMCU_EnableDBGStandbyMode>:
|
|
* in Standby mode even when this bit is enabled
|
|
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
|
|
{
|
|
80017e0: b480 push {r7}
|
|
80017e2: af00 add r7, sp, #0
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
|
80017e4: 4b04 ldr r3, [pc, #16] @ (80017f8 <LL_DBGMCU_EnableDBGStandbyMode+0x18>)
|
|
80017e6: 685b ldr r3, [r3, #4]
|
|
80017e8: 4a03 ldr r2, [pc, #12] @ (80017f8 <LL_DBGMCU_EnableDBGStandbyMode+0x18>)
|
|
80017ea: f043 0304 orr.w r3, r3, #4
|
|
80017ee: 6053 str r3, [r2, #4]
|
|
}
|
|
80017f0: bf00 nop
|
|
80017f2: 46bd mov sp, r7
|
|
80017f4: bc80 pop {r7}
|
|
80017f6: 4770 bx lr
|
|
80017f8: e0042000 .word 0xe0042000
|
|
|
|
080017fc <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80017fc: b580 push {r7, lr}
|
|
80017fe: b082 sub sp, #8
|
|
8001800: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001802: 2300 movs r3, #0
|
|
8001804: 71fb strb r3, [r7, #7]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
#ifdef CORE_CM0PLUS
|
|
#else
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001806: 2003 movs r0, #3
|
|
8001808: f000 f914 bl 8001a34 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
#if defined(DUAL_CORE) && defined(CORE_CM0PLUS)
|
|
SystemCoreClock = HAL_RCC_GetHCLK2Freq();
|
|
#else
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
800180c: f002 f8a2 bl 8003954 <HAL_RCC_GetHCLKFreq>
|
|
8001810: 4603 mov r3, r0
|
|
8001812: 4a09 ldr r2, [pc, #36] @ (8001838 <HAL_Init+0x3c>)
|
|
8001814: 6013 str r3, [r2, #0]
|
|
#endif
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8001816: 200f movs r0, #15
|
|
8001818: f7ff f9a8 bl 8000b6c <HAL_InitTick>
|
|
800181c: 4603 mov r3, r0
|
|
800181e: 2b00 cmp r3, #0
|
|
8001820: d002 beq.n 8001828 <HAL_Init+0x2c>
|
|
{
|
|
status = HAL_ERROR;
|
|
8001822: 2301 movs r3, #1
|
|
8001824: 71fb strb r3, [r7, #7]
|
|
8001826: e001 b.n 800182c <HAL_Init+0x30>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001828: f7ff f865 bl 80008f6 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800182c: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
800182e: 4618 mov r0, r3
|
|
8001830: 3708 adds r7, #8
|
|
8001832: 46bd mov sp, r7
|
|
8001834: bd80 pop {r7, pc}
|
|
8001836: bf00 nop
|
|
8001838: 20000000 .word 0x20000000
|
|
|
|
0800183c <HAL_SuspendTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SuspendTick(void)
|
|
{
|
|
800183c: b480 push {r7}
|
|
800183e: af00 add r7, sp, #0
|
|
/* Disable SysTick Interrupt */
|
|
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
|
8001840: 4b04 ldr r3, [pc, #16] @ (8001854 <HAL_SuspendTick+0x18>)
|
|
8001842: 681b ldr r3, [r3, #0]
|
|
8001844: 4a03 ldr r2, [pc, #12] @ (8001854 <HAL_SuspendTick+0x18>)
|
|
8001846: f023 0302 bic.w r3, r3, #2
|
|
800184a: 6013 str r3, [r2, #0]
|
|
}
|
|
800184c: bf00 nop
|
|
800184e: 46bd mov sp, r7
|
|
8001850: bc80 pop {r7}
|
|
8001852: 4770 bx lr
|
|
8001854: e000e010 .word 0xe000e010
|
|
|
|
08001858 <HAL_ResumeTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ResumeTick(void)
|
|
{
|
|
8001858: b480 push {r7}
|
|
800185a: af00 add r7, sp, #0
|
|
/* Enable SysTick Interrupt */
|
|
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
|
800185c: 4b04 ldr r3, [pc, #16] @ (8001870 <HAL_ResumeTick+0x18>)
|
|
800185e: 681b ldr r3, [r3, #0]
|
|
8001860: 4a03 ldr r2, [pc, #12] @ (8001870 <HAL_ResumeTick+0x18>)
|
|
8001862: f043 0302 orr.w r3, r3, #2
|
|
8001866: 6013 str r3, [r2, #0]
|
|
}
|
|
8001868: bf00 nop
|
|
800186a: 46bd mov sp, r7
|
|
800186c: bc80 pop {r7}
|
|
800186e: 4770 bx lr
|
|
8001870: e000e010 .word 0xe000e010
|
|
|
|
08001874 <HAL_DBGMCU_EnableDBGSleepMode>:
|
|
/**
|
|
* @brief Enable the CPU1 Debug Module during SLEEP mode
|
|
* @retval None
|
|
*/
|
|
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
|
{
|
|
8001874: b580 push {r7, lr}
|
|
8001876: af00 add r7, sp, #0
|
|
LL_DBGMCU_EnableDBGSleepMode();
|
|
8001878: f7ff ff96 bl 80017a8 <LL_DBGMCU_EnableDBGSleepMode>
|
|
}
|
|
800187c: bf00 nop
|
|
800187e: bd80 pop {r7, pc}
|
|
|
|
08001880 <HAL_DBGMCU_EnableDBGStopMode>:
|
|
* @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged
|
|
* in Stop mode even when this bit is enabled
|
|
* @retval None
|
|
*/
|
|
void HAL_DBGMCU_EnableDBGStopMode(void)
|
|
{
|
|
8001880: b580 push {r7, lr}
|
|
8001882: af00 add r7, sp, #0
|
|
LL_DBGMCU_EnableDBGStopMode();
|
|
8001884: f7ff ff9e bl 80017c4 <LL_DBGMCU_EnableDBGStopMode>
|
|
}
|
|
8001888: bf00 nop
|
|
800188a: bd80 pop {r7, pc}
|
|
|
|
0800188c <HAL_DBGMCU_EnableDBGStandbyMode>:
|
|
* @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged
|
|
* in Standby mode even when this bit is enabled
|
|
* @retval None
|
|
*/
|
|
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
|
{
|
|
800188c: b580 push {r7, lr}
|
|
800188e: af00 add r7, sp, #0
|
|
LL_DBGMCU_EnableDBGStandbyMode();
|
|
8001890: f7ff ffa6 bl 80017e0 <LL_DBGMCU_EnableDBGStandbyMode>
|
|
}
|
|
8001894: bf00 nop
|
|
8001896: bd80 pop {r7, pc}
|
|
|
|
08001898 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001898: b480 push {r7}
|
|
800189a: b085 sub sp, #20
|
|
800189c: af00 add r7, sp, #0
|
|
800189e: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80018a0: 687b ldr r3, [r7, #4]
|
|
80018a2: f003 0307 and.w r3, r3, #7
|
|
80018a6: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80018a8: 4b0c ldr r3, [pc, #48] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018aa: 68db ldr r3, [r3, #12]
|
|
80018ac: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80018ae: 68ba ldr r2, [r7, #8]
|
|
80018b0: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80018b4: 4013 ands r3, r2
|
|
80018b6: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80018b8: 68fb ldr r3, [r7, #12]
|
|
80018ba: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80018bc: 68bb ldr r3, [r7, #8]
|
|
80018be: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80018c0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80018c4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80018c8: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80018ca: 4a04 ldr r2, [pc, #16] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018cc: 68bb ldr r3, [r7, #8]
|
|
80018ce: 60d3 str r3, [r2, #12]
|
|
}
|
|
80018d0: bf00 nop
|
|
80018d2: 3714 adds r7, #20
|
|
80018d4: 46bd mov sp, r7
|
|
80018d6: bc80 pop {r7}
|
|
80018d8: 4770 bx lr
|
|
80018da: bf00 nop
|
|
80018dc: e000ed00 .word 0xe000ed00
|
|
|
|
080018e0 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80018e0: b480 push {r7}
|
|
80018e2: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80018e4: 4b04 ldr r3, [pc, #16] @ (80018f8 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80018e6: 68db ldr r3, [r3, #12]
|
|
80018e8: 0a1b lsrs r3, r3, #8
|
|
80018ea: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80018ee: 4618 mov r0, r3
|
|
80018f0: 46bd mov sp, r7
|
|
80018f2: bc80 pop {r7}
|
|
80018f4: 4770 bx lr
|
|
80018f6: bf00 nop
|
|
80018f8: e000ed00 .word 0xe000ed00
|
|
|
|
080018fc <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80018fc: b480 push {r7}
|
|
80018fe: b083 sub sp, #12
|
|
8001900: af00 add r7, sp, #0
|
|
8001902: 4603 mov r3, r0
|
|
8001904: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001906: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800190a: 2b00 cmp r3, #0
|
|
800190c: db0b blt.n 8001926 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
800190e: 79fb ldrb r3, [r7, #7]
|
|
8001910: f003 021f and.w r2, r3, #31
|
|
8001914: 4906 ldr r1, [pc, #24] @ (8001930 <__NVIC_EnableIRQ+0x34>)
|
|
8001916: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800191a: 095b lsrs r3, r3, #5
|
|
800191c: 2001 movs r0, #1
|
|
800191e: fa00 f202 lsl.w r2, r0, r2
|
|
8001922: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001926: bf00 nop
|
|
8001928: 370c adds r7, #12
|
|
800192a: 46bd mov sp, r7
|
|
800192c: bc80 pop {r7}
|
|
800192e: 4770 bx lr
|
|
8001930: e000e100 .word 0xe000e100
|
|
|
|
08001934 <__NVIC_DisableIRQ>:
|
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001934: b480 push {r7}
|
|
8001936: b083 sub sp, #12
|
|
8001938: af00 add r7, sp, #0
|
|
800193a: 4603 mov r3, r0
|
|
800193c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800193e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001942: 2b00 cmp r3, #0
|
|
8001944: db12 blt.n 800196c <__NVIC_DisableIRQ+0x38>
|
|
{
|
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8001946: 79fb ldrb r3, [r7, #7]
|
|
8001948: f003 021f and.w r2, r3, #31
|
|
800194c: 490a ldr r1, [pc, #40] @ (8001978 <__NVIC_DisableIRQ+0x44>)
|
|
800194e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001952: 095b lsrs r3, r3, #5
|
|
8001954: 2001 movs r0, #1
|
|
8001956: fa00 f202 lsl.w r2, r0, r2
|
|
800195a: 3320 adds r3, #32
|
|
800195c: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
\details Acts as a special kind of Data Memory Barrier.
|
|
It completes when all explicit memory accesses before this instruction complete.
|
|
*/
|
|
__STATIC_FORCEINLINE void __DSB(void)
|
|
{
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
|
8001960: f3bf 8f4f dsb sy
|
|
}
|
|
8001964: bf00 nop
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|
8001966: f3bf 8f6f isb sy
|
|
}
|
|
800196a: bf00 nop
|
|
__DSB();
|
|
__ISB();
|
|
}
|
|
}
|
|
800196c: bf00 nop
|
|
800196e: 370c adds r7, #12
|
|
8001970: 46bd mov sp, r7
|
|
8001972: bc80 pop {r7}
|
|
8001974: 4770 bx lr
|
|
8001976: bf00 nop
|
|
8001978: e000e100 .word 0xe000e100
|
|
|
|
0800197c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
800197c: b480 push {r7}
|
|
800197e: b083 sub sp, #12
|
|
8001980: af00 add r7, sp, #0
|
|
8001982: 4603 mov r3, r0
|
|
8001984: 6039 str r1, [r7, #0]
|
|
8001986: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001988: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800198c: 2b00 cmp r3, #0
|
|
800198e: db0a blt.n 80019a6 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001990: 683b ldr r3, [r7, #0]
|
|
8001992: b2da uxtb r2, r3
|
|
8001994: 490c ldr r1, [pc, #48] @ (80019c8 <__NVIC_SetPriority+0x4c>)
|
|
8001996: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800199a: 0112 lsls r2, r2, #4
|
|
800199c: b2d2 uxtb r2, r2
|
|
800199e: 440b add r3, r1
|
|
80019a0: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
80019a4: e00a b.n 80019bc <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80019a6: 683b ldr r3, [r7, #0]
|
|
80019a8: b2da uxtb r2, r3
|
|
80019aa: 4908 ldr r1, [pc, #32] @ (80019cc <__NVIC_SetPriority+0x50>)
|
|
80019ac: 79fb ldrb r3, [r7, #7]
|
|
80019ae: f003 030f and.w r3, r3, #15
|
|
80019b2: 3b04 subs r3, #4
|
|
80019b4: 0112 lsls r2, r2, #4
|
|
80019b6: b2d2 uxtb r2, r2
|
|
80019b8: 440b add r3, r1
|
|
80019ba: 761a strb r2, [r3, #24]
|
|
}
|
|
80019bc: bf00 nop
|
|
80019be: 370c adds r7, #12
|
|
80019c0: 46bd mov sp, r7
|
|
80019c2: bc80 pop {r7}
|
|
80019c4: 4770 bx lr
|
|
80019c6: bf00 nop
|
|
80019c8: e000e100 .word 0xe000e100
|
|
80019cc: e000ed00 .word 0xe000ed00
|
|
|
|
080019d0 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80019d0: b480 push {r7}
|
|
80019d2: b089 sub sp, #36 @ 0x24
|
|
80019d4: af00 add r7, sp, #0
|
|
80019d6: 60f8 str r0, [r7, #12]
|
|
80019d8: 60b9 str r1, [r7, #8]
|
|
80019da: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80019dc: 68fb ldr r3, [r7, #12]
|
|
80019de: f003 0307 and.w r3, r3, #7
|
|
80019e2: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80019e4: 69fb ldr r3, [r7, #28]
|
|
80019e6: f1c3 0307 rsb r3, r3, #7
|
|
80019ea: 2b04 cmp r3, #4
|
|
80019ec: bf28 it cs
|
|
80019ee: 2304 movcs r3, #4
|
|
80019f0: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80019f2: 69fb ldr r3, [r7, #28]
|
|
80019f4: 3304 adds r3, #4
|
|
80019f6: 2b06 cmp r3, #6
|
|
80019f8: d902 bls.n 8001a00 <NVIC_EncodePriority+0x30>
|
|
80019fa: 69fb ldr r3, [r7, #28]
|
|
80019fc: 3b03 subs r3, #3
|
|
80019fe: e000 b.n 8001a02 <NVIC_EncodePriority+0x32>
|
|
8001a00: 2300 movs r3, #0
|
|
8001a02: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001a04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8001a08: 69bb ldr r3, [r7, #24]
|
|
8001a0a: fa02 f303 lsl.w r3, r2, r3
|
|
8001a0e: 43da mvns r2, r3
|
|
8001a10: 68bb ldr r3, [r7, #8]
|
|
8001a12: 401a ands r2, r3
|
|
8001a14: 697b ldr r3, [r7, #20]
|
|
8001a16: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8001a18: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8001a1c: 697b ldr r3, [r7, #20]
|
|
8001a1e: fa01 f303 lsl.w r3, r1, r3
|
|
8001a22: 43d9 mvns r1, r3
|
|
8001a24: 687b ldr r3, [r7, #4]
|
|
8001a26: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001a28: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8001a2a: 4618 mov r0, r3
|
|
8001a2c: 3724 adds r7, #36 @ 0x24
|
|
8001a2e: 46bd mov sp, r7
|
|
8001a30: bc80 pop {r7}
|
|
8001a32: 4770 bx lr
|
|
|
|
08001a34 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001a34: b580 push {r7, lr}
|
|
8001a36: b082 sub sp, #8
|
|
8001a38: af00 add r7, sp, #0
|
|
8001a3a: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001a3c: 6878 ldr r0, [r7, #4]
|
|
8001a3e: f7ff ff2b bl 8001898 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001a42: bf00 nop
|
|
8001a44: 3708 adds r7, #8
|
|
8001a46: 46bd mov sp, r7
|
|
8001a48: bd80 pop {r7, pc}
|
|
|
|
08001a4a <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001a4a: b580 push {r7, lr}
|
|
8001a4c: b086 sub sp, #24
|
|
8001a4e: af00 add r7, sp, #0
|
|
8001a50: 4603 mov r3, r0
|
|
8001a52: 60b9 str r1, [r7, #8]
|
|
8001a54: 607a str r2, [r7, #4]
|
|
8001a56: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001a58: f7ff ff42 bl 80018e0 <__NVIC_GetPriorityGrouping>
|
|
8001a5c: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001a5e: 687a ldr r2, [r7, #4]
|
|
8001a60: 68b9 ldr r1, [r7, #8]
|
|
8001a62: 6978 ldr r0, [r7, #20]
|
|
8001a64: f7ff ffb4 bl 80019d0 <NVIC_EncodePriority>
|
|
8001a68: 4602 mov r2, r0
|
|
8001a6a: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001a6e: 4611 mov r1, r2
|
|
8001a70: 4618 mov r0, r3
|
|
8001a72: f7ff ff83 bl 800197c <__NVIC_SetPriority>
|
|
}
|
|
8001a76: bf00 nop
|
|
8001a78: 3718 adds r7, #24
|
|
8001a7a: 46bd mov sp, r7
|
|
8001a7c: bd80 pop {r7, pc}
|
|
|
|
08001a7e <HAL_NVIC_EnableIRQ>:
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer
|
|
* to the appropriate CMSIS device file (stm32wlxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001a7e: b580 push {r7, lr}
|
|
8001a80: b082 sub sp, #8
|
|
8001a82: af00 add r7, sp, #0
|
|
8001a84: 4603 mov r3, r0
|
|
8001a86: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001a88: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001a8c: 4618 mov r0, r3
|
|
8001a8e: f7ff ff35 bl 80018fc <__NVIC_EnableIRQ>
|
|
}
|
|
8001a92: bf00 nop
|
|
8001a94: 3708 adds r7, #8
|
|
8001a96: 46bd mov sp, r7
|
|
8001a98: bd80 pop {r7, pc}
|
|
|
|
08001a9a <HAL_NVIC_DisableIRQ>:
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer
|
|
* to the appropriate CMSIS device file (stm32wlxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001a9a: b580 push {r7, lr}
|
|
8001a9c: b082 sub sp, #8
|
|
8001a9e: af00 add r7, sp, #0
|
|
8001aa0: 4603 mov r3, r0
|
|
8001aa2: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Disable interrupt */
|
|
NVIC_DisableIRQ(IRQn);
|
|
8001aa4: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001aa8: 4618 mov r0, r3
|
|
8001aaa: f7ff ff43 bl 8001934 <__NVIC_DisableIRQ>
|
|
}
|
|
8001aae: bf00 nop
|
|
8001ab0: 3708 adds r7, #8
|
|
8001ab2: 46bd mov sp, r7
|
|
8001ab4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001ab8 <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001ab8: b580 push {r7, lr}
|
|
8001aba: b082 sub sp, #8
|
|
8001abc: af00 add r7, sp, #0
|
|
8001abe: 6078 str r0, [r7, #4]
|
|
/* Check the DMA handle allocation */
|
|
if (hdma == NULL)
|
|
8001ac0: 687b ldr r3, [r7, #4]
|
|
8001ac2: 2b00 cmp r3, #0
|
|
8001ac4: d101 bne.n 8001aca <HAL_DMA_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001ac6: 2301 movs r3, #1
|
|
8001ac8: e08e b.n 8001be8 <HAL_DMA_Init+0x130>
|
|
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
|
|
|
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
|
|
|
|
/* Compute the channel index */
|
|
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
|
8001aca: 687b ldr r3, [r7, #4]
|
|
8001acc: 681b ldr r3, [r3, #0]
|
|
8001ace: 461a mov r2, r3
|
|
8001ad0: 4b47 ldr r3, [pc, #284] @ (8001bf0 <HAL_DMA_Init+0x138>)
|
|
8001ad2: 429a cmp r2, r3
|
|
8001ad4: d80f bhi.n 8001af6 <HAL_DMA_Init+0x3e>
|
|
{
|
|
/* DMA1 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
8001ad6: 687b ldr r3, [r7, #4]
|
|
8001ad8: 681b ldr r3, [r3, #0]
|
|
8001ada: 461a mov r2, r3
|
|
8001adc: 4b45 ldr r3, [pc, #276] @ (8001bf4 <HAL_DMA_Init+0x13c>)
|
|
8001ade: 4413 add r3, r2
|
|
8001ae0: 4a45 ldr r2, [pc, #276] @ (8001bf8 <HAL_DMA_Init+0x140>)
|
|
8001ae2: fba2 2303 umull r2, r3, r2, r3
|
|
8001ae6: 091b lsrs r3, r3, #4
|
|
8001ae8: 009a lsls r2, r3, #2
|
|
8001aea: 687b ldr r3, [r7, #4]
|
|
8001aec: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA1;
|
|
8001aee: 687b ldr r3, [r7, #4]
|
|
8001af0: 4a42 ldr r2, [pc, #264] @ (8001bfc <HAL_DMA_Init+0x144>)
|
|
8001af2: 641a str r2, [r3, #64] @ 0x40
|
|
8001af4: e00e b.n 8001b14 <HAL_DMA_Init+0x5c>
|
|
}
|
|
else
|
|
{
|
|
/* DMA2 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
|
8001af6: 687b ldr r3, [r7, #4]
|
|
8001af8: 681b ldr r3, [r3, #0]
|
|
8001afa: 461a mov r2, r3
|
|
8001afc: 4b40 ldr r3, [pc, #256] @ (8001c00 <HAL_DMA_Init+0x148>)
|
|
8001afe: 4413 add r3, r2
|
|
8001b00: 4a3d ldr r2, [pc, #244] @ (8001bf8 <HAL_DMA_Init+0x140>)
|
|
8001b02: fba2 2303 umull r2, r3, r2, r3
|
|
8001b06: 091b lsrs r3, r3, #4
|
|
8001b08: 009a lsls r2, r3, #2
|
|
8001b0a: 687b ldr r3, [r7, #4]
|
|
8001b0c: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA2;
|
|
8001b0e: 687b ldr r3, [r7, #4]
|
|
8001b10: 4a3c ldr r2, [pc, #240] @ (8001c04 <HAL_DMA_Init+0x14c>)
|
|
8001b12: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8001b14: 687b ldr r3, [r7, #4]
|
|
8001b16: 2202 movs r2, #2
|
|
8001b18: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
|
|
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
|
8001b1c: 687b ldr r3, [r7, #4]
|
|
8001b1e: 681b ldr r3, [r3, #0]
|
|
8001b20: 681b ldr r3, [r3, #0]
|
|
8001b22: 687a ldr r2, [r7, #4]
|
|
8001b24: 6812 ldr r2, [r2, #0]
|
|
8001b26: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
8001b2a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8001b2e: 6013 str r3, [r2, #0]
|
|
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
|
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
|
|
|
|
/* Set the DMA Channel configuration */
|
|
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
|
|
8001b30: 687b ldr r3, [r7, #4]
|
|
8001b32: 681b ldr r3, [r3, #0]
|
|
8001b34: 6819 ldr r1, [r3, #0]
|
|
8001b36: 687b ldr r3, [r7, #4]
|
|
8001b38: 689a ldr r2, [r3, #8]
|
|
8001b3a: 687b ldr r3, [r7, #4]
|
|
8001b3c: 68db ldr r3, [r3, #12]
|
|
8001b3e: 431a orrs r2, r3
|
|
8001b40: 687b ldr r3, [r7, #4]
|
|
8001b42: 691b ldr r3, [r3, #16]
|
|
8001b44: 431a orrs r2, r3
|
|
8001b46: 687b ldr r3, [r7, #4]
|
|
8001b48: 695b ldr r3, [r3, #20]
|
|
8001b4a: 431a orrs r2, r3
|
|
8001b4c: 687b ldr r3, [r7, #4]
|
|
8001b4e: 699b ldr r3, [r3, #24]
|
|
8001b50: 431a orrs r2, r3
|
|
8001b52: 687b ldr r3, [r7, #4]
|
|
8001b54: 69db ldr r3, [r3, #28]
|
|
8001b56: 431a orrs r2, r3
|
|
8001b58: 687b ldr r3, [r7, #4]
|
|
8001b5a: 6a1b ldr r3, [r3, #32]
|
|
8001b5c: 431a orrs r2, r3
|
|
8001b5e: 687b ldr r3, [r7, #4]
|
|
8001b60: 681b ldr r3, [r3, #0]
|
|
8001b62: 430a orrs r2, r1
|
|
8001b64: 601a str r2, [r3, #0]
|
|
hdma->Init.Mode | hdma->Init.Priority));
|
|
|
|
/* Initialize parameters for DMAMUX channel :
|
|
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
|
|
*/
|
|
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
|
8001b66: 6878 ldr r0, [r7, #4]
|
|
8001b68: f000 fb52 bl 8002210 <DMA_CalcDMAMUXChannelBaseAndMask>
|
|
|
|
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
|
8001b6c: 687b ldr r3, [r7, #4]
|
|
8001b6e: 689b ldr r3, [r3, #8]
|
|
8001b70: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
8001b74: d102 bne.n 8001b7c <HAL_DMA_Init+0xc4>
|
|
{
|
|
/* if memory to memory force the request to 0*/
|
|
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
|
|
8001b76: 687b ldr r3, [r7, #4]
|
|
8001b78: 2200 movs r2, #0
|
|
8001b7a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Set peripheral request to DMAMUX channel */
|
|
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
|
|
8001b7c: 687b ldr r3, [r7, #4]
|
|
8001b7e: 685a ldr r2, [r3, #4]
|
|
8001b80: 687b ldr r3, [r7, #4]
|
|
8001b82: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001b84: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8001b88: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001b8a: 687b ldr r3, [r7, #4]
|
|
8001b8c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001b8e: 687a ldr r2, [r7, #4]
|
|
8001b90: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001b92: 605a str r2, [r3, #4]
|
|
|
|
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
|
8001b94: 687b ldr r3, [r7, #4]
|
|
8001b96: 685b ldr r3, [r3, #4]
|
|
8001b98: 2b00 cmp r3, #0
|
|
8001b9a: d010 beq.n 8001bbe <HAL_DMA_Init+0x106>
|
|
8001b9c: 687b ldr r3, [r7, #4]
|
|
8001b9e: 685b ldr r3, [r3, #4]
|
|
8001ba0: 2b04 cmp r3, #4
|
|
8001ba2: d80c bhi.n 8001bbe <HAL_DMA_Init+0x106>
|
|
{
|
|
/* Initialize parameters for DMAMUX request generator :
|
|
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
|
|
*/
|
|
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
|
|
8001ba4: 6878 ldr r0, [r7, #4]
|
|
8001ba6: f000 fb7b bl 80022a0 <DMA_CalcDMAMUXRequestGenBaseAndMask>
|
|
|
|
/* Reset the DMAMUX request generator register*/
|
|
hdma->DMAmuxRequestGen->RGCR = 0U;
|
|
8001baa: 687b ldr r3, [r7, #4]
|
|
8001bac: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001bae: 2200 movs r2, #0
|
|
8001bb0: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001bb2: 687b ldr r3, [r7, #4]
|
|
8001bb4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001bb6: 687a ldr r2, [r7, #4]
|
|
8001bb8: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001bba: 605a str r2, [r3, #4]
|
|
8001bbc: e008 b.n 8001bd0 <HAL_DMA_Init+0x118>
|
|
}
|
|
else
|
|
{
|
|
hdma->DMAmuxRequestGen = NULL;
|
|
8001bbe: 687b ldr r3, [r7, #4]
|
|
8001bc0: 2200 movs r2, #0
|
|
8001bc2: 655a str r2, [r3, #84] @ 0x54
|
|
hdma->DMAmuxRequestGenStatus = NULL;
|
|
8001bc4: 687b ldr r3, [r7, #4]
|
|
8001bc6: 2200 movs r2, #0
|
|
8001bc8: 659a str r2, [r3, #88] @ 0x58
|
|
hdma->DMAmuxRequestGenStatusMask = 0U;
|
|
8001bca: 687b ldr r3, [r7, #4]
|
|
8001bcc: 2200 movs r2, #0
|
|
8001bce: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8001bd0: 687b ldr r3, [r7, #4]
|
|
8001bd2: 2200 movs r2, #0
|
|
8001bd4: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001bd6: 687b ldr r3, [r7, #4]
|
|
8001bd8: 2201 movs r2, #1
|
|
8001bda: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
8001bde: 687b ldr r3, [r7, #4]
|
|
8001be0: 2200 movs r2, #0
|
|
8001be2: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8001be6: 2300 movs r3, #0
|
|
}
|
|
8001be8: 4618 mov r0, r3
|
|
8001bea: 3708 adds r7, #8
|
|
8001bec: 46bd mov sp, r7
|
|
8001bee: bd80 pop {r7, pc}
|
|
8001bf0: 40020407 .word 0x40020407
|
|
8001bf4: bffdfff8 .word 0xbffdfff8
|
|
8001bf8: cccccccd .word 0xcccccccd
|
|
8001bfc: 40020000 .word 0x40020000
|
|
8001c00: bffdfbf8 .word 0xbffdfbf8
|
|
8001c04: 40020400 .word 0x40020400
|
|
|
|
08001c08 <HAL_DMA_DeInit>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001c08: b580 push {r7, lr}
|
|
8001c0a: b082 sub sp, #8
|
|
8001c0c: af00 add r7, sp, #0
|
|
8001c0e: 6078 str r0, [r7, #4]
|
|
/* Check the DMA handle allocation */
|
|
if (NULL == hdma)
|
|
8001c10: 687b ldr r3, [r7, #4]
|
|
8001c12: 2b00 cmp r3, #0
|
|
8001c14: d101 bne.n 8001c1a <HAL_DMA_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c16: 2301 movs r3, #1
|
|
8001c18: e07b b.n 8001d12 <HAL_DMA_DeInit+0x10a>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
|
|
|
/* Disable the selected DMA Channelx */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001c1a: 687b ldr r3, [r7, #4]
|
|
8001c1c: 681b ldr r3, [r3, #0]
|
|
8001c1e: 681a ldr r2, [r3, #0]
|
|
8001c20: 687b ldr r3, [r7, #4]
|
|
8001c22: 681b ldr r3, [r3, #0]
|
|
8001c24: f022 0201 bic.w r2, r2, #1
|
|
8001c28: 601a str r2, [r3, #0]
|
|
|
|
/* Compute the channel index */
|
|
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
|
8001c2a: 687b ldr r3, [r7, #4]
|
|
8001c2c: 681b ldr r3, [r3, #0]
|
|
8001c2e: 461a mov r2, r3
|
|
8001c30: 4b3a ldr r3, [pc, #232] @ (8001d1c <HAL_DMA_DeInit+0x114>)
|
|
8001c32: 429a cmp r2, r3
|
|
8001c34: d80f bhi.n 8001c56 <HAL_DMA_DeInit+0x4e>
|
|
{
|
|
/* DMA1 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
8001c36: 687b ldr r3, [r7, #4]
|
|
8001c38: 681b ldr r3, [r3, #0]
|
|
8001c3a: 461a mov r2, r3
|
|
8001c3c: 4b38 ldr r3, [pc, #224] @ (8001d20 <HAL_DMA_DeInit+0x118>)
|
|
8001c3e: 4413 add r3, r2
|
|
8001c40: 4a38 ldr r2, [pc, #224] @ (8001d24 <HAL_DMA_DeInit+0x11c>)
|
|
8001c42: fba2 2303 umull r2, r3, r2, r3
|
|
8001c46: 091b lsrs r3, r3, #4
|
|
8001c48: 009a lsls r2, r3, #2
|
|
8001c4a: 687b ldr r3, [r7, #4]
|
|
8001c4c: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA1;
|
|
8001c4e: 687b ldr r3, [r7, #4]
|
|
8001c50: 4a35 ldr r2, [pc, #212] @ (8001d28 <HAL_DMA_DeInit+0x120>)
|
|
8001c52: 641a str r2, [r3, #64] @ 0x40
|
|
8001c54: e00e b.n 8001c74 <HAL_DMA_DeInit+0x6c>
|
|
}
|
|
else
|
|
{
|
|
/* DMA2 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
|
8001c56: 687b ldr r3, [r7, #4]
|
|
8001c58: 681b ldr r3, [r3, #0]
|
|
8001c5a: 461a mov r2, r3
|
|
8001c5c: 4b33 ldr r3, [pc, #204] @ (8001d2c <HAL_DMA_DeInit+0x124>)
|
|
8001c5e: 4413 add r3, r2
|
|
8001c60: 4a30 ldr r2, [pc, #192] @ (8001d24 <HAL_DMA_DeInit+0x11c>)
|
|
8001c62: fba2 2303 umull r2, r3, r2, r3
|
|
8001c66: 091b lsrs r3, r3, #4
|
|
8001c68: 009a lsls r2, r3, #2
|
|
8001c6a: 687b ldr r3, [r7, #4]
|
|
8001c6c: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA2;
|
|
8001c6e: 687b ldr r3, [r7, #4]
|
|
8001c70: 4a2f ldr r2, [pc, #188] @ (8001d30 <HAL_DMA_DeInit+0x128>)
|
|
8001c72: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
/* Reset DMA Channel control register */
|
|
hdma->Instance->CCR = 0U;
|
|
8001c74: 687b ldr r3, [r7, #4]
|
|
8001c76: 681b ldr r3, [r3, #0]
|
|
8001c78: 2200 movs r2, #0
|
|
8001c7a: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
8001c7e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001c80: f003 021c and.w r2, r3, #28
|
|
8001c84: 687b ldr r3, [r7, #4]
|
|
8001c86: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001c88: 2101 movs r1, #1
|
|
8001c8a: fa01 f202 lsl.w r2, r1, r2
|
|
8001c8e: 605a str r2, [r3, #4]
|
|
|
|
/* Initialize parameters for DMAMUX channel :
|
|
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
|
|
|
|
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
|
8001c90: 6878 ldr r0, [r7, #4]
|
|
8001c92: f000 fabd bl 8002210 <DMA_CalcDMAMUXChannelBaseAndMask>
|
|
|
|
/* Reset the DMAMUX channel that corresponds to the DMA channel */
|
|
hdma->DMAmuxChannel->CCR = 0U;
|
|
8001c96: 687b ldr r3, [r7, #4]
|
|
8001c98: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001c9a: 2200 movs r2, #0
|
|
8001c9c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001c9e: 687b ldr r3, [r7, #4]
|
|
8001ca0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001ca2: 687a ldr r2, [r7, #4]
|
|
8001ca4: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001ca6: 605a str r2, [r3, #4]
|
|
|
|
/* Reset Request generator parameters if any */
|
|
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
|
8001ca8: 687b ldr r3, [r7, #4]
|
|
8001caa: 685b ldr r3, [r3, #4]
|
|
8001cac: 2b00 cmp r3, #0
|
|
8001cae: d00f beq.n 8001cd0 <HAL_DMA_DeInit+0xc8>
|
|
8001cb0: 687b ldr r3, [r7, #4]
|
|
8001cb2: 685b ldr r3, [r3, #4]
|
|
8001cb4: 2b04 cmp r3, #4
|
|
8001cb6: d80b bhi.n 8001cd0 <HAL_DMA_DeInit+0xc8>
|
|
{
|
|
/* Initialize parameters for DMAMUX request generator :
|
|
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
|
|
*/
|
|
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
|
|
8001cb8: 6878 ldr r0, [r7, #4]
|
|
8001cba: f000 faf1 bl 80022a0 <DMA_CalcDMAMUXRequestGenBaseAndMask>
|
|
|
|
/* Reset the DMAMUX request generator register*/
|
|
hdma->DMAmuxRequestGen->RGCR = 0U;
|
|
8001cbe: 687b ldr r3, [r7, #4]
|
|
8001cc0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001cc2: 2200 movs r2, #0
|
|
8001cc4: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001cc6: 687b ldr r3, [r7, #4]
|
|
8001cc8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001cca: 687a ldr r2, [r7, #4]
|
|
8001ccc: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001cce: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
hdma->DMAmuxRequestGen = NULL;
|
|
8001cd0: 687b ldr r3, [r7, #4]
|
|
8001cd2: 2200 movs r2, #0
|
|
8001cd4: 655a str r2, [r3, #84] @ 0x54
|
|
hdma->DMAmuxRequestGenStatus = NULL;
|
|
8001cd6: 687b ldr r3, [r7, #4]
|
|
8001cd8: 2200 movs r2, #0
|
|
8001cda: 659a str r2, [r3, #88] @ 0x58
|
|
hdma->DMAmuxRequestGenStatusMask = 0U;
|
|
8001cdc: 687b ldr r3, [r7, #4]
|
|
8001cde: 2200 movs r2, #0
|
|
8001ce0: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Clean callbacks */
|
|
hdma->XferCpltCallback = NULL;
|
|
8001ce2: 687b ldr r3, [r7, #4]
|
|
8001ce4: 2200 movs r2, #0
|
|
8001ce6: 62da str r2, [r3, #44] @ 0x2c
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
8001ce8: 687b ldr r3, [r7, #4]
|
|
8001cea: 2200 movs r2, #0
|
|
8001cec: 631a str r2, [r3, #48] @ 0x30
|
|
hdma->XferErrorCallback = NULL;
|
|
8001cee: 687b ldr r3, [r7, #4]
|
|
8001cf0: 2200 movs r2, #0
|
|
8001cf2: 635a str r2, [r3, #52] @ 0x34
|
|
hdma->XferAbortCallback = NULL;
|
|
8001cf4: 687b ldr r3, [r7, #4]
|
|
8001cf6: 2200 movs r2, #0
|
|
8001cf8: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8001cfa: 687b ldr r3, [r7, #4]
|
|
8001cfc: 2200 movs r2, #0
|
|
8001cfe: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the DMA state */
|
|
hdma->State = HAL_DMA_STATE_RESET;
|
|
8001d00: 687b ldr r3, [r7, #4]
|
|
8001d02: 2200 movs r2, #0
|
|
8001d04: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
8001d08: 687b ldr r3, [r7, #4]
|
|
8001d0a: 2200 movs r2, #0
|
|
8001d0c: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8001d10: 2300 movs r3, #0
|
|
}
|
|
8001d12: 4618 mov r0, r3
|
|
8001d14: 3708 adds r7, #8
|
|
8001d16: 46bd mov sp, r7
|
|
8001d18: bd80 pop {r7, pc}
|
|
8001d1a: bf00 nop
|
|
8001d1c: 40020407 .word 0x40020407
|
|
8001d20: bffdfff8 .word 0xbffdfff8
|
|
8001d24: cccccccd .word 0xcccccccd
|
|
8001d28: 40020000 .word 0x40020000
|
|
8001d2c: bffdfbf8 .word 0xbffdfbf8
|
|
8001d30: 40020400 .word 0x40020400
|
|
|
|
08001d34 <HAL_DMA_Start_IT>:
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
|
|
uint32_t DataLength)
|
|
{
|
|
8001d34: b580 push {r7, lr}
|
|
8001d36: b086 sub sp, #24
|
|
8001d38: af00 add r7, sp, #0
|
|
8001d3a: 60f8 str r0, [r7, #12]
|
|
8001d3c: 60b9 str r1, [r7, #8]
|
|
8001d3e: 607a str r2, [r7, #4]
|
|
8001d40: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001d42: 2300 movs r3, #0
|
|
8001d44: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
8001d46: 68fb ldr r3, [r7, #12]
|
|
8001d48: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8001d4c: 2b01 cmp r3, #1
|
|
8001d4e: d101 bne.n 8001d54 <HAL_DMA_Start_IT+0x20>
|
|
8001d50: 2302 movs r3, #2
|
|
8001d52: e069 b.n 8001e28 <HAL_DMA_Start_IT+0xf4>
|
|
8001d54: 68fb ldr r3, [r7, #12]
|
|
8001d56: 2201 movs r2, #1
|
|
8001d58: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (hdma->State == HAL_DMA_STATE_READY)
|
|
8001d5c: 68fb ldr r3, [r7, #12]
|
|
8001d5e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8001d62: b2db uxtb r3, r3
|
|
8001d64: 2b01 cmp r3, #1
|
|
8001d66: d155 bne.n 8001e14 <HAL_DMA_Start_IT+0xe0>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8001d68: 68fb ldr r3, [r7, #12]
|
|
8001d6a: 2202 movs r2, #2
|
|
8001d6c: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8001d70: 68fb ldr r3, [r7, #12]
|
|
8001d72: 2200 movs r2, #0
|
|
8001d74: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001d76: 68fb ldr r3, [r7, #12]
|
|
8001d78: 681b ldr r3, [r3, #0]
|
|
8001d7a: 681a ldr r2, [r3, #0]
|
|
8001d7c: 68fb ldr r3, [r7, #12]
|
|
8001d7e: 681b ldr r3, [r3, #0]
|
|
8001d80: f022 0201 bic.w r2, r2, #1
|
|
8001d84: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source, destination address and the data length & clear flags*/
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
8001d86: 683b ldr r3, [r7, #0]
|
|
8001d88: 687a ldr r2, [r7, #4]
|
|
8001d8a: 68b9 ldr r1, [r7, #8]
|
|
8001d8c: 68f8 ldr r0, [r7, #12]
|
|
8001d8e: f000 fa02 bl 8002196 <DMA_SetConfig>
|
|
|
|
/* Enable the transfer complete interrupt */
|
|
/* Enable the transfer Error interrupt */
|
|
if (NULL != hdma->XferHalfCpltCallback)
|
|
8001d92: 68fb ldr r3, [r7, #12]
|
|
8001d94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001d96: 2b00 cmp r3, #0
|
|
8001d98: d008 beq.n 8001dac <HAL_DMA_Start_IT+0x78>
|
|
{
|
|
/* Enable the Half transfer complete interrupt as well */
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8001d9a: 68fb ldr r3, [r7, #12]
|
|
8001d9c: 681b ldr r3, [r3, #0]
|
|
8001d9e: 681a ldr r2, [r3, #0]
|
|
8001da0: 68fb ldr r3, [r7, #12]
|
|
8001da2: 681b ldr r3, [r3, #0]
|
|
8001da4: f042 020e orr.w r2, r2, #14
|
|
8001da8: 601a str r2, [r3, #0]
|
|
8001daa: e00f b.n 8001dcc <HAL_DMA_Start_IT+0x98>
|
|
}
|
|
else
|
|
{
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
8001dac: 68fb ldr r3, [r7, #12]
|
|
8001dae: 681b ldr r3, [r3, #0]
|
|
8001db0: 681a ldr r2, [r3, #0]
|
|
8001db2: 68fb ldr r3, [r7, #12]
|
|
8001db4: 681b ldr r3, [r3, #0]
|
|
8001db6: f022 0204 bic.w r2, r2, #4
|
|
8001dba: 601a str r2, [r3, #0]
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
|
8001dbc: 68fb ldr r3, [r7, #12]
|
|
8001dbe: 681b ldr r3, [r3, #0]
|
|
8001dc0: 681a ldr r2, [r3, #0]
|
|
8001dc2: 68fb ldr r3, [r7, #12]
|
|
8001dc4: 681b ldr r3, [r3, #0]
|
|
8001dc6: f042 020a orr.w r2, r2, #10
|
|
8001dca: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Check if DMAMUX Synchronization is enabled*/
|
|
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
|
8001dcc: 68fb ldr r3, [r7, #12]
|
|
8001dce: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001dd0: 681b ldr r3, [r3, #0]
|
|
8001dd2: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001dd6: 2b00 cmp r3, #0
|
|
8001dd8: d007 beq.n 8001dea <HAL_DMA_Start_IT+0xb6>
|
|
{
|
|
/* Enable DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
|
8001dda: 68fb ldr r3, [r7, #12]
|
|
8001ddc: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001dde: 681a ldr r2, [r3, #0]
|
|
8001de0: 68fb ldr r3, [r7, #12]
|
|
8001de2: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001de4: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8001de8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if (hdma->DMAmuxRequestGen != NULL)
|
|
8001dea: 68fb ldr r3, [r7, #12]
|
|
8001dec: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001dee: 2b00 cmp r3, #0
|
|
8001df0: d007 beq.n 8001e02 <HAL_DMA_Start_IT+0xce>
|
|
{
|
|
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
|
|
/* enable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
|
8001df2: 68fb ldr r3, [r7, #12]
|
|
8001df4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001df6: 681a ldr r2, [r3, #0]
|
|
8001df8: 68fb ldr r3, [r7, #12]
|
|
8001dfa: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001dfc: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8001e00: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8001e02: 68fb ldr r3, [r7, #12]
|
|
8001e04: 681b ldr r3, [r3, #0]
|
|
8001e06: 681a ldr r2, [r3, #0]
|
|
8001e08: 68fb ldr r3, [r7, #12]
|
|
8001e0a: 681b ldr r3, [r3, #0]
|
|
8001e0c: f042 0201 orr.w r2, r2, #1
|
|
8001e10: 601a str r2, [r3, #0]
|
|
8001e12: e008 b.n 8001e26 <HAL_DMA_Start_IT+0xf2>
|
|
}
|
|
else
|
|
{
|
|
/* Change the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
|
8001e14: 68fb ldr r3, [r7, #12]
|
|
8001e16: 2280 movs r2, #128 @ 0x80
|
|
8001e18: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001e1a: 68fb ldr r3, [r7, #12]
|
|
8001e1c: 2200 movs r2, #0
|
|
8001e1e: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Return error status */
|
|
status = HAL_ERROR;
|
|
8001e22: 2301 movs r3, #1
|
|
8001e24: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8001e26: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001e28: 4618 mov r0, r3
|
|
8001e2a: 3718 adds r7, #24
|
|
8001e2c: 46bd mov sp, r7
|
|
8001e2e: bd80 pop {r7, pc}
|
|
|
|
08001e30 <HAL_DMA_Abort>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001e30: b480 push {r7}
|
|
8001e32: b083 sub sp, #12
|
|
8001e34: af00 add r7, sp, #0
|
|
8001e36: 6078 str r0, [r7, #4]
|
|
/* Check the DMA peripheral handle */
|
|
if (NULL == hdma)
|
|
8001e38: 687b ldr r3, [r7, #4]
|
|
8001e3a: 2b00 cmp r3, #0
|
|
8001e3c: d101 bne.n 8001e42 <HAL_DMA_Abort+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001e3e: 2301 movs r3, #1
|
|
8001e40: e04f b.n 8001ee2 <HAL_DMA_Abort+0xb2>
|
|
}
|
|
|
|
/* Check the DMA peripheral state */
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8001e42: 687b ldr r3, [r7, #4]
|
|
8001e44: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8001e48: b2db uxtb r3, r3
|
|
8001e4a: 2b02 cmp r3, #2
|
|
8001e4c: d008 beq.n 8001e60 <HAL_DMA_Abort+0x30>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001e4e: 687b ldr r3, [r7, #4]
|
|
8001e50: 2204 movs r2, #4
|
|
8001e52: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001e54: 687b ldr r3, [r7, #4]
|
|
8001e56: 2200 movs r2, #0
|
|
8001e58: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8001e5c: 2301 movs r3, #1
|
|
8001e5e: e040 b.n 8001ee2 <HAL_DMA_Abort+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001e60: 687b ldr r3, [r7, #4]
|
|
8001e62: 681b ldr r3, [r3, #0]
|
|
8001e64: 681a ldr r2, [r3, #0]
|
|
8001e66: 687b ldr r3, [r7, #4]
|
|
8001e68: 681b ldr r3, [r3, #0]
|
|
8001e6a: f022 0201 bic.w r2, r2, #1
|
|
8001e6e: 601a str r2, [r3, #0]
|
|
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8001e70: 687b ldr r3, [r7, #4]
|
|
8001e72: 681b ldr r3, [r3, #0]
|
|
8001e74: 681a ldr r2, [r3, #0]
|
|
8001e76: 687b ldr r3, [r7, #4]
|
|
8001e78: 681b ldr r3, [r3, #0]
|
|
8001e7a: f022 020e bic.w r2, r2, #14
|
|
8001e7e: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8001e80: 687b ldr r3, [r7, #4]
|
|
8001e82: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001e84: 681a ldr r2, [r3, #0]
|
|
8001e86: 687b ldr r3, [r7, #4]
|
|
8001e88: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001e8a: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001e8e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8001e90: 687b ldr r3, [r7, #4]
|
|
8001e92: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001e94: f003 021c and.w r2, r3, #28
|
|
8001e98: 687b ldr r3, [r7, #4]
|
|
8001e9a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001e9c: 2101 movs r1, #1
|
|
8001e9e: fa01 f202 lsl.w r2, r1, r2
|
|
8001ea2: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001ea4: 687b ldr r3, [r7, #4]
|
|
8001ea6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001ea8: 687a ldr r2, [r7, #4]
|
|
8001eaa: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001eac: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != NULL)
|
|
8001eae: 687b ldr r3, [r7, #4]
|
|
8001eb0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001eb2: 2b00 cmp r3, #0
|
|
8001eb4: d00c beq.n 8001ed0 <HAL_DMA_Abort+0xa0>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8001eb6: 687b ldr r3, [r7, #4]
|
|
8001eb8: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001eba: 681a ldr r2, [r3, #0]
|
|
8001ebc: 687b ldr r3, [r7, #4]
|
|
8001ebe: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001ec0: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001ec4: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001ec6: 687b ldr r3, [r7, #4]
|
|
8001ec8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001eca: 687a ldr r2, [r7, #4]
|
|
8001ecc: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001ece: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001ed0: 687b ldr r3, [r7, #4]
|
|
8001ed2: 2201 movs r2, #1
|
|
8001ed4: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001ed8: 687b ldr r3, [r7, #4]
|
|
8001eda: 2200 movs r2, #0
|
|
8001edc: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001ee0: 2300 movs r3, #0
|
|
}
|
|
8001ee2: 4618 mov r0, r3
|
|
8001ee4: 370c adds r7, #12
|
|
8001ee6: 46bd mov sp, r7
|
|
8001ee8: bc80 pop {r7}
|
|
8001eea: 4770 bx lr
|
|
|
|
08001eec <HAL_DMA_Abort_IT>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001eec: b580 push {r7, lr}
|
|
8001eee: b084 sub sp, #16
|
|
8001ef0: af00 add r7, sp, #0
|
|
8001ef2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001ef4: 2300 movs r3, #0
|
|
8001ef6: 73fb strb r3, [r7, #15]
|
|
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8001ef8: 687b ldr r3, [r7, #4]
|
|
8001efa: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8001efe: b2db uxtb r3, r3
|
|
8001f00: 2b02 cmp r3, #2
|
|
8001f02: d005 beq.n 8001f10 <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001f04: 687b ldr r3, [r7, #4]
|
|
8001f06: 2204 movs r2, #4
|
|
8001f08: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8001f0a: 2301 movs r3, #1
|
|
8001f0c: 73fb strb r3, [r7, #15]
|
|
8001f0e: e047 b.n 8001fa0 <HAL_DMA_Abort_IT+0xb4>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001f10: 687b ldr r3, [r7, #4]
|
|
8001f12: 681b ldr r3, [r3, #0]
|
|
8001f14: 681a ldr r2, [r3, #0]
|
|
8001f16: 687b ldr r3, [r7, #4]
|
|
8001f18: 681b ldr r3, [r3, #0]
|
|
8001f1a: f022 0201 bic.w r2, r2, #1
|
|
8001f1e: 601a str r2, [r3, #0]
|
|
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8001f20: 687b ldr r3, [r7, #4]
|
|
8001f22: 681b ldr r3, [r3, #0]
|
|
8001f24: 681a ldr r2, [r3, #0]
|
|
8001f26: 687b ldr r3, [r7, #4]
|
|
8001f28: 681b ldr r3, [r3, #0]
|
|
8001f2a: f022 020e bic.w r2, r2, #14
|
|
8001f2e: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8001f30: 687b ldr r3, [r7, #4]
|
|
8001f32: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001f34: 681a ldr r2, [r3, #0]
|
|
8001f36: 687b ldr r3, [r7, #4]
|
|
8001f38: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001f3a: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001f3e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8001f40: 687b ldr r3, [r7, #4]
|
|
8001f42: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001f44: f003 021c and.w r2, r3, #28
|
|
8001f48: 687b ldr r3, [r7, #4]
|
|
8001f4a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001f4c: 2101 movs r1, #1
|
|
8001f4e: fa01 f202 lsl.w r2, r1, r2
|
|
8001f52: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001f54: 687b ldr r3, [r7, #4]
|
|
8001f56: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001f58: 687a ldr r2, [r7, #4]
|
|
8001f5a: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001f5c: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != NULL)
|
|
8001f5e: 687b ldr r3, [r7, #4]
|
|
8001f60: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001f62: 2b00 cmp r3, #0
|
|
8001f64: d00c beq.n 8001f80 <HAL_DMA_Abort_IT+0x94>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8001f66: 687b ldr r3, [r7, #4]
|
|
8001f68: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001f6a: 681a ldr r2, [r3, #0]
|
|
8001f6c: 687b ldr r3, [r7, #4]
|
|
8001f6e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001f70: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001f74: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001f76: 687b ldr r3, [r7, #4]
|
|
8001f78: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001f7a: 687a ldr r2, [r7, #4]
|
|
8001f7c: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001f7e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001f80: 687b ldr r3, [r7, #4]
|
|
8001f82: 2201 movs r2, #1
|
|
8001f84: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001f88: 687b ldr r3, [r7, #4]
|
|
8001f8a: 2200 movs r2, #0
|
|
8001f8c: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8001f90: 687b ldr r3, [r7, #4]
|
|
8001f92: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001f94: 2b00 cmp r3, #0
|
|
8001f96: d003 beq.n 8001fa0 <HAL_DMA_Abort_IT+0xb4>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
8001f98: 687b ldr r3, [r7, #4]
|
|
8001f9a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001f9c: 6878 ldr r0, [r7, #4]
|
|
8001f9e: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
8001fa0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001fa2: 4618 mov r0, r3
|
|
8001fa4: 3710 adds r7, #16
|
|
8001fa6: 46bd mov sp, r7
|
|
8001fa8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001fac <HAL_DMA_IRQHandler>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001fac: b580 push {r7, lr}
|
|
8001fae: b084 sub sp, #16
|
|
8001fb0: af00 add r7, sp, #0
|
|
8001fb2: 6078 str r0, [r7, #4]
|
|
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
|
8001fb4: 687b ldr r3, [r7, #4]
|
|
8001fb6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001fb8: 681b ldr r3, [r3, #0]
|
|
8001fba: 60fb str r3, [r7, #12]
|
|
uint32_t source_it = hdma->Instance->CCR;
|
|
8001fbc: 687b ldr r3, [r7, #4]
|
|
8001fbe: 681b ldr r3, [r3, #0]
|
|
8001fc0: 681b ldr r3, [r3, #0]
|
|
8001fc2: 60bb str r3, [r7, #8]
|
|
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
|
8001fc4: 687b ldr r3, [r7, #4]
|
|
8001fc6: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001fc8: f003 031c and.w r3, r3, #28
|
|
8001fcc: 2204 movs r2, #4
|
|
8001fce: 409a lsls r2, r3
|
|
8001fd0: 68fb ldr r3, [r7, #12]
|
|
8001fd2: 4013 ands r3, r2
|
|
8001fd4: 2b00 cmp r3, #0
|
|
8001fd6: d027 beq.n 8002028 <HAL_DMA_IRQHandler+0x7c>
|
|
8001fd8: 68bb ldr r3, [r7, #8]
|
|
8001fda: f003 0304 and.w r3, r3, #4
|
|
8001fde: 2b00 cmp r3, #0
|
|
8001fe0: d022 beq.n 8002028 <HAL_DMA_IRQHandler+0x7c>
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
8001fe2: 687b ldr r3, [r7, #4]
|
|
8001fe4: 681b ldr r3, [r3, #0]
|
|
8001fe6: 681b ldr r3, [r3, #0]
|
|
8001fe8: f003 0320 and.w r3, r3, #32
|
|
8001fec: 2b00 cmp r3, #0
|
|
8001fee: d107 bne.n 8002000 <HAL_DMA_IRQHandler+0x54>
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
8001ff0: 687b ldr r3, [r7, #4]
|
|
8001ff2: 681b ldr r3, [r3, #0]
|
|
8001ff4: 681a ldr r2, [r3, #0]
|
|
8001ff6: 687b ldr r3, [r7, #4]
|
|
8001ff8: 681b ldr r3, [r3, #0]
|
|
8001ffa: f022 0204 bic.w r2, r2, #4
|
|
8001ffe: 601a str r2, [r3, #0]
|
|
}
|
|
/* Clear the half transfer complete flag */
|
|
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
|
8002000: 687b ldr r3, [r7, #4]
|
|
8002002: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002004: f003 021c and.w r2, r3, #28
|
|
8002008: 687b ldr r3, [r7, #4]
|
|
800200a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800200c: 2104 movs r1, #4
|
|
800200e: fa01 f202 lsl.w r2, r1, r2
|
|
8002012: 605a str r2, [r3, #4]
|
|
|
|
/* DMA peripheral state is not updated in Half Transfer */
|
|
/* but in Transfer Complete case */
|
|
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
8002014: 687b ldr r3, [r7, #4]
|
|
8002016: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002018: 2b00 cmp r3, #0
|
|
800201a: f000 8081 beq.w 8002120 <HAL_DMA_IRQHandler+0x174>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
800201e: 687b ldr r3, [r7, #4]
|
|
8002020: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002022: 6878 ldr r0, [r7, #4]
|
|
8002024: 4798 blx r3
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
8002026: e07b b.n 8002120 <HAL_DMA_IRQHandler+0x174>
|
|
}
|
|
}
|
|
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
|
|
8002028: 687b ldr r3, [r7, #4]
|
|
800202a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800202c: f003 031c and.w r3, r3, #28
|
|
8002030: 2202 movs r2, #2
|
|
8002032: 409a lsls r2, r3
|
|
8002034: 68fb ldr r3, [r7, #12]
|
|
8002036: 4013 ands r3, r2
|
|
8002038: 2b00 cmp r3, #0
|
|
800203a: d03d beq.n 80020b8 <HAL_DMA_IRQHandler+0x10c>
|
|
800203c: 68bb ldr r3, [r7, #8]
|
|
800203e: f003 0302 and.w r3, r3, #2
|
|
8002042: 2b00 cmp r3, #0
|
|
8002044: d038 beq.n 80020b8 <HAL_DMA_IRQHandler+0x10c>
|
|
{
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
8002046: 687b ldr r3, [r7, #4]
|
|
8002048: 681b ldr r3, [r3, #0]
|
|
800204a: 681b ldr r3, [r3, #0]
|
|
800204c: f003 0320 and.w r3, r3, #32
|
|
8002050: 2b00 cmp r3, #0
|
|
8002052: d10b bne.n 800206c <HAL_DMA_IRQHandler+0xc0>
|
|
{
|
|
/* Disable the transfer complete and error interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
|
8002054: 687b ldr r3, [r7, #4]
|
|
8002056: 681b ldr r3, [r3, #0]
|
|
8002058: 681a ldr r2, [r3, #0]
|
|
800205a: 687b ldr r3, [r7, #4]
|
|
800205c: 681b ldr r3, [r3, #0]
|
|
800205e: f022 020a bic.w r2, r2, #10
|
|
8002062: 601a str r2, [r3, #0]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002064: 687b ldr r3, [r7, #4]
|
|
8002066: 2201 movs r2, #1
|
|
8002068: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
}
|
|
/* Clear the transfer complete flag */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
|
|
800206c: 687b ldr r3, [r7, #4]
|
|
800206e: 681b ldr r3, [r3, #0]
|
|
8002070: 461a mov r2, r3
|
|
8002072: 4b2e ldr r3, [pc, #184] @ (800212c <HAL_DMA_IRQHandler+0x180>)
|
|
8002074: 429a cmp r2, r3
|
|
8002076: d909 bls.n 800208c <HAL_DMA_IRQHandler+0xe0>
|
|
8002078: 687b ldr r3, [r7, #4]
|
|
800207a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800207c: f003 031c and.w r3, r3, #28
|
|
8002080: 4a2b ldr r2, [pc, #172] @ (8002130 <HAL_DMA_IRQHandler+0x184>)
|
|
8002082: 2102 movs r1, #2
|
|
8002084: fa01 f303 lsl.w r3, r1, r3
|
|
8002088: 6053 str r3, [r2, #4]
|
|
800208a: e008 b.n 800209e <HAL_DMA_IRQHandler+0xf2>
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
800208e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002090: f003 031c and.w r3, r3, #28
|
|
8002094: 4a27 ldr r2, [pc, #156] @ (8002134 <HAL_DMA_IRQHandler+0x188>)
|
|
8002096: 2102 movs r1, #2
|
|
8002098: fa01 f303 lsl.w r3, r1, r3
|
|
800209c: 6053 str r3, [r2, #4]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800209e: 687b ldr r3, [r7, #4]
|
|
80020a0: 2200 movs r2, #0
|
|
80020a2: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (hdma->XferCpltCallback != NULL)
|
|
80020a6: 687b ldr r3, [r7, #4]
|
|
80020a8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80020aa: 2b00 cmp r3, #0
|
|
80020ac: d038 beq.n 8002120 <HAL_DMA_IRQHandler+0x174>
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
80020ae: 687b ldr r3, [r7, #4]
|
|
80020b0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80020b2: 6878 ldr r0, [r7, #4]
|
|
80020b4: 4798 blx r3
|
|
if (hdma->XferCpltCallback != NULL)
|
|
80020b6: e033 b.n 8002120 <HAL_DMA_IRQHandler+0x174>
|
|
}
|
|
}
|
|
|
|
/* Transfer Error Interrupt management **************************************/
|
|
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
|
|
80020b8: 687b ldr r3, [r7, #4]
|
|
80020ba: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80020bc: f003 031c and.w r3, r3, #28
|
|
80020c0: 2208 movs r2, #8
|
|
80020c2: 409a lsls r2, r3
|
|
80020c4: 68fb ldr r3, [r7, #12]
|
|
80020c6: 4013 ands r3, r2
|
|
80020c8: 2b00 cmp r3, #0
|
|
80020ca: d02a beq.n 8002122 <HAL_DMA_IRQHandler+0x176>
|
|
80020cc: 68bb ldr r3, [r7, #8]
|
|
80020ce: f003 0308 and.w r3, r3, #8
|
|
80020d2: 2b00 cmp r3, #0
|
|
80020d4: d025 beq.n 8002122 <HAL_DMA_IRQHandler+0x176>
|
|
{
|
|
/* When a DMA transfer error occurs */
|
|
/* A hardware clear of its EN bits is performed */
|
|
/* Disable ALL DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
80020d6: 687b ldr r3, [r7, #4]
|
|
80020d8: 681b ldr r3, [r3, #0]
|
|
80020da: 681a ldr r2, [r3, #0]
|
|
80020dc: 687b ldr r3, [r7, #4]
|
|
80020de: 681b ldr r3, [r3, #0]
|
|
80020e0: f022 020e bic.w r2, r2, #14
|
|
80020e4: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
80020e6: 687b ldr r3, [r7, #4]
|
|
80020e8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80020ea: f003 021c and.w r2, r3, #28
|
|
80020ee: 687b ldr r3, [r7, #4]
|
|
80020f0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80020f2: 2101 movs r1, #1
|
|
80020f4: fa01 f202 lsl.w r2, r1, r2
|
|
80020f8: 605a str r2, [r3, #4]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
|
80020fa: 687b ldr r3, [r7, #4]
|
|
80020fc: 2201 movs r2, #1
|
|
80020fe: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002100: 687b ldr r3, [r7, #4]
|
|
8002102: 2201 movs r2, #1
|
|
8002104: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002108: 687b ldr r3, [r7, #4]
|
|
800210a: 2200 movs r2, #0
|
|
800210c: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (hdma->XferErrorCallback != NULL)
|
|
8002110: 687b ldr r3, [r7, #4]
|
|
8002112: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8002114: 2b00 cmp r3, #0
|
|
8002116: d004 beq.n 8002122 <HAL_DMA_IRQHandler+0x176>
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
8002118: 687b ldr r3, [r7, #4]
|
|
800211a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800211c: 6878 ldr r0, [r7, #4]
|
|
800211e: 4798 blx r3
|
|
}
|
|
else
|
|
{
|
|
/* Nothing To Do */
|
|
}
|
|
return;
|
|
8002120: bf00 nop
|
|
8002122: bf00 nop
|
|
}
|
|
8002124: 3710 adds r7, #16
|
|
8002126: 46bd mov sp, r7
|
|
8002128: bd80 pop {r7, pc}
|
|
800212a: bf00 nop
|
|
800212c: 40020080 .word 0x40020080
|
|
8002130: 40020400 .word 0x40020400
|
|
8002134: 40020000 .word 0x40020000
|
|
|
|
08002138 <HAL_DMA_ConfigChannelAttributes>:
|
|
* @param ChannelAttributes specifies the DMA channel secure/privilege attributes.
|
|
* This parameter can be a one or a combination of @ref DMA_Channel_Attributes
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes)
|
|
{
|
|
8002138: b480 push {r7}
|
|
800213a: b085 sub sp, #20
|
|
800213c: af00 add r7, sp, #0
|
|
800213e: 6078 str r0, [r7, #4]
|
|
8002140: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002142: 2300 movs r3, #0
|
|
8002144: 72fb strb r3, [r7, #11]
|
|
#if defined (CORE_CM0PLUS)
|
|
uint32_t ccr_SECM;
|
|
#endif /* CORE_CM0PLUS */
|
|
|
|
/* Check the DMA peripheral handle */
|
|
if (hdma == NULL)
|
|
8002146: 687b ldr r3, [r7, #4]
|
|
8002148: 2b00 cmp r3, #0
|
|
800214a: d103 bne.n 8002154 <HAL_DMA_ConfigChannelAttributes+0x1c>
|
|
{
|
|
status = HAL_ERROR;
|
|
800214c: 2301 movs r3, #1
|
|
800214e: 72fb strb r3, [r7, #11]
|
|
return status;
|
|
8002150: 7afb ldrb r3, [r7, #11]
|
|
8002152: e01b b.n 800218c <HAL_DMA_ConfigChannelAttributes+0x54>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
|
|
|
|
/* Read CCR register */
|
|
ccr = READ_REG(hdma->Instance->CCR);
|
|
8002154: 687b ldr r3, [r7, #4]
|
|
8002156: 681b ldr r3, [r3, #0]
|
|
8002158: 681b ldr r3, [r3, #0]
|
|
800215a: 60fb str r3, [r7, #12]
|
|
|
|
/* Apply any requested privilege/non-privilege attributes */
|
|
if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) != 0U)
|
|
800215c: 683b ldr r3, [r7, #0]
|
|
800215e: f003 0310 and.w r3, r3, #16
|
|
8002162: 2b00 cmp r3, #0
|
|
8002164: d00d beq.n 8002182 <HAL_DMA_ConfigChannelAttributes+0x4a>
|
|
{
|
|
if ((ChannelAttributes & DMA_CCR_PRIV) != 0U)
|
|
8002166: 683b ldr r3, [r7, #0]
|
|
8002168: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800216c: 2b00 cmp r3, #0
|
|
800216e: d004 beq.n 800217a <HAL_DMA_ConfigChannelAttributes+0x42>
|
|
{
|
|
SET_BIT(ccr, DMA_CCR_PRIV);
|
|
8002170: 68fb ldr r3, [r7, #12]
|
|
8002172: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002176: 60fb str r3, [r7, #12]
|
|
8002178: e003 b.n 8002182 <HAL_DMA_ConfigChannelAttributes+0x4a>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(ccr, DMA_CCR_PRIV);
|
|
800217a: 68fb ldr r3, [r7, #12]
|
|
800217c: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
|
|
8002180: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
#endif /* CORE_CM0PLUS */
|
|
|
|
/* Update CCR Register: PRIV, SECM, SCEC, DSEC bits */
|
|
WRITE_REG(hdma->Instance->CCR, ccr);
|
|
8002182: 687b ldr r3, [r7, #4]
|
|
8002184: 681b ldr r3, [r3, #0]
|
|
8002186: 68fa ldr r2, [r7, #12]
|
|
8002188: 601a str r2, [r3, #0]
|
|
|
|
return status;
|
|
800218a: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
800218c: 4618 mov r0, r3
|
|
800218e: 3714 adds r7, #20
|
|
8002190: 46bd mov sp, r7
|
|
8002192: bc80 pop {r7}
|
|
8002194: 4770 bx lr
|
|
|
|
08002196 <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
8002196: b480 push {r7}
|
|
8002198: b085 sub sp, #20
|
|
800219a: af00 add r7, sp, #0
|
|
800219c: 60f8 str r0, [r7, #12]
|
|
800219e: 60b9 str r1, [r7, #8]
|
|
80021a0: 607a str r2, [r7, #4]
|
|
80021a2: 603b str r3, [r7, #0]
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
80021a4: 68fb ldr r3, [r7, #12]
|
|
80021a6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80021a8: 68fa ldr r2, [r7, #12]
|
|
80021aa: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
80021ac: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != NULL)
|
|
80021ae: 68fb ldr r3, [r7, #12]
|
|
80021b0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80021b2: 2b00 cmp r3, #0
|
|
80021b4: d004 beq.n 80021c0 <DMA_SetConfig+0x2a>
|
|
{
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
80021b6: 68fb ldr r3, [r7, #12]
|
|
80021b8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80021ba: 68fa ldr r2, [r7, #12]
|
|
80021bc: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
80021be: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
80021c0: 68fb ldr r3, [r7, #12]
|
|
80021c2: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80021c4: f003 021c and.w r2, r3, #28
|
|
80021c8: 68fb ldr r3, [r7, #12]
|
|
80021ca: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80021cc: 2101 movs r1, #1
|
|
80021ce: fa01 f202 lsl.w r2, r1, r2
|
|
80021d2: 605a str r2, [r3, #4]
|
|
|
|
/* Configure DMA Channel data length */
|
|
hdma->Instance->CNDTR = DataLength;
|
|
80021d4: 68fb ldr r3, [r7, #12]
|
|
80021d6: 681b ldr r3, [r3, #0]
|
|
80021d8: 683a ldr r2, [r7, #0]
|
|
80021da: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
80021dc: 68fb ldr r3, [r7, #12]
|
|
80021de: 689b ldr r3, [r3, #8]
|
|
80021e0: 2b10 cmp r3, #16
|
|
80021e2: d108 bne.n 80021f6 <DMA_SetConfig+0x60>
|
|
{
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CPAR = DstAddress;
|
|
80021e4: 68fb ldr r3, [r7, #12]
|
|
80021e6: 681b ldr r3, [r3, #0]
|
|
80021e8: 687a ldr r2, [r7, #4]
|
|
80021ea: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CMAR = SrcAddress;
|
|
80021ec: 68fb ldr r3, [r7, #12]
|
|
80021ee: 681b ldr r3, [r3, #0]
|
|
80021f0: 68ba ldr r2, [r7, #8]
|
|
80021f2: 60da str r2, [r3, #12]
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CMAR = DstAddress;
|
|
}
|
|
}
|
|
80021f4: e007 b.n 8002206 <DMA_SetConfig+0x70>
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
80021f6: 68fb ldr r3, [r7, #12]
|
|
80021f8: 681b ldr r3, [r3, #0]
|
|
80021fa: 68ba ldr r2, [r7, #8]
|
|
80021fc: 609a str r2, [r3, #8]
|
|
hdma->Instance->CMAR = DstAddress;
|
|
80021fe: 68fb ldr r3, [r7, #12]
|
|
8002200: 681b ldr r3, [r3, #0]
|
|
8002202: 687a ldr r2, [r7, #4]
|
|
8002204: 60da str r2, [r3, #12]
|
|
}
|
|
8002206: bf00 nop
|
|
8002208: 3714 adds r7, #20
|
|
800220a: 46bd mov sp, r7
|
|
800220c: bc80 pop {r7}
|
|
800220e: 4770 bx lr
|
|
|
|
08002210 <DMA_CalcDMAMUXChannelBaseAndMask>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8002210: b480 push {r7}
|
|
8002212: b085 sub sp, #20
|
|
8002214: af00 add r7, sp, #0
|
|
8002216: 6078 str r0, [r7, #4]
|
|
uint32_t channel_number;
|
|
|
|
/* check if instance is not outside the DMA channel range */
|
|
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
|
|
8002218: 687b ldr r3, [r7, #4]
|
|
800221a: 681b ldr r3, [r3, #0]
|
|
800221c: 461a mov r2, r3
|
|
800221e: 4b1c ldr r3, [pc, #112] @ (8002290 <DMA_CalcDMAMUXChannelBaseAndMask+0x80>)
|
|
8002220: 429a cmp r2, r3
|
|
8002222: d813 bhi.n 800224c <DMA_CalcDMAMUXChannelBaseAndMask+0x3c>
|
|
{
|
|
/* DMA1 */
|
|
/* Associate a DMA Channel to a DMAMUX channel */
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
|
|
8002224: 687b ldr r3, [r7, #4]
|
|
8002226: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002228: 089b lsrs r3, r3, #2
|
|
800222a: 009b lsls r3, r3, #2
|
|
800222c: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
|
|
8002230: f503 3302 add.w r3, r3, #133120 @ 0x20800
|
|
8002234: 687a ldr r2, [r7, #4]
|
|
8002236: 6493 str r3, [r2, #72] @ 0x48
|
|
|
|
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
|
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
|
8002238: 687b ldr r3, [r7, #4]
|
|
800223a: 681b ldr r3, [r3, #0]
|
|
800223c: b2db uxtb r3, r3
|
|
800223e: 3b08 subs r3, #8
|
|
8002240: 4a14 ldr r2, [pc, #80] @ (8002294 <DMA_CalcDMAMUXChannelBaseAndMask+0x84>)
|
|
8002242: fba2 2303 umull r2, r3, r2, r3
|
|
8002246: 091b lsrs r3, r3, #4
|
|
8002248: 60fb str r3, [r7, #12]
|
|
800224a: e011 b.n 8002270 <DMA_CalcDMAMUXChannelBaseAndMask+0x60>
|
|
}
|
|
else
|
|
{
|
|
/* DMA2 */
|
|
/* Associate a DMA Channel to a DMAMUX channel */
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
|
|
800224c: 687b ldr r3, [r7, #4]
|
|
800224e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002250: 089b lsrs r3, r3, #2
|
|
8002252: 009a lsls r2, r3, #2
|
|
8002254: 4b10 ldr r3, [pc, #64] @ (8002298 <DMA_CalcDMAMUXChannelBaseAndMask+0x88>)
|
|
8002256: 4413 add r3, r2
|
|
8002258: 687a ldr r2, [r7, #4]
|
|
800225a: 6493 str r3, [r2, #72] @ 0x48
|
|
|
|
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
|
channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
|
|
800225c: 687b ldr r3, [r7, #4]
|
|
800225e: 681b ldr r3, [r3, #0]
|
|
8002260: b2db uxtb r3, r3
|
|
8002262: 3b08 subs r3, #8
|
|
8002264: 4a0b ldr r2, [pc, #44] @ (8002294 <DMA_CalcDMAMUXChannelBaseAndMask+0x84>)
|
|
8002266: fba2 2303 umull r2, r3, r2, r3
|
|
800226a: 091b lsrs r3, r3, #4
|
|
800226c: 3307 adds r3, #7
|
|
800226e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
|
|
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
|
|
8002270: 687b ldr r3, [r7, #4]
|
|
8002272: 4a0a ldr r2, [pc, #40] @ (800229c <DMA_CalcDMAMUXChannelBaseAndMask+0x8c>)
|
|
8002274: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
|
|
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
|
|
8002276: 68fb ldr r3, [r7, #12]
|
|
8002278: f003 031f and.w r3, r3, #31
|
|
800227c: 2201 movs r2, #1
|
|
800227e: 409a lsls r2, r3
|
|
8002280: 687b ldr r3, [r7, #4]
|
|
8002282: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
8002284: bf00 nop
|
|
8002286: 3714 adds r7, #20
|
|
8002288: 46bd mov sp, r7
|
|
800228a: bc80 pop {r7}
|
|
800228c: 4770 bx lr
|
|
800228e: bf00 nop
|
|
8002290: 40020407 .word 0x40020407
|
|
8002294: cccccccd .word 0xcccccccd
|
|
8002298: 4002081c .word 0x4002081c
|
|
800229c: 40020880 .word 0x40020880
|
|
|
|
080022a0 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
|
|
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80022a0: b480 push {r7}
|
|
80022a2: b085 sub sp, #20
|
|
80022a4: af00 add r7, sp, #0
|
|
80022a6: 6078 str r0, [r7, #4]
|
|
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
|
|
80022a8: 687b ldr r3, [r7, #4]
|
|
80022aa: 685b ldr r3, [r3, #4]
|
|
80022ac: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80022b0: 60fb str r3, [r7, #12]
|
|
|
|
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
|
|
80022b2: 68fa ldr r2, [r7, #12]
|
|
80022b4: 4b0a ldr r3, [pc, #40] @ (80022e0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
|
|
80022b6: 4413 add r3, r2
|
|
80022b8: 009b lsls r3, r3, #2
|
|
80022ba: 461a mov r2, r3
|
|
80022bc: 687b ldr r3, [r7, #4]
|
|
80022be: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
|
|
80022c0: 687b ldr r3, [r7, #4]
|
|
80022c2: 4a08 ldr r2, [pc, #32] @ (80022e4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
|
|
80022c4: 659a str r2, [r3, #88] @ 0x58
|
|
|
|
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
|
|
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
|
|
80022c6: 68fb ldr r3, [r7, #12]
|
|
80022c8: 3b01 subs r3, #1
|
|
80022ca: f003 0303 and.w r3, r3, #3
|
|
80022ce: 2201 movs r2, #1
|
|
80022d0: 409a lsls r2, r3
|
|
80022d2: 687b ldr r3, [r7, #4]
|
|
80022d4: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
80022d6: bf00 nop
|
|
80022d8: 3714 adds r7, #20
|
|
80022da: 46bd mov sp, r7
|
|
80022dc: bc80 pop {r7}
|
|
80022de: 4770 bx lr
|
|
80022e0: 1000823f .word 0x1000823f
|
|
80022e4: 40020940 .word 0x40020940
|
|
|
|
080022e8 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80022e8: b480 push {r7}
|
|
80022ea: b087 sub sp, #28
|
|
80022ec: af00 add r7, sp, #0
|
|
80022ee: 6078 str r0, [r7, #4]
|
|
80022f0: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80022f2: 2300 movs r3, #0
|
|
80022f4: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80022f6: e140 b.n 800257a <HAL_GPIO_Init+0x292>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80022f8: 683b ldr r3, [r7, #0]
|
|
80022fa: 681a ldr r2, [r3, #0]
|
|
80022fc: 2101 movs r1, #1
|
|
80022fe: 697b ldr r3, [r7, #20]
|
|
8002300: fa01 f303 lsl.w r3, r1, r3
|
|
8002304: 4013 ands r3, r2
|
|
8002306: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8002308: 68fb ldr r3, [r7, #12]
|
|
800230a: 2b00 cmp r3, #0
|
|
800230c: f000 8132 beq.w 8002574 <HAL_GPIO_Init+0x28c>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8002310: 683b ldr r3, [r7, #0]
|
|
8002312: 685b ldr r3, [r3, #4]
|
|
8002314: f003 0303 and.w r3, r3, #3
|
|
8002318: 2b01 cmp r3, #1
|
|
800231a: d005 beq.n 8002328 <HAL_GPIO_Init+0x40>
|
|
800231c: 683b ldr r3, [r7, #0]
|
|
800231e: 685b ldr r3, [r3, #4]
|
|
8002320: f003 0303 and.w r3, r3, #3
|
|
8002324: 2b02 cmp r3, #2
|
|
8002326: d130 bne.n 800238a <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8002328: 687b ldr r3, [r7, #4]
|
|
800232a: 689b ldr r3, [r3, #8]
|
|
800232c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
|
800232e: 697b ldr r3, [r7, #20]
|
|
8002330: 005b lsls r3, r3, #1
|
|
8002332: 2203 movs r2, #3
|
|
8002334: fa02 f303 lsl.w r3, r2, r3
|
|
8002338: 43db mvns r3, r3
|
|
800233a: 693a ldr r2, [r7, #16]
|
|
800233c: 4013 ands r3, r2
|
|
800233e: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8002340: 683b ldr r3, [r7, #0]
|
|
8002342: 68da ldr r2, [r3, #12]
|
|
8002344: 697b ldr r3, [r7, #20]
|
|
8002346: 005b lsls r3, r3, #1
|
|
8002348: fa02 f303 lsl.w r3, r2, r3
|
|
800234c: 693a ldr r2, [r7, #16]
|
|
800234e: 4313 orrs r3, r2
|
|
8002350: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8002352: 687b ldr r3, [r7, #4]
|
|
8002354: 693a ldr r2, [r7, #16]
|
|
8002356: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8002358: 687b ldr r3, [r7, #4]
|
|
800235a: 685b ldr r3, [r3, #4]
|
|
800235c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
800235e: 2201 movs r2, #1
|
|
8002360: 697b ldr r3, [r7, #20]
|
|
8002362: fa02 f303 lsl.w r3, r2, r3
|
|
8002366: 43db mvns r3, r3
|
|
8002368: 693a ldr r2, [r7, #16]
|
|
800236a: 4013 ands r3, r2
|
|
800236c: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
800236e: 683b ldr r3, [r7, #0]
|
|
8002370: 685b ldr r3, [r3, #4]
|
|
8002372: 091b lsrs r3, r3, #4
|
|
8002374: f003 0201 and.w r2, r3, #1
|
|
8002378: 697b ldr r3, [r7, #20]
|
|
800237a: fa02 f303 lsl.w r3, r2, r3
|
|
800237e: 693a ldr r2, [r7, #16]
|
|
8002380: 4313 orrs r3, r2
|
|
8002382: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8002384: 687b ldr r3, [r7, #4]
|
|
8002386: 693a ldr r2, [r7, #16]
|
|
8002388: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800238a: 683b ldr r3, [r7, #0]
|
|
800238c: 685b ldr r3, [r3, #4]
|
|
800238e: f003 0303 and.w r3, r3, #3
|
|
8002392: 2b03 cmp r3, #3
|
|
8002394: d017 beq.n 80023c6 <HAL_GPIO_Init+0xde>
|
|
{
|
|
temp = GPIOx->PUPDR;
|
|
8002396: 687b ldr r3, [r7, #4]
|
|
8002398: 68db ldr r3, [r3, #12]
|
|
800239a: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
800239c: 697b ldr r3, [r7, #20]
|
|
800239e: 005b lsls r3, r3, #1
|
|
80023a0: 2203 movs r2, #3
|
|
80023a2: fa02 f303 lsl.w r3, r2, r3
|
|
80023a6: 43db mvns r3, r3
|
|
80023a8: 693a ldr r2, [r7, #16]
|
|
80023aa: 4013 ands r3, r2
|
|
80023ac: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
80023ae: 683b ldr r3, [r7, #0]
|
|
80023b0: 689a ldr r2, [r3, #8]
|
|
80023b2: 697b ldr r3, [r7, #20]
|
|
80023b4: 005b lsls r3, r3, #1
|
|
80023b6: fa02 f303 lsl.w r3, r2, r3
|
|
80023ba: 693a ldr r2, [r7, #16]
|
|
80023bc: 4313 orrs r3, r2
|
|
80023be: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
80023c0: 687b ldr r3, [r7, #4]
|
|
80023c2: 693a ldr r2, [r7, #16]
|
|
80023c4: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80023c6: 683b ldr r3, [r7, #0]
|
|
80023c8: 685b ldr r3, [r3, #4]
|
|
80023ca: f003 0303 and.w r3, r3, #3
|
|
80023ce: 2b02 cmp r3, #2
|
|
80023d0: d123 bne.n 800241a <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
80023d2: 697b ldr r3, [r7, #20]
|
|
80023d4: 08da lsrs r2, r3, #3
|
|
80023d6: 687b ldr r3, [r7, #4]
|
|
80023d8: 3208 adds r2, #8
|
|
80023da: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80023de: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFU << ((position & 0x07U) * 4U));
|
|
80023e0: 697b ldr r3, [r7, #20]
|
|
80023e2: f003 0307 and.w r3, r3, #7
|
|
80023e6: 009b lsls r3, r3, #2
|
|
80023e8: 220f movs r2, #15
|
|
80023ea: fa02 f303 lsl.w r3, r2, r3
|
|
80023ee: 43db mvns r3, r3
|
|
80023f0: 693a ldr r2, [r7, #16]
|
|
80023f2: 4013 ands r3, r2
|
|
80023f4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
|
|
80023f6: 683b ldr r3, [r7, #0]
|
|
80023f8: 691a ldr r2, [r3, #16]
|
|
80023fa: 697b ldr r3, [r7, #20]
|
|
80023fc: f003 0307 and.w r3, r3, #7
|
|
8002400: 009b lsls r3, r3, #2
|
|
8002402: fa02 f303 lsl.w r3, r2, r3
|
|
8002406: 693a ldr r2, [r7, #16]
|
|
8002408: 4313 orrs r3, r2
|
|
800240a: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
800240c: 697b ldr r3, [r7, #20]
|
|
800240e: 08da lsrs r2, r3, #3
|
|
8002410: 687b ldr r3, [r7, #4]
|
|
8002412: 3208 adds r2, #8
|
|
8002414: 6939 ldr r1, [r7, #16]
|
|
8002416: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
800241a: 687b ldr r3, [r7, #4]
|
|
800241c: 681b ldr r3, [r3, #0]
|
|
800241e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
|
8002420: 697b ldr r3, [r7, #20]
|
|
8002422: 005b lsls r3, r3, #1
|
|
8002424: 2203 movs r2, #3
|
|
8002426: fa02 f303 lsl.w r3, r2, r3
|
|
800242a: 43db mvns r3, r3
|
|
800242c: 693a ldr r2, [r7, #16]
|
|
800242e: 4013 ands r3, r2
|
|
8002430: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8002432: 683b ldr r3, [r7, #0]
|
|
8002434: 685b ldr r3, [r3, #4]
|
|
8002436: f003 0203 and.w r2, r3, #3
|
|
800243a: 697b ldr r3, [r7, #20]
|
|
800243c: 005b lsls r3, r3, #1
|
|
800243e: fa02 f303 lsl.w r3, r2, r3
|
|
8002442: 693a ldr r2, [r7, #16]
|
|
8002444: 4313 orrs r3, r2
|
|
8002446: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8002448: 687b ldr r3, [r7, #4]
|
|
800244a: 693a ldr r2, [r7, #16]
|
|
800244c: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
800244e: 683b ldr r3, [r7, #0]
|
|
8002450: 685b ldr r3, [r3, #4]
|
|
8002452: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8002456: 2b00 cmp r3, #0
|
|
8002458: f000 808c beq.w 8002574 <HAL_GPIO_Init+0x28c>
|
|
{
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
800245c: 4a4e ldr r2, [pc, #312] @ (8002598 <HAL_GPIO_Init+0x2b0>)
|
|
800245e: 697b ldr r3, [r7, #20]
|
|
8002460: 089b lsrs r3, r3, #2
|
|
8002462: 3302 adds r3, #2
|
|
8002464: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8002468: 613b str r3, [r7, #16]
|
|
temp &= ~(0x07uL << (4U * (position & 0x03U)));
|
|
800246a: 697b ldr r3, [r7, #20]
|
|
800246c: f003 0303 and.w r3, r3, #3
|
|
8002470: 009b lsls r3, r3, #2
|
|
8002472: 2207 movs r2, #7
|
|
8002474: fa02 f303 lsl.w r3, r2, r3
|
|
8002478: 43db mvns r3, r3
|
|
800247a: 693a ldr r2, [r7, #16]
|
|
800247c: 4013 ands r3, r2
|
|
800247e: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
|
|
8002480: 687b ldr r3, [r7, #4]
|
|
8002482: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8002486: d00d beq.n 80024a4 <HAL_GPIO_Init+0x1bc>
|
|
8002488: 687b ldr r3, [r7, #4]
|
|
800248a: 4a44 ldr r2, [pc, #272] @ (800259c <HAL_GPIO_Init+0x2b4>)
|
|
800248c: 4293 cmp r3, r2
|
|
800248e: d007 beq.n 80024a0 <HAL_GPIO_Init+0x1b8>
|
|
8002490: 687b ldr r3, [r7, #4]
|
|
8002492: 4a43 ldr r2, [pc, #268] @ (80025a0 <HAL_GPIO_Init+0x2b8>)
|
|
8002494: 4293 cmp r3, r2
|
|
8002496: d101 bne.n 800249c <HAL_GPIO_Init+0x1b4>
|
|
8002498: 2302 movs r3, #2
|
|
800249a: e004 b.n 80024a6 <HAL_GPIO_Init+0x1be>
|
|
800249c: 2307 movs r3, #7
|
|
800249e: e002 b.n 80024a6 <HAL_GPIO_Init+0x1be>
|
|
80024a0: 2301 movs r3, #1
|
|
80024a2: e000 b.n 80024a6 <HAL_GPIO_Init+0x1be>
|
|
80024a4: 2300 movs r3, #0
|
|
80024a6: 697a ldr r2, [r7, #20]
|
|
80024a8: f002 0203 and.w r2, r2, #3
|
|
80024ac: 0092 lsls r2, r2, #2
|
|
80024ae: 4093 lsls r3, r2
|
|
80024b0: 693a ldr r2, [r7, #16]
|
|
80024b2: 4313 orrs r3, r2
|
|
80024b4: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
80024b6: 4938 ldr r1, [pc, #224] @ (8002598 <HAL_GPIO_Init+0x2b0>)
|
|
80024b8: 697b ldr r3, [r7, #20]
|
|
80024ba: 089b lsrs r3, r3, #2
|
|
80024bc: 3302 adds r3, #2
|
|
80024be: 693a ldr r2, [r7, #16]
|
|
80024c0: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
80024c4: 4b37 ldr r3, [pc, #220] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
80024c6: 681b ldr r3, [r3, #0]
|
|
80024c8: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80024ca: 68fb ldr r3, [r7, #12]
|
|
80024cc: 43db mvns r3, r3
|
|
80024ce: 693a ldr r2, [r7, #16]
|
|
80024d0: 4013 ands r3, r2
|
|
80024d2: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
80024d4: 683b ldr r3, [r7, #0]
|
|
80024d6: 685b ldr r3, [r3, #4]
|
|
80024d8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80024dc: 2b00 cmp r3, #0
|
|
80024de: d003 beq.n 80024e8 <HAL_GPIO_Init+0x200>
|
|
{
|
|
temp |= iocurrent;
|
|
80024e0: 693a ldr r2, [r7, #16]
|
|
80024e2: 68fb ldr r3, [r7, #12]
|
|
80024e4: 4313 orrs r3, r2
|
|
80024e6: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
80024e8: 4a2e ldr r2, [pc, #184] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
80024ea: 693b ldr r3, [r7, #16]
|
|
80024ec: 6013 str r3, [r2, #0]
|
|
|
|
temp = EXTI->FTSR1;
|
|
80024ee: 4b2d ldr r3, [pc, #180] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
80024f0: 685b ldr r3, [r3, #4]
|
|
80024f2: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80024f4: 68fb ldr r3, [r7, #12]
|
|
80024f6: 43db mvns r3, r3
|
|
80024f8: 693a ldr r2, [r7, #16]
|
|
80024fa: 4013 ands r3, r2
|
|
80024fc: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
80024fe: 683b ldr r3, [r7, #0]
|
|
8002500: 685b ldr r3, [r3, #4]
|
|
8002502: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8002506: 2b00 cmp r3, #0
|
|
8002508: d003 beq.n 8002512 <HAL_GPIO_Init+0x22a>
|
|
{
|
|
temp |= iocurrent;
|
|
800250a: 693a ldr r2, [r7, #16]
|
|
800250c: 68fb ldr r3, [r7, #12]
|
|
800250e: 4313 orrs r3, r2
|
|
8002510: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8002512: 4a24 ldr r2, [pc, #144] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
8002514: 693b ldr r3, [r7, #16]
|
|
8002516: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
#ifdef CORE_CM0PLUS
|
|
temp = EXTI->C2IMR1;
|
|
#else
|
|
temp = EXTI->IMR1;
|
|
8002518: 4b22 ldr r3, [pc, #136] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
800251a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800251e: 613b str r3, [r7, #16]
|
|
#endif /* CORE_CM0PLUS */
|
|
temp &= ~(iocurrent);
|
|
8002520: 68fb ldr r3, [r7, #12]
|
|
8002522: 43db mvns r3, r3
|
|
8002524: 693a ldr r2, [r7, #16]
|
|
8002526: 4013 ands r3, r2
|
|
8002528: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
800252a: 683b ldr r3, [r7, #0]
|
|
800252c: 685b ldr r3, [r3, #4]
|
|
800252e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002532: 2b00 cmp r3, #0
|
|
8002534: d003 beq.n 800253e <HAL_GPIO_Init+0x256>
|
|
{
|
|
temp |= iocurrent;
|
|
8002536: 693a ldr r2, [r7, #16]
|
|
8002538: 68fb ldr r3, [r7, #12]
|
|
800253a: 4313 orrs r3, r2
|
|
800253c: 613b str r3, [r7, #16]
|
|
}
|
|
#ifdef CORE_CM0PLUS
|
|
EXTI->C2IMR1 = temp;
|
|
#else
|
|
EXTI->IMR1 = temp;
|
|
800253e: 4a19 ldr r2, [pc, #100] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
8002540: 693b ldr r3, [r7, #16]
|
|
8002542: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
#endif /* CORE_CM0PLUS */
|
|
|
|
#ifdef CORE_CM0PLUS
|
|
temp = EXTI->C2EMR1;
|
|
#else
|
|
temp = EXTI->EMR1;
|
|
8002546: 4b17 ldr r3, [pc, #92] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
8002548: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800254c: 613b str r3, [r7, #16]
|
|
#endif /* CORE_CM0PLUS */
|
|
temp &= ~(iocurrent);
|
|
800254e: 68fb ldr r3, [r7, #12]
|
|
8002550: 43db mvns r3, r3
|
|
8002552: 693a ldr r2, [r7, #16]
|
|
8002554: 4013 ands r3, r2
|
|
8002556: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8002558: 683b ldr r3, [r7, #0]
|
|
800255a: 685b ldr r3, [r3, #4]
|
|
800255c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002560: 2b00 cmp r3, #0
|
|
8002562: d003 beq.n 800256c <HAL_GPIO_Init+0x284>
|
|
{
|
|
temp |= iocurrent;
|
|
8002564: 693a ldr r2, [r7, #16]
|
|
8002566: 68fb ldr r3, [r7, #12]
|
|
8002568: 4313 orrs r3, r2
|
|
800256a: 613b str r3, [r7, #16]
|
|
}
|
|
#ifdef CORE_CM0PLUS
|
|
EXTI->C2EMR1 = temp;
|
|
#else
|
|
EXTI->EMR1 = temp;
|
|
800256c: 4a0d ldr r2, [pc, #52] @ (80025a4 <HAL_GPIO_Init+0x2bc>)
|
|
800256e: 693b ldr r3, [r7, #16]
|
|
8002570: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
#endif /* CORE_CM0PLUS */
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8002574: 697b ldr r3, [r7, #20]
|
|
8002576: 3301 adds r3, #1
|
|
8002578: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800257a: 683b ldr r3, [r7, #0]
|
|
800257c: 681a ldr r2, [r3, #0]
|
|
800257e: 697b ldr r3, [r7, #20]
|
|
8002580: fa22 f303 lsr.w r3, r2, r3
|
|
8002584: 2b00 cmp r3, #0
|
|
8002586: f47f aeb7 bne.w 80022f8 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
800258a: bf00 nop
|
|
800258c: bf00 nop
|
|
800258e: 371c adds r7, #28
|
|
8002590: 46bd mov sp, r7
|
|
8002592: bc80 pop {r7}
|
|
8002594: 4770 bx lr
|
|
8002596: bf00 nop
|
|
8002598: 40010000 .word 0x40010000
|
|
800259c: 48000400 .word 0x48000400
|
|
80025a0: 48000800 .word 0x48000800
|
|
80025a4: 58000800 .word 0x58000800
|
|
|
|
080025a8 <HAL_GPIO_DeInit>:
|
|
* @param GPIO_Pin specifies the port bit to be written.
|
|
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|
{
|
|
80025a8: b480 push {r7}
|
|
80025aa: b087 sub sp, #28
|
|
80025ac: af00 add r7, sp, #0
|
|
80025ae: 6078 str r0, [r7, #4]
|
|
80025b0: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80025b2: 2300 movs r3, #0
|
|
80025b4: 617b str r3, [r7, #20]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* Configure the port pins */
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
80025b6: e0af b.n 8002718 <HAL_GPIO_DeInit+0x170>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Pin) & (1uL << position);
|
|
80025b8: 2201 movs r2, #1
|
|
80025ba: 697b ldr r3, [r7, #20]
|
|
80025bc: fa02 f303 lsl.w r3, r2, r3
|
|
80025c0: 683a ldr r2, [r7, #0]
|
|
80025c2: 4013 ands r3, r2
|
|
80025c4: 613b str r3, [r7, #16]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80025c6: 693b ldr r3, [r7, #16]
|
|
80025c8: 2b00 cmp r3, #0
|
|
80025ca: f000 80a2 beq.w 8002712 <HAL_GPIO_DeInit+0x16a>
|
|
{
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
|
/* Clear the External Interrupt or Event for the current IO */
|
|
|
|
tmp = SYSCFG->EXTICR[position >> 2u];
|
|
80025ce: 4a59 ldr r2, [pc, #356] @ (8002734 <HAL_GPIO_DeInit+0x18c>)
|
|
80025d0: 697b ldr r3, [r7, #20]
|
|
80025d2: 089b lsrs r3, r3, #2
|
|
80025d4: 3302 adds r3, #2
|
|
80025d6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80025da: 60fb str r3, [r7, #12]
|
|
tmp &= (0x07uL << (4U * (position & 0x03U)));
|
|
80025dc: 697b ldr r3, [r7, #20]
|
|
80025de: f003 0303 and.w r3, r3, #3
|
|
80025e2: 009b lsls r3, r3, #2
|
|
80025e4: 2207 movs r2, #7
|
|
80025e6: fa02 f303 lsl.w r3, r2, r3
|
|
80025ea: 68fa ldr r2, [r7, #12]
|
|
80025ec: 4013 ands r3, r2
|
|
80025ee: 60fb str r3, [r7, #12]
|
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
|
|
80025f0: 687b ldr r3, [r7, #4]
|
|
80025f2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
80025f6: d00d beq.n 8002614 <HAL_GPIO_DeInit+0x6c>
|
|
80025f8: 687b ldr r3, [r7, #4]
|
|
80025fa: 4a4f ldr r2, [pc, #316] @ (8002738 <HAL_GPIO_DeInit+0x190>)
|
|
80025fc: 4293 cmp r3, r2
|
|
80025fe: d007 beq.n 8002610 <HAL_GPIO_DeInit+0x68>
|
|
8002600: 687b ldr r3, [r7, #4]
|
|
8002602: 4a4e ldr r2, [pc, #312] @ (800273c <HAL_GPIO_DeInit+0x194>)
|
|
8002604: 4293 cmp r3, r2
|
|
8002606: d101 bne.n 800260c <HAL_GPIO_DeInit+0x64>
|
|
8002608: 2302 movs r3, #2
|
|
800260a: e004 b.n 8002616 <HAL_GPIO_DeInit+0x6e>
|
|
800260c: 2307 movs r3, #7
|
|
800260e: e002 b.n 8002616 <HAL_GPIO_DeInit+0x6e>
|
|
8002610: 2301 movs r3, #1
|
|
8002612: e000 b.n 8002616 <HAL_GPIO_DeInit+0x6e>
|
|
8002614: 2300 movs r3, #0
|
|
8002616: 697a ldr r2, [r7, #20]
|
|
8002618: f002 0203 and.w r2, r2, #3
|
|
800261c: 0092 lsls r2, r2, #2
|
|
800261e: 4093 lsls r3, r2
|
|
8002620: 68fa ldr r2, [r7, #12]
|
|
8002622: 429a cmp r2, r3
|
|
8002624: d136 bne.n 8002694 <HAL_GPIO_DeInit+0xec>
|
|
/* Clear EXTI line configuration */
|
|
#ifdef CORE_CM0PLUS
|
|
EXTI->C2IMR1 &= ~(iocurrent);
|
|
EXTI->C2EMR1 &= ~(iocurrent);
|
|
#else
|
|
EXTI->IMR1 &= ~(iocurrent);
|
|
8002626: 4b46 ldr r3, [pc, #280] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
8002628: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
|
|
800262c: 693b ldr r3, [r7, #16]
|
|
800262e: 43db mvns r3, r3
|
|
8002630: 4943 ldr r1, [pc, #268] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
8002632: 4013 ands r3, r2
|
|
8002634: f8c1 3080 str.w r3, [r1, #128] @ 0x80
|
|
EXTI->EMR1 &= ~(iocurrent);
|
|
8002638: 4b41 ldr r3, [pc, #260] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
800263a: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
|
|
800263e: 693b ldr r3, [r7, #16]
|
|
8002640: 43db mvns r3, r3
|
|
8002642: 493f ldr r1, [pc, #252] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
8002644: 4013 ands r3, r2
|
|
8002646: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
#endif /* CORE_CM0PLUS */
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
EXTI->RTSR1 &= ~(iocurrent);
|
|
800264a: 4b3d ldr r3, [pc, #244] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
800264c: 681a ldr r2, [r3, #0]
|
|
800264e: 693b ldr r3, [r7, #16]
|
|
8002650: 43db mvns r3, r3
|
|
8002652: 493b ldr r1, [pc, #236] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
8002654: 4013 ands r3, r2
|
|
8002656: 600b str r3, [r1, #0]
|
|
EXTI->FTSR1 &= ~(iocurrent);
|
|
8002658: 4b39 ldr r3, [pc, #228] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
800265a: 685a ldr r2, [r3, #4]
|
|
800265c: 693b ldr r3, [r7, #16]
|
|
800265e: 43db mvns r3, r3
|
|
8002660: 4937 ldr r1, [pc, #220] @ (8002740 <HAL_GPIO_DeInit+0x198>)
|
|
8002662: 4013 ands r3, r2
|
|
8002664: 604b str r3, [r1, #4]
|
|
|
|
/* Clear EXTICR configuration */
|
|
tmp = 0x07uL << (4u * (position & 0x03U));
|
|
8002666: 697b ldr r3, [r7, #20]
|
|
8002668: f003 0303 and.w r3, r3, #3
|
|
800266c: 009b lsls r3, r3, #2
|
|
800266e: 2207 movs r2, #7
|
|
8002670: fa02 f303 lsl.w r3, r2, r3
|
|
8002674: 60fb str r3, [r7, #12]
|
|
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
|
8002676: 4a2f ldr r2, [pc, #188] @ (8002734 <HAL_GPIO_DeInit+0x18c>)
|
|
8002678: 697b ldr r3, [r7, #20]
|
|
800267a: 089b lsrs r3, r3, #2
|
|
800267c: 3302 adds r3, #2
|
|
800267e: f852 1023 ldr.w r1, [r2, r3, lsl #2]
|
|
8002682: 68fb ldr r3, [r7, #12]
|
|
8002684: 43da mvns r2, r3
|
|
8002686: 482b ldr r0, [pc, #172] @ (8002734 <HAL_GPIO_DeInit+0x18c>)
|
|
8002688: 697b ldr r3, [r7, #20]
|
|
800268a: 089b lsrs r3, r3, #2
|
|
800268c: 400a ands r2, r1
|
|
800268e: 3302 adds r3, #2
|
|
8002690: f840 2023 str.w r2, [r0, r3, lsl #2]
|
|
}
|
|
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
|
/* Configure IO in Analog Mode */
|
|
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
|
|
8002694: 687b ldr r3, [r7, #4]
|
|
8002696: 681a ldr r2, [r3, #0]
|
|
8002698: 697b ldr r3, [r7, #20]
|
|
800269a: 005b lsls r3, r3, #1
|
|
800269c: 2103 movs r1, #3
|
|
800269e: fa01 f303 lsl.w r3, r1, r3
|
|
80026a2: 431a orrs r2, r3
|
|
80026a4: 687b ldr r3, [r7, #4]
|
|
80026a6: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the default Alternate Function in current IO */
|
|
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
|
|
80026a8: 697b ldr r3, [r7, #20]
|
|
80026aa: 08da lsrs r2, r3, #3
|
|
80026ac: 687b ldr r3, [r7, #4]
|
|
80026ae: 3208 adds r2, #8
|
|
80026b0: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
80026b4: 697b ldr r3, [r7, #20]
|
|
80026b6: f003 0307 and.w r3, r3, #7
|
|
80026ba: 009b lsls r3, r3, #2
|
|
80026bc: 220f movs r2, #15
|
|
80026be: fa02 f303 lsl.w r3, r2, r3
|
|
80026c2: 43db mvns r3, r3
|
|
80026c4: 697a ldr r2, [r7, #20]
|
|
80026c6: 08d2 lsrs r2, r2, #3
|
|
80026c8: 4019 ands r1, r3
|
|
80026ca: 687b ldr r3, [r7, #4]
|
|
80026cc: 3208 adds r2, #8
|
|
80026ce: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Configure the default value for IO Speed */
|
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
|
80026d2: 687b ldr r3, [r7, #4]
|
|
80026d4: 689a ldr r2, [r3, #8]
|
|
80026d6: 697b ldr r3, [r7, #20]
|
|
80026d8: 005b lsls r3, r3, #1
|
|
80026da: 2103 movs r1, #3
|
|
80026dc: fa01 f303 lsl.w r3, r1, r3
|
|
80026e0: 43db mvns r3, r3
|
|
80026e2: 401a ands r2, r3
|
|
80026e4: 687b ldr r3, [r7, #4]
|
|
80026e6: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the default value IO Output Type */
|
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
80026e8: 687b ldr r3, [r7, #4]
|
|
80026ea: 685a ldr r2, [r3, #4]
|
|
80026ec: 2101 movs r1, #1
|
|
80026ee: 697b ldr r3, [r7, #20]
|
|
80026f0: fa01 f303 lsl.w r3, r1, r3
|
|
80026f4: 43db mvns r3, r3
|
|
80026f6: 401a ands r2, r3
|
|
80026f8: 687b ldr r3, [r7, #4]
|
|
80026fa: 605a str r2, [r3, #4]
|
|
|
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
80026fc: 687b ldr r3, [r7, #4]
|
|
80026fe: 68da ldr r2, [r3, #12]
|
|
8002700: 697b ldr r3, [r7, #20]
|
|
8002702: 005b lsls r3, r3, #1
|
|
8002704: 2103 movs r1, #3
|
|
8002706: fa01 f303 lsl.w r3, r1, r3
|
|
800270a: 43db mvns r3, r3
|
|
800270c: 401a ands r2, r3
|
|
800270e: 687b ldr r3, [r7, #4]
|
|
8002710: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
position++;
|
|
8002712: 697b ldr r3, [r7, #20]
|
|
8002714: 3301 adds r3, #1
|
|
8002716: 617b str r3, [r7, #20]
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
8002718: 683a ldr r2, [r7, #0]
|
|
800271a: 697b ldr r3, [r7, #20]
|
|
800271c: fa22 f303 lsr.w r3, r2, r3
|
|
8002720: 2b00 cmp r3, #0
|
|
8002722: f47f af49 bne.w 80025b8 <HAL_GPIO_DeInit+0x10>
|
|
}
|
|
}
|
|
8002726: bf00 nop
|
|
8002728: bf00 nop
|
|
800272a: 371c adds r7, #28
|
|
800272c: 46bd mov sp, r7
|
|
800272e: bc80 pop {r7}
|
|
8002730: 4770 bx lr
|
|
8002732: bf00 nop
|
|
8002734: 40010000 .word 0x40010000
|
|
8002738: 48000400 .word 0x48000400
|
|
800273c: 48000800 .word 0x48000800
|
|
8002740: 58000800 .word 0x58000800
|
|
|
|
08002744 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8002744: b480 push {r7}
|
|
8002746: b083 sub sp, #12
|
|
8002748: af00 add r7, sp, #0
|
|
800274a: 6078 str r0, [r7, #4]
|
|
800274c: 460b mov r3, r1
|
|
800274e: 807b strh r3, [r7, #2]
|
|
8002750: 4613 mov r3, r2
|
|
8002752: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8002754: 787b ldrb r3, [r7, #1]
|
|
8002756: 2b00 cmp r3, #0
|
|
8002758: d003 beq.n 8002762 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
800275a: 887a ldrh r2, [r7, #2]
|
|
800275c: 687b ldr r3, [r7, #4]
|
|
800275e: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8002760: e002 b.n 8002768 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8002762: 887a ldrh r2, [r7, #2]
|
|
8002764: 687b ldr r3, [r7, #4]
|
|
8002766: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8002768: bf00 nop
|
|
800276a: 370c adds r7, #12
|
|
800276c: 46bd mov sp, r7
|
|
800276e: bc80 pop {r7}
|
|
8002770: 4770 bx lr
|
|
...
|
|
|
|
08002774 <HAL_GPIO_EXTI_IRQHandler>:
|
|
* @brief Handle EXTI interrupt request.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|
{
|
|
8002774: b580 push {r7, lr}
|
|
8002776: b082 sub sp, #8
|
|
8002778: af00 add r7, sp, #0
|
|
800277a: 4603 mov r3, r0
|
|
800277c: 80fb strh r3, [r7, #6]
|
|
/* EXTI line interrupt detected */
|
|
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
|
800277e: 4b08 ldr r3, [pc, #32] @ (80027a0 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
8002780: 68da ldr r2, [r3, #12]
|
|
8002782: 88fb ldrh r3, [r7, #6]
|
|
8002784: 4013 ands r3, r2
|
|
8002786: 2b00 cmp r3, #0
|
|
8002788: d006 beq.n 8002798 <HAL_GPIO_EXTI_IRQHandler+0x24>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
|
800278a: 4a05 ldr r2, [pc, #20] @ (80027a0 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
800278c: 88fb ldrh r3, [r7, #6]
|
|
800278e: 60d3 str r3, [r2, #12]
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
|
8002790: 88fb ldrh r3, [r7, #6]
|
|
8002792: 4618 mov r0, r3
|
|
8002794: f009 fadc bl 800bd50 <HAL_GPIO_EXTI_Callback>
|
|
}
|
|
}
|
|
8002798: bf00 nop
|
|
800279a: 3708 adds r7, #8
|
|
800279c: 46bd mov sp, r7
|
|
800279e: bd80 pop {r7, pc}
|
|
80027a0: 58000800 .word 0x58000800
|
|
|
|
080027a4 <HAL_PWR_EnableBkUpAccess>:
|
|
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
|
* backup domain.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
80027a4: b480 push {r7}
|
|
80027a6: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80027a8: 4b04 ldr r3, [pc, #16] @ (80027bc <HAL_PWR_EnableBkUpAccess+0x18>)
|
|
80027aa: 681b ldr r3, [r3, #0]
|
|
80027ac: 4a03 ldr r2, [pc, #12] @ (80027bc <HAL_PWR_EnableBkUpAccess+0x18>)
|
|
80027ae: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80027b2: 6013 str r3, [r2, #0]
|
|
}
|
|
80027b4: bf00 nop
|
|
80027b6: 46bd mov sp, r7
|
|
80027b8: bc80 pop {r7}
|
|
80027ba: 4770 bx lr
|
|
80027bc: 58000400 .word 0x58000400
|
|
|
|
080027c0 <HAL_PWR_EnterSLEEPMode>:
|
|
* @note When WFI entry is used, tick interrupt have to be disabled if not desired as
|
|
* the interrupt wake up source.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
|
{
|
|
80027c0: b580 push {r7, lr}
|
|
80027c2: b082 sub sp, #8
|
|
80027c4: af00 add r7, sp, #0
|
|
80027c6: 6078 str r0, [r7, #4]
|
|
80027c8: 460b mov r3, r1
|
|
80027ca: 70fb strb r3, [r7, #3]
|
|
/* Check the parameters */
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
|
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
|
|
|
/* Set Regulator parameter */
|
|
if (Regulator == PWR_MAINREGULATOR_ON)
|
|
80027cc: 687b ldr r3, [r7, #4]
|
|
80027ce: 2b00 cmp r3, #0
|
|
80027d0: d10c bne.n 80027ec <HAL_PWR_EnterSLEEPMode+0x2c>
|
|
{
|
|
/* If in low-power run mode at this point, exit it */
|
|
if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF)))
|
|
80027d2: 4b13 ldr r3, [pc, #76] @ (8002820 <HAL_PWR_EnterSLEEPMode+0x60>)
|
|
80027d4: 695b ldr r3, [r3, #20]
|
|
80027d6: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80027da: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80027de: d10d bne.n 80027fc <HAL_PWR_EnterSLEEPMode+0x3c>
|
|
{
|
|
if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
|
|
80027e0: f000 f83c bl 800285c <HAL_PWREx_DisableLowPowerRunMode>
|
|
80027e4: 4603 mov r3, r0
|
|
80027e6: 2b00 cmp r3, #0
|
|
80027e8: d008 beq.n 80027fc <HAL_PWR_EnterSLEEPMode+0x3c>
|
|
{
|
|
return ;
|
|
80027ea: e015 b.n 8002818 <HAL_PWR_EnterSLEEPMode+0x58>
|
|
}
|
|
else
|
|
{
|
|
/* If in run mode, first move to low-power run mode.
|
|
The system clock frequency must be below 2 MHz at this point. */
|
|
if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF)))
|
|
80027ec: 4b0c ldr r3, [pc, #48] @ (8002820 <HAL_PWR_EnterSLEEPMode+0x60>)
|
|
80027ee: 695b ldr r3, [r3, #20]
|
|
80027f0: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80027f4: 2b00 cmp r3, #0
|
|
80027f6: d101 bne.n 80027fc <HAL_PWR_EnterSLEEPMode+0x3c>
|
|
{
|
|
HAL_PWREx_EnableLowPowerRunMode();
|
|
80027f8: f000 f822 bl 8002840 <HAL_PWREx_EnableLowPowerRunMode>
|
|
}
|
|
}
|
|
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
80027fc: 4b09 ldr r3, [pc, #36] @ (8002824 <HAL_PWR_EnterSLEEPMode+0x64>)
|
|
80027fe: 691b ldr r3, [r3, #16]
|
|
8002800: 4a08 ldr r2, [pc, #32] @ (8002824 <HAL_PWR_EnterSLEEPMode+0x64>)
|
|
8002802: f023 0304 bic.w r3, r3, #4
|
|
8002806: 6113 str r3, [r2, #16]
|
|
|
|
/* Select SLEEP mode entry -------------------------------------------------*/
|
|
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
|
8002808: 78fb ldrb r3, [r7, #3]
|
|
800280a: 2b01 cmp r3, #1
|
|
800280c: d101 bne.n 8002812 <HAL_PWR_EnterSLEEPMode+0x52>
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI();
|
|
800280e: bf30 wfi
|
|
8002810: e002 b.n 8002818 <HAL_PWR_EnterSLEEPMode+0x58>
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__SEV();
|
|
8002812: bf40 sev
|
|
__WFE();
|
|
8002814: bf20 wfe
|
|
__WFE();
|
|
8002816: bf20 wfe
|
|
}
|
|
}
|
|
8002818: 3708 adds r7, #8
|
|
800281a: 46bd mov sp, r7
|
|
800281c: bd80 pop {r7, pc}
|
|
800281e: bf00 nop
|
|
8002820: 58000400 .word 0x58000400
|
|
8002824: e000ed00 .word 0xe000ed00
|
|
|
|
08002828 <HAL_PWREx_GetVoltageRange>:
|
|
/**
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
8002828: b480 push {r7}
|
|
800282a: af00 add r7, sp, #0
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
800282c: 4b03 ldr r3, [pc, #12] @ (800283c <HAL_PWREx_GetVoltageRange+0x14>)
|
|
800282e: 681b ldr r3, [r3, #0]
|
|
8002830: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
}
|
|
8002834: 4618 mov r0, r3
|
|
8002836: 46bd mov sp, r7
|
|
8002838: bc80 pop {r7}
|
|
800283a: 4770 bx lr
|
|
800283c: 58000400 .word 0x58000400
|
|
|
|
08002840 <HAL_PWREx_EnableLowPowerRunMode>:
|
|
* @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
|
|
* @note Clock frequency must be reduced below 2 MHz.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnableLowPowerRunMode(void)
|
|
{
|
|
8002840: b480 push {r7}
|
|
8002842: af00 add r7, sp, #0
|
|
/* Set Regulator parameter */
|
|
SET_BIT(PWR->CR1, PWR_CR1_LPR);
|
|
8002844: 4b04 ldr r3, [pc, #16] @ (8002858 <HAL_PWREx_EnableLowPowerRunMode+0x18>)
|
|
8002846: 681b ldr r3, [r3, #0]
|
|
8002848: 4a03 ldr r2, [pc, #12] @ (8002858 <HAL_PWREx_EnableLowPowerRunMode+0x18>)
|
|
800284a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800284e: 6013 str r3, [r2, #0]
|
|
}
|
|
8002850: bf00 nop
|
|
8002852: 46bd mov sp, r7
|
|
8002854: bc80 pop {r7}
|
|
8002856: 4770 bx lr
|
|
8002858: 58000400 .word 0x58000400
|
|
|
|
0800285c <HAL_PWREx_DisableLowPowerRunMode>:
|
|
* returns HAL_TIMEOUT status). The system clock frequency can then be
|
|
* increased above 2 MHz.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
|
|
{
|
|
800285c: b480 push {r7}
|
|
800285e: b083 sub sp, #12
|
|
8002860: af00 add r7, sp, #0
|
|
uint32_t wait_loop_index;
|
|
|
|
/* Clear LPR bit */
|
|
CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
|
|
8002862: 4b16 ldr r3, [pc, #88] @ (80028bc <HAL_PWREx_DisableLowPowerRunMode+0x60>)
|
|
8002864: 681b ldr r3, [r3, #0]
|
|
8002866: 4a15 ldr r2, [pc, #84] @ (80028bc <HAL_PWREx_DisableLowPowerRunMode+0x60>)
|
|
8002868: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800286c: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until REGLPF is reset */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL);
|
|
800286e: 4b14 ldr r3, [pc, #80] @ (80028c0 <HAL_PWREx_DisableLowPowerRunMode+0x64>)
|
|
8002870: 681b ldr r3, [r3, #0]
|
|
8002872: 2232 movs r2, #50 @ 0x32
|
|
8002874: fb02 f303 mul.w r3, r2, r3
|
|
8002878: 4a12 ldr r2, [pc, #72] @ (80028c4 <HAL_PWREx_DisableLowPowerRunMode+0x68>)
|
|
800287a: fba2 2303 umull r2, r3, r2, r3
|
|
800287e: 0c9b lsrs r3, r3, #18
|
|
8002880: 607b str r3, [r7, #4]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
|
|
8002882: e002 b.n 800288a <HAL_PWREx_DisableLowPowerRunMode+0x2e>
|
|
{
|
|
wait_loop_index--;
|
|
8002884: 687b ldr r3, [r7, #4]
|
|
8002886: 3b01 subs r3, #1
|
|
8002888: 607b str r3, [r7, #4]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
|
|
800288a: 4b0c ldr r3, [pc, #48] @ (80028bc <HAL_PWREx_DisableLowPowerRunMode+0x60>)
|
|
800288c: 695b ldr r3, [r3, #20]
|
|
800288e: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8002892: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8002896: d102 bne.n 800289e <HAL_PWREx_DisableLowPowerRunMode+0x42>
|
|
8002898: 687b ldr r3, [r7, #4]
|
|
800289a: 2b00 cmp r3, #0
|
|
800289c: d1f2 bne.n 8002884 <HAL_PWREx_DisableLowPowerRunMode+0x28>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF)))
|
|
800289e: 4b07 ldr r3, [pc, #28] @ (80028bc <HAL_PWREx_DisableLowPowerRunMode+0x60>)
|
|
80028a0: 695b ldr r3, [r3, #20]
|
|
80028a2: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80028a6: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80028aa: d101 bne.n 80028b0 <HAL_PWREx_DisableLowPowerRunMode+0x54>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80028ac: 2303 movs r3, #3
|
|
80028ae: e000 b.n 80028b2 <HAL_PWREx_DisableLowPowerRunMode+0x56>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80028b0: 2300 movs r3, #0
|
|
}
|
|
80028b2: 4618 mov r0, r3
|
|
80028b4: 370c adds r7, #12
|
|
80028b6: 46bd mov sp, r7
|
|
80028b8: bc80 pop {r7}
|
|
80028ba: 4770 bx lr
|
|
80028bc: 58000400 .word 0x58000400
|
|
80028c0: 20000000 .word 0x20000000
|
|
80028c4: 431bde83 .word 0x431bde83
|
|
|
|
080028c8 <HAL_PWREx_EnterSTOP2Mode>:
|
|
* @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
* @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
|
|
{
|
|
80028c8: b480 push {r7}
|
|
80028ca: b083 sub sp, #12
|
|
80028cc: af00 add r7, sp, #0
|
|
80028ce: 4603 mov r3, r0
|
|
80028d0: 71fb strb r3, [r7, #7]
|
|
#ifdef CORE_CM0PLUS
|
|
/* Set Stop mode 2 */
|
|
MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2);
|
|
#else
|
|
/* Set Stop mode 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2);
|
|
80028d2: 4b10 ldr r3, [pc, #64] @ (8002914 <HAL_PWREx_EnterSTOP2Mode+0x4c>)
|
|
80028d4: 681b ldr r3, [r3, #0]
|
|
80028d6: f023 0307 bic.w r3, r3, #7
|
|
80028da: 4a0e ldr r2, [pc, #56] @ (8002914 <HAL_PWREx_EnterSTOP2Mode+0x4c>)
|
|
80028dc: f043 0302 orr.w r3, r3, #2
|
|
80028e0: 6013 str r3, [r2, #0]
|
|
#endif /* CORE_CM0PLUS */
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
80028e2: 4b0d ldr r3, [pc, #52] @ (8002918 <HAL_PWREx_EnterSTOP2Mode+0x50>)
|
|
80028e4: 691b ldr r3, [r3, #16]
|
|
80028e6: 4a0c ldr r2, [pc, #48] @ (8002918 <HAL_PWREx_EnterSTOP2Mode+0x50>)
|
|
80028e8: f043 0304 orr.w r3, r3, #4
|
|
80028ec: 6113 str r3, [r2, #16]
|
|
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
|
if (STOPEntry == PWR_STOPENTRY_WFI)
|
|
80028ee: 79fb ldrb r3, [r7, #7]
|
|
80028f0: 2b01 cmp r3, #1
|
|
80028f2: d101 bne.n 80028f8 <HAL_PWREx_EnterSTOP2Mode+0x30>
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI();
|
|
80028f4: bf30 wfi
|
|
80028f6: e002 b.n 80028fe <HAL_PWREx_EnterSTOP2Mode+0x36>
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__SEV();
|
|
80028f8: bf40 sev
|
|
__WFE();
|
|
80028fa: bf20 wfe
|
|
__WFE();
|
|
80028fc: bf20 wfe
|
|
}
|
|
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
80028fe: 4b06 ldr r3, [pc, #24] @ (8002918 <HAL_PWREx_EnterSTOP2Mode+0x50>)
|
|
8002900: 691b ldr r3, [r3, #16]
|
|
8002902: 4a05 ldr r2, [pc, #20] @ (8002918 <HAL_PWREx_EnterSTOP2Mode+0x50>)
|
|
8002904: f023 0304 bic.w r3, r3, #4
|
|
8002908: 6113 str r3, [r2, #16]
|
|
}
|
|
800290a: bf00 nop
|
|
800290c: 370c adds r7, #12
|
|
800290e: 46bd mov sp, r7
|
|
8002910: bc80 pop {r7}
|
|
8002912: 4770 bx lr
|
|
8002914: 58000400 .word 0x58000400
|
|
8002918: e000ed00 .word 0xe000ed00
|
|
|
|
0800291c <LL_PWR_IsEnabledBkUpAccess>:
|
|
{
|
|
800291c: b480 push {r7}
|
|
800291e: af00 add r7, sp, #0
|
|
return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
|
|
8002920: 4b06 ldr r3, [pc, #24] @ (800293c <LL_PWR_IsEnabledBkUpAccess+0x20>)
|
|
8002922: 681b ldr r3, [r3, #0]
|
|
8002924: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002928: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
800292c: d101 bne.n 8002932 <LL_PWR_IsEnabledBkUpAccess+0x16>
|
|
800292e: 2301 movs r3, #1
|
|
8002930: e000 b.n 8002934 <LL_PWR_IsEnabledBkUpAccess+0x18>
|
|
8002932: 2300 movs r3, #0
|
|
}
|
|
8002934: 4618 mov r0, r3
|
|
8002936: 46bd mov sp, r7
|
|
8002938: bc80 pop {r7}
|
|
800293a: 4770 bx lr
|
|
800293c: 58000400 .word 0x58000400
|
|
|
|
08002940 <LL_RCC_HSE_EnableTcxo>:
|
|
{
|
|
8002940: b480 push {r7}
|
|
8002942: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR);
|
|
8002944: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002948: 681b ldr r3, [r3, #0]
|
|
800294a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800294e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8002952: 6013 str r3, [r2, #0]
|
|
}
|
|
8002954: bf00 nop
|
|
8002956: 46bd mov sp, r7
|
|
8002958: bc80 pop {r7}
|
|
800295a: 4770 bx lr
|
|
|
|
0800295c <LL_RCC_HSE_DisableTcxo>:
|
|
{
|
|
800295c: b480 push {r7}
|
|
800295e: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR);
|
|
8002960: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002964: 681b ldr r3, [r3, #0]
|
|
8002966: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800296a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800296e: 6013 str r3, [r2, #0]
|
|
}
|
|
8002970: bf00 nop
|
|
8002972: 46bd mov sp, r7
|
|
8002974: bc80 pop {r7}
|
|
8002976: 4770 bx lr
|
|
|
|
08002978 <LL_RCC_HSE_IsEnabledDiv2>:
|
|
{
|
|
8002978: b480 push {r7}
|
|
800297a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
|
|
800297c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002980: 681b ldr r3, [r3, #0]
|
|
8002982: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002986: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800298a: d101 bne.n 8002990 <LL_RCC_HSE_IsEnabledDiv2+0x18>
|
|
800298c: 2301 movs r3, #1
|
|
800298e: e000 b.n 8002992 <LL_RCC_HSE_IsEnabledDiv2+0x1a>
|
|
8002990: 2300 movs r3, #0
|
|
}
|
|
8002992: 4618 mov r0, r3
|
|
8002994: 46bd mov sp, r7
|
|
8002996: bc80 pop {r7}
|
|
8002998: 4770 bx lr
|
|
|
|
0800299a <LL_RCC_HSE_Enable>:
|
|
{
|
|
800299a: b480 push {r7}
|
|
800299c: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_HSEON);
|
|
800299e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80029a2: 681b ldr r3, [r3, #0]
|
|
80029a4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
80029a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80029ac: 6013 str r3, [r2, #0]
|
|
}
|
|
80029ae: bf00 nop
|
|
80029b0: 46bd mov sp, r7
|
|
80029b2: bc80 pop {r7}
|
|
80029b4: 4770 bx lr
|
|
|
|
080029b6 <LL_RCC_HSE_Disable>:
|
|
{
|
|
80029b6: b480 push {r7}
|
|
80029b8: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
|
|
80029ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80029be: 681b ldr r3, [r3, #0]
|
|
80029c0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
80029c4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80029c8: 6013 str r3, [r2, #0]
|
|
}
|
|
80029ca: bf00 nop
|
|
80029cc: 46bd mov sp, r7
|
|
80029ce: bc80 pop {r7}
|
|
80029d0: 4770 bx lr
|
|
|
|
080029d2 <LL_RCC_HSE_IsReady>:
|
|
{
|
|
80029d2: b480 push {r7}
|
|
80029d4: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
|
|
80029d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80029da: 681b ldr r3, [r3, #0]
|
|
80029dc: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80029e0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
80029e4: d101 bne.n 80029ea <LL_RCC_HSE_IsReady+0x18>
|
|
80029e6: 2301 movs r3, #1
|
|
80029e8: e000 b.n 80029ec <LL_RCC_HSE_IsReady+0x1a>
|
|
80029ea: 2300 movs r3, #0
|
|
}
|
|
80029ec: 4618 mov r0, r3
|
|
80029ee: 46bd mov sp, r7
|
|
80029f0: bc80 pop {r7}
|
|
80029f2: 4770 bx lr
|
|
|
|
080029f4 <LL_RCC_HSI_Enable>:
|
|
{
|
|
80029f4: b480 push {r7}
|
|
80029f6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_HSION);
|
|
80029f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80029fc: 681b ldr r3, [r3, #0]
|
|
80029fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002a02: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002a06: 6013 str r3, [r2, #0]
|
|
}
|
|
8002a08: bf00 nop
|
|
8002a0a: 46bd mov sp, r7
|
|
8002a0c: bc80 pop {r7}
|
|
8002a0e: 4770 bx lr
|
|
|
|
08002a10 <LL_RCC_HSI_Disable>:
|
|
{
|
|
8002a10: b480 push {r7}
|
|
8002a12: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
|
|
8002a14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002a18: 681b ldr r3, [r3, #0]
|
|
8002a1a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002a1e: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8002a22: 6013 str r3, [r2, #0]
|
|
}
|
|
8002a24: bf00 nop
|
|
8002a26: 46bd mov sp, r7
|
|
8002a28: bc80 pop {r7}
|
|
8002a2a: 4770 bx lr
|
|
|
|
08002a2c <LL_RCC_HSI_IsReady>:
|
|
{
|
|
8002a2c: b480 push {r7}
|
|
8002a2e: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
|
|
8002a30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002a34: 681b ldr r3, [r3, #0]
|
|
8002a36: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002a3a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002a3e: d101 bne.n 8002a44 <LL_RCC_HSI_IsReady+0x18>
|
|
8002a40: 2301 movs r3, #1
|
|
8002a42: e000 b.n 8002a46 <LL_RCC_HSI_IsReady+0x1a>
|
|
8002a44: 2300 movs r3, #0
|
|
}
|
|
8002a46: 4618 mov r0, r3
|
|
8002a48: 46bd mov sp, r7
|
|
8002a4a: bc80 pop {r7}
|
|
8002a4c: 4770 bx lr
|
|
|
|
08002a4e <LL_RCC_HSI_SetCalibTrimming>:
|
|
{
|
|
8002a4e: b480 push {r7}
|
|
8002a50: b083 sub sp, #12
|
|
8002a52: af00 add r7, sp, #0
|
|
8002a54: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
|
|
8002a56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002a5a: 685b ldr r3, [r3, #4]
|
|
8002a5c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
8002a60: 687b ldr r3, [r7, #4]
|
|
8002a62: 061b lsls r3, r3, #24
|
|
8002a64: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002a68: 4313 orrs r3, r2
|
|
8002a6a: 604b str r3, [r1, #4]
|
|
}
|
|
8002a6c: bf00 nop
|
|
8002a6e: 370c adds r7, #12
|
|
8002a70: 46bd mov sp, r7
|
|
8002a72: bc80 pop {r7}
|
|
8002a74: 4770 bx lr
|
|
|
|
08002a76 <LL_RCC_LSE_IsReady>:
|
|
{
|
|
8002a76: b480 push {r7}
|
|
8002a78: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
|
|
8002a7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002a7e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002a82: f003 0302 and.w r3, r3, #2
|
|
8002a86: 2b02 cmp r3, #2
|
|
8002a88: d101 bne.n 8002a8e <LL_RCC_LSE_IsReady+0x18>
|
|
8002a8a: 2301 movs r3, #1
|
|
8002a8c: e000 b.n 8002a90 <LL_RCC_LSE_IsReady+0x1a>
|
|
8002a8e: 2300 movs r3, #0
|
|
}
|
|
8002a90: 4618 mov r0, r3
|
|
8002a92: 46bd mov sp, r7
|
|
8002a94: bc80 pop {r7}
|
|
8002a96: 4770 bx lr
|
|
|
|
08002a98 <LL_RCC_LSI_Enable>:
|
|
{
|
|
8002a98: b480 push {r7}
|
|
8002a9a: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSION);
|
|
8002a9c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002aa0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002aa4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002aa8: f043 0301 orr.w r3, r3, #1
|
|
8002aac: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
8002ab0: bf00 nop
|
|
8002ab2: 46bd mov sp, r7
|
|
8002ab4: bc80 pop {r7}
|
|
8002ab6: 4770 bx lr
|
|
|
|
08002ab8 <LL_RCC_LSI_Disable>:
|
|
{
|
|
8002ab8: b480 push {r7}
|
|
8002aba: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
|
|
8002abc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002ac0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002ac4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002ac8: f023 0301 bic.w r3, r3, #1
|
|
8002acc: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
8002ad0: bf00 nop
|
|
8002ad2: 46bd mov sp, r7
|
|
8002ad4: bc80 pop {r7}
|
|
8002ad6: 4770 bx lr
|
|
|
|
08002ad8 <LL_RCC_LSI_IsReady>:
|
|
{
|
|
8002ad8: b480 push {r7}
|
|
8002ada: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
|
|
8002adc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002ae0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002ae4: f003 0302 and.w r3, r3, #2
|
|
8002ae8: 2b02 cmp r3, #2
|
|
8002aea: d101 bne.n 8002af0 <LL_RCC_LSI_IsReady+0x18>
|
|
8002aec: 2301 movs r3, #1
|
|
8002aee: e000 b.n 8002af2 <LL_RCC_LSI_IsReady+0x1a>
|
|
8002af0: 2300 movs r3, #0
|
|
}
|
|
8002af2: 4618 mov r0, r3
|
|
8002af4: 46bd mov sp, r7
|
|
8002af6: bc80 pop {r7}
|
|
8002af8: 4770 bx lr
|
|
|
|
08002afa <LL_RCC_MSI_Enable>:
|
|
{
|
|
8002afa: b480 push {r7}
|
|
8002afc: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSION);
|
|
8002afe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b02: 681b ldr r3, [r3, #0]
|
|
8002b04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002b08: f043 0301 orr.w r3, r3, #1
|
|
8002b0c: 6013 str r3, [r2, #0]
|
|
}
|
|
8002b0e: bf00 nop
|
|
8002b10: 46bd mov sp, r7
|
|
8002b12: bc80 pop {r7}
|
|
8002b14: 4770 bx lr
|
|
|
|
08002b16 <LL_RCC_MSI_Disable>:
|
|
{
|
|
8002b16: b480 push {r7}
|
|
8002b18: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_MSION);
|
|
8002b1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b1e: 681b ldr r3, [r3, #0]
|
|
8002b20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002b24: f023 0301 bic.w r3, r3, #1
|
|
8002b28: 6013 str r3, [r2, #0]
|
|
}
|
|
8002b2a: bf00 nop
|
|
8002b2c: 46bd mov sp, r7
|
|
8002b2e: bc80 pop {r7}
|
|
8002b30: 4770 bx lr
|
|
|
|
08002b32 <LL_RCC_MSI_IsReady>:
|
|
{
|
|
8002b32: b480 push {r7}
|
|
8002b34: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
|
|
8002b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b3a: 681b ldr r3, [r3, #0]
|
|
8002b3c: f003 0302 and.w r3, r3, #2
|
|
8002b40: 2b02 cmp r3, #2
|
|
8002b42: d101 bne.n 8002b48 <LL_RCC_MSI_IsReady+0x16>
|
|
8002b44: 2301 movs r3, #1
|
|
8002b46: e000 b.n 8002b4a <LL_RCC_MSI_IsReady+0x18>
|
|
8002b48: 2300 movs r3, #0
|
|
}
|
|
8002b4a: 4618 mov r0, r3
|
|
8002b4c: 46bd mov sp, r7
|
|
8002b4e: bc80 pop {r7}
|
|
8002b50: 4770 bx lr
|
|
|
|
08002b52 <LL_RCC_MSI_IsEnabledRangeSelect>:
|
|
{
|
|
8002b52: b480 push {r7}
|
|
8002b54: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL);
|
|
8002b56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b5a: 681b ldr r3, [r3, #0]
|
|
8002b5c: f003 0308 and.w r3, r3, #8
|
|
8002b60: 2b08 cmp r3, #8
|
|
8002b62: d101 bne.n 8002b68 <LL_RCC_MSI_IsEnabledRangeSelect+0x16>
|
|
8002b64: 2301 movs r3, #1
|
|
8002b66: e000 b.n 8002b6a <LL_RCC_MSI_IsEnabledRangeSelect+0x18>
|
|
8002b68: 2300 movs r3, #0
|
|
}
|
|
8002b6a: 4618 mov r0, r3
|
|
8002b6c: 46bd mov sp, r7
|
|
8002b6e: bc80 pop {r7}
|
|
8002b70: 4770 bx lr
|
|
|
|
08002b72 <LL_RCC_MSI_GetRange>:
|
|
{
|
|
8002b72: b480 push {r7}
|
|
8002b74: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
|
|
8002b76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b7a: 681b ldr r3, [r3, #0]
|
|
8002b7c: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
8002b80: 4618 mov r0, r3
|
|
8002b82: 46bd mov sp, r7
|
|
8002b84: bc80 pop {r7}
|
|
8002b86: 4770 bx lr
|
|
|
|
08002b88 <LL_RCC_MSI_GetRangeAfterStandby>:
|
|
{
|
|
8002b88: b480 push {r7}
|
|
8002b8a: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
|
|
8002b8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002b90: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002b94: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
}
|
|
8002b98: 4618 mov r0, r3
|
|
8002b9a: 46bd mov sp, r7
|
|
8002b9c: bc80 pop {r7}
|
|
8002b9e: 4770 bx lr
|
|
|
|
08002ba0 <LL_RCC_MSI_SetCalibTrimming>:
|
|
{
|
|
8002ba0: b480 push {r7}
|
|
8002ba2: b083 sub sp, #12
|
|
8002ba4: af00 add r7, sp, #0
|
|
8002ba6: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
|
|
8002ba8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002bac: 685b ldr r3, [r3, #4]
|
|
8002bae: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8002bb2: 687b ldr r3, [r7, #4]
|
|
8002bb4: 021b lsls r3, r3, #8
|
|
8002bb6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002bba: 4313 orrs r3, r2
|
|
8002bbc: 604b str r3, [r1, #4]
|
|
}
|
|
8002bbe: bf00 nop
|
|
8002bc0: 370c adds r7, #12
|
|
8002bc2: 46bd mov sp, r7
|
|
8002bc4: bc80 pop {r7}
|
|
8002bc6: 4770 bx lr
|
|
|
|
08002bc8 <LL_RCC_SetSysClkSource>:
|
|
{
|
|
8002bc8: b480 push {r7}
|
|
8002bca: b083 sub sp, #12
|
|
8002bcc: af00 add r7, sp, #0
|
|
8002bce: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
|
|
8002bd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002bd4: 689b ldr r3, [r3, #8]
|
|
8002bd6: f023 0203 bic.w r2, r3, #3
|
|
8002bda: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002bde: 687b ldr r3, [r7, #4]
|
|
8002be0: 4313 orrs r3, r2
|
|
8002be2: 608b str r3, [r1, #8]
|
|
}
|
|
8002be4: bf00 nop
|
|
8002be6: 370c adds r7, #12
|
|
8002be8: 46bd mov sp, r7
|
|
8002bea: bc80 pop {r7}
|
|
8002bec: 4770 bx lr
|
|
|
|
08002bee <LL_RCC_GetSysClkSource>:
|
|
{
|
|
8002bee: b480 push {r7}
|
|
8002bf0: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
|
8002bf2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002bf6: 689b ldr r3, [r3, #8]
|
|
8002bf8: f003 030c and.w r3, r3, #12
|
|
}
|
|
8002bfc: 4618 mov r0, r3
|
|
8002bfe: 46bd mov sp, r7
|
|
8002c00: bc80 pop {r7}
|
|
8002c02: 4770 bx lr
|
|
|
|
08002c04 <LL_RCC_SetAHBPrescaler>:
|
|
{
|
|
8002c04: b480 push {r7}
|
|
8002c06: b083 sub sp, #12
|
|
8002c08: af00 add r7, sp, #0
|
|
8002c0a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
|
|
8002c0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002c10: 689b ldr r3, [r3, #8]
|
|
8002c12: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002c16: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002c1a: 687b ldr r3, [r7, #4]
|
|
8002c1c: 4313 orrs r3, r2
|
|
8002c1e: 608b str r3, [r1, #8]
|
|
}
|
|
8002c20: bf00 nop
|
|
8002c22: 370c adds r7, #12
|
|
8002c24: 46bd mov sp, r7
|
|
8002c26: bc80 pop {r7}
|
|
8002c28: 4770 bx lr
|
|
|
|
08002c2a <LL_C2_RCC_SetAHBPrescaler>:
|
|
{
|
|
8002c2a: b480 push {r7}
|
|
8002c2c: b083 sub sp, #12
|
|
8002c2e: af00 add r7, sp, #0
|
|
8002c30: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
|
|
8002c32: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002c36: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
8002c3a: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002c3e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002c42: 687b ldr r3, [r7, #4]
|
|
8002c44: 4313 orrs r3, r2
|
|
8002c46: f8c1 3108 str.w r3, [r1, #264] @ 0x108
|
|
}
|
|
8002c4a: bf00 nop
|
|
8002c4c: 370c adds r7, #12
|
|
8002c4e: 46bd mov sp, r7
|
|
8002c50: bc80 pop {r7}
|
|
8002c52: 4770 bx lr
|
|
|
|
08002c54 <LL_RCC_SetAHB3Prescaler>:
|
|
{
|
|
8002c54: b480 push {r7}
|
|
8002c56: b083 sub sp, #12
|
|
8002c58: af00 add r7, sp, #0
|
|
8002c5a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
|
|
8002c5c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002c60: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
8002c64: f023 020f bic.w r2, r3, #15
|
|
8002c68: 687b ldr r3, [r7, #4]
|
|
8002c6a: 091b lsrs r3, r3, #4
|
|
8002c6c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002c70: 4313 orrs r3, r2
|
|
8002c72: f8c1 3108 str.w r3, [r1, #264] @ 0x108
|
|
}
|
|
8002c76: bf00 nop
|
|
8002c78: 370c adds r7, #12
|
|
8002c7a: 46bd mov sp, r7
|
|
8002c7c: bc80 pop {r7}
|
|
8002c7e: 4770 bx lr
|
|
|
|
08002c80 <LL_RCC_SetAPB1Prescaler>:
|
|
{
|
|
8002c80: b480 push {r7}
|
|
8002c82: b083 sub sp, #12
|
|
8002c84: af00 add r7, sp, #0
|
|
8002c86: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
|
|
8002c88: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002c8c: 689b ldr r3, [r3, #8]
|
|
8002c8e: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
8002c92: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002c96: 687b ldr r3, [r7, #4]
|
|
8002c98: 4313 orrs r3, r2
|
|
8002c9a: 608b str r3, [r1, #8]
|
|
}
|
|
8002c9c: bf00 nop
|
|
8002c9e: 370c adds r7, #12
|
|
8002ca0: 46bd mov sp, r7
|
|
8002ca2: bc80 pop {r7}
|
|
8002ca4: 4770 bx lr
|
|
|
|
08002ca6 <LL_RCC_SetAPB2Prescaler>:
|
|
{
|
|
8002ca6: b480 push {r7}
|
|
8002ca8: b083 sub sp, #12
|
|
8002caa: af00 add r7, sp, #0
|
|
8002cac: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
|
|
8002cae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002cb2: 689b ldr r3, [r3, #8]
|
|
8002cb4: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8002cb8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002cbc: 687b ldr r3, [r7, #4]
|
|
8002cbe: 4313 orrs r3, r2
|
|
8002cc0: 608b str r3, [r1, #8]
|
|
}
|
|
8002cc2: bf00 nop
|
|
8002cc4: 370c adds r7, #12
|
|
8002cc6: 46bd mov sp, r7
|
|
8002cc8: bc80 pop {r7}
|
|
8002cca: 4770 bx lr
|
|
|
|
08002ccc <LL_RCC_GetAHBPrescaler>:
|
|
{
|
|
8002ccc: b480 push {r7}
|
|
8002cce: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
|
|
8002cd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002cd4: 689b ldr r3, [r3, #8]
|
|
8002cd6: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
8002cda: 4618 mov r0, r3
|
|
8002cdc: 46bd mov sp, r7
|
|
8002cde: bc80 pop {r7}
|
|
8002ce0: 4770 bx lr
|
|
|
|
08002ce2 <LL_RCC_GetAHB3Prescaler>:
|
|
{
|
|
8002ce2: b480 push {r7}
|
|
8002ce4: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
|
|
8002ce6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002cea: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
8002cee: 011b lsls r3, r3, #4
|
|
8002cf0: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
8002cf4: 4618 mov r0, r3
|
|
8002cf6: 46bd mov sp, r7
|
|
8002cf8: bc80 pop {r7}
|
|
8002cfa: 4770 bx lr
|
|
|
|
08002cfc <LL_RCC_GetAPB1Prescaler>:
|
|
{
|
|
8002cfc: b480 push {r7}
|
|
8002cfe: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
|
|
8002d00: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d04: 689b ldr r3, [r3, #8]
|
|
8002d06: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
}
|
|
8002d0a: 4618 mov r0, r3
|
|
8002d0c: 46bd mov sp, r7
|
|
8002d0e: bc80 pop {r7}
|
|
8002d10: 4770 bx lr
|
|
|
|
08002d12 <LL_RCC_GetAPB2Prescaler>:
|
|
{
|
|
8002d12: b480 push {r7}
|
|
8002d14: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
|
|
8002d16: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d1a: 689b ldr r3, [r3, #8]
|
|
8002d1c: f403 5360 and.w r3, r3, #14336 @ 0x3800
|
|
}
|
|
8002d20: 4618 mov r0, r3
|
|
8002d22: 46bd mov sp, r7
|
|
8002d24: bc80 pop {r7}
|
|
8002d26: 4770 bx lr
|
|
|
|
08002d28 <LL_RCC_PLL_Enable>:
|
|
* @brief Enable PLL
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
|
|
{
|
|
8002d28: b480 push {r7}
|
|
8002d2a: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLON);
|
|
8002d2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d30: 681b ldr r3, [r3, #0]
|
|
8002d32: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002d36: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8002d3a: 6013 str r3, [r2, #0]
|
|
}
|
|
8002d3c: bf00 nop
|
|
8002d3e: 46bd mov sp, r7
|
|
8002d40: bc80 pop {r7}
|
|
8002d42: 4770 bx lr
|
|
|
|
08002d44 <LL_RCC_PLL_Disable>:
|
|
* @note Cannot be disabled if the PLL clock is used as the system clock
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Disable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
|
|
{
|
|
8002d44: b480 push {r7}
|
|
8002d46: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
|
|
8002d48: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d4c: 681b ldr r3, [r3, #0]
|
|
8002d4e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002d52: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8002d56: 6013 str r3, [r2, #0]
|
|
}
|
|
8002d58: bf00 nop
|
|
8002d5a: 46bd mov sp, r7
|
|
8002d5c: bc80 pop {r7}
|
|
8002d5e: 4770 bx lr
|
|
|
|
08002d60 <LL_RCC_PLL_IsReady>:
|
|
* @brief Check if PLL Ready
|
|
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
|
|
{
|
|
8002d60: b480 push {r7}
|
|
8002d62: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
|
|
8002d64: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d68: 681b ldr r3, [r3, #0]
|
|
8002d6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002d6e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8002d72: d101 bne.n 8002d78 <LL_RCC_PLL_IsReady+0x18>
|
|
8002d74: 2301 movs r3, #1
|
|
8002d76: e000 b.n 8002d7a <LL_RCC_PLL_IsReady+0x1a>
|
|
8002d78: 2300 movs r3, #0
|
|
}
|
|
8002d7a: 4618 mov r0, r3
|
|
8002d7c: 46bd mov sp, r7
|
|
8002d7e: bc80 pop {r7}
|
|
8002d80: 4770 bx lr
|
|
|
|
08002d82 <LL_RCC_PLL_GetN>:
|
|
* @brief Get Main PLL multiplication factor for VCO
|
|
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
|
|
* @retval Between 6 and 127
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
|
|
{
|
|
8002d82: b480 push {r7}
|
|
8002d84: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8002d86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002d8a: 68db ldr r3, [r3, #12]
|
|
8002d8c: 0a1b lsrs r3, r3, #8
|
|
8002d8e: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
}
|
|
8002d92: 4618 mov r0, r3
|
|
8002d94: 46bd mov sp, r7
|
|
8002d96: bc80 pop {r7}
|
|
8002d98: 4770 bx lr
|
|
|
|
08002d9a <LL_RCC_PLL_GetR>:
|
|
* @arg @ref LL_RCC_PLLR_DIV_6
|
|
* @arg @ref LL_RCC_PLLR_DIV_7
|
|
* @arg @ref LL_RCC_PLLR_DIV_8
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
|
|
{
|
|
8002d9a: b480 push {r7}
|
|
8002d9c: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
|
|
8002d9e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002da2: 68db ldr r3, [r3, #12]
|
|
8002da4: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000
|
|
}
|
|
8002da8: 4618 mov r0, r3
|
|
8002daa: 46bd mov sp, r7
|
|
8002dac: bc80 pop {r7}
|
|
8002dae: 4770 bx lr
|
|
|
|
08002db0 <LL_RCC_PLL_GetDivider>:
|
|
* @arg @ref LL_RCC_PLLM_DIV_6
|
|
* @arg @ref LL_RCC_PLLM_DIV_7
|
|
* @arg @ref LL_RCC_PLLM_DIV_8
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
|
|
{
|
|
8002db0: b480 push {r7}
|
|
8002db2: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
|
|
8002db4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002db8: 68db ldr r3, [r3, #12]
|
|
8002dba: f003 0370 and.w r3, r3, #112 @ 0x70
|
|
}
|
|
8002dbe: 4618 mov r0, r3
|
|
8002dc0: 46bd mov sp, r7
|
|
8002dc2: bc80 pop {r7}
|
|
8002dc4: 4770 bx lr
|
|
|
|
08002dc6 <LL_RCC_PLL_GetMainSource>:
|
|
* @arg @ref LL_RCC_PLLSOURCE_MSI
|
|
* @arg @ref LL_RCC_PLLSOURCE_HSI
|
|
* @arg @ref LL_RCC_PLLSOURCE_HSE
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
|
|
{
|
|
8002dc6: b480 push {r7}
|
|
8002dc8: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
|
|
8002dca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002dce: 68db ldr r3, [r3, #12]
|
|
8002dd0: f003 0303 and.w r3, r3, #3
|
|
}
|
|
8002dd4: 4618 mov r0, r3
|
|
8002dd6: 46bd mov sp, r7
|
|
8002dd8: bc80 pop {r7}
|
|
8002dda: 4770 bx lr
|
|
|
|
08002ddc <LL_RCC_IsActiveFlag_HPRE>:
|
|
* @brief Check if HCLK1 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
|
|
{
|
|
8002ddc: b480 push {r7}
|
|
8002dde: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
|
|
8002de0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002de4: 689b ldr r3, [r3, #8]
|
|
8002de6: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002dea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8002dee: d101 bne.n 8002df4 <LL_RCC_IsActiveFlag_HPRE+0x18>
|
|
8002df0: 2301 movs r3, #1
|
|
8002df2: e000 b.n 8002df6 <LL_RCC_IsActiveFlag_HPRE+0x1a>
|
|
8002df4: 2300 movs r3, #0
|
|
}
|
|
8002df6: 4618 mov r0, r3
|
|
8002df8: 46bd mov sp, r7
|
|
8002dfa: bc80 pop {r7}
|
|
8002dfc: 4770 bx lr
|
|
|
|
08002dfe <LL_RCC_IsActiveFlag_C2HPRE>:
|
|
* @brief Check if HCLK2 prescaler flag value has been applied or not
|
|
* @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
|
|
{
|
|
8002dfe: b480 push {r7}
|
|
8002e00: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
|
|
8002e02: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002e06: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
8002e0a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002e0e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
8002e12: d101 bne.n 8002e18 <LL_RCC_IsActiveFlag_C2HPRE+0x1a>
|
|
8002e14: 2301 movs r3, #1
|
|
8002e16: e000 b.n 8002e1a <LL_RCC_IsActiveFlag_C2HPRE+0x1c>
|
|
8002e18: 2300 movs r3, #0
|
|
}
|
|
8002e1a: 4618 mov r0, r3
|
|
8002e1c: 46bd mov sp, r7
|
|
8002e1e: bc80 pop {r7}
|
|
8002e20: 4770 bx lr
|
|
|
|
08002e22 <LL_RCC_IsActiveFlag_SHDHPRE>:
|
|
* @brief Check if HCLK3 prescaler flag value has been applied or not
|
|
* @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
|
|
{
|
|
8002e22: b480 push {r7}
|
|
8002e24: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
|
|
8002e26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002e2a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
8002e2e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002e32: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8002e36: d101 bne.n 8002e3c <LL_RCC_IsActiveFlag_SHDHPRE+0x1a>
|
|
8002e38: 2301 movs r3, #1
|
|
8002e3a: e000 b.n 8002e3e <LL_RCC_IsActiveFlag_SHDHPRE+0x1c>
|
|
8002e3c: 2300 movs r3, #0
|
|
}
|
|
8002e3e: 4618 mov r0, r3
|
|
8002e40: 46bd mov sp, r7
|
|
8002e42: bc80 pop {r7}
|
|
8002e44: 4770 bx lr
|
|
|
|
08002e46 <LL_RCC_IsActiveFlag_PPRE1>:
|
|
* @brief Check if PLCK1 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
|
|
{
|
|
8002e46: b480 push {r7}
|
|
8002e48: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
|
|
8002e4a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002e4e: 689b ldr r3, [r3, #8]
|
|
8002e50: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002e54: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
8002e58: d101 bne.n 8002e5e <LL_RCC_IsActiveFlag_PPRE1+0x18>
|
|
8002e5a: 2301 movs r3, #1
|
|
8002e5c: e000 b.n 8002e60 <LL_RCC_IsActiveFlag_PPRE1+0x1a>
|
|
8002e5e: 2300 movs r3, #0
|
|
}
|
|
8002e60: 4618 mov r0, r3
|
|
8002e62: 46bd mov sp, r7
|
|
8002e64: bc80 pop {r7}
|
|
8002e66: 4770 bx lr
|
|
|
|
08002e68 <LL_RCC_IsActiveFlag_PPRE2>:
|
|
* @brief Check if PLCK2 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
|
|
{
|
|
8002e68: b480 push {r7}
|
|
8002e6a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
|
|
8002e6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002e70: 689b ldr r3, [r3, #8]
|
|
8002e72: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8002e76: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8002e7a: d101 bne.n 8002e80 <LL_RCC_IsActiveFlag_PPRE2+0x18>
|
|
8002e7c: 2301 movs r3, #1
|
|
8002e7e: e000 b.n 8002e82 <LL_RCC_IsActiveFlag_PPRE2+0x1a>
|
|
8002e80: 2300 movs r3, #0
|
|
}
|
|
8002e82: 4618 mov r0, r3
|
|
8002e84: 46bd mov sp, r7
|
|
8002e86: bc80 pop {r7}
|
|
8002e88: 4770 bx lr
|
|
...
|
|
|
|
08002e8c <HAL_RCC_OscConfig>:
|
|
* contains the configuration information for the RCC Oscillators.
|
|
* @note The PLL is not disabled when used as system clock.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8002e8c: b580 push {r7, lr}
|
|
8002e8e: b088 sub sp, #32
|
|
8002e90: af00 add r7, sp, #0
|
|
8002e92: 6078 str r0, [r7, #4]
|
|
uint32_t sysclk_source;
|
|
uint32_t pll_config;
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8002e94: 687b ldr r3, [r7, #4]
|
|
8002e96: 2b00 cmp r3, #0
|
|
8002e98: d101 bne.n 8002e9e <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e9a: 2301 movs r3, #1
|
|
8002e9c: e36f b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8002e9e: f7ff fea6 bl 8002bee <LL_RCC_GetSysClkSource>
|
|
8002ea2: 61f8 str r0, [r7, #28]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8002ea4: f7ff ff8f bl 8002dc6 <LL_RCC_PLL_GetMainSource>
|
|
8002ea8: 61b8 str r0, [r7, #24]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
8002eaa: 687b ldr r3, [r7, #4]
|
|
8002eac: 681b ldr r3, [r3, #0]
|
|
8002eae: f003 0320 and.w r3, r3, #32
|
|
8002eb2: 2b00 cmp r3, #0
|
|
8002eb4: f000 80c4 beq.w 8003040 <HAL_RCC_OscConfig+0x1b4>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* When the MSI is used as system clock it will not be disabled */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
|
|
8002eb8: 69fb ldr r3, [r7, #28]
|
|
8002eba: 2b00 cmp r3, #0
|
|
8002ebc: d005 beq.n 8002eca <HAL_RCC_OscConfig+0x3e>
|
|
8002ebe: 69fb ldr r3, [r7, #28]
|
|
8002ec0: 2b0c cmp r3, #12
|
|
8002ec2: d176 bne.n 8002fb2 <HAL_RCC_OscConfig+0x126>
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
8002ec4: 69bb ldr r3, [r7, #24]
|
|
8002ec6: 2b01 cmp r3, #1
|
|
8002ec8: d173 bne.n 8002fb2 <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
|
|
8002eca: 687b ldr r3, [r7, #4]
|
|
8002ecc: 6a1b ldr r3, [r3, #32]
|
|
8002ece: 2b00 cmp r3, #0
|
|
8002ed0: d101 bne.n 8002ed6 <HAL_RCC_OscConfig+0x4a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002ed2: 2301 movs r3, #1
|
|
8002ed4: e353 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the AHB3 clock
|
|
and the supply voltage of the device. */
|
|
if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
8002ed6: 687b ldr r3, [r7, #4]
|
|
8002ed8: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8002eda: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002ede: 681b ldr r3, [r3, #0]
|
|
8002ee0: f003 0308 and.w r3, r3, #8
|
|
8002ee4: 2b00 cmp r3, #0
|
|
8002ee6: d005 beq.n 8002ef4 <HAL_RCC_OscConfig+0x68>
|
|
8002ee8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002eec: 681b ldr r3, [r3, #0]
|
|
8002eee: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8002ef2: e006 b.n 8002f02 <HAL_RCC_OscConfig+0x76>
|
|
8002ef4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002ef8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002efc: 091b lsrs r3, r3, #4
|
|
8002efe: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8002f02: 4293 cmp r3, r2
|
|
8002f04: d222 bcs.n 8002f4c <HAL_RCC_OscConfig+0xc0>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8002f06: 687b ldr r3, [r7, #4]
|
|
8002f08: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002f0a: 4618 mov r0, r3
|
|
8002f0c: f000 fd5a bl 80039c4 <RCC_SetFlashLatencyFromMSIRange>
|
|
8002f10: 4603 mov r3, r0
|
|
8002f12: 2b00 cmp r3, #0
|
|
8002f14: d001 beq.n 8002f1a <HAL_RCC_OscConfig+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f16: 2301 movs r3, #1
|
|
8002f18: e331 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002f1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002f1e: 681b ldr r3, [r3, #0]
|
|
8002f20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002f24: f043 0308 orr.w r3, r3, #8
|
|
8002f28: 6013 str r3, [r2, #0]
|
|
8002f2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002f2e: 681b ldr r3, [r3, #0]
|
|
8002f30: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002f34: 687b ldr r3, [r7, #4]
|
|
8002f36: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002f38: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002f3c: 4313 orrs r3, r2
|
|
8002f3e: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8002f40: 687b ldr r3, [r7, #4]
|
|
8002f42: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002f44: 4618 mov r0, r3
|
|
8002f46: f7ff fe2b bl 8002ba0 <LL_RCC_MSI_SetCalibTrimming>
|
|
8002f4a: e021 b.n 8002f90 <HAL_RCC_OscConfig+0x104>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range. */
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002f4c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002f50: 681b ldr r3, [r3, #0]
|
|
8002f52: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002f56: f043 0308 orr.w r3, r3, #8
|
|
8002f5a: 6013 str r3, [r2, #0]
|
|
8002f5c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002f60: 681b ldr r3, [r3, #0]
|
|
8002f62: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002f66: 687b ldr r3, [r7, #4]
|
|
8002f68: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002f6a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002f6e: 4313 orrs r3, r2
|
|
8002f70: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8002f72: 687b ldr r3, [r7, #4]
|
|
8002f74: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002f76: 4618 mov r0, r3
|
|
8002f78: f7ff fe12 bl 8002ba0 <LL_RCC_MSI_SetCalibTrimming>
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8002f7c: 687b ldr r3, [r7, #4]
|
|
8002f7e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002f80: 4618 mov r0, r3
|
|
8002f82: f000 fd1f bl 80039c4 <RCC_SetFlashLatencyFromMSIRange>
|
|
8002f86: 4603 mov r3, r0
|
|
8002f88: 2b00 cmp r3, #0
|
|
8002f8a: d001 beq.n 8002f90 <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f8c: 2301 movs r3, #1
|
|
8002f8e: e2f6 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
8002f90: f000 fce0 bl 8003954 <HAL_RCC_GetHCLKFreq>
|
|
8002f94: 4603 mov r3, r0
|
|
8002f96: 4aa7 ldr r2, [pc, #668] @ (8003234 <HAL_RCC_OscConfig+0x3a8>)
|
|
8002f98: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8002f9a: 4ba7 ldr r3, [pc, #668] @ (8003238 <HAL_RCC_OscConfig+0x3ac>)
|
|
8002f9c: 681b ldr r3, [r3, #0]
|
|
8002f9e: 4618 mov r0, r3
|
|
8002fa0: f7fd fde4 bl 8000b6c <HAL_InitTick>
|
|
8002fa4: 4603 mov r3, r0
|
|
8002fa6: 74fb strb r3, [r7, #19]
|
|
if (status != HAL_OK)
|
|
8002fa8: 7cfb ldrb r3, [r7, #19]
|
|
8002faa: 2b00 cmp r3, #0
|
|
8002fac: d047 beq.n 800303e <HAL_RCC_OscConfig+0x1b2>
|
|
{
|
|
return status;
|
|
8002fae: 7cfb ldrb r3, [r7, #19]
|
|
8002fb0: e2e5 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8002fb2: 687b ldr r3, [r7, #4]
|
|
8002fb4: 6a1b ldr r3, [r3, #32]
|
|
8002fb6: 2b00 cmp r3, #0
|
|
8002fb8: d02c beq.n 8003014 <HAL_RCC_OscConfig+0x188>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
8002fba: f7ff fd9e bl 8002afa <LL_RCC_MSI_Enable>
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8002fbe: f7fd fddf bl 8000b80 <HAL_GetTick>
|
|
8002fc2: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till MSI is ready */
|
|
while (LL_RCC_MSI_IsReady() == 0U)
|
|
8002fc4: e008 b.n 8002fd8 <HAL_RCC_OscConfig+0x14c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8002fc6: f7fd fddb bl 8000b80 <HAL_GetTick>
|
|
8002fca: 4602 mov r2, r0
|
|
8002fcc: 697b ldr r3, [r7, #20]
|
|
8002fce: 1ad3 subs r3, r2, r3
|
|
8002fd0: 2b02 cmp r3, #2
|
|
8002fd2: d901 bls.n 8002fd8 <HAL_RCC_OscConfig+0x14c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002fd4: 2303 movs r3, #3
|
|
8002fd6: e2d2 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_MSI_IsReady() == 0U)
|
|
8002fd8: f7ff fdab bl 8002b32 <LL_RCC_MSI_IsReady>
|
|
8002fdc: 4603 mov r3, r0
|
|
8002fde: 2b00 cmp r3, #0
|
|
8002fe0: d0f1 beq.n 8002fc6 <HAL_RCC_OscConfig+0x13a>
|
|
}
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range. */
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002fe2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002fe6: 681b ldr r3, [r3, #0]
|
|
8002fe8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8002fec: f043 0308 orr.w r3, r3, #8
|
|
8002ff0: 6013 str r3, [r2, #0]
|
|
8002ff2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002ff6: 681b ldr r3, [r3, #0]
|
|
8002ff8: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002ffc: 687b ldr r3, [r7, #4]
|
|
8002ffe: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003000: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003004: 4313 orrs r3, r2
|
|
8003006: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value. */
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8003008: 687b ldr r3, [r7, #4]
|
|
800300a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800300c: 4618 mov r0, r3
|
|
800300e: f7ff fdc7 bl 8002ba0 <LL_RCC_MSI_SetCalibTrimming>
|
|
8003012: e015 b.n 8003040 <HAL_RCC_OscConfig+0x1b4>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
8003014: f7ff fd7f bl 8002b16 <LL_RCC_MSI_Disable>
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8003018: f7fd fdb2 bl 8000b80 <HAL_GetTick>
|
|
800301c: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till MSI is disabled */
|
|
while (LL_RCC_MSI_IsReady() != 0U)
|
|
800301e: e008 b.n 8003032 <HAL_RCC_OscConfig+0x1a6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8003020: f7fd fdae bl 8000b80 <HAL_GetTick>
|
|
8003024: 4602 mov r2, r0
|
|
8003026: 697b ldr r3, [r7, #20]
|
|
8003028: 1ad3 subs r3, r2, r3
|
|
800302a: 2b02 cmp r3, #2
|
|
800302c: d901 bls.n 8003032 <HAL_RCC_OscConfig+0x1a6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800302e: 2303 movs r3, #3
|
|
8003030: e2a5 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_MSI_IsReady() != 0U)
|
|
8003032: f7ff fd7e bl 8002b32 <LL_RCC_MSI_IsReady>
|
|
8003036: 4603 mov r3, r0
|
|
8003038: 2b00 cmp r3, #0
|
|
800303a: d1f1 bne.n 8003020 <HAL_RCC_OscConfig+0x194>
|
|
800303c: e000 b.n 8003040 <HAL_RCC_OscConfig+0x1b4>
|
|
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
|
|
800303e: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8003040: 687b ldr r3, [r7, #4]
|
|
8003042: 681b ldr r3, [r3, #0]
|
|
8003044: f003 0301 and.w r3, r3, #1
|
|
8003048: 2b00 cmp r3, #0
|
|
800304a: d058 beq.n 80030fe <HAL_RCC_OscConfig+0x272>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
|
|
800304c: 69fb ldr r3, [r7, #28]
|
|
800304e: 2b08 cmp r3, #8
|
|
8003050: d005 beq.n 800305e <HAL_RCC_OscConfig+0x1d2>
|
|
8003052: 69fb ldr r3, [r7, #28]
|
|
8003054: 2b0c cmp r3, #12
|
|
8003056: d108 bne.n 800306a <HAL_RCC_OscConfig+0x1de>
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
8003058: 69bb ldr r3, [r7, #24]
|
|
800305a: 2b03 cmp r3, #3
|
|
800305c: d105 bne.n 800306a <HAL_RCC_OscConfig+0x1de>
|
|
{
|
|
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
|
|
800305e: 687b ldr r3, [r7, #4]
|
|
8003060: 685b ldr r3, [r3, #4]
|
|
8003062: 2b00 cmp r3, #0
|
|
8003064: d14b bne.n 80030fe <HAL_RCC_OscConfig+0x272>
|
|
{
|
|
return HAL_ERROR;
|
|
8003066: 2301 movs r3, #1
|
|
8003068: e289 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
/* Check HSE division factor */
|
|
assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv));
|
|
|
|
/* Set HSE division factor */
|
|
MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv);
|
|
800306a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800306e: 681b ldr r3, [r3, #0]
|
|
8003070: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
|
|
8003074: 687b ldr r3, [r7, #4]
|
|
8003076: 689b ldr r3, [r3, #8]
|
|
8003078: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800307c: 4313 orrs r3, r2
|
|
800307e: 600b str r3, [r1, #0]
|
|
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8003080: 687b ldr r3, [r7, #4]
|
|
8003082: 685b ldr r3, [r3, #4]
|
|
8003084: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8003088: d102 bne.n 8003090 <HAL_RCC_OscConfig+0x204>
|
|
800308a: f7ff fc86 bl 800299a <LL_RCC_HSE_Enable>
|
|
800308e: e00d b.n 80030ac <HAL_RCC_OscConfig+0x220>
|
|
8003090: 687b ldr r3, [r7, #4]
|
|
8003092: 685b ldr r3, [r3, #4]
|
|
8003094: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000
|
|
8003098: d104 bne.n 80030a4 <HAL_RCC_OscConfig+0x218>
|
|
800309a: f7ff fc51 bl 8002940 <LL_RCC_HSE_EnableTcxo>
|
|
800309e: f7ff fc7c bl 800299a <LL_RCC_HSE_Enable>
|
|
80030a2: e003 b.n 80030ac <HAL_RCC_OscConfig+0x220>
|
|
80030a4: f7ff fc87 bl 80029b6 <LL_RCC_HSE_Disable>
|
|
80030a8: f7ff fc58 bl 800295c <LL_RCC_HSE_DisableTcxo>
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80030ac: 687b ldr r3, [r7, #4]
|
|
80030ae: 685b ldr r3, [r3, #4]
|
|
80030b0: 2b00 cmp r3, #0
|
|
80030b2: d012 beq.n 80030da <HAL_RCC_OscConfig+0x24e>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80030b4: f7fd fd64 bl 8000b80 <HAL_GetTick>
|
|
80030b8: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (LL_RCC_HSE_IsReady() == 0U)
|
|
80030ba: e008 b.n 80030ce <HAL_RCC_OscConfig+0x242>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80030bc: f7fd fd60 bl 8000b80 <HAL_GetTick>
|
|
80030c0: 4602 mov r2, r0
|
|
80030c2: 697b ldr r3, [r7, #20]
|
|
80030c4: 1ad3 subs r3, r2, r3
|
|
80030c6: 2b64 cmp r3, #100 @ 0x64
|
|
80030c8: d901 bls.n 80030ce <HAL_RCC_OscConfig+0x242>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80030ca: 2303 movs r3, #3
|
|
80030cc: e257 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_HSE_IsReady() == 0U)
|
|
80030ce: f7ff fc80 bl 80029d2 <LL_RCC_HSE_IsReady>
|
|
80030d2: 4603 mov r3, r0
|
|
80030d4: 2b00 cmp r3, #0
|
|
80030d6: d0f1 beq.n 80030bc <HAL_RCC_OscConfig+0x230>
|
|
80030d8: e011 b.n 80030fe <HAL_RCC_OscConfig+0x272>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80030da: f7fd fd51 bl 8000b80 <HAL_GetTick>
|
|
80030de: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (LL_RCC_HSE_IsReady() != 0U)
|
|
80030e0: e008 b.n 80030f4 <HAL_RCC_OscConfig+0x268>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80030e2: f7fd fd4d bl 8000b80 <HAL_GetTick>
|
|
80030e6: 4602 mov r2, r0
|
|
80030e8: 697b ldr r3, [r7, #20]
|
|
80030ea: 1ad3 subs r3, r2, r3
|
|
80030ec: 2b64 cmp r3, #100 @ 0x64
|
|
80030ee: d901 bls.n 80030f4 <HAL_RCC_OscConfig+0x268>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80030f0: 2303 movs r3, #3
|
|
80030f2: e244 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_HSE_IsReady() != 0U)
|
|
80030f4: f7ff fc6d bl 80029d2 <LL_RCC_HSE_IsReady>
|
|
80030f8: 4603 mov r3, r0
|
|
80030fa: 2b00 cmp r3, #0
|
|
80030fc: d1f1 bne.n 80030e2 <HAL_RCC_OscConfig+0x256>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80030fe: 687b ldr r3, [r7, #4]
|
|
8003100: 681b ldr r3, [r3, #0]
|
|
8003102: f003 0302 and.w r3, r3, #2
|
|
8003106: 2b00 cmp r3, #0
|
|
8003108: d046 beq.n 8003198 <HAL_RCC_OscConfig+0x30c>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
|
|
800310a: 69fb ldr r3, [r7, #28]
|
|
800310c: 2b04 cmp r3, #4
|
|
800310e: d005 beq.n 800311c <HAL_RCC_OscConfig+0x290>
|
|
8003110: 69fb ldr r3, [r7, #28]
|
|
8003112: 2b0c cmp r3, #12
|
|
8003114: d10e bne.n 8003134 <HAL_RCC_OscConfig+0x2a8>
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
8003116: 69bb ldr r3, [r7, #24]
|
|
8003118: 2b02 cmp r3, #2
|
|
800311a: d10b bne.n 8003134 <HAL_RCC_OscConfig+0x2a8>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
800311c: 687b ldr r3, [r7, #4]
|
|
800311e: 691b ldr r3, [r3, #16]
|
|
8003120: 2b00 cmp r3, #0
|
|
8003122: d101 bne.n 8003128 <HAL_RCC_OscConfig+0x29c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003124: 2301 movs r3, #1
|
|
8003126: e22a b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003128: 687b ldr r3, [r7, #4]
|
|
800312a: 695b ldr r3, [r3, #20]
|
|
800312c: 4618 mov r0, r3
|
|
800312e: f7ff fc8e bl 8002a4e <LL_RCC_HSI_SetCalibTrimming>
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
8003132: e031 b.n 8003198 <HAL_RCC_OscConfig+0x30c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8003134: 687b ldr r3, [r7, #4]
|
|
8003136: 691b ldr r3, [r3, #16]
|
|
8003138: 2b00 cmp r3, #0
|
|
800313a: d019 beq.n 8003170 <HAL_RCC_OscConfig+0x2e4>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800313c: f7ff fc5a bl 80029f4 <LL_RCC_HSI_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003140: f7fd fd1e bl 8000b80 <HAL_GetTick>
|
|
8003144: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (LL_RCC_HSI_IsReady() == 0U)
|
|
8003146: e008 b.n 800315a <HAL_RCC_OscConfig+0x2ce>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003148: f7fd fd1a bl 8000b80 <HAL_GetTick>
|
|
800314c: 4602 mov r2, r0
|
|
800314e: 697b ldr r3, [r7, #20]
|
|
8003150: 1ad3 subs r3, r2, r3
|
|
8003152: 2b02 cmp r3, #2
|
|
8003154: d901 bls.n 800315a <HAL_RCC_OscConfig+0x2ce>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003156: 2303 movs r3, #3
|
|
8003158: e211 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_HSI_IsReady() == 0U)
|
|
800315a: f7ff fc67 bl 8002a2c <LL_RCC_HSI_IsReady>
|
|
800315e: 4603 mov r3, r0
|
|
8003160: 2b00 cmp r3, #0
|
|
8003162: d0f1 beq.n 8003148 <HAL_RCC_OscConfig+0x2bc>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003164: 687b ldr r3, [r7, #4]
|
|
8003166: 695b ldr r3, [r3, #20]
|
|
8003168: 4618 mov r0, r3
|
|
800316a: f7ff fc70 bl 8002a4e <LL_RCC_HSI_SetCalibTrimming>
|
|
800316e: e013 b.n 8003198 <HAL_RCC_OscConfig+0x30c>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003170: f7ff fc4e bl 8002a10 <LL_RCC_HSI_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003174: f7fd fd04 bl 8000b80 <HAL_GetTick>
|
|
8003178: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (LL_RCC_HSI_IsReady() != 0U)
|
|
800317a: e008 b.n 800318e <HAL_RCC_OscConfig+0x302>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800317c: f7fd fd00 bl 8000b80 <HAL_GetTick>
|
|
8003180: 4602 mov r2, r0
|
|
8003182: 697b ldr r3, [r7, #20]
|
|
8003184: 1ad3 subs r3, r2, r3
|
|
8003186: 2b02 cmp r3, #2
|
|
8003188: d901 bls.n 800318e <HAL_RCC_OscConfig+0x302>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800318a: 2303 movs r3, #3
|
|
800318c: e1f7 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_HSI_IsReady() != 0U)
|
|
800318e: f7ff fc4d bl 8002a2c <LL_RCC_HSI_IsReady>
|
|
8003192: 4603 mov r3, r0
|
|
8003194: 2b00 cmp r3, #0
|
|
8003196: d1f1 bne.n 800317c <HAL_RCC_OscConfig+0x2f0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003198: 687b ldr r3, [r7, #4]
|
|
800319a: 681b ldr r3, [r3, #0]
|
|
800319c: f003 0308 and.w r3, r3, #8
|
|
80031a0: 2b00 cmp r3, #0
|
|
80031a2: d06e beq.n 8003282 <HAL_RCC_OscConfig+0x3f6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80031a4: 687b ldr r3, [r7, #4]
|
|
80031a6: 699b ldr r3, [r3, #24]
|
|
80031a8: 2b00 cmp r3, #0
|
|
80031aa: d056 beq.n 800325a <HAL_RCC_OscConfig+0x3ce>
|
|
{
|
|
uint32_t csr_temp = RCC->CSR;
|
|
80031ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80031b0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80031b4: 60fb str r3, [r7, #12]
|
|
|
|
/* Check LSI division factor */
|
|
assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));
|
|
|
|
if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE))
|
|
80031b6: 687b ldr r3, [r7, #4]
|
|
80031b8: 69da ldr r2, [r3, #28]
|
|
80031ba: 68fb ldr r3, [r7, #12]
|
|
80031bc: f003 0310 and.w r3, r3, #16
|
|
80031c0: 429a cmp r2, r3
|
|
80031c2: d031 beq.n 8003228 <HAL_RCC_OscConfig+0x39c>
|
|
{
|
|
if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \
|
|
80031c4: 68fb ldr r3, [r7, #12]
|
|
80031c6: f003 0302 and.w r3, r3, #2
|
|
80031ca: 2b00 cmp r3, #0
|
|
80031cc: d006 beq.n 80031dc <HAL_RCC_OscConfig+0x350>
|
|
((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))
|
|
80031ce: 68fb ldr r3, [r7, #12]
|
|
80031d0: f003 0301 and.w r3, r3, #1
|
|
if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \
|
|
80031d4: 2b00 cmp r3, #0
|
|
80031d6: d101 bne.n 80031dc <HAL_RCC_OscConfig+0x350>
|
|
{
|
|
/* If LSIRDY is set while LSION is not enabled,
|
|
LSIPRE can't be updated */
|
|
return HAL_ERROR;
|
|
80031d8: 2301 movs r3, #1
|
|
80031da: e1d0 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
|
|
/* Turn off LSI before changing RCC_CSR_LSIPRE */
|
|
if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
80031dc: 68fb ldr r3, [r7, #12]
|
|
80031de: f003 0301 and.w r3, r3, #1
|
|
80031e2: 2b00 cmp r3, #0
|
|
80031e4: d013 beq.n 800320e <HAL_RCC_OscConfig+0x382>
|
|
{
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80031e6: f7ff fc67 bl 8002ab8 <LL_RCC_LSI_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80031ea: f7fd fcc9 bl 8000b80 <HAL_GetTick>
|
|
80031ee: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
80031f0: e008 b.n 8003204 <HAL_RCC_OscConfig+0x378>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80031f2: f7fd fcc5 bl 8000b80 <HAL_GetTick>
|
|
80031f6: 4602 mov r2, r0
|
|
80031f8: 697b ldr r3, [r7, #20]
|
|
80031fa: 1ad3 subs r3, r2, r3
|
|
80031fc: 2b11 cmp r3, #17
|
|
80031fe: d901 bls.n 8003204 <HAL_RCC_OscConfig+0x378>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003200: 2303 movs r3, #3
|
|
8003202: e1bc b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
8003204: f7ff fc68 bl 8002ad8 <LL_RCC_LSI_IsReady>
|
|
8003208: 4603 mov r3, r0
|
|
800320a: 2b00 cmp r3, #0
|
|
800320c: d1f1 bne.n 80031f2 <HAL_RCC_OscConfig+0x366>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set LSI division factor */
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv);
|
|
800320e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003212: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003216: f023 0210 bic.w r2, r3, #16
|
|
800321a: 687b ldr r3, [r7, #4]
|
|
800321c: 69db ldr r3, [r3, #28]
|
|
800321e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003222: 4313 orrs r3, r2
|
|
8003224: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003228: f7ff fc36 bl 8002a98 <LL_RCC_LSI_Enable>
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800322c: f7fd fca8 bl 8000b80 <HAL_GetTick>
|
|
8003230: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (LL_RCC_LSI_IsReady() == 0U)
|
|
8003232: e00c b.n 800324e <HAL_RCC_OscConfig+0x3c2>
|
|
8003234: 20000000 .word 0x20000000
|
|
8003238: 20000004 .word 0x20000004
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
800323c: f7fd fca0 bl 8000b80 <HAL_GetTick>
|
|
8003240: 4602 mov r2, r0
|
|
8003242: 697b ldr r3, [r7, #20]
|
|
8003244: 1ad3 subs r3, r2, r3
|
|
8003246: 2b11 cmp r3, #17
|
|
8003248: d901 bls.n 800324e <HAL_RCC_OscConfig+0x3c2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800324a: 2303 movs r3, #3
|
|
800324c: e197 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_LSI_IsReady() == 0U)
|
|
800324e: f7ff fc43 bl 8002ad8 <LL_RCC_LSI_IsReady>
|
|
8003252: 4603 mov r3, r0
|
|
8003254: 2b00 cmp r3, #0
|
|
8003256: d0f1 beq.n 800323c <HAL_RCC_OscConfig+0x3b0>
|
|
8003258: e013 b.n 8003282 <HAL_RCC_OscConfig+0x3f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
800325a: f7ff fc2d bl 8002ab8 <LL_RCC_LSI_Disable>
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800325e: f7fd fc8f bl 8000b80 <HAL_GetTick>
|
|
8003262: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
8003264: e008 b.n 8003278 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003266: f7fd fc8b bl 8000b80 <HAL_GetTick>
|
|
800326a: 4602 mov r2, r0
|
|
800326c: 697b ldr r3, [r7, #20]
|
|
800326e: 1ad3 subs r3, r2, r3
|
|
8003270: 2b11 cmp r3, #17
|
|
8003272: d901 bls.n 8003278 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003274: 2303 movs r3, #3
|
|
8003276: e182 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
8003278: f7ff fc2e bl 8002ad8 <LL_RCC_LSI_IsReady>
|
|
800327c: 4603 mov r3, r0
|
|
800327e: 2b00 cmp r3, #0
|
|
8003280: d1f1 bne.n 8003266 <HAL_RCC_OscConfig+0x3da>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003282: 687b ldr r3, [r7, #4]
|
|
8003284: 681b ldr r3, [r3, #0]
|
|
8003286: f003 0304 and.w r3, r3, #4
|
|
800328a: 2b00 cmp r3, #0
|
|
800328c: f000 80d8 beq.w 8003440 <HAL_RCC_OscConfig+0x5b4>
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
|
if (LL_PWR_IsEnabledBkUpAccess() == 0U)
|
|
8003290: f7ff fb44 bl 800291c <LL_PWR_IsEnabledBkUpAccess>
|
|
8003294: 4603 mov r3, r0
|
|
8003296: 2b00 cmp r3, #0
|
|
8003298: d113 bne.n 80032c2 <HAL_RCC_OscConfig+0x436>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
800329a: f7ff fa83 bl 80027a4 <HAL_PWR_EnableBkUpAccess>
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800329e: f7fd fc6f bl 8000b80 <HAL_GetTick>
|
|
80032a2: 6178 str r0, [r7, #20]
|
|
|
|
while (LL_PWR_IsEnabledBkUpAccess() == 0U)
|
|
80032a4: e008 b.n 80032b8 <HAL_RCC_OscConfig+0x42c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80032a6: f7fd fc6b bl 8000b80 <HAL_GetTick>
|
|
80032aa: 4602 mov r2, r0
|
|
80032ac: 697b ldr r3, [r7, #20]
|
|
80032ae: 1ad3 subs r3, r2, r3
|
|
80032b0: 2b02 cmp r3, #2
|
|
80032b2: d901 bls.n 80032b8 <HAL_RCC_OscConfig+0x42c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80032b4: 2303 movs r3, #3
|
|
80032b6: e162 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_PWR_IsEnabledBkUpAccess() == 0U)
|
|
80032b8: f7ff fb30 bl 800291c <LL_PWR_IsEnabledBkUpAccess>
|
|
80032bc: 4603 mov r3, r0
|
|
80032be: 2b00 cmp r3, #0
|
|
80032c0: d0f1 beq.n 80032a6 <HAL_RCC_OscConfig+0x41a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
80032c2: 687b ldr r3, [r7, #4]
|
|
80032c4: 68db ldr r3, [r3, #12]
|
|
80032c6: 2b00 cmp r3, #0
|
|
80032c8: d07b beq.n 80033c2 <HAL_RCC_OscConfig+0x536>
|
|
{
|
|
/* Enable LSE bypasss (if requested) */
|
|
if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)
|
|
80032ca: 687b ldr r3, [r7, #4]
|
|
80032cc: 68db ldr r3, [r3, #12]
|
|
80032ce: 2b85 cmp r3, #133 @ 0x85
|
|
80032d0: d003 beq.n 80032da <HAL_RCC_OscConfig+0x44e>
|
|
|| (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY))
|
|
80032d2: 687b ldr r3, [r7, #4]
|
|
80032d4: 68db ldr r3, [r3, #12]
|
|
80032d6: 2b05 cmp r3, #5
|
|
80032d8: d109 bne.n 80032ee <HAL_RCC_OscConfig+0x462>
|
|
{
|
|
/* LSE oscillator bypass enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
80032da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80032de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80032e2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
80032e6: f043 0304 orr.w r3, r3, #4
|
|
80032ea: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80032ee: f7fd fc47 bl 8000b80 <HAL_GetTick>
|
|
80032f2: 6178 str r0, [r7, #20]
|
|
|
|
/* LSE oscillator enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
80032f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80032f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80032fc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003300: f043 0301 orr.w r3, r3, #1
|
|
8003304: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait till LSE is ready */
|
|
while (LL_RCC_LSE_IsReady() == 0U)
|
|
8003308: e00a b.n 8003320 <HAL_RCC_OscConfig+0x494>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800330a: f7fd fc39 bl 8000b80 <HAL_GetTick>
|
|
800330e: 4602 mov r2, r0
|
|
8003310: 697b ldr r3, [r7, #20]
|
|
8003312: 1ad3 subs r3, r2, r3
|
|
8003314: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003318: 4293 cmp r3, r2
|
|
800331a: d901 bls.n 8003320 <HAL_RCC_OscConfig+0x494>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800331c: 2303 movs r3, #3
|
|
800331e: e12e b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_LSE_IsReady() == 0U)
|
|
8003320: f7ff fba9 bl 8002a76 <LL_RCC_LSE_IsReady>
|
|
8003324: 4603 mov r3, r0
|
|
8003326: 2b00 cmp r3, #0
|
|
8003328: d0ef beq.n 800330a <HAL_RCC_OscConfig+0x47e>
|
|
}
|
|
}
|
|
|
|
/* Enable LSE system clock (if requested) */
|
|
if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON)
|
|
800332a: 687b ldr r3, [r7, #4]
|
|
800332c: 68db ldr r3, [r3, #12]
|
|
800332e: 2b81 cmp r3, #129 @ 0x81
|
|
8003330: d003 beq.n 800333a <HAL_RCC_OscConfig+0x4ae>
|
|
|| (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS))
|
|
8003332: 687b ldr r3, [r7, #4]
|
|
8003334: 68db ldr r3, [r3, #12]
|
|
8003336: 2b85 cmp r3, #133 @ 0x85
|
|
8003338: d121 bne.n 800337e <HAL_RCC_OscConfig+0x4f2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800333a: f7fd fc21 bl 8000b80 <HAL_GetTick>
|
|
800333e: 6178 str r0, [r7, #20]
|
|
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
8003340: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003344: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003348: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800334c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8003350: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait till LSESYS is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
|
|
8003354: e00a b.n 800336c <HAL_RCC_OscConfig+0x4e0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003356: f7fd fc13 bl 8000b80 <HAL_GetTick>
|
|
800335a: 4602 mov r2, r0
|
|
800335c: 697b ldr r3, [r7, #20]
|
|
800335e: 1ad3 subs r3, r2, r3
|
|
8003360: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003364: 4293 cmp r3, r2
|
|
8003366: d901 bls.n 800336c <HAL_RCC_OscConfig+0x4e0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003368: 2303 movs r3, #3
|
|
800336a: e108 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
|
|
800336c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003370: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003374: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003378: 2b00 cmp r3, #0
|
|
800337a: d0ec beq.n 8003356 <HAL_RCC_OscConfig+0x4ca>
|
|
if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON)
|
|
800337c: e060 b.n 8003440 <HAL_RCC_OscConfig+0x5b4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800337e: f7fd fbff bl 8000b80 <HAL_GetTick>
|
|
8003382: 6178 str r0, [r7, #20]
|
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
8003384: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003388: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800338c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003390: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8003394: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
8003398: e00a b.n 80033b0 <HAL_RCC_OscConfig+0x524>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800339a: f7fd fbf1 bl 8000b80 <HAL_GetTick>
|
|
800339e: 4602 mov r2, r0
|
|
80033a0: 697b ldr r3, [r7, #20]
|
|
80033a2: 1ad3 subs r3, r2, r3
|
|
80033a4: f241 3288 movw r2, #5000 @ 0x1388
|
|
80033a8: 4293 cmp r3, r2
|
|
80033aa: d901 bls.n 80033b0 <HAL_RCC_OscConfig+0x524>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80033ac: 2303 movs r3, #3
|
|
80033ae: e0e6 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
80033b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80033b4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80033b8: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80033bc: 2b00 cmp r3, #0
|
|
80033be: d1ec bne.n 800339a <HAL_RCC_OscConfig+0x50e>
|
|
80033c0: e03e b.n 8003440 <HAL_RCC_OscConfig+0x5b4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80033c2: f7fd fbdd bl 8000b80 <HAL_GetTick>
|
|
80033c6: 6178 str r0, [r7, #20]
|
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
80033c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80033cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80033d0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
80033d4: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80033d8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
80033dc: e00a b.n 80033f4 <HAL_RCC_OscConfig+0x568>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80033de: f7fd fbcf bl 8000b80 <HAL_GetTick>
|
|
80033e2: 4602 mov r2, r0
|
|
80033e4: 697b ldr r3, [r7, #20]
|
|
80033e6: 1ad3 subs r3, r2, r3
|
|
80033e8: f241 3288 movw r2, #5000 @ 0x1388
|
|
80033ec: 4293 cmp r3, r2
|
|
80033ee: d901 bls.n 80033f4 <HAL_RCC_OscConfig+0x568>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80033f0: 2303 movs r3, #3
|
|
80033f2: e0c4 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
80033f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80033f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80033fc: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003400: 2b00 cmp r3, #0
|
|
8003402: d1ec bne.n 80033de <HAL_RCC_OscConfig+0x552>
|
|
}
|
|
}
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003404: f7fd fbbc bl 8000b80 <HAL_GetTick>
|
|
8003408: 6178 str r0, [r7, #20]
|
|
|
|
/* LSE oscillator disable */
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
800340a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800340e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003412: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003416: f023 0301 bic.w r3, r3, #1
|
|
800341a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (LL_RCC_LSE_IsReady() != 0U)
|
|
800341e: e00a b.n 8003436 <HAL_RCC_OscConfig+0x5aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003420: f7fd fbae bl 8000b80 <HAL_GetTick>
|
|
8003424: 4602 mov r2, r0
|
|
8003426: 697b ldr r3, [r7, #20]
|
|
8003428: 1ad3 subs r3, r2, r3
|
|
800342a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800342e: 4293 cmp r3, r2
|
|
8003430: d901 bls.n 8003436 <HAL_RCC_OscConfig+0x5aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003432: 2303 movs r3, #3
|
|
8003434: e0a3 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_LSE_IsReady() != 0U)
|
|
8003436: f7ff fb1e bl 8002a76 <LL_RCC_LSE_IsReady>
|
|
800343a: 4603 mov r3, r0
|
|
800343c: 2b00 cmp r3, #0
|
|
800343e: d1ef bne.n 8003420 <HAL_RCC_OscConfig+0x594>
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8003440: 687b ldr r3, [r7, #4]
|
|
8003442: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003444: 2b00 cmp r3, #0
|
|
8003446: f000 8099 beq.w 800357c <HAL_RCC_OscConfig+0x6f0>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
800344a: 69fb ldr r3, [r7, #28]
|
|
800344c: 2b0c cmp r3, #12
|
|
800344e: d06c beq.n 800352a <HAL_RCC_OscConfig+0x69e>
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8003450: 687b ldr r3, [r7, #4]
|
|
8003452: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003454: 2b02 cmp r3, #2
|
|
8003456: d14b bne.n 80034f0 <HAL_RCC_OscConfig+0x664>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003458: f7ff fc74 bl 8002d44 <LL_RCC_PLL_Disable>
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800345c: f7fd fb90 bl 8000b80 <HAL_GetTick>
|
|
8003460: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
8003462: e008 b.n 8003476 <HAL_RCC_OscConfig+0x5ea>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003464: f7fd fb8c bl 8000b80 <HAL_GetTick>
|
|
8003468: 4602 mov r2, r0
|
|
800346a: 697b ldr r3, [r7, #20]
|
|
800346c: 1ad3 subs r3, r2, r3
|
|
800346e: 2b0a cmp r3, #10
|
|
8003470: d901 bls.n 8003476 <HAL_RCC_OscConfig+0x5ea>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003472: 2303 movs r3, #3
|
|
8003474: e083 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
8003476: f7ff fc73 bl 8002d60 <LL_RCC_PLL_IsReady>
|
|
800347a: 4603 mov r3, r0
|
|
800347c: 2b00 cmp r3, #0
|
|
800347e: d1f1 bne.n 8003464 <HAL_RCC_OscConfig+0x5d8>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8003480: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003484: 68da ldr r2, [r3, #12]
|
|
8003486: 4b40 ldr r3, [pc, #256] @ (8003588 <HAL_RCC_OscConfig+0x6fc>)
|
|
8003488: 4013 ands r3, r2
|
|
800348a: 687a ldr r2, [r7, #4]
|
|
800348c: 6b11 ldr r1, [r2, #48] @ 0x30
|
|
800348e: 687a ldr r2, [r7, #4]
|
|
8003490: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
8003492: 4311 orrs r1, r2
|
|
8003494: 687a ldr r2, [r7, #4]
|
|
8003496: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8003498: 0212 lsls r2, r2, #8
|
|
800349a: 4311 orrs r1, r2
|
|
800349c: 687a ldr r2, [r7, #4]
|
|
800349e: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
80034a0: 4311 orrs r1, r2
|
|
80034a2: 687a ldr r2, [r7, #4]
|
|
80034a4: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
80034a6: 4311 orrs r1, r2
|
|
80034a8: 687a ldr r2, [r7, #4]
|
|
80034aa: 6c52 ldr r2, [r2, #68] @ 0x44
|
|
80034ac: 430a orrs r2, r1
|
|
80034ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80034b2: 4313 orrs r3, r2
|
|
80034b4: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80034b6: f7ff fc37 bl 8002d28 <LL_RCC_PLL_Enable>
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
80034ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80034be: 68db ldr r3, [r3, #12]
|
|
80034c0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
80034c4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80034c8: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80034ca: f7fd fb59 bl 8000b80 <HAL_GetTick>
|
|
80034ce: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (LL_RCC_PLL_IsReady() == 0U)
|
|
80034d0: e008 b.n 80034e4 <HAL_RCC_OscConfig+0x658>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80034d2: f7fd fb55 bl 8000b80 <HAL_GetTick>
|
|
80034d6: 4602 mov r2, r0
|
|
80034d8: 697b ldr r3, [r7, #20]
|
|
80034da: 1ad3 subs r3, r2, r3
|
|
80034dc: 2b0a cmp r3, #10
|
|
80034de: d901 bls.n 80034e4 <HAL_RCC_OscConfig+0x658>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80034e0: 2303 movs r3, #3
|
|
80034e2: e04c b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_PLL_IsReady() == 0U)
|
|
80034e4: f7ff fc3c bl 8002d60 <LL_RCC_PLL_IsReady>
|
|
80034e8: 4603 mov r3, r0
|
|
80034ea: 2b00 cmp r3, #0
|
|
80034ec: d0f1 beq.n 80034d2 <HAL_RCC_OscConfig+0x646>
|
|
80034ee: e045 b.n 800357c <HAL_RCC_OscConfig+0x6f0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80034f0: f7ff fc28 bl 8002d44 <LL_RCC_PLL_Disable>
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80034f4: f7fd fb44 bl 8000b80 <HAL_GetTick>
|
|
80034f8: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
80034fa: e008 b.n 800350e <HAL_RCC_OscConfig+0x682>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80034fc: f7fd fb40 bl 8000b80 <HAL_GetTick>
|
|
8003500: 4602 mov r2, r0
|
|
8003502: 697b ldr r3, [r7, #20]
|
|
8003504: 1ad3 subs r3, r2, r3
|
|
8003506: 2b0a cmp r3, #10
|
|
8003508: d901 bls.n 800350e <HAL_RCC_OscConfig+0x682>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800350a: 2303 movs r3, #3
|
|
800350c: e037 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
800350e: f7ff fc27 bl 8002d60 <LL_RCC_PLL_IsReady>
|
|
8003512: 4603 mov r3, r0
|
|
8003514: 2b00 cmp r3, #0
|
|
8003516: d1f1 bne.n 80034fc <HAL_RCC_OscConfig+0x670>
|
|
}
|
|
}
|
|
|
|
/* Disable the PLL source and outputs to save power when PLL is off */
|
|
CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN));
|
|
8003518: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800351c: 68da ldr r2, [r3, #12]
|
|
800351e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003522: 4b1a ldr r3, [pc, #104] @ (800358c <HAL_RCC_OscConfig+0x700>)
|
|
8003524: 4013 ands r3, r2
|
|
8003526: 60cb str r3, [r1, #12]
|
|
8003528: e028 b.n 800357c <HAL_RCC_OscConfig+0x6f0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
800352a: 687b ldr r3, [r7, #4]
|
|
800352c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800352e: 2b01 cmp r3, #1
|
|
8003530: d101 bne.n 8003536 <HAL_RCC_OscConfig+0x6aa>
|
|
{
|
|
return HAL_ERROR;
|
|
8003532: 2301 movs r3, #1
|
|
8003534: e023 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8003536: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800353a: 68db ldr r3, [r3, #12]
|
|
800353c: 61bb str r3, [r7, #24]
|
|
if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource)
|
|
800353e: 69bb ldr r3, [r7, #24]
|
|
8003540: f003 0203 and.w r2, r3, #3
|
|
8003544: 687b ldr r3, [r7, #4]
|
|
8003546: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003548: 429a cmp r2, r3
|
|
800354a: d115 bne.n 8003578 <HAL_RCC_OscConfig+0x6ec>
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM)
|
|
800354c: 69bb ldr r3, [r7, #24]
|
|
800354e: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
8003552: 687b ldr r3, [r7, #4]
|
|
8003554: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003556: 429a cmp r2, r3
|
|
8003558: d10e bne.n 8003578 <HAL_RCC_OscConfig+0x6ec>
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos))
|
|
800355a: 69bb ldr r3, [r7, #24]
|
|
800355c: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
8003560: 687b ldr r3, [r7, #4]
|
|
8003562: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003564: 021b lsls r3, r3, #8
|
|
8003566: 429a cmp r2, r3
|
|
8003568: d106 bne.n 8003578 <HAL_RCC_OscConfig+0x6ec>
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
|
|
800356a: 69bb ldr r3, [r7, #24]
|
|
800356c: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000
|
|
8003570: 687b ldr r3, [r7, #4]
|
|
8003572: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003574: 429a cmp r2, r3
|
|
8003576: d001 beq.n 800357c <HAL_RCC_OscConfig+0x6f0>
|
|
{
|
|
return HAL_ERROR;
|
|
8003578: 2301 movs r3, #1
|
|
800357a: e000 b.n 800357e <HAL_RCC_OscConfig+0x6f2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800357c: 2300 movs r3, #0
|
|
}
|
|
800357e: 4618 mov r0, r3
|
|
8003580: 3720 adds r7, #32
|
|
8003582: 46bd mov sp, r7
|
|
8003584: bd80 pop {r7, pc}
|
|
8003586: bf00 nop
|
|
8003588: 11c1808c .word 0x11c1808c
|
|
800358c: eefefffc .word 0xeefefffc
|
|
|
|
08003590 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8003590: b580 push {r7, lr}
|
|
8003592: b084 sub sp, #16
|
|
8003594: af00 add r7, sp, #0
|
|
8003596: 6078 str r0, [r7, #4]
|
|
8003598: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800359a: 687b ldr r3, [r7, #4]
|
|
800359c: 2b00 cmp r3, #0
|
|
800359e: d101 bne.n 80035a4 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80035a0: 2301 movs r3, #1
|
|
80035a2: e12c b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the FLASH clock
|
|
(HCLK3) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80035a4: 4b98 ldr r3, [pc, #608] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80035a6: 681b ldr r3, [r3, #0]
|
|
80035a8: f003 0307 and.w r3, r3, #7
|
|
80035ac: 683a ldr r2, [r7, #0]
|
|
80035ae: 429a cmp r2, r3
|
|
80035b0: d91b bls.n 80035ea <HAL_RCC_ClockConfig+0x5a>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80035b2: 4b95 ldr r3, [pc, #596] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80035b4: 681b ldr r3, [r3, #0]
|
|
80035b6: f023 0207 bic.w r2, r3, #7
|
|
80035ba: 4993 ldr r1, [pc, #588] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80035bc: 683b ldr r3, [r7, #0]
|
|
80035be: 4313 orrs r3, r2
|
|
80035c0: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80035c2: f7fd fadd bl 8000b80 <HAL_GetTick>
|
|
80035c6: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80035c8: e008 b.n 80035dc <HAL_RCC_ClockConfig+0x4c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
80035ca: f7fd fad9 bl 8000b80 <HAL_GetTick>
|
|
80035ce: 4602 mov r2, r0
|
|
80035d0: 68fb ldr r3, [r7, #12]
|
|
80035d2: 1ad3 subs r3, r2, r3
|
|
80035d4: 2b02 cmp r3, #2
|
|
80035d6: d901 bls.n 80035dc <HAL_RCC_ClockConfig+0x4c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80035d8: 2303 movs r3, #3
|
|
80035da: e110 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80035dc: 4b8a ldr r3, [pc, #552] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80035de: 681b ldr r3, [r3, #0]
|
|
80035e0: f003 0307 and.w r3, r3, #7
|
|
80035e4: 683a ldr r2, [r7, #0]
|
|
80035e6: 429a cmp r2, r3
|
|
80035e8: d1ef bne.n 80035ca <HAL_RCC_ClockConfig+0x3a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80035ea: 687b ldr r3, [r7, #4]
|
|
80035ec: 681b ldr r3, [r3, #0]
|
|
80035ee: f003 0302 and.w r3, r3, #2
|
|
80035f2: 2b00 cmp r3, #0
|
|
80035f4: d016 beq.n 8003624 <HAL_RCC_ClockConfig+0x94>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider));
|
|
LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider);
|
|
80035f6: 687b ldr r3, [r7, #4]
|
|
80035f8: 689b ldr r3, [r3, #8]
|
|
80035fa: 4618 mov r0, r3
|
|
80035fc: f7ff fb02 bl 8002c04 <LL_RCC_SetAHBPrescaler>
|
|
|
|
/* HCLK1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
8003600: f7fd fabe bl 8000b80 <HAL_GetTick>
|
|
8003604: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
|
|
8003606: e008 b.n 800361a <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
8003608: f7fd faba bl 8000b80 <HAL_GetTick>
|
|
800360c: 4602 mov r2, r0
|
|
800360e: 68fb ldr r3, [r7, #12]
|
|
8003610: 1ad3 subs r3, r2, r3
|
|
8003612: 2b02 cmp r3, #2
|
|
8003614: d901 bls.n 800361a <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003616: 2303 movs r3, #3
|
|
8003618: e0f1 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
|
|
800361a: f7ff fbdf bl 8002ddc <LL_RCC_IsActiveFlag_HPRE>
|
|
800361e: 4603 mov r3, r0
|
|
8003620: 2b00 cmp r3, #0
|
|
8003622: d0f1 beq.n 8003608 <HAL_RCC_ClockConfig+0x78>
|
|
}
|
|
}
|
|
|
|
#if defined(DUAL_CORE)
|
|
/*-------------------------- HCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2)
|
|
8003624: 687b ldr r3, [r7, #4]
|
|
8003626: 681b ldr r3, [r3, #0]
|
|
8003628: f003 0320 and.w r3, r3, #32
|
|
800362c: 2b00 cmp r3, #0
|
|
800362e: d016 beq.n 800365e <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider));
|
|
LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider);
|
|
8003630: 687b ldr r3, [r7, #4]
|
|
8003632: 695b ldr r3, [r3, #20]
|
|
8003634: 4618 mov r0, r3
|
|
8003636: f7ff faf8 bl 8002c2a <LL_C2_RCC_SetAHBPrescaler>
|
|
|
|
/* HCLK2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800363a: f7fd faa1 bl 8000b80 <HAL_GetTick>
|
|
800363e: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
|
|
8003640: e008 b.n 8003654 <HAL_RCC_ClockConfig+0xc4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
8003642: f7fd fa9d bl 8000b80 <HAL_GetTick>
|
|
8003646: 4602 mov r2, r0
|
|
8003648: 68fb ldr r3, [r7, #12]
|
|
800364a: 1ad3 subs r3, r2, r3
|
|
800364c: 2b02 cmp r3, #2
|
|
800364e: d901 bls.n 8003654 <HAL_RCC_ClockConfig+0xc4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003650: 2303 movs r3, #3
|
|
8003652: e0d4 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
|
|
8003654: f7ff fbd3 bl 8002dfe <LL_RCC_IsActiveFlag_C2HPRE>
|
|
8003658: 4603 mov r3, r0
|
|
800365a: 2b00 cmp r3, #0
|
|
800365c: d0f1 beq.n 8003642 <HAL_RCC_ClockConfig+0xb2>
|
|
}
|
|
}
|
|
#endif /* DUAL_CORE */
|
|
|
|
/*-------------------------- HCLK3 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3)
|
|
800365e: 687b ldr r3, [r7, #4]
|
|
8003660: 681b ldr r3, [r3, #0]
|
|
8003662: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003666: 2b00 cmp r3, #0
|
|
8003668: d016 beq.n 8003698 <HAL_RCC_ClockConfig+0x108>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider));
|
|
LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider);
|
|
800366a: 687b ldr r3, [r7, #4]
|
|
800366c: 699b ldr r3, [r3, #24]
|
|
800366e: 4618 mov r0, r3
|
|
8003670: f7ff faf0 bl 8002c54 <LL_RCC_SetAHB3Prescaler>
|
|
|
|
/* AHB shared prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
8003674: f7fd fa84 bl 8000b80 <HAL_GetTick>
|
|
8003678: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
|
|
800367a: e008 b.n 800368e <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800367c: f7fd fa80 bl 8000b80 <HAL_GetTick>
|
|
8003680: 4602 mov r2, r0
|
|
8003682: 68fb ldr r3, [r7, #12]
|
|
8003684: 1ad3 subs r3, r2, r3
|
|
8003686: 2b02 cmp r3, #2
|
|
8003688: d901 bls.n 800368e <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800368a: 2303 movs r3, #3
|
|
800368c: e0b7 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
|
|
800368e: f7ff fbc8 bl 8002e22 <LL_RCC_IsActiveFlag_SHDHPRE>
|
|
8003692: 4603 mov r3, r0
|
|
8003694: 2b00 cmp r3, #0
|
|
8003696: d0f1 beq.n 800367c <HAL_RCC_ClockConfig+0xec>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003698: 687b ldr r3, [r7, #4]
|
|
800369a: 681b ldr r3, [r3, #0]
|
|
800369c: f003 0304 and.w r3, r3, #4
|
|
80036a0: 2b00 cmp r3, #0
|
|
80036a2: d016 beq.n 80036d2 <HAL_RCC_ClockConfig+0x142>
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider));
|
|
LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider);
|
|
80036a4: 687b ldr r3, [r7, #4]
|
|
80036a6: 68db ldr r3, [r3, #12]
|
|
80036a8: 4618 mov r0, r3
|
|
80036aa: f7ff fae9 bl 8002c80 <LL_RCC_SetAPB1Prescaler>
|
|
|
|
/* APB1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
80036ae: f7fd fa67 bl 8000b80 <HAL_GetTick>
|
|
80036b2: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
|
|
80036b4: e008 b.n 80036c8 <HAL_RCC_ClockConfig+0x138>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
80036b6: f7fd fa63 bl 8000b80 <HAL_GetTick>
|
|
80036ba: 4602 mov r2, r0
|
|
80036bc: 68fb ldr r3, [r7, #12]
|
|
80036be: 1ad3 subs r3, r2, r3
|
|
80036c0: 2b02 cmp r3, #2
|
|
80036c2: d901 bls.n 80036c8 <HAL_RCC_ClockConfig+0x138>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80036c4: 2303 movs r3, #3
|
|
80036c6: e09a b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
|
|
80036c8: f7ff fbbd bl 8002e46 <LL_RCC_IsActiveFlag_PPRE1>
|
|
80036cc: 4603 mov r3, r0
|
|
80036ce: 2b00 cmp r3, #0
|
|
80036d0: d0f1 beq.n 80036b6 <HAL_RCC_ClockConfig+0x126>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80036d2: 687b ldr r3, [r7, #4]
|
|
80036d4: 681b ldr r3, [r3, #0]
|
|
80036d6: f003 0308 and.w r3, r3, #8
|
|
80036da: 2b00 cmp r3, #0
|
|
80036dc: d017 beq.n 800370e <HAL_RCC_ClockConfig+0x17e>
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider));
|
|
LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U);
|
|
80036de: 687b ldr r3, [r7, #4]
|
|
80036e0: 691b ldr r3, [r3, #16]
|
|
80036e2: 00db lsls r3, r3, #3
|
|
80036e4: 4618 mov r0, r3
|
|
80036e6: f7ff fade bl 8002ca6 <LL_RCC_SetAPB2Prescaler>
|
|
|
|
/* APB2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
80036ea: f7fd fa49 bl 8000b80 <HAL_GetTick>
|
|
80036ee: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
|
|
80036f0: e008 b.n 8003704 <HAL_RCC_ClockConfig+0x174>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
80036f2: f7fd fa45 bl 8000b80 <HAL_GetTick>
|
|
80036f6: 4602 mov r2, r0
|
|
80036f8: 68fb ldr r3, [r7, #12]
|
|
80036fa: 1ad3 subs r3, r2, r3
|
|
80036fc: 2b02 cmp r3, #2
|
|
80036fe: d901 bls.n 8003704 <HAL_RCC_ClockConfig+0x174>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003700: 2303 movs r3, #3
|
|
8003702: e07c b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
|
|
8003704: f7ff fbb0 bl 8002e68 <LL_RCC_IsActiveFlag_PPRE2>
|
|
8003708: 4603 mov r3, r0
|
|
800370a: 2b00 cmp r3, #0
|
|
800370c: d0f1 beq.n 80036f2 <HAL_RCC_ClockConfig+0x162>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800370e: 687b ldr r3, [r7, #4]
|
|
8003710: 681b ldr r3, [r3, #0]
|
|
8003712: f003 0301 and.w r3, r3, #1
|
|
8003716: 2b00 cmp r3, #0
|
|
8003718: d043 beq.n 80037a2 <HAL_RCC_ClockConfig+0x212>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800371a: 687b ldr r3, [r7, #4]
|
|
800371c: 685b ldr r3, [r3, #4]
|
|
800371e: 2b02 cmp r3, #2
|
|
8003720: d106 bne.n 8003730 <HAL_RCC_ClockConfig+0x1a0>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (LL_RCC_HSE_IsReady() == 0U)
|
|
8003722: f7ff f956 bl 80029d2 <LL_RCC_HSE_IsReady>
|
|
8003726: 4603 mov r3, r0
|
|
8003728: 2b00 cmp r3, #0
|
|
800372a: d11e bne.n 800376a <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
800372c: 2301 movs r3, #1
|
|
800372e: e066 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8003730: 687b ldr r3, [r7, #4]
|
|
8003732: 685b ldr r3, [r3, #4]
|
|
8003734: 2b03 cmp r3, #3
|
|
8003736: d106 bne.n 8003746 <HAL_RCC_ClockConfig+0x1b6>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (LL_RCC_PLL_IsReady() == 0U)
|
|
8003738: f7ff fb12 bl 8002d60 <LL_RCC_PLL_IsReady>
|
|
800373c: 4603 mov r3, r0
|
|
800373e: 2b00 cmp r3, #0
|
|
8003740: d113 bne.n 800376a <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
8003742: 2301 movs r3, #1
|
|
8003744: e05b b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
8003746: 687b ldr r3, [r7, #4]
|
|
8003748: 685b ldr r3, [r3, #4]
|
|
800374a: 2b00 cmp r3, #0
|
|
800374c: d106 bne.n 800375c <HAL_RCC_ClockConfig+0x1cc>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if (LL_RCC_MSI_IsReady() == 0U)
|
|
800374e: f7ff f9f0 bl 8002b32 <LL_RCC_MSI_IsReady>
|
|
8003752: 4603 mov r3, r0
|
|
8003754: 2b00 cmp r3, #0
|
|
8003756: d108 bne.n 800376a <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
8003758: 2301 movs r3, #1
|
|
800375a: e050 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (LL_RCC_HSI_IsReady() == 0U)
|
|
800375c: f7ff f966 bl 8002a2c <LL_RCC_HSI_IsReady>
|
|
8003760: 4603 mov r3, r0
|
|
8003762: 2b00 cmp r3, #0
|
|
8003764: d101 bne.n 800376a <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
8003766: 2301 movs r3, #1
|
|
8003768: e049 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
}
|
|
|
|
}
|
|
|
|
/* apply system clock switch */
|
|
LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
|
|
800376a: 687b ldr r3, [r7, #4]
|
|
800376c: 685b ldr r3, [r3, #4]
|
|
800376e: 4618 mov r0, r3
|
|
8003770: f7ff fa2a bl 8002bc8 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003774: f7fd fa04 bl 8000b80 <HAL_GetTick>
|
|
8003778: 60f8 str r0, [r7, #12]
|
|
|
|
/* check system clock source switch status */
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800377a: e00a b.n 8003792 <HAL_RCC_ClockConfig+0x202>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800377c: f7fd fa00 bl 8000b80 <HAL_GetTick>
|
|
8003780: 4602 mov r2, r0
|
|
8003782: 68fb ldr r3, [r7, #12]
|
|
8003784: 1ad3 subs r3, r2, r3
|
|
8003786: f241 3288 movw r2, #5000 @ 0x1388
|
|
800378a: 4293 cmp r3, r2
|
|
800378c: d901 bls.n 8003792 <HAL_RCC_ClockConfig+0x202>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800378e: 2303 movs r3, #3
|
|
8003790: e035 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8003792: f7ff fa2c bl 8002bee <LL_RCC_GetSysClkSource>
|
|
8003796: 4602 mov r2, r0
|
|
8003798: 687b ldr r3, [r7, #4]
|
|
800379a: 685b ldr r3, [r3, #4]
|
|
800379c: 009b lsls r3, r3, #2
|
|
800379e: 429a cmp r2, r3
|
|
80037a0: d1ec bne.n 800377c <HAL_RCC_ClockConfig+0x1ec>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80037a2: 4b19 ldr r3, [pc, #100] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80037a4: 681b ldr r3, [r3, #0]
|
|
80037a6: f003 0307 and.w r3, r3, #7
|
|
80037aa: 683a ldr r2, [r7, #0]
|
|
80037ac: 429a cmp r2, r3
|
|
80037ae: d21b bcs.n 80037e8 <HAL_RCC_ClockConfig+0x258>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80037b0: 4b15 ldr r3, [pc, #84] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80037b2: 681b ldr r3, [r3, #0]
|
|
80037b4: f023 0207 bic.w r2, r3, #7
|
|
80037b8: 4913 ldr r1, [pc, #76] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80037ba: 683b ldr r3, [r7, #0]
|
|
80037bc: 4313 orrs r3, r2
|
|
80037be: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80037c0: f7fd f9de bl 8000b80 <HAL_GetTick>
|
|
80037c4: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80037c6: e008 b.n 80037da <HAL_RCC_ClockConfig+0x24a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
80037c8: f7fd f9da bl 8000b80 <HAL_GetTick>
|
|
80037cc: 4602 mov r2, r0
|
|
80037ce: 68fb ldr r3, [r7, #12]
|
|
80037d0: 1ad3 subs r3, r2, r3
|
|
80037d2: 2b02 cmp r3, #2
|
|
80037d4: d901 bls.n 80037da <HAL_RCC_ClockConfig+0x24a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80037d6: 2303 movs r3, #3
|
|
80037d8: e011 b.n 80037fe <HAL_RCC_ClockConfig+0x26e>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80037da: 4b0b ldr r3, [pc, #44] @ (8003808 <HAL_RCC_ClockConfig+0x278>)
|
|
80037dc: 681b ldr r3, [r3, #0]
|
|
80037de: f003 0307 and.w r3, r3, #7
|
|
80037e2: 683a ldr r2, [r7, #0]
|
|
80037e4: 429a cmp r2, r3
|
|
80037e6: d1ef bne.n 80037c8 <HAL_RCC_ClockConfig+0x238>
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
80037e8: f000 f8b4 bl 8003954 <HAL_RCC_GetHCLKFreq>
|
|
80037ec: 4603 mov r3, r0
|
|
80037ee: 4a07 ldr r2, [pc, #28] @ (800380c <HAL_RCC_ClockConfig+0x27c>)
|
|
80037f0: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
return HAL_InitTick(uwTickPrio);
|
|
80037f2: 4b07 ldr r3, [pc, #28] @ (8003810 <HAL_RCC_ClockConfig+0x280>)
|
|
80037f4: 681b ldr r3, [r3, #0]
|
|
80037f6: 4618 mov r0, r3
|
|
80037f8: f7fd f9b8 bl 8000b6c <HAL_InitTick>
|
|
80037fc: 4603 mov r3, r0
|
|
}
|
|
80037fe: 4618 mov r0, r3
|
|
8003800: 3710 adds r7, #16
|
|
8003802: 46bd mov sp, r7
|
|
8003804: bd80 pop {r7, pc}
|
|
8003806: bf00 nop
|
|
8003808: 58004000 .word 0x58004000
|
|
800380c: 20000000 .word 0x20000000
|
|
8003810: 20000004 .word 0x20000004
|
|
|
|
08003814 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003814: b590 push {r4, r7, lr}
|
|
8003816: b087 sub sp, #28
|
|
8003818: af00 add r7, sp, #0
|
|
uint32_t sysclk_source;
|
|
uint32_t pllsource;
|
|
uint32_t sysclockfreq = 0U;
|
|
800381a: 2300 movs r3, #0
|
|
800381c: 617b str r3, [r7, #20]
|
|
uint32_t msifreq = 0U;
|
|
800381e: 2300 movs r3, #0
|
|
8003820: 613b str r3, [r7, #16]
|
|
uint32_t pllinputfreq;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003822: f7ff f9e4 bl 8002bee <LL_RCC_GetSysClkSource>
|
|
8003826: 60b8 str r0, [r7, #8]
|
|
pllsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8003828: f7ff facd bl 8002dc6 <LL_RCC_PLL_GetMainSource>
|
|
800382c: 6078 str r0, [r7, #4]
|
|
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
|
|
800382e: 68bb ldr r3, [r7, #8]
|
|
8003830: 2b00 cmp r3, #0
|
|
8003832: d005 beq.n 8003840 <HAL_RCC_GetSysClockFreq+0x2c>
|
|
8003834: 68bb ldr r3, [r7, #8]
|
|
8003836: 2b0c cmp r3, #12
|
|
8003838: d139 bne.n 80038ae <HAL_RCC_GetSysClockFreq+0x9a>
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI)))
|
|
800383a: 687b ldr r3, [r7, #4]
|
|
800383c: 2b01 cmp r3, #1
|
|
800383e: d136 bne.n 80038ae <HAL_RCC_GetSysClockFreq+0x9a>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
/* Retrieve MSI frequency range in Hz */
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
|
|
8003840: f7ff f987 bl 8002b52 <LL_RCC_MSI_IsEnabledRangeSelect>
|
|
8003844: 4603 mov r3, r0
|
|
8003846: 2b00 cmp r3, #0
|
|
8003848: d115 bne.n 8003876 <HAL_RCC_GetSysClockFreq+0x62>
|
|
800384a: f7ff f982 bl 8002b52 <LL_RCC_MSI_IsEnabledRangeSelect>
|
|
800384e: 4603 mov r3, r0
|
|
8003850: 2b01 cmp r3, #1
|
|
8003852: d106 bne.n 8003862 <HAL_RCC_GetSysClockFreq+0x4e>
|
|
8003854: f7ff f98d bl 8002b72 <LL_RCC_MSI_GetRange>
|
|
8003858: 4603 mov r3, r0
|
|
800385a: 0a1b lsrs r3, r3, #8
|
|
800385c: f003 030f and.w r3, r3, #15
|
|
8003860: e005 b.n 800386e <HAL_RCC_GetSysClockFreq+0x5a>
|
|
8003862: f7ff f991 bl 8002b88 <LL_RCC_MSI_GetRangeAfterStandby>
|
|
8003866: 4603 mov r3, r0
|
|
8003868: 0a1b lsrs r3, r3, #8
|
|
800386a: f003 030f and.w r3, r3, #15
|
|
800386e: 4a36 ldr r2, [pc, #216] @ (8003948 <HAL_RCC_GetSysClockFreq+0x134>)
|
|
8003870: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003874: e014 b.n 80038a0 <HAL_RCC_GetSysClockFreq+0x8c>
|
|
8003876: f7ff f96c bl 8002b52 <LL_RCC_MSI_IsEnabledRangeSelect>
|
|
800387a: 4603 mov r3, r0
|
|
800387c: 2b01 cmp r3, #1
|
|
800387e: d106 bne.n 800388e <HAL_RCC_GetSysClockFreq+0x7a>
|
|
8003880: f7ff f977 bl 8002b72 <LL_RCC_MSI_GetRange>
|
|
8003884: 4603 mov r3, r0
|
|
8003886: 091b lsrs r3, r3, #4
|
|
8003888: f003 030f and.w r3, r3, #15
|
|
800388c: e005 b.n 800389a <HAL_RCC_GetSysClockFreq+0x86>
|
|
800388e: f7ff f97b bl 8002b88 <LL_RCC_MSI_GetRangeAfterStandby>
|
|
8003892: 4603 mov r3, r0
|
|
8003894: 091b lsrs r3, r3, #4
|
|
8003896: f003 030f and.w r3, r3, #15
|
|
800389a: 4a2b ldr r2, [pc, #172] @ (8003948 <HAL_RCC_GetSysClockFreq+0x134>)
|
|
800389c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80038a0: 613b str r3, [r7, #16]
|
|
((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
|
|
LL_RCC_MSI_GetRange() :
|
|
LL_RCC_MSI_GetRangeAfterStandby()));
|
|
|
|
/* Get SYSCLK source */
|
|
if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
80038a2: 68bb ldr r3, [r7, #8]
|
|
80038a4: 2b00 cmp r3, #0
|
|
80038a6: d115 bne.n 80038d4 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msifreq;
|
|
80038a8: 693b ldr r3, [r7, #16]
|
|
80038aa: 617b str r3, [r7, #20]
|
|
if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
80038ac: e012 b.n 80038d4 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80038ae: 68bb ldr r3, [r7, #8]
|
|
80038b0: 2b04 cmp r3, #4
|
|
80038b2: d102 bne.n 80038ba <HAL_RCC_GetSysClockFreq+0xa6>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
80038b4: 4b25 ldr r3, [pc, #148] @ (800394c <HAL_RCC_GetSysClockFreq+0x138>)
|
|
80038b6: 617b str r3, [r7, #20]
|
|
80038b8: e00c b.n 80038d4 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
80038ba: 68bb ldr r3, [r7, #8]
|
|
80038bc: 2b08 cmp r3, #8
|
|
80038be: d109 bne.n 80038d4 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
{
|
|
/* HSE used as system clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
80038c0: f7ff f85a bl 8002978 <LL_RCC_HSE_IsEnabledDiv2>
|
|
80038c4: 4603 mov r3, r0
|
|
80038c6: 2b01 cmp r3, #1
|
|
80038c8: d102 bne.n 80038d0 <HAL_RCC_GetSysClockFreq+0xbc>
|
|
{
|
|
sysclockfreq = HSE_VALUE / 2U;
|
|
80038ca: 4b20 ldr r3, [pc, #128] @ (800394c <HAL_RCC_GetSysClockFreq+0x138>)
|
|
80038cc: 617b str r3, [r7, #20]
|
|
80038ce: e001 b.n 80038d4 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
80038d0: 4b1f ldr r3, [pc, #124] @ (8003950 <HAL_RCC_GetSysClockFreq+0x13c>)
|
|
80038d2: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
80038d4: f7ff f98b bl 8002bee <LL_RCC_GetSysClkSource>
|
|
80038d8: 4603 mov r3, r0
|
|
80038da: 2b0c cmp r3, #12
|
|
80038dc: d12f bne.n 800393e <HAL_RCC_GetSysClockFreq+0x12a>
|
|
{
|
|
/* PLL used as system clock source */
|
|
pllsource = LL_RCC_PLL_GetMainSource();
|
|
80038de: f7ff fa72 bl 8002dc6 <LL_RCC_PLL_GetMainSource>
|
|
80038e2: 6078 str r0, [r7, #4]
|
|
|
|
switch (pllsource)
|
|
80038e4: 687b ldr r3, [r7, #4]
|
|
80038e6: 2b02 cmp r3, #2
|
|
80038e8: d003 beq.n 80038f2 <HAL_RCC_GetSysClockFreq+0xde>
|
|
80038ea: 687b ldr r3, [r7, #4]
|
|
80038ec: 2b03 cmp r3, #3
|
|
80038ee: d003 beq.n 80038f8 <HAL_RCC_GetSysClockFreq+0xe4>
|
|
80038f0: e00d b.n 800390e <HAL_RCC_GetSysClockFreq+0xfa>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllinputfreq = HSI_VALUE;
|
|
80038f2: 4b16 ldr r3, [pc, #88] @ (800394c <HAL_RCC_GetSysClockFreq+0x138>)
|
|
80038f4: 60fb str r3, [r7, #12]
|
|
break;
|
|
80038f6: e00d b.n 8003914 <HAL_RCC_GetSysClockFreq+0x100>
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
80038f8: f7ff f83e bl 8002978 <LL_RCC_HSE_IsEnabledDiv2>
|
|
80038fc: 4603 mov r3, r0
|
|
80038fe: 2b01 cmp r3, #1
|
|
8003900: d102 bne.n 8003908 <HAL_RCC_GetSysClockFreq+0xf4>
|
|
{
|
|
pllinputfreq = HSE_VALUE / 2U;
|
|
8003902: 4b12 ldr r3, [pc, #72] @ (800394c <HAL_RCC_GetSysClockFreq+0x138>)
|
|
8003904: 60fb str r3, [r7, #12]
|
|
}
|
|
else
|
|
{
|
|
pllinputfreq = HSE_VALUE;
|
|
}
|
|
break;
|
|
8003906: e005 b.n 8003914 <HAL_RCC_GetSysClockFreq+0x100>
|
|
pllinputfreq = HSE_VALUE;
|
|
8003908: 4b11 ldr r3, [pc, #68] @ (8003950 <HAL_RCC_GetSysClockFreq+0x13c>)
|
|
800390a: 60fb str r3, [r7, #12]
|
|
break;
|
|
800390c: e002 b.n 8003914 <HAL_RCC_GetSysClockFreq+0x100>
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllinputfreq = msifreq;
|
|
800390e: 693b ldr r3, [r7, #16]
|
|
8003910: 60fb str r3, [r7, #12]
|
|
break;
|
|
8003912: bf00 nop
|
|
}
|
|
sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
|
|
8003914: f7ff fa35 bl 8002d82 <LL_RCC_PLL_GetN>
|
|
8003918: 4602 mov r2, r0
|
|
800391a: 68fb ldr r3, [r7, #12]
|
|
800391c: fb03 f402 mul.w r4, r3, r2
|
|
8003920: f7ff fa46 bl 8002db0 <LL_RCC_PLL_GetDivider>
|
|
8003924: 4603 mov r3, r0
|
|
8003926: 091b lsrs r3, r3, #4
|
|
8003928: 3301 adds r3, #1
|
|
800392a: fbb4 f4f3 udiv r4, r4, r3
|
|
800392e: f7ff fa34 bl 8002d9a <LL_RCC_PLL_GetR>
|
|
8003932: 4603 mov r3, r0
|
|
8003934: 0f5b lsrs r3, r3, #29
|
|
8003936: 3301 adds r3, #1
|
|
8003938: fbb4 f3f3 udiv r3, r4, r3
|
|
800393c: 617b str r3, [r7, #20]
|
|
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
|
|
}
|
|
|
|
return sysclockfreq;
|
|
800393e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8003940: 4618 mov r0, r3
|
|
8003942: 371c adds r7, #28
|
|
8003944: 46bd mov sp, r7
|
|
8003946: bd90 pop {r4, r7, pc}
|
|
8003948: 0800d928 .word 0x0800d928
|
|
800394c: 00f42400 .word 0x00f42400
|
|
8003950: 01e84800 .word 0x01e84800
|
|
|
|
08003954 <HAL_RCC_GetHCLKFreq>:
|
|
/**
|
|
* @brief Return the HCLK frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8003954: b598 push {r3, r4, r7, lr}
|
|
8003956: af00 add r7, sp, #0
|
|
/* Get SysClock and Compute HCLK1 frequency --------------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler())));
|
|
8003958: f7ff ff5c bl 8003814 <HAL_RCC_GetSysClockFreq>
|
|
800395c: 4604 mov r4, r0
|
|
800395e: f7ff f9b5 bl 8002ccc <LL_RCC_GetAHBPrescaler>
|
|
8003962: 4603 mov r3, r0
|
|
8003964: 091b lsrs r3, r3, #4
|
|
8003966: f003 030f and.w r3, r3, #15
|
|
800396a: 4a03 ldr r2, [pc, #12] @ (8003978 <HAL_RCC_GetHCLKFreq+0x24>)
|
|
800396c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003970: fbb4 f3f3 udiv r3, r4, r3
|
|
}
|
|
8003974: 4618 mov r0, r3
|
|
8003976: bd98 pop {r3, r4, r7, pc}
|
|
8003978: 0800d8c8 .word 0x0800d8c8
|
|
|
|
0800397c <HAL_RCC_GetPCLK1Freq>:
|
|
/**
|
|
* @brief Return the PCLK1 frequency.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
800397c: b598 push {r3, r4, r7, lr}
|
|
800397e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency -----------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
|
|
8003980: f7ff ffe8 bl 8003954 <HAL_RCC_GetHCLKFreq>
|
|
8003984: 4604 mov r4, r0
|
|
8003986: f7ff f9b9 bl 8002cfc <LL_RCC_GetAPB1Prescaler>
|
|
800398a: 4603 mov r3, r0
|
|
800398c: 0a1b lsrs r3, r3, #8
|
|
800398e: 4a03 ldr r2, [pc, #12] @ (800399c <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
8003990: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003994: fa24 f303 lsr.w r3, r4, r3
|
|
}
|
|
8003998: 4618 mov r0, r3
|
|
800399a: bd98 pop {r3, r4, r7, pc}
|
|
800399c: 0800d908 .word 0x0800d908
|
|
|
|
080039a0 <HAL_RCC_GetPCLK2Freq>:
|
|
/**
|
|
* @brief Return the PCLK2 frequency.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80039a0: b598 push {r3, r4, r7, lr}
|
|
80039a2: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency -----------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler())));
|
|
80039a4: f7ff ffd6 bl 8003954 <HAL_RCC_GetHCLKFreq>
|
|
80039a8: 4604 mov r4, r0
|
|
80039aa: f7ff f9b2 bl 8002d12 <LL_RCC_GetAPB2Prescaler>
|
|
80039ae: 4603 mov r3, r0
|
|
80039b0: 0adb lsrs r3, r3, #11
|
|
80039b2: 4a03 ldr r2, [pc, #12] @ (80039c0 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80039b4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80039b8: fa24 f303 lsr.w r3, r4, r3
|
|
}
|
|
80039bc: 4618 mov r0, r3
|
|
80039be: bd98 pop {r3, r4, r7, pc}
|
|
80039c0: 0800d908 .word 0x0800d908
|
|
|
|
080039c4 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
|
|
{
|
|
80039c4: b590 push {r4, r7, lr}
|
|
80039c6: b085 sub sp, #20
|
|
80039c8: af00 add r7, sp, #0
|
|
80039ca: 6078 str r0, [r7, #4]
|
|
uint32_t flash_clksrcfreq;
|
|
uint32_t msifreq;
|
|
|
|
/* MSI frequency range in Hz */
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range);
|
|
80039cc: 687b ldr r3, [r7, #4]
|
|
80039ce: 091b lsrs r3, r3, #4
|
|
80039d0: f003 030f and.w r3, r3, #15
|
|
80039d4: 4a10 ldr r2, [pc, #64] @ (8003a18 <RCC_SetFlashLatencyFromMSIRange+0x54>)
|
|
80039d6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80039da: 60fb str r3, [r7, #12]
|
|
flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler());
|
|
80039dc: f7ff f981 bl 8002ce2 <LL_RCC_GetAHB3Prescaler>
|
|
80039e0: 4603 mov r3, r0
|
|
80039e2: 091b lsrs r3, r3, #4
|
|
80039e4: f003 030f and.w r3, r3, #15
|
|
80039e8: 4a0c ldr r2, [pc, #48] @ (8003a1c <RCC_SetFlashLatencyFromMSIRange+0x58>)
|
|
80039ea: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80039ee: 68fa ldr r2, [r7, #12]
|
|
80039f0: fbb2 f3f3 udiv r3, r2, r3
|
|
80039f4: 60bb str r3, [r7, #8]
|
|
|
|
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
|
|
80039f6: 68bb ldr r3, [r7, #8]
|
|
80039f8: 4a09 ldr r2, [pc, #36] @ (8003a20 <RCC_SetFlashLatencyFromMSIRange+0x5c>)
|
|
80039fa: fba2 2303 umull r2, r3, r2, r3
|
|
80039fe: 0c9c lsrs r4, r3, #18
|
|
8003a00: f7fe ff12 bl 8002828 <HAL_PWREx_GetVoltageRange>
|
|
8003a04: 4603 mov r3, r0
|
|
8003a06: 4619 mov r1, r3
|
|
8003a08: 4620 mov r0, r4
|
|
8003a0a: f000 f80b bl 8003a24 <RCC_SetFlashLatency>
|
|
8003a0e: 4603 mov r3, r0
|
|
}
|
|
8003a10: 4618 mov r0, r3
|
|
8003a12: 3714 adds r7, #20
|
|
8003a14: 46bd mov sp, r7
|
|
8003a16: bd90 pop {r4, r7, pc}
|
|
8003a18: 0800d928 .word 0x0800d928
|
|
8003a1c: 0800d8c8 .word 0x0800d8c8
|
|
8003a20: 431bde83 .word 0x431bde83
|
|
|
|
08003a24 <RCC_SetFlashLatency>:
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
|
|
{
|
|
8003a24: b580 push {r7, lr}
|
|
8003a26: b08e sub sp, #56 @ 0x38
|
|
8003a28: af00 add r7, sp, #0
|
|
8003a2a: 6078 str r0, [r7, #4]
|
|
8003a2c: 6039 str r1, [r7, #0]
|
|
/* Flash Clock source (HCLK3) range in MHz for VCORE range1 */
|
|
const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48};
|
|
8003a2e: 4a3a ldr r2, [pc, #232] @ (8003b18 <RCC_SetFlashLatency+0xf4>)
|
|
8003a30: f107 0320 add.w r3, r7, #32
|
|
8003a34: e892 0003 ldmia.w r2, {r0, r1}
|
|
8003a38: 6018 str r0, [r3, #0]
|
|
8003a3a: 3304 adds r3, #4
|
|
8003a3c: 8019 strh r1, [r3, #0]
|
|
|
|
/* Flash Clock source (HCLK3) range in MHz for VCORE range2 */
|
|
const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16};
|
|
8003a3e: 4a37 ldr r2, [pc, #220] @ (8003b1c <RCC_SetFlashLatency+0xf8>)
|
|
8003a40: f107 0318 add.w r3, r7, #24
|
|
8003a44: e892 0003 ldmia.w r2, {r0, r1}
|
|
8003a48: 6018 str r0, [r3, #0]
|
|
8003a4a: 3304 adds r3, #4
|
|
8003a4c: 8019 strh r1, [r3, #0]
|
|
|
|
/* Flash Latency range */
|
|
const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2};
|
|
8003a4e: 4a34 ldr r2, [pc, #208] @ (8003b20 <RCC_SetFlashLatency+0xfc>)
|
|
8003a50: f107 030c add.w r3, r7, #12
|
|
8003a54: ca07 ldmia r2, {r0, r1, r2}
|
|
8003a56: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
8003a5a: 2300 movs r3, #0
|
|
8003a5c: 637b str r3, [r7, #52] @ 0x34
|
|
uint32_t tickstart;
|
|
|
|
if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8003a5e: 683b ldr r3, [r7, #0]
|
|
8003a60: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8003a64: d11b bne.n 8003a9e <RCC_SetFlashLatency+0x7a>
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
|
|
8003a66: 2300 movs r3, #0
|
|
8003a68: 633b str r3, [r7, #48] @ 0x30
|
|
8003a6a: e014 b.n 8003a96 <RCC_SetFlashLatency+0x72>
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
|
|
8003a6c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8003a6e: 005b lsls r3, r3, #1
|
|
8003a70: 3338 adds r3, #56 @ 0x38
|
|
8003a72: 443b add r3, r7
|
|
8003a74: f833 3c18 ldrh.w r3, [r3, #-24]
|
|
8003a78: 461a mov r2, r3
|
|
8003a7a: 687b ldr r3, [r7, #4]
|
|
8003a7c: 4293 cmp r3, r2
|
|
8003a7e: d807 bhi.n 8003a90 <RCC_SetFlashLatency+0x6c>
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
8003a80: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8003a82: 009b lsls r3, r3, #2
|
|
8003a84: 3338 adds r3, #56 @ 0x38
|
|
8003a86: 443b add r3, r7
|
|
8003a88: f853 3c2c ldr.w r3, [r3, #-44]
|
|
8003a8c: 637b str r3, [r7, #52] @ 0x34
|
|
break;
|
|
8003a8e: e021 b.n 8003ad4 <RCC_SetFlashLatency+0xb0>
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
|
|
8003a90: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8003a92: 3301 adds r3, #1
|
|
8003a94: 633b str r3, [r7, #48] @ 0x30
|
|
8003a96: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8003a98: 2b02 cmp r3, #2
|
|
8003a9a: d9e7 bls.n 8003a6c <RCC_SetFlashLatency+0x48>
|
|
8003a9c: e01a b.n 8003ad4 <RCC_SetFlashLatency+0xb0>
|
|
}
|
|
}
|
|
}
|
|
else /* PWR_REGULATOR_VOLTAGE_SCALE2 */
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
|
|
8003a9e: 2300 movs r3, #0
|
|
8003aa0: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003aa2: e014 b.n 8003ace <RCC_SetFlashLatency+0xaa>
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index])
|
|
8003aa4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003aa6: 005b lsls r3, r3, #1
|
|
8003aa8: 3338 adds r3, #56 @ 0x38
|
|
8003aaa: 443b add r3, r7
|
|
8003aac: f833 3c20 ldrh.w r3, [r3, #-32]
|
|
8003ab0: 461a mov r2, r3
|
|
8003ab2: 687b ldr r3, [r7, #4]
|
|
8003ab4: 4293 cmp r3, r2
|
|
8003ab6: d807 bhi.n 8003ac8 <RCC_SetFlashLatency+0xa4>
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
8003ab8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003aba: 009b lsls r3, r3, #2
|
|
8003abc: 3338 adds r3, #56 @ 0x38
|
|
8003abe: 443b add r3, r7
|
|
8003ac0: f853 3c2c ldr.w r3, [r3, #-44]
|
|
8003ac4: 637b str r3, [r7, #52] @ 0x34
|
|
break;
|
|
8003ac6: e005 b.n 8003ad4 <RCC_SetFlashLatency+0xb0>
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
|
|
8003ac8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003aca: 3301 adds r3, #1
|
|
8003acc: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003ace: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003ad0: 2b02 cmp r3, #2
|
|
8003ad2: d9e7 bls.n 8003aa4 <RCC_SetFlashLatency+0x80>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
8003ad4: 4b13 ldr r3, [pc, #76] @ (8003b24 <RCC_SetFlashLatency+0x100>)
|
|
8003ad6: 681b ldr r3, [r3, #0]
|
|
8003ad8: f023 0207 bic.w r2, r3, #7
|
|
8003adc: 4911 ldr r1, [pc, #68] @ (8003b24 <RCC_SetFlashLatency+0x100>)
|
|
8003ade: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8003ae0: 4313 orrs r3, r2
|
|
8003ae2: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ae4: f7fd f84c bl 8000b80 <HAL_GetTick>
|
|
8003ae8: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != latency)
|
|
8003aea: e008 b.n 8003afe <RCC_SetFlashLatency+0xda>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
8003aec: f7fd f848 bl 8000b80 <HAL_GetTick>
|
|
8003af0: 4602 mov r2, r0
|
|
8003af2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003af4: 1ad3 subs r3, r2, r3
|
|
8003af6: 2b02 cmp r3, #2
|
|
8003af8: d901 bls.n 8003afe <RCC_SetFlashLatency+0xda>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003afa: 2303 movs r3, #3
|
|
8003afc: e007 b.n 8003b0e <RCC_SetFlashLatency+0xea>
|
|
while (__HAL_FLASH_GET_LATENCY() != latency)
|
|
8003afe: 4b09 ldr r3, [pc, #36] @ (8003b24 <RCC_SetFlashLatency+0x100>)
|
|
8003b00: 681b ldr r3, [r3, #0]
|
|
8003b02: f003 0307 and.w r3, r3, #7
|
|
8003b06: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8003b08: 429a cmp r2, r3
|
|
8003b0a: d1ef bne.n 8003aec <RCC_SetFlashLatency+0xc8>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003b0c: 2300 movs r3, #0
|
|
}
|
|
8003b0e: 4618 mov r0, r3
|
|
8003b10: 3738 adds r7, #56 @ 0x38
|
|
8003b12: 46bd mov sp, r7
|
|
8003b14: bd80 pop {r7, pc}
|
|
8003b16: bf00 nop
|
|
8003b18: 0800d50c .word 0x0800d50c
|
|
8003b1c: 0800d514 .word 0x0800d514
|
|
8003b20: 0800d51c .word 0x0800d51c
|
|
8003b24: 58004000 .word 0x58004000
|
|
|
|
08003b28 <LL_RCC_LSE_IsReady>:
|
|
{
|
|
8003b28: b480 push {r7}
|
|
8003b2a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
|
|
8003b2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003b30: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003b34: f003 0302 and.w r3, r3, #2
|
|
8003b38: 2b02 cmp r3, #2
|
|
8003b3a: d101 bne.n 8003b40 <LL_RCC_LSE_IsReady+0x18>
|
|
8003b3c: 2301 movs r3, #1
|
|
8003b3e: e000 b.n 8003b42 <LL_RCC_LSE_IsReady+0x1a>
|
|
8003b40: 2300 movs r3, #0
|
|
}
|
|
8003b42: 4618 mov r0, r3
|
|
8003b44: 46bd mov sp, r7
|
|
8003b46: bc80 pop {r7}
|
|
8003b48: 4770 bx lr
|
|
|
|
08003b4a <LL_RCC_SetUSARTClockSource>:
|
|
{
|
|
8003b4a: b480 push {r7}
|
|
8003b4c: b083 sub sp, #12
|
|
8003b4e: af00 add r7, sp, #0
|
|
8003b50: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU));
|
|
8003b52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003b56: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
8003b5a: 687b ldr r3, [r7, #4]
|
|
8003b5c: 0c1b lsrs r3, r3, #16
|
|
8003b5e: 43db mvns r3, r3
|
|
8003b60: 401a ands r2, r3
|
|
8003b62: 687b ldr r3, [r7, #4]
|
|
8003b64: b29b uxth r3, r3
|
|
8003b66: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003b6a: 4313 orrs r3, r2
|
|
8003b6c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003b70: bf00 nop
|
|
8003b72: 370c adds r7, #12
|
|
8003b74: 46bd mov sp, r7
|
|
8003b76: bc80 pop {r7}
|
|
8003b78: 4770 bx lr
|
|
|
|
08003b7a <LL_RCC_SetI2SClockSource>:
|
|
{
|
|
8003b7a: b480 push {r7}
|
|
8003b7c: b083 sub sp, #12
|
|
8003b7e: af00 add r7, sp, #0
|
|
8003b80: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource);
|
|
8003b82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003b86: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003b8a: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8003b8e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003b92: 687b ldr r3, [r7, #4]
|
|
8003b94: 4313 orrs r3, r2
|
|
8003b96: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003b9a: bf00 nop
|
|
8003b9c: 370c adds r7, #12
|
|
8003b9e: 46bd mov sp, r7
|
|
8003ba0: bc80 pop {r7}
|
|
8003ba2: 4770 bx lr
|
|
|
|
08003ba4 <LL_RCC_SetLPUARTClockSource>:
|
|
{
|
|
8003ba4: b480 push {r7}
|
|
8003ba6: b083 sub sp, #12
|
|
8003ba8: af00 add r7, sp, #0
|
|
8003baa: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
|
|
8003bac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003bb0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003bb4: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8003bb8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003bbc: 687b ldr r3, [r7, #4]
|
|
8003bbe: 4313 orrs r3, r2
|
|
8003bc0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003bc4: bf00 nop
|
|
8003bc6: 370c adds r7, #12
|
|
8003bc8: 46bd mov sp, r7
|
|
8003bca: bc80 pop {r7}
|
|
8003bcc: 4770 bx lr
|
|
|
|
08003bce <LL_RCC_SetI2CClockSource>:
|
|
{
|
|
8003bce: b480 push {r7}
|
|
8003bd0: b083 sub sp, #12
|
|
8003bd2: af00 add r7, sp, #0
|
|
8003bd4: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
|
|
8003bd6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003bda: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
8003bde: 687b ldr r3, [r7, #4]
|
|
8003be0: 091b lsrs r3, r3, #4
|
|
8003be2: f403 237f and.w r3, r3, #1044480 @ 0xff000
|
|
8003be6: 43db mvns r3, r3
|
|
8003be8: 401a ands r2, r3
|
|
8003bea: 687b ldr r3, [r7, #4]
|
|
8003bec: 011b lsls r3, r3, #4
|
|
8003bee: f403 237f and.w r3, r3, #1044480 @ 0xff000
|
|
8003bf2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003bf6: 4313 orrs r3, r2
|
|
8003bf8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003bfc: bf00 nop
|
|
8003bfe: 370c adds r7, #12
|
|
8003c00: 46bd mov sp, r7
|
|
8003c02: bc80 pop {r7}
|
|
8003c04: 4770 bx lr
|
|
|
|
08003c06 <LL_RCC_SetLPTIMClockSource>:
|
|
{
|
|
8003c06: b480 push {r7}
|
|
8003c08: b083 sub sp, #12
|
|
8003c0a: af00 add r7, sp, #0
|
|
8003c0c: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
|
|
8003c0e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003c12: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
8003c16: 687b ldr r3, [r7, #4]
|
|
8003c18: 0c1b lsrs r3, r3, #16
|
|
8003c1a: 041b lsls r3, r3, #16
|
|
8003c1c: 43db mvns r3, r3
|
|
8003c1e: 401a ands r2, r3
|
|
8003c20: 687b ldr r3, [r7, #4]
|
|
8003c22: 041b lsls r3, r3, #16
|
|
8003c24: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003c28: 4313 orrs r3, r2
|
|
8003c2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003c2e: bf00 nop
|
|
8003c30: 370c adds r7, #12
|
|
8003c32: 46bd mov sp, r7
|
|
8003c34: bc80 pop {r7}
|
|
8003c36: 4770 bx lr
|
|
|
|
08003c38 <LL_RCC_SetRNGClockSource>:
|
|
{
|
|
8003c38: b480 push {r7}
|
|
8003c3a: b083 sub sp, #12
|
|
8003c3c: af00 add r7, sp, #0
|
|
8003c3e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
|
|
8003c40: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003c44: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003c48: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000
|
|
8003c4c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003c50: 687b ldr r3, [r7, #4]
|
|
8003c52: 4313 orrs r3, r2
|
|
8003c54: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003c58: bf00 nop
|
|
8003c5a: 370c adds r7, #12
|
|
8003c5c: 46bd mov sp, r7
|
|
8003c5e: bc80 pop {r7}
|
|
8003c60: 4770 bx lr
|
|
|
|
08003c62 <LL_RCC_SetADCClockSource>:
|
|
{
|
|
8003c62: b480 push {r7}
|
|
8003c64: b083 sub sp, #12
|
|
8003c66: af00 add r7, sp, #0
|
|
8003c68: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
|
|
8003c6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003c6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003c72: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8003c76: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003c7a: 687b ldr r3, [r7, #4]
|
|
8003c7c: 4313 orrs r3, r2
|
|
8003c7e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
8003c82: bf00 nop
|
|
8003c84: 370c adds r7, #12
|
|
8003c86: 46bd mov sp, r7
|
|
8003c88: bc80 pop {r7}
|
|
8003c8a: 4770 bx lr
|
|
|
|
08003c8c <LL_RCC_SetRTCClockSource>:
|
|
{
|
|
8003c8c: b480 push {r7}
|
|
8003c8e: b083 sub sp, #12
|
|
8003c90: af00 add r7, sp, #0
|
|
8003c92: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
|
|
8003c94: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003c98: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003c9c: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8003ca0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8003ca4: 687b ldr r3, [r7, #4]
|
|
8003ca6: 4313 orrs r3, r2
|
|
8003ca8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
8003cac: bf00 nop
|
|
8003cae: 370c adds r7, #12
|
|
8003cb0: 46bd mov sp, r7
|
|
8003cb2: bc80 pop {r7}
|
|
8003cb4: 4770 bx lr
|
|
|
|
08003cb6 <LL_RCC_GetRTCClockSource>:
|
|
{
|
|
8003cb6: b480 push {r7}
|
|
8003cb8: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
|
|
8003cba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003cbe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003cc2: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
}
|
|
8003cc6: 4618 mov r0, r3
|
|
8003cc8: 46bd mov sp, r7
|
|
8003cca: bc80 pop {r7}
|
|
8003ccc: 4770 bx lr
|
|
|
|
08003cce <LL_RCC_ForceBackupDomainReset>:
|
|
{
|
|
8003cce: b480 push {r7}
|
|
8003cd0: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
8003cd2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003cd6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003cda: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003cde: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003ce2: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
8003ce6: bf00 nop
|
|
8003ce8: 46bd mov sp, r7
|
|
8003cea: bc80 pop {r7}
|
|
8003cec: 4770 bx lr
|
|
|
|
08003cee <LL_RCC_ReleaseBackupDomainReset>:
|
|
{
|
|
8003cee: b480 push {r7}
|
|
8003cf0: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
8003cf2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003cf6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003cfa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003cfe: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8003d02: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
8003d06: bf00 nop
|
|
8003d08: 46bd mov sp, r7
|
|
8003d0a: bc80 pop {r7}
|
|
8003d0c: 4770 bx lr
|
|
...
|
|
|
|
08003d10 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8003d10: b580 push {r7, lr}
|
|
8003d12: b086 sub sp, #24
|
|
8003d14: af00 add r7, sp, #0
|
|
8003d16: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister = 0;
|
|
8003d18: 2300 movs r3, #0
|
|
8003d1a: 617b str r3, [r7, #20]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8003d1c: 2300 movs r3, #0
|
|
8003d1e: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8003d20: 2300 movs r3, #0
|
|
8003d22: 74bb strb r3, [r7, #18]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8003d24: 687b ldr r3, [r7, #4]
|
|
8003d26: 681b ldr r3, [r3, #0]
|
|
8003d28: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003d2c: 2b00 cmp r3, #0
|
|
8003d2e: d058 beq.n 8003de2 <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
|
|
/* Enable write access to Backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8003d30: f7fe fd38 bl 80027a4 <HAL_PWR_EnableBkUpAccess>
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003d34: f7fc ff24 bl 8000b80 <HAL_GetTick>
|
|
8003d38: 60f8 str r0, [r7, #12]
|
|
|
|
while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)))
|
|
8003d3a: e009 b.n 8003d50 <HAL_RCCEx_PeriphCLKConfig+0x40>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003d3c: f7fc ff20 bl 8000b80 <HAL_GetTick>
|
|
8003d40: 4602 mov r2, r0
|
|
8003d42: 68fb ldr r3, [r7, #12]
|
|
8003d44: 1ad3 subs r3, r2, r3
|
|
8003d46: 2b02 cmp r3, #2
|
|
8003d48: d902 bls.n 8003d50 <HAL_RCCEx_PeriphCLKConfig+0x40>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8003d4a: 2303 movs r3, #3
|
|
8003d4c: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8003d4e: e006 b.n 8003d5e <HAL_RCCEx_PeriphCLKConfig+0x4e>
|
|
while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)))
|
|
8003d50: 4b7b ldr r3, [pc, #492] @ (8003f40 <HAL_RCCEx_PeriphCLKConfig+0x230>)
|
|
8003d52: 681b ldr r3, [r3, #0]
|
|
8003d54: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003d58: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8003d5c: d1ee bne.n 8003d3c <HAL_RCCEx_PeriphCLKConfig+0x2c>
|
|
}
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
8003d5e: 7cfb ldrb r3, [r7, #19]
|
|
8003d60: 2b00 cmp r3, #0
|
|
8003d62: d13c bne.n 8003dde <HAL_RCCEx_PeriphCLKConfig+0xce>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified */
|
|
if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection)
|
|
8003d64: f7ff ffa7 bl 8003cb6 <LL_RCC_GetRTCClockSource>
|
|
8003d68: 4602 mov r2, r0
|
|
8003d6a: 687b ldr r3, [r7, #4]
|
|
8003d6c: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003d6e: 429a cmp r2, r3
|
|
8003d70: d00f beq.n 8003d92 <HAL_RCCEx_PeriphCLKConfig+0x82>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
8003d72: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003d76: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d7a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8003d7e: 617b str r3, [r7, #20]
|
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8003d80: f7ff ffa5 bl 8003cce <LL_RCC_ForceBackupDomainReset>
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8003d84: f7ff ffb3 bl 8003cee <LL_RCC_ReleaseBackupDomainReset>
|
|
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8003d88: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003d8c: 697b ldr r3, [r7, #20]
|
|
8003d8e: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY))
|
|
8003d92: 697b ldr r3, [r7, #20]
|
|
8003d94: f003 0302 and.w r3, r3, #2
|
|
8003d98: 2b00 cmp r3, #0
|
|
8003d9a: d014 beq.n 8003dc6 <HAL_RCCEx_PeriphCLKConfig+0xb6>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d9c: f7fc fef0 bl 8000b80 <HAL_GetTick>
|
|
8003da0: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (LL_RCC_LSE_IsReady() != 1U)
|
|
8003da2: e00b b.n 8003dbc <HAL_RCCEx_PeriphCLKConfig+0xac>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003da4: f7fc feec bl 8000b80 <HAL_GetTick>
|
|
8003da8: 4602 mov r2, r0
|
|
8003daa: 68fb ldr r3, [r7, #12]
|
|
8003dac: 1ad3 subs r3, r2, r3
|
|
8003dae: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003db2: 4293 cmp r3, r2
|
|
8003db4: d902 bls.n 8003dbc <HAL_RCCEx_PeriphCLKConfig+0xac>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8003db6: 2303 movs r3, #3
|
|
8003db8: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8003dba: e004 b.n 8003dc6 <HAL_RCCEx_PeriphCLKConfig+0xb6>
|
|
while (LL_RCC_LSE_IsReady() != 1U)
|
|
8003dbc: f7ff feb4 bl 8003b28 <LL_RCC_LSE_IsReady>
|
|
8003dc0: 4603 mov r3, r0
|
|
8003dc2: 2b01 cmp r3, #1
|
|
8003dc4: d1ee bne.n 8003da4 <HAL_RCCEx_PeriphCLKConfig+0x94>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
8003dc6: 7cfb ldrb r3, [r7, #19]
|
|
8003dc8: 2b00 cmp r3, #0
|
|
8003dca: d105 bne.n 8003dd8 <HAL_RCCEx_PeriphCLKConfig+0xc8>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8003dcc: 687b ldr r3, [r7, #4]
|
|
8003dce: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003dd0: 4618 mov r0, r3
|
|
8003dd2: f7ff ff5b bl 8003c8c <LL_RCC_SetRTCClockSource>
|
|
8003dd6: e004 b.n 8003de2 <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003dd8: 7cfb ldrb r3, [r7, #19]
|
|
8003dda: 74bb strb r3, [r7, #18]
|
|
8003ddc: e001 b.n 8003de2 <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003dde: 7cfb ldrb r3, [r7, #19]
|
|
8003de0: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
}
|
|
|
|
/*-------------------- USART1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8003de2: 687b ldr r3, [r7, #4]
|
|
8003de4: 681b ldr r3, [r3, #0]
|
|
8003de6: f003 0301 and.w r3, r3, #1
|
|
8003dea: 2b00 cmp r3, #0
|
|
8003dec: d004 beq.n 8003df8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
8003dee: 687b ldr r3, [r7, #4]
|
|
8003df0: 685b ldr r3, [r3, #4]
|
|
8003df2: 4618 mov r0, r3
|
|
8003df4: f7ff fea9 bl 8003b4a <LL_RCC_SetUSARTClockSource>
|
|
}
|
|
|
|
/*-------------------- USART2 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8003df8: 687b ldr r3, [r7, #4]
|
|
8003dfa: 681b ldr r3, [r3, #0]
|
|
8003dfc: f003 0302 and.w r3, r3, #2
|
|
8003e00: 2b00 cmp r3, #0
|
|
8003e02: d004 beq.n 8003e0e <HAL_RCCEx_PeriphCLKConfig+0xfe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
8003e04: 687b ldr r3, [r7, #4]
|
|
8003e06: 689b ldr r3, [r3, #8]
|
|
8003e08: 4618 mov r0, r3
|
|
8003e0a: f7ff fe9e bl 8003b4a <LL_RCC_SetUSARTClockSource>
|
|
}
|
|
|
|
/*-------------------- LPUART1 clock source configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
8003e0e: 687b ldr r3, [r7, #4]
|
|
8003e10: 681b ldr r3, [r3, #0]
|
|
8003e12: f003 0320 and.w r3, r3, #32
|
|
8003e16: 2b00 cmp r3, #0
|
|
8003e18: d004 beq.n 8003e24 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUAR1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8003e1a: 687b ldr r3, [r7, #4]
|
|
8003e1c: 691b ldr r3, [r3, #16]
|
|
8003e1e: 4618 mov r0, r3
|
|
8003e20: f7ff fec0 bl 8003ba4 <LL_RCC_SetLPUARTClockSource>
|
|
}
|
|
|
|
/*-------------------- LPTIM1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
8003e24: 687b ldr r3, [r7, #4]
|
|
8003e26: 681b ldr r3, [r3, #0]
|
|
8003e28: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003e2c: 2b00 cmp r3, #0
|
|
8003e2e: d004 beq.n 8003e3a <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
|
|
|
|
/* Configure the LPTIM1 clock source */
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
8003e30: 687b ldr r3, [r7, #4]
|
|
8003e32: 6a1b ldr r3, [r3, #32]
|
|
8003e34: 4618 mov r0, r3
|
|
8003e36: f7ff fee6 bl 8003c06 <LL_RCC_SetLPTIMClockSource>
|
|
}
|
|
|
|
/*-------------------- LPTIM2 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
8003e3a: 687b ldr r3, [r7, #4]
|
|
8003e3c: 681b ldr r3, [r3, #0]
|
|
8003e3e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003e42: 2b00 cmp r3, #0
|
|
8003e44: d004 beq.n 8003e50 <HAL_RCCEx_PeriphCLKConfig+0x140>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
|
|
|
|
/* Configure the LPTIM2 clock source */
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
8003e46: 687b ldr r3, [r7, #4]
|
|
8003e48: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003e4a: 4618 mov r0, r3
|
|
8003e4c: f7ff fedb bl 8003c06 <LL_RCC_SetLPTIMClockSource>
|
|
}
|
|
|
|
/*-------------------- LPTIM3 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3))
|
|
8003e50: 687b ldr r3, [r7, #4]
|
|
8003e52: 681b ldr r3, [r3, #0]
|
|
8003e54: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003e58: 2b00 cmp r3, #0
|
|
8003e5a: d004 beq.n 8003e66 <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection));
|
|
|
|
/* Configure the LPTIM3 clock source */
|
|
__HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection);
|
|
8003e5c: 687b ldr r3, [r7, #4]
|
|
8003e5e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003e60: 4618 mov r0, r3
|
|
8003e62: f7ff fed0 bl 8003c06 <LL_RCC_SetLPTIMClockSource>
|
|
}
|
|
|
|
/*-------------------- I2C1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8003e66: 687b ldr r3, [r7, #4]
|
|
8003e68: 681b ldr r3, [r3, #0]
|
|
8003e6a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003e6e: 2b00 cmp r3, #0
|
|
8003e70: d004 beq.n 8003e7c <HAL_RCCEx_PeriphCLKConfig+0x16c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8003e72: 687b ldr r3, [r7, #4]
|
|
8003e74: 695b ldr r3, [r3, #20]
|
|
8003e76: 4618 mov r0, r3
|
|
8003e78: f7ff fea9 bl 8003bce <LL_RCC_SetI2CClockSource>
|
|
}
|
|
|
|
/*-------------------- I2C2 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
8003e7c: 687b ldr r3, [r7, #4]
|
|
8003e7e: 681b ldr r3, [r3, #0]
|
|
8003e80: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003e84: 2b00 cmp r3, #0
|
|
8003e86: d004 beq.n 8003e92 <HAL_RCCEx_PeriphCLKConfig+0x182>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
8003e88: 687b ldr r3, [r7, #4]
|
|
8003e8a: 699b ldr r3, [r3, #24]
|
|
8003e8c: 4618 mov r0, r3
|
|
8003e8e: f7ff fe9e bl 8003bce <LL_RCC_SetI2CClockSource>
|
|
}
|
|
|
|
/*-------------------- I2C3 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
8003e92: 687b ldr r3, [r7, #4]
|
|
8003e94: 681b ldr r3, [r3, #0]
|
|
8003e96: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003e9a: 2b00 cmp r3, #0
|
|
8003e9c: d004 beq.n 8003ea8 <HAL_RCCEx_PeriphCLKConfig+0x198>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
8003e9e: 687b ldr r3, [r7, #4]
|
|
8003ea0: 69db ldr r3, [r3, #28]
|
|
8003ea2: 4618 mov r0, r3
|
|
8003ea4: f7ff fe93 bl 8003bce <LL_RCC_SetI2CClockSource>
|
|
}
|
|
|
|
/*-------------------- I2S2 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2))
|
|
8003ea8: 687b ldr r3, [r7, #4]
|
|
8003eaa: 681b ldr r3, [r3, #0]
|
|
8003eac: f003 0310 and.w r3, r3, #16
|
|
8003eb0: 2b00 cmp r3, #0
|
|
8003eb2: d011 beq.n 8003ed8 <HAL_RCCEx_PeriphCLKConfig+0x1c8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
|
|
|
|
/* Configure the I2S2 clock source */
|
|
__HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
|
|
8003eb4: 687b ldr r3, [r7, #4]
|
|
8003eb6: 68db ldr r3, [r3, #12]
|
|
8003eb8: 4618 mov r0, r3
|
|
8003eba: f7ff fe5e bl 8003b7a <LL_RCC_SetI2SClockSource>
|
|
|
|
if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL)
|
|
8003ebe: 687b ldr r3, [r7, #4]
|
|
8003ec0: 68db ldr r3, [r3, #12]
|
|
8003ec2: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8003ec6: d107 bne.n 8003ed8 <HAL_RCCEx_PeriphCLKConfig+0x1c8>
|
|
{
|
|
/* Enable RCC_PLL_I2S2CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK);
|
|
8003ec8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003ecc: 68db ldr r3, [r3, #12]
|
|
8003ece: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003ed2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003ed6: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
/*-------------------- RNG clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8003ed8: 687b ldr r3, [r7, #4]
|
|
8003eda: 681b ldr r3, [r3, #0]
|
|
8003edc: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8003ee0: 2b00 cmp r3, #0
|
|
8003ee2: d010 beq.n 8003f06 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8003ee4: 687b ldr r3, [r7, #4]
|
|
8003ee6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003ee8: 4618 mov r0, r3
|
|
8003eea: f7ff fea5 bl 8003c38 <LL_RCC_SetRNGClockSource>
|
|
|
|
if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8003eee: 687b ldr r3, [r7, #4]
|
|
8003ef0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003ef2: 2b00 cmp r3, #0
|
|
8003ef4: d107 bne.n 8003f06 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
|
|
{
|
|
/* Enable RCC_PLL_RNGCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
|
|
8003ef6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003efa: 68db ldr r3, [r3, #12]
|
|
8003efc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003f00: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003f04: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
/*-------------------- ADC clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8003f06: 687b ldr r3, [r7, #4]
|
|
8003f08: 681b ldr r3, [r3, #0]
|
|
8003f0a: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8003f0e: 2b00 cmp r3, #0
|
|
8003f10: d011 beq.n 8003f36 <HAL_RCCEx_PeriphCLKConfig+0x226>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8003f12: 687b ldr r3, [r7, #4]
|
|
8003f14: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003f16: 4618 mov r0, r3
|
|
8003f18: f7ff fea3 bl 8003c62 <LL_RCC_SetADCClockSource>
|
|
|
|
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
|
|
8003f1c: 687b ldr r3, [r7, #4]
|
|
8003f1e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003f20: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003f24: d107 bne.n 8003f36 <HAL_RCCEx_PeriphCLKConfig+0x226>
|
|
{
|
|
/* Enable RCC_PLL_RNGCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
|
|
8003f26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8003f2a: 68db ldr r3, [r3, #12]
|
|
8003f2c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8003f30: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003f34: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8003f36: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8003f38: 4618 mov r0, r3
|
|
8003f3a: 3718 adds r7, #24
|
|
8003f3c: 46bd mov sp, r7
|
|
8003f3e: bd80 pop {r7, pc}
|
|
8003f40: 58000400 .word 0x58000400
|
|
|
|
08003f44 <HAL_RTC_Init>:
|
|
* @brief Initialize the RTC peripheral
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8003f44: b580 push {r7, lr}
|
|
8003f46: b084 sub sp, #16
|
|
8003f48: af00 add r7, sp, #0
|
|
8003f4a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|
8003f4c: 2301 movs r3, #1
|
|
8003f4e: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the RTC peripheral state */
|
|
if (hrtc != NULL)
|
|
8003f50: 687b ldr r3, [r7, #4]
|
|
8003f52: 2b00 cmp r3, #0
|
|
8003f54: d07b beq.n 800404e <HAL_RTC_Init+0x10a>
|
|
{
|
|
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
|
|
}
|
|
}
|
|
#else
|
|
if (hrtc->State == HAL_RTC_STATE_RESET)
|
|
8003f56: 687b ldr r3, [r7, #4]
|
|
8003f58: f893 302d ldrb.w r3, [r3, #45] @ 0x2d
|
|
8003f5c: b2db uxtb r3, r3
|
|
8003f5e: 2b00 cmp r3, #0
|
|
8003f60: d106 bne.n 8003f70 <HAL_RTC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
8003f62: 687b ldr r3, [r7, #4]
|
|
8003f64: 2200 movs r2, #0
|
|
8003f66: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
/* Initialize RTC MSP */
|
|
HAL_RTC_MspInit(hrtc);
|
|
8003f6a: 6878 ldr r0, [r7, #4]
|
|
8003f6c: f7fc fc4c bl 8000808 <HAL_RTC_MspInit>
|
|
}
|
|
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8003f70: 687b ldr r3, [r7, #4]
|
|
8003f72: 2202 movs r2, #2
|
|
8003f74: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Check whether the calendar needs to be initialized */
|
|
if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
|
|
8003f78: 4b37 ldr r3, [pc, #220] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003f7a: 68db ldr r3, [r3, #12]
|
|
8003f7c: f003 0310 and.w r3, r3, #16
|
|
8003f80: 2b10 cmp r3, #16
|
|
8003f82: d05b beq.n 800403c <HAL_RTC_Init+0xf8>
|
|
{
|
|
/* Check that the RTC mode is not 'binary only' */
|
|
if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY)
|
|
8003f84: 4b34 ldr r3, [pc, #208] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003f86: 68db ldr r3, [r3, #12]
|
|
8003f88: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003f8c: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8003f90: d051 beq.n 8004036 <HAL_RTC_Init+0xf2>
|
|
{
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8003f92: 4b31 ldr r3, [pc, #196] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003f94: 22ca movs r2, #202 @ 0xca
|
|
8003f96: 625a str r2, [r3, #36] @ 0x24
|
|
8003f98: 4b2f ldr r3, [pc, #188] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003f9a: 2253 movs r2, #83 @ 0x53
|
|
8003f9c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Enter Initialization mode */
|
|
status = RTC_EnterInitMode(hrtc);
|
|
8003f9e: 6878 ldr r0, [r7, #4]
|
|
8003fa0: f000 fa14 bl 80043cc <RTC_EnterInitMode>
|
|
8003fa4: 4603 mov r3, r0
|
|
8003fa6: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
8003fa8: 7bfb ldrb r3, [r7, #15]
|
|
8003faa: 2b00 cmp r3, #0
|
|
8003fac: d13f bne.n 800402e <HAL_RTC_Init+0xea>
|
|
{
|
|
/* Clear RTC_CR FMT, OSEL and POL Bits */
|
|
CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
|
|
8003fae: 4b2a ldr r3, [pc, #168] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fb0: 699b ldr r3, [r3, #24]
|
|
8003fb2: 4a29 ldr r2, [pc, #164] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fb4: f023 638e bic.w r3, r3, #74448896 @ 0x4700000
|
|
8003fb8: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8003fbc: 6193 str r3, [r2, #24]
|
|
/* Set RTC_CR register */
|
|
SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
|
|
8003fbe: 4b26 ldr r3, [pc, #152] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fc0: 699a ldr r2, [r3, #24]
|
|
8003fc2: 687b ldr r3, [r7, #4]
|
|
8003fc4: 6859 ldr r1, [r3, #4]
|
|
8003fc6: 687b ldr r3, [r7, #4]
|
|
8003fc8: 691b ldr r3, [r3, #16]
|
|
8003fca: 4319 orrs r1, r3
|
|
8003fcc: 687b ldr r3, [r7, #4]
|
|
8003fce: 699b ldr r3, [r3, #24]
|
|
8003fd0: 430b orrs r3, r1
|
|
8003fd2: 4921 ldr r1, [pc, #132] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fd4: 4313 orrs r3, r2
|
|
8003fd6: 618b str r3, [r1, #24]
|
|
|
|
/* Configure the RTC PRER */
|
|
WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
|
|
8003fd8: 687b ldr r3, [r7, #4]
|
|
8003fda: 68da ldr r2, [r3, #12]
|
|
8003fdc: 687b ldr r3, [r7, #4]
|
|
8003fde: 689b ldr r3, [r3, #8]
|
|
8003fe0: 041b lsls r3, r3, #16
|
|
8003fe2: 491d ldr r1, [pc, #116] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fe4: 4313 orrs r3, r2
|
|
8003fe6: 610b str r3, [r1, #16]
|
|
|
|
/* Configure the Binary mode */
|
|
MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
|
|
8003fe8: 4b1b ldr r3, [pc, #108] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003fea: 68db ldr r3, [r3, #12]
|
|
8003fec: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8003ff0: 687b ldr r3, [r7, #4]
|
|
8003ff2: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
8003ff4: 687b ldr r3, [r7, #4]
|
|
8003ff6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003ff8: 430b orrs r3, r1
|
|
8003ffa: 4917 ldr r1, [pc, #92] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8003ffc: 4313 orrs r3, r2
|
|
8003ffe: 60cb str r3, [r1, #12]
|
|
|
|
/* Exit Initialization mode */
|
|
status = RTC_ExitInitMode(hrtc);
|
|
8004000: 6878 ldr r0, [r7, #4]
|
|
8004002: f000 fa17 bl 8004434 <RTC_ExitInitMode>
|
|
8004006: 4603 mov r3, r0
|
|
8004008: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
800400a: 7bfb ldrb r3, [r7, #15]
|
|
800400c: 2b00 cmp r3, #0
|
|
800400e: d10e bne.n 800402e <HAL_RTC_Init+0xea>
|
|
{
|
|
MODIFY_REG(RTC->CR, \
|
|
8004010: 4b11 ldr r3, [pc, #68] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8004012: 699b ldr r3, [r3, #24]
|
|
8004014: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
|
|
8004018: 687b ldr r3, [r7, #4]
|
|
800401a: 6a19 ldr r1, [r3, #32]
|
|
800401c: 687b ldr r3, [r7, #4]
|
|
800401e: 69db ldr r3, [r3, #28]
|
|
8004020: 4319 orrs r1, r3
|
|
8004022: 687b ldr r3, [r7, #4]
|
|
8004024: 695b ldr r3, [r3, #20]
|
|
8004026: 430b orrs r3, r1
|
|
8004028: 490b ldr r1, [pc, #44] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
800402a: 4313 orrs r3, r2
|
|
800402c: 618b str r3, [r1, #24]
|
|
hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
|
|
}
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800402e: 4b0a ldr r3, [pc, #40] @ (8004058 <HAL_RTC_Init+0x114>)
|
|
8004030: 22ff movs r2, #255 @ 0xff
|
|
8004032: 625a str r2, [r3, #36] @ 0x24
|
|
8004034: e004 b.n 8004040 <HAL_RTC_Init+0xfc>
|
|
}
|
|
else
|
|
{
|
|
/* The calendar does not need to be initialized as the 'binary only' mode is selected */
|
|
status = HAL_OK;
|
|
8004036: 2300 movs r3, #0
|
|
8004038: 73fb strb r3, [r7, #15]
|
|
800403a: e001 b.n 8004040 <HAL_RTC_Init+0xfc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The calendar is already initialized */
|
|
status = HAL_OK;
|
|
800403c: 2300 movs r3, #0
|
|
800403e: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
8004040: 7bfb ldrb r3, [r7, #15]
|
|
8004042: 2b00 cmp r3, #0
|
|
8004044: d103 bne.n 800404e <HAL_RTC_Init+0x10a>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8004046: 687b ldr r3, [r7, #4]
|
|
8004048: 2201 movs r2, #1
|
|
800404a: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800404e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004050: 4618 mov r0, r3
|
|
8004052: 3710 adds r7, #16
|
|
8004054: 46bd mov sp, r7
|
|
8004056: bd80 pop {r7, pc}
|
|
8004058: 40002800 .word 0x40002800
|
|
|
|
0800405c <HAL_RTC_SetAlarm_IT>:
|
|
* @arg RTC_FORMAT_BIN: Binary format
|
|
* @arg RTC_FORMAT_BCD: BCD format
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
|
|
{
|
|
800405c: b590 push {r4, r7, lr}
|
|
800405e: b087 sub sp, #28
|
|
8004060: af00 add r7, sp, #0
|
|
8004062: 60f8 str r0, [r7, #12]
|
|
8004064: 60b9 str r1, [r7, #8]
|
|
8004066: 607a str r2, [r7, #4]
|
|
uint32_t tmpreg = 0;
|
|
8004068: 2300 movs r3, #0
|
|
800406a: 617b str r3, [r7, #20]
|
|
uint32_t binaryMode;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800406c: 68fb ldr r3, [r7, #12]
|
|
800406e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
8004072: 2b01 cmp r3, #1
|
|
8004074: d101 bne.n 800407a <HAL_RTC_SetAlarm_IT+0x1e>
|
|
8004076: 2302 movs r3, #2
|
|
8004078: e0f3 b.n 8004262 <HAL_RTC_SetAlarm_IT+0x206>
|
|
800407a: 68fb ldr r3, [r7, #12]
|
|
800407c: 2201 movs r2, #1
|
|
800407e: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8004082: 68fb ldr r3, [r7, #12]
|
|
8004084: 2202 movs r2, #2
|
|
8004086: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos)));
|
|
}
|
|
#endif /* USE_FULL_ASSERT */
|
|
|
|
/* Get Binary mode (32-bit free-running counter configuration) */
|
|
binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN);
|
|
800408a: 4b78 ldr r3, [pc, #480] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800408c: 68db ldr r3, [r3, #12]
|
|
800408e: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004092: 613b str r3, [r7, #16]
|
|
|
|
if (binaryMode != RTC_BINARY_ONLY)
|
|
8004094: 693b ldr r3, [r7, #16]
|
|
8004096: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
800409a: d06a beq.n 8004172 <HAL_RTC_SetAlarm_IT+0x116>
|
|
{
|
|
if (Format == RTC_FORMAT_BIN)
|
|
800409c: 687b ldr r3, [r7, #4]
|
|
800409e: 2b00 cmp r3, #0
|
|
80040a0: d13a bne.n 8004118 <HAL_RTC_SetAlarm_IT+0xbc>
|
|
{
|
|
if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
|
|
80040a2: 4b72 ldr r3, [pc, #456] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80040a4: 699b ldr r3, [r3, #24]
|
|
80040a6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80040aa: 2b00 cmp r3, #0
|
|
80040ac: d102 bne.n 80040b4 <HAL_RTC_SetAlarm_IT+0x58>
|
|
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
|
|
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sAlarm->AlarmTime.TimeFormat = 0x00U;
|
|
80040ae: 68bb ldr r3, [r7, #8]
|
|
80040b0: 2200 movs r2, #0
|
|
80040b2: 70da strb r2, [r3, #3]
|
|
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
|
|
}
|
|
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
|
|
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
|
|
|
|
if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY)
|
|
80040b4: 68bb ldr r3, [r7, #8]
|
|
80040b6: 695b ldr r3, [r3, #20]
|
|
80040b8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
{
|
|
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
|
|
}
|
|
}
|
|
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
80040bc: 68bb ldr r3, [r7, #8]
|
|
80040be: 781b ldrb r3, [r3, #0]
|
|
80040c0: 4618 mov r0, r3
|
|
80040c2: f000 f9f5 bl 80044b0 <RTC_ByteToBcd2>
|
|
80040c6: 4603 mov r3, r0
|
|
80040c8: 041c lsls r4, r3, #16
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
|
|
80040ca: 68bb ldr r3, [r7, #8]
|
|
80040cc: 785b ldrb r3, [r3, #1]
|
|
80040ce: 4618 mov r0, r3
|
|
80040d0: f000 f9ee bl 80044b0 <RTC_ByteToBcd2>
|
|
80040d4: 4603 mov r3, r0
|
|
80040d6: 021b lsls r3, r3, #8
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
80040d8: 431c orrs r4, r3
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
|
|
80040da: 68bb ldr r3, [r7, #8]
|
|
80040dc: 789b ldrb r3, [r3, #2]
|
|
80040de: 4618 mov r0, r3
|
|
80040e0: f000 f9e6 bl 80044b0 <RTC_ByteToBcd2>
|
|
80040e4: 4603 mov r3, r0
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
|
|
80040e6: ea44 0203 orr.w r2, r4, r3
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
|
|
80040ea: 68bb ldr r3, [r7, #8]
|
|
80040ec: 78db ldrb r3, [r3, #3]
|
|
80040ee: 059b lsls r3, r3, #22
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
|
|
80040f0: ea42 0403 orr.w r4, r2, r3
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
|
|
80040f4: 68bb ldr r3, [r7, #8]
|
|
80040f6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
80040fa: 4618 mov r0, r3
|
|
80040fc: f000 f9d8 bl 80044b0 <RTC_ByteToBcd2>
|
|
8004100: 4603 mov r3, r0
|
|
8004102: 061b lsls r3, r3, #24
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
|
|
8004104: ea44 0203 orr.w r2, r4, r3
|
|
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
|
|
8004108: 68bb ldr r3, [r7, #8]
|
|
800410a: 6a1b ldr r3, [r3, #32]
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
|
|
800410c: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmMask));
|
|
800410e: 68bb ldr r3, [r7, #8]
|
|
8004110: 695b ldr r3, [r3, #20]
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
8004112: 4313 orrs r3, r2
|
|
8004114: 617b str r3, [r7, #20]
|
|
8004116: e02c b.n 8004172 <HAL_RTC_SetAlarm_IT+0x116>
|
|
}
|
|
else /* Format BCD */
|
|
{
|
|
if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL)
|
|
8004118: 68bb ldr r3, [r7, #8]
|
|
800411a: 695b ldr r3, [r3, #20]
|
|
800411c: f1b3 3f80 cmp.w r3, #2155905152 @ 0x80808080
|
|
8004120: d00d beq.n 800413e <HAL_RTC_SetAlarm_IT+0xe2>
|
|
{
|
|
if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS)
|
|
8004122: 68bb ldr r3, [r7, #8]
|
|
8004124: 695b ldr r3, [r3, #20]
|
|
8004126: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
800412a: d008 beq.n 800413e <HAL_RTC_SetAlarm_IT+0xe2>
|
|
{
|
|
if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
|
|
800412c: 4b4f ldr r3, [pc, #316] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800412e: 699b ldr r3, [r3, #24]
|
|
8004130: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004134: 2b00 cmp r3, #0
|
|
8004136: d102 bne.n 800413e <HAL_RTC_SetAlarm_IT+0xe2>
|
|
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
|
|
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sAlarm->AlarmTime.TimeFormat = 0x00U;
|
|
8004138: 68bb ldr r3, [r7, #8]
|
|
800413a: 2200 movs r2, #0
|
|
800413c: 70da strb r2, [r3, #3]
|
|
{
|
|
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
|
|
}
|
|
}
|
|
#endif /* USE_FULL_ASSERT */
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
800413e: 68bb ldr r3, [r7, #8]
|
|
8004140: 781b ldrb r3, [r3, #0]
|
|
8004142: 041a lsls r2, r3, #16
|
|
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
|
|
8004144: 68bb ldr r3, [r7, #8]
|
|
8004146: 785b ldrb r3, [r3, #1]
|
|
8004148: 021b lsls r3, r3, #8
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
800414a: 4313 orrs r3, r2
|
|
((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
|
|
800414c: 68ba ldr r2, [r7, #8]
|
|
800414e: 7892 ldrb r2, [r2, #2]
|
|
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
|
|
8004150: 431a orrs r2, r3
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
|
|
8004152: 68bb ldr r3, [r7, #8]
|
|
8004154: 78db ldrb r3, [r3, #3]
|
|
8004156: 059b lsls r3, r3, #22
|
|
((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
|
|
8004158: 431a orrs r2, r3
|
|
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
|
|
800415a: 68bb ldr r3, [r7, #8]
|
|
800415c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8004160: 061b lsls r3, r3, #24
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
|
|
8004162: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
|
|
8004164: 68bb ldr r3, [r7, #8]
|
|
8004166: 6a1b ldr r3, [r3, #32]
|
|
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
|
|
8004168: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmMask));
|
|
800416a: 68bb ldr r3, [r7, #8]
|
|
800416c: 695b ldr r3, [r3, #20]
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
|
|
800416e: 4313 orrs r3, r2
|
|
8004170: 617b str r3, [r7, #20]
|
|
|
|
}
|
|
}
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8004172: 4b3e ldr r3, [pc, #248] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004174: 22ca movs r2, #202 @ 0xca
|
|
8004176: 625a str r2, [r3, #36] @ 0x24
|
|
8004178: 4b3c ldr r3, [pc, #240] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800417a: 2253 movs r2, #83 @ 0x53
|
|
800417c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Configure the Alarm register */
|
|
if (sAlarm->Alarm == RTC_ALARM_A)
|
|
800417e: 68bb ldr r3, [r7, #8]
|
|
8004180: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004182: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8004186: d12c bne.n 80041e2 <HAL_RTC_SetAlarm_IT+0x186>
|
|
{
|
|
/* Disable the Alarm A interrupt */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
|
|
8004188: 4b38 ldr r3, [pc, #224] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800418a: 699b ldr r3, [r3, #24]
|
|
800418c: 4a37 ldr r2, [pc, #220] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800418e: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
8004192: 6193 str r3, [r2, #24]
|
|
/* Clear flag alarm A */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
|
|
8004194: 4b35 ldr r3, [pc, #212] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004196: 2201 movs r2, #1
|
|
8004198: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
if (binaryMode == RTC_BINARY_ONLY)
|
|
800419a: 693b ldr r3, [r7, #16]
|
|
800419c: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80041a0: d107 bne.n 80041b2 <HAL_RTC_SetAlarm_IT+0x156>
|
|
{
|
|
RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr;
|
|
80041a2: 68bb ldr r3, [r7, #8]
|
|
80041a4: 699a ldr r2, [r3, #24]
|
|
80041a6: 68bb ldr r3, [r7, #8]
|
|
80041a8: 69db ldr r3, [r3, #28]
|
|
80041aa: 4930 ldr r1, [pc, #192] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041ac: 4313 orrs r3, r2
|
|
80041ae: 644b str r3, [r1, #68] @ 0x44
|
|
80041b0: e006 b.n 80041c0 <HAL_RTC_SetAlarm_IT+0x164>
|
|
}
|
|
else
|
|
{
|
|
WRITE_REG(RTC->ALRMAR, tmpreg);
|
|
80041b2: 4a2e ldr r2, [pc, #184] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041b4: 697b ldr r3, [r7, #20]
|
|
80041b6: 6413 str r3, [r2, #64] @ 0x40
|
|
WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask);
|
|
80041b8: 4a2c ldr r2, [pc, #176] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041ba: 68bb ldr r3, [r7, #8]
|
|
80041bc: 699b ldr r3, [r3, #24]
|
|
80041be: 6453 str r3, [r2, #68] @ 0x44
|
|
}
|
|
|
|
WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds);
|
|
80041c0: 4a2a ldr r2, [pc, #168] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041c2: 68bb ldr r3, [r7, #8]
|
|
80041c4: 685b ldr r3, [r3, #4]
|
|
80041c6: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Store in the handle the Alarm A enabled */
|
|
SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF);
|
|
80041c8: 68fb ldr r3, [r7, #12]
|
|
80041ca: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80041cc: f043 0201 orr.w r2, r3, #1
|
|
80041d0: 68fb ldr r3, [r7, #12]
|
|
80041d2: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Configure the Alarm interrupt */
|
|
SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
|
|
80041d4: 4b25 ldr r3, [pc, #148] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041d6: 699b ldr r3, [r3, #24]
|
|
80041d8: 4a24 ldr r2, [pc, #144] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041da: f443 5388 orr.w r3, r3, #4352 @ 0x1100
|
|
80041de: 6193 str r3, [r2, #24]
|
|
80041e0: e02b b.n 800423a <HAL_RTC_SetAlarm_IT+0x1de>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Alarm B interrupt */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
|
|
80041e2: 4b22 ldr r3, [pc, #136] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041e4: 699b ldr r3, [r3, #24]
|
|
80041e6: 4a21 ldr r2, [pc, #132] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041e8: f423 5308 bic.w r3, r3, #8704 @ 0x2200
|
|
80041ec: 6193 str r3, [r2, #24]
|
|
/* Clear flag alarm B */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
|
|
80041ee: 4b1f ldr r3, [pc, #124] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
80041f0: 2202 movs r2, #2
|
|
80041f2: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
if (binaryMode == RTC_BINARY_ONLY)
|
|
80041f4: 693b ldr r3, [r7, #16]
|
|
80041f6: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80041fa: d107 bne.n 800420c <HAL_RTC_SetAlarm_IT+0x1b0>
|
|
{
|
|
WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
|
|
80041fc: 68bb ldr r3, [r7, #8]
|
|
80041fe: 699a ldr r2, [r3, #24]
|
|
8004200: 68bb ldr r3, [r7, #8]
|
|
8004202: 69db ldr r3, [r3, #28]
|
|
8004204: 4919 ldr r1, [pc, #100] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004206: 4313 orrs r3, r2
|
|
8004208: 64cb str r3, [r1, #76] @ 0x4c
|
|
800420a: e006 b.n 800421a <HAL_RTC_SetAlarm_IT+0x1be>
|
|
}
|
|
else
|
|
{
|
|
WRITE_REG(RTC->ALRMBR, tmpreg);
|
|
800420c: 4a17 ldr r2, [pc, #92] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800420e: 697b ldr r3, [r7, #20]
|
|
8004210: 6493 str r3, [r2, #72] @ 0x48
|
|
WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask);
|
|
8004212: 4a16 ldr r2, [pc, #88] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004214: 68bb ldr r3, [r7, #8]
|
|
8004216: 699b ldr r3, [r3, #24]
|
|
8004218: 64d3 str r3, [r2, #76] @ 0x4c
|
|
}
|
|
|
|
WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds);
|
|
800421a: 4a14 ldr r2, [pc, #80] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800421c: 68bb ldr r3, [r7, #8]
|
|
800421e: 685b ldr r3, [r3, #4]
|
|
8004220: 6753 str r3, [r2, #116] @ 0x74
|
|
|
|
/* Store in the handle the Alarm B enabled */
|
|
SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF);
|
|
8004222: 68fb ldr r3, [r7, #12]
|
|
8004224: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004226: f043 0202 orr.w r2, r3, #2
|
|
800422a: 68fb ldr r3, [r7, #12]
|
|
800422c: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Configure the Alarm interrupt */
|
|
SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
|
|
800422e: 4b0f ldr r3, [pc, #60] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004230: 699b ldr r3, [r3, #24]
|
|
8004232: 4a0e ldr r2, [pc, #56] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
8004234: f443 5308 orr.w r3, r3, #8704 @ 0x2200
|
|
8004238: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
/* RTC Alarm Interrupt Configuration: EXTI configuration */
|
|
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
|
|
800423a: 4b0d ldr r3, [pc, #52] @ (8004270 <HAL_RTC_SetAlarm_IT+0x214>)
|
|
800423c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8004240: 4a0b ldr r2, [pc, #44] @ (8004270 <HAL_RTC_SetAlarm_IT+0x214>)
|
|
8004242: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8004246: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800424a: 4b08 ldr r3, [pc, #32] @ (800426c <HAL_RTC_SetAlarm_IT+0x210>)
|
|
800424c: 22ff movs r2, #255 @ 0xff
|
|
800424e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8004250: 68fb ldr r3, [r7, #12]
|
|
8004252: 2201 movs r2, #1
|
|
8004254: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
8004258: 68fb ldr r3, [r7, #12]
|
|
800425a: 2200 movs r2, #0
|
|
800425c: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
8004260: 2300 movs r3, #0
|
|
}
|
|
8004262: 4618 mov r0, r3
|
|
8004264: 371c adds r7, #28
|
|
8004266: 46bd mov sp, r7
|
|
8004268: bd90 pop {r4, r7, pc}
|
|
800426a: bf00 nop
|
|
800426c: 40002800 .word 0x40002800
|
|
8004270: 58000800 .word 0x58000800
|
|
|
|
08004274 <HAL_RTC_DeactivateAlarm>:
|
|
* @arg RTC_ALARM_A: AlarmA
|
|
* @arg RTC_ALARM_B: AlarmB
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
|
|
{
|
|
8004274: b480 push {r7}
|
|
8004276: b083 sub sp, #12
|
|
8004278: af00 add r7, sp, #0
|
|
800427a: 6078 str r0, [r7, #4]
|
|
800427c: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_ALARM(Alarm));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800427e: 687b ldr r3, [r7, #4]
|
|
8004280: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
8004284: 2b01 cmp r3, #1
|
|
8004286: d101 bne.n 800428c <HAL_RTC_DeactivateAlarm+0x18>
|
|
8004288: 2302 movs r3, #2
|
|
800428a: e048 b.n 800431e <HAL_RTC_DeactivateAlarm+0xaa>
|
|
800428c: 687b ldr r3, [r7, #4]
|
|
800428e: 2201 movs r2, #1
|
|
8004290: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8004294: 687b ldr r3, [r7, #4]
|
|
8004296: 2202 movs r2, #2
|
|
8004298: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800429c: 4b22 ldr r3, [pc, #136] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
800429e: 22ca movs r2, #202 @ 0xca
|
|
80042a0: 625a str r2, [r3, #36] @ 0x24
|
|
80042a2: 4b21 ldr r3, [pc, #132] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042a4: 2253 movs r2, #83 @ 0x53
|
|
80042a6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
if (Alarm == RTC_ALARM_A)
|
|
80042a8: 683b ldr r3, [r7, #0]
|
|
80042aa: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80042ae: d115 bne.n 80042dc <HAL_RTC_DeactivateAlarm+0x68>
|
|
{
|
|
/* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
|
|
80042b0: 4b1d ldr r3, [pc, #116] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042b2: 699b ldr r3, [r3, #24]
|
|
80042b4: 4a1c ldr r2, [pc, #112] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042b6: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
80042ba: 6193 str r3, [r2, #24]
|
|
|
|
/* AlarmA, Clear SSCLR */
|
|
CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR);
|
|
80042bc: 4b1a ldr r3, [pc, #104] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042be: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80042c0: 4a19 ldr r2, [pc, #100] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042c2: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80042c6: 6453 str r3, [r2, #68] @ 0x44
|
|
|
|
/* Store in the handle the Alarm A disabled */
|
|
CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF);
|
|
80042c8: 687b ldr r3, [r7, #4]
|
|
80042ca: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80042cc: f023 0201 bic.w r2, r3, #1
|
|
80042d0: 687b ldr r3, [r7, #4]
|
|
80042d2: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Clear AlarmA flag */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
|
|
80042d4: 4b14 ldr r3, [pc, #80] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042d6: 2201 movs r2, #1
|
|
80042d8: 65da str r2, [r3, #92] @ 0x5c
|
|
80042da: e014 b.n 8004306 <HAL_RTC_DeactivateAlarm+0x92>
|
|
}
|
|
else
|
|
{
|
|
/* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
|
|
80042dc: 4b12 ldr r3, [pc, #72] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042de: 699b ldr r3, [r3, #24]
|
|
80042e0: 4a11 ldr r2, [pc, #68] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042e2: f423 5308 bic.w r3, r3, #8704 @ 0x2200
|
|
80042e6: 6193 str r3, [r2, #24]
|
|
|
|
/* AlarmB, Clear SSCLR */
|
|
CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR);
|
|
80042e8: 4b0f ldr r3, [pc, #60] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042ea: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80042ec: 4a0e ldr r2, [pc, #56] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
80042ee: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80042f2: 64d3 str r3, [r2, #76] @ 0x4c
|
|
|
|
/* Store in the handle the Alarm B disabled */
|
|
CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF);
|
|
80042f4: 687b ldr r3, [r7, #4]
|
|
80042f6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80042f8: f023 0202 bic.w r2, r3, #2
|
|
80042fc: 687b ldr r3, [r7, #4]
|
|
80042fe: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Clear AlarmB flag */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
|
|
8004300: 4b09 ldr r3, [pc, #36] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
8004302: 2202 movs r2, #2
|
|
8004304: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
8004306: 4b08 ldr r3, [pc, #32] @ (8004328 <HAL_RTC_DeactivateAlarm+0xb4>)
|
|
8004308: 22ff movs r2, #255 @ 0xff
|
|
800430a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800430c: 687b ldr r3, [r7, #4]
|
|
800430e: 2201 movs r2, #1
|
|
8004310: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
8004314: 687b ldr r3, [r7, #4]
|
|
8004316: 2200 movs r2, #0
|
|
8004318: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
800431c: 2300 movs r3, #0
|
|
}
|
|
800431e: 4618 mov r0, r3
|
|
8004320: 370c adds r7, #12
|
|
8004322: 46bd mov sp, r7
|
|
8004324: bc80 pop {r7}
|
|
8004326: 4770 bx lr
|
|
8004328: 40002800 .word 0x40002800
|
|
|
|
0800432c <HAL_RTC_AlarmIRQHandler>:
|
|
* @brief Handle Alarm interrupt request.
|
|
* @param hrtc RTC handle
|
|
* @retval None
|
|
*/
|
|
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800432c: b580 push {r7, lr}
|
|
800432e: b084 sub sp, #16
|
|
8004330: af00 add r7, sp, #0
|
|
8004332: 6078 str r0, [r7, #4]
|
|
uint32_t tmp = READ_REG(RTC->MISR) & READ_REG(hrtc->IsEnabled.RtcFeatures);
|
|
8004334: 4b11 ldr r3, [pc, #68] @ (800437c <HAL_RTC_AlarmIRQHandler+0x50>)
|
|
8004336: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
8004338: 687b ldr r3, [r7, #4]
|
|
800433a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800433c: 4013 ands r3, r2
|
|
800433e: 60fb str r3, [r7, #12]
|
|
|
|
if ((tmp & RTC_MISR_ALRAMF) != 0U)
|
|
8004340: 68fb ldr r3, [r7, #12]
|
|
8004342: f003 0301 and.w r3, r3, #1
|
|
8004346: 2b00 cmp r3, #0
|
|
8004348: d005 beq.n 8004356 <HAL_RTC_AlarmIRQHandler+0x2a>
|
|
{
|
|
/* Clear the AlarmA interrupt pending bit */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
|
|
800434a: 4b0c ldr r3, [pc, #48] @ (800437c <HAL_RTC_AlarmIRQHandler+0x50>)
|
|
800434c: 2201 movs r2, #1
|
|
800434e: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
/* Call Compare Match registered Callback */
|
|
hrtc->AlarmAEventCallback(hrtc);
|
|
#else
|
|
HAL_RTC_AlarmAEventCallback(hrtc);
|
|
8004350: 6878 ldr r0, [r7, #4]
|
|
8004352: f7fc fe06 bl 8000f62 <HAL_RTC_AlarmAEventCallback>
|
|
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
if ((tmp & RTC_MISR_ALRBMF) != 0U)
|
|
8004356: 68fb ldr r3, [r7, #12]
|
|
8004358: f003 0302 and.w r3, r3, #2
|
|
800435c: 2b00 cmp r3, #0
|
|
800435e: d005 beq.n 800436c <HAL_RTC_AlarmIRQHandler+0x40>
|
|
{
|
|
/* Clear the AlarmB interrupt pending bit */
|
|
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
|
|
8004360: 4b06 ldr r3, [pc, #24] @ (800437c <HAL_RTC_AlarmIRQHandler+0x50>)
|
|
8004362: 2202 movs r2, #2
|
|
8004364: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
/* Call Compare Match registered Callback */
|
|
hrtc->AlarmBEventCallback(hrtc);
|
|
#else
|
|
HAL_RTCEx_AlarmBEventCallback(hrtc);
|
|
8004366: 6878 ldr r0, [r7, #4]
|
|
8004368: f000 f94a bl 8004600 <HAL_RTCEx_AlarmBEventCallback>
|
|
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800436c: 687b ldr r3, [r7, #4]
|
|
800436e: 2201 movs r2, #1
|
|
8004370: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
}
|
|
8004374: bf00 nop
|
|
8004376: 3710 adds r7, #16
|
|
8004378: 46bd mov sp, r7
|
|
800437a: bd80 pop {r7, pc}
|
|
800437c: 40002800 .word 0x40002800
|
|
|
|
08004380 <HAL_RTC_WaitForSynchro>:
|
|
* correctly copied into the RTC_TR and RTC_DR shadow registers.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8004380: b580 push {r7, lr}
|
|
8004382: b084 sub sp, #16
|
|
8004384: af00 add r7, sp, #0
|
|
8004386: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
UNUSED(hrtc);
|
|
/* Clear RSF flag */
|
|
CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
|
|
8004388: 4b0f ldr r3, [pc, #60] @ (80043c8 <HAL_RTC_WaitForSynchro+0x48>)
|
|
800438a: 68db ldr r3, [r3, #12]
|
|
800438c: 4a0e ldr r2, [pc, #56] @ (80043c8 <HAL_RTC_WaitForSynchro+0x48>)
|
|
800438e: f023 0320 bic.w r3, r3, #32
|
|
8004392: 60d3 str r3, [r2, #12]
|
|
|
|
tickstart = HAL_GetTick();
|
|
8004394: f7fc fbf4 bl 8000b80 <HAL_GetTick>
|
|
8004398: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait the registers to be synchronised */
|
|
while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
|
|
800439a: e009 b.n 80043b0 <HAL_RTC_WaitForSynchro+0x30>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
800439c: f7fc fbf0 bl 8000b80 <HAL_GetTick>
|
|
80043a0: 4602 mov r2, r0
|
|
80043a2: 68fb ldr r3, [r7, #12]
|
|
80043a4: 1ad3 subs r3, r2, r3
|
|
80043a6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
80043aa: d901 bls.n 80043b0 <HAL_RTC_WaitForSynchro+0x30>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80043ac: 2303 movs r3, #3
|
|
80043ae: e006 b.n 80043be <HAL_RTC_WaitForSynchro+0x3e>
|
|
while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
|
|
80043b0: 4b05 ldr r3, [pc, #20] @ (80043c8 <HAL_RTC_WaitForSynchro+0x48>)
|
|
80043b2: 68db ldr r3, [r3, #12]
|
|
80043b4: f003 0320 and.w r3, r3, #32
|
|
80043b8: 2b00 cmp r3, #0
|
|
80043ba: d0ef beq.n 800439c <HAL_RTC_WaitForSynchro+0x1c>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80043bc: 2300 movs r3, #0
|
|
}
|
|
80043be: 4618 mov r0, r3
|
|
80043c0: 3710 adds r7, #16
|
|
80043c2: 46bd mov sp, r7
|
|
80043c4: bd80 pop {r7, pc}
|
|
80043c6: bf00 nop
|
|
80043c8: 40002800 .word 0x40002800
|
|
|
|
080043cc <RTC_EnterInitMode>:
|
|
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
80043cc: b580 push {r7, lr}
|
|
80043ce: b084 sub sp, #16
|
|
80043d0: af00 add r7, sp, #0
|
|
80043d2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80043d4: 2300 movs r3, #0
|
|
80043d6: 73fb strb r3, [r7, #15]
|
|
|
|
UNUSED(hrtc);
|
|
/* Check if the Initialization mode is set */
|
|
if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
|
|
80043d8: 4b15 ldr r3, [pc, #84] @ (8004430 <RTC_EnterInitMode+0x64>)
|
|
80043da: 68db ldr r3, [r3, #12]
|
|
80043dc: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80043e0: 2b00 cmp r3, #0
|
|
80043e2: d120 bne.n 8004426 <RTC_EnterInitMode+0x5a>
|
|
{
|
|
/* Set the Initialization mode */
|
|
SET_BIT(RTC->ICSR, RTC_ICSR_INIT);
|
|
80043e4: 4b12 ldr r3, [pc, #72] @ (8004430 <RTC_EnterInitMode+0x64>)
|
|
80043e6: 68db ldr r3, [r3, #12]
|
|
80043e8: 4a11 ldr r2, [pc, #68] @ (8004430 <RTC_EnterInitMode+0x64>)
|
|
80043ea: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80043ee: 60d3 str r3, [r2, #12]
|
|
|
|
tickstart = HAL_GetTick();
|
|
80043f0: f7fc fbc6 bl 8000b80 <HAL_GetTick>
|
|
80043f4: 60b8 str r0, [r7, #8]
|
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
|
while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
|
|
80043f6: e00d b.n 8004414 <RTC_EnterInitMode+0x48>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
80043f8: f7fc fbc2 bl 8000b80 <HAL_GetTick>
|
|
80043fc: 4602 mov r2, r0
|
|
80043fe: 68bb ldr r3, [r7, #8]
|
|
8004400: 1ad3 subs r3, r2, r3
|
|
8004402: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8004406: d905 bls.n 8004414 <RTC_EnterInitMode+0x48>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8004408: 2303 movs r3, #3
|
|
800440a: 73fb strb r3, [r7, #15]
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800440c: 687b ldr r3, [r7, #4]
|
|
800440e: 2203 movs r2, #3
|
|
8004410: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
|
|
8004414: 4b06 ldr r3, [pc, #24] @ (8004430 <RTC_EnterInitMode+0x64>)
|
|
8004416: 68db ldr r3, [r3, #12]
|
|
8004418: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800441c: 2b00 cmp r3, #0
|
|
800441e: d102 bne.n 8004426 <RTC_EnterInitMode+0x5a>
|
|
8004420: 7bfb ldrb r3, [r7, #15]
|
|
8004422: 2b03 cmp r3, #3
|
|
8004424: d1e8 bne.n 80043f8 <RTC_EnterInitMode+0x2c>
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8004426: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004428: 4618 mov r0, r3
|
|
800442a: 3710 adds r7, #16
|
|
800442c: 46bd mov sp, r7
|
|
800442e: bd80 pop {r7, pc}
|
|
8004430: 40002800 .word 0x40002800
|
|
|
|
08004434 <RTC_ExitInitMode>:
|
|
* @brief Exit the RTC Initialization mode.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8004434: b580 push {r7, lr}
|
|
8004436: b084 sub sp, #16
|
|
8004438: af00 add r7, sp, #0
|
|
800443a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800443c: 2300 movs r3, #0
|
|
800443e: 73fb strb r3, [r7, #15]
|
|
|
|
/* Exit Initialization mode */
|
|
CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
|
|
8004440: 4b1a ldr r3, [pc, #104] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
8004442: 68db ldr r3, [r3, #12]
|
|
8004444: 4a19 ldr r2, [pc, #100] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
8004446: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800444a: 60d3 str r3, [r2, #12]
|
|
|
|
/* If CR_BYPSHAD bit = 0, wait for synchro */
|
|
if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
|
|
800444c: 4b17 ldr r3, [pc, #92] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
800444e: 699b ldr r3, [r3, #24]
|
|
8004450: f003 0320 and.w r3, r3, #32
|
|
8004454: 2b00 cmp r3, #0
|
|
8004456: d10c bne.n 8004472 <RTC_ExitInitMode+0x3e>
|
|
{
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
8004458: 6878 ldr r0, [r7, #4]
|
|
800445a: f7ff ff91 bl 8004380 <HAL_RTC_WaitForSynchro>
|
|
800445e: 4603 mov r3, r0
|
|
8004460: 2b00 cmp r3, #0
|
|
8004462: d01e beq.n 80044a2 <RTC_ExitInitMode+0x6e>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
8004464: 687b ldr r3, [r7, #4]
|
|
8004466: 2203 movs r2, #3
|
|
8004468: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
status = HAL_TIMEOUT;
|
|
800446c: 2303 movs r3, #3
|
|
800446e: 73fb strb r3, [r7, #15]
|
|
8004470: e017 b.n 80044a2 <RTC_ExitInitMode+0x6e>
|
|
}
|
|
}
|
|
else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */
|
|
{
|
|
/* Clear BYPSHAD bit */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8004472: 4b0e ldr r3, [pc, #56] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
8004474: 699b ldr r3, [r3, #24]
|
|
8004476: 4a0d ldr r2, [pc, #52] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
8004478: f023 0320 bic.w r3, r3, #32
|
|
800447c: 6193 str r3, [r2, #24]
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
800447e: 6878 ldr r0, [r7, #4]
|
|
8004480: f7ff ff7e bl 8004380 <HAL_RTC_WaitForSynchro>
|
|
8004484: 4603 mov r3, r0
|
|
8004486: 2b00 cmp r3, #0
|
|
8004488: d005 beq.n 8004496 <RTC_ExitInitMode+0x62>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800448a: 687b ldr r3, [r7, #4]
|
|
800448c: 2203 movs r2, #3
|
|
800448e: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
status = HAL_TIMEOUT;
|
|
8004492: 2303 movs r3, #3
|
|
8004494: 73fb strb r3, [r7, #15]
|
|
}
|
|
/* Restore BYPSHAD bit */
|
|
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8004496: 4b05 ldr r3, [pc, #20] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
8004498: 699b ldr r3, [r3, #24]
|
|
800449a: 4a04 ldr r2, [pc, #16] @ (80044ac <RTC_ExitInitMode+0x78>)
|
|
800449c: f043 0320 orr.w r3, r3, #32
|
|
80044a0: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return status;
|
|
80044a2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80044a4: 4618 mov r0, r3
|
|
80044a6: 3710 adds r7, #16
|
|
80044a8: 46bd mov sp, r7
|
|
80044aa: bd80 pop {r7, pc}
|
|
80044ac: 40002800 .word 0x40002800
|
|
|
|
080044b0 <RTC_ByteToBcd2>:
|
|
* @brief Convert a 2 digit decimal to BCD format.
|
|
* @param Value Byte to be converted
|
|
* @retval Converted byte
|
|
*/
|
|
uint8_t RTC_ByteToBcd2(uint8_t Value)
|
|
{
|
|
80044b0: b480 push {r7}
|
|
80044b2: b085 sub sp, #20
|
|
80044b4: af00 add r7, sp, #0
|
|
80044b6: 4603 mov r3, r0
|
|
80044b8: 71fb strb r3, [r7, #7]
|
|
uint32_t bcdhigh = 0U;
|
|
80044ba: 2300 movs r3, #0
|
|
80044bc: 60fb str r3, [r7, #12]
|
|
uint8_t tmp_Value = Value;
|
|
80044be: 79fb ldrb r3, [r7, #7]
|
|
80044c0: 72fb strb r3, [r7, #11]
|
|
|
|
while (tmp_Value >= 10U)
|
|
80044c2: e005 b.n 80044d0 <RTC_ByteToBcd2+0x20>
|
|
{
|
|
bcdhigh++;
|
|
80044c4: 68fb ldr r3, [r7, #12]
|
|
80044c6: 3301 adds r3, #1
|
|
80044c8: 60fb str r3, [r7, #12]
|
|
tmp_Value -= 10U;
|
|
80044ca: 7afb ldrb r3, [r7, #11]
|
|
80044cc: 3b0a subs r3, #10
|
|
80044ce: 72fb strb r3, [r7, #11]
|
|
while (tmp_Value >= 10U)
|
|
80044d0: 7afb ldrb r3, [r7, #11]
|
|
80044d2: 2b09 cmp r3, #9
|
|
80044d4: d8f6 bhi.n 80044c4 <RTC_ByteToBcd2+0x14>
|
|
}
|
|
|
|
return ((uint8_t)(bcdhigh << 4U) | tmp_Value);
|
|
80044d6: 68fb ldr r3, [r7, #12]
|
|
80044d8: b2db uxtb r3, r3
|
|
80044da: 011b lsls r3, r3, #4
|
|
80044dc: b2da uxtb r2, r3
|
|
80044de: 7afb ldrb r3, [r7, #11]
|
|
80044e0: 4313 orrs r3, r2
|
|
80044e2: b2db uxtb r3, r3
|
|
}
|
|
80044e4: 4618 mov r0, r3
|
|
80044e6: 3714 adds r7, #20
|
|
80044e8: 46bd mov sp, r7
|
|
80044ea: bc80 pop {r7}
|
|
80044ec: 4770 bx lr
|
|
...
|
|
|
|
080044f0 <HAL_RTCEx_EnableBypassShadow>:
|
|
* directly from the Calendar counter.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
80044f0: b480 push {r7}
|
|
80044f2: b083 sub sp, #12
|
|
80044f4: af00 add r7, sp, #0
|
|
80044f6: 6078 str r0, [r7, #4]
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
80044f8: 687b ldr r3, [r7, #4]
|
|
80044fa: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
80044fe: 2b01 cmp r3, #1
|
|
8004500: d101 bne.n 8004506 <HAL_RTCEx_EnableBypassShadow+0x16>
|
|
8004502: 2302 movs r3, #2
|
|
8004504: e01f b.n 8004546 <HAL_RTCEx_EnableBypassShadow+0x56>
|
|
8004506: 687b ldr r3, [r7, #4]
|
|
8004508: 2201 movs r2, #1
|
|
800450a: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800450e: 687b ldr r3, [r7, #4]
|
|
8004510: 2202 movs r2, #2
|
|
8004512: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8004516: 4b0e ldr r3, [pc, #56] @ (8004550 <HAL_RTCEx_EnableBypassShadow+0x60>)
|
|
8004518: 22ca movs r2, #202 @ 0xca
|
|
800451a: 625a str r2, [r3, #36] @ 0x24
|
|
800451c: 4b0c ldr r3, [pc, #48] @ (8004550 <HAL_RTCEx_EnableBypassShadow+0x60>)
|
|
800451e: 2253 movs r2, #83 @ 0x53
|
|
8004520: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Set the BYPSHAD bit */
|
|
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8004522: 4b0b ldr r3, [pc, #44] @ (8004550 <HAL_RTCEx_EnableBypassShadow+0x60>)
|
|
8004524: 699b ldr r3, [r3, #24]
|
|
8004526: 4a0a ldr r2, [pc, #40] @ (8004550 <HAL_RTCEx_EnableBypassShadow+0x60>)
|
|
8004528: f043 0320 orr.w r3, r3, #32
|
|
800452c: 6193 str r3, [r2, #24]
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800452e: 4b08 ldr r3, [pc, #32] @ (8004550 <HAL_RTCEx_EnableBypassShadow+0x60>)
|
|
8004530: 22ff movs r2, #255 @ 0xff
|
|
8004532: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8004534: 687b ldr r3, [r7, #4]
|
|
8004536: 2201 movs r2, #1
|
|
8004538: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800453c: 687b ldr r3, [r7, #4]
|
|
800453e: 2200 movs r2, #0
|
|
8004540: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
8004544: 2300 movs r3, #0
|
|
}
|
|
8004546: 4618 mov r0, r3
|
|
8004548: 370c adds r7, #12
|
|
800454a: 46bd mov sp, r7
|
|
800454c: bc80 pop {r7}
|
|
800454e: 4770 bx lr
|
|
8004550: 40002800 .word 0x40002800
|
|
|
|
08004554 <HAL_RTCEx_SetSSRU_IT>:
|
|
* @brief Set SSR Underflow detection with Interrupt.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8004554: b480 push {r7}
|
|
8004556: b083 sub sp, #12
|
|
8004558: af00 add r7, sp, #0
|
|
800455a: 6078 str r0, [r7, #4]
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800455c: 687b ldr r3, [r7, #4]
|
|
800455e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
8004562: 2b01 cmp r3, #1
|
|
8004564: d101 bne.n 800456a <HAL_RTCEx_SetSSRU_IT+0x16>
|
|
8004566: 2302 movs r3, #2
|
|
8004568: e027 b.n 80045ba <HAL_RTCEx_SetSSRU_IT+0x66>
|
|
800456a: 687b ldr r3, [r7, #4]
|
|
800456c: 2201 movs r2, #1
|
|
800456e: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8004572: 687b ldr r3, [r7, #4]
|
|
8004574: 2202 movs r2, #2
|
|
8004576: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800457a: 4b12 ldr r3, [pc, #72] @ (80045c4 <HAL_RTCEx_SetSSRU_IT+0x70>)
|
|
800457c: 22ca movs r2, #202 @ 0xca
|
|
800457e: 625a str r2, [r3, #36] @ 0x24
|
|
8004580: 4b10 ldr r3, [pc, #64] @ (80045c4 <HAL_RTCEx_SetSSRU_IT+0x70>)
|
|
8004582: 2253 movs r2, #83 @ 0x53
|
|
8004584: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Enable IT SSRU */
|
|
__HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU);
|
|
8004586: 4b0f ldr r3, [pc, #60] @ (80045c4 <HAL_RTCEx_SetSSRU_IT+0x70>)
|
|
8004588: 699b ldr r3, [r3, #24]
|
|
800458a: 4a0e ldr r2, [pc, #56] @ (80045c4 <HAL_RTCEx_SetSSRU_IT+0x70>)
|
|
800458c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8004590: 6193 str r3, [r2, #24]
|
|
|
|
/* RTC SSRU Interrupt Configuration: EXTI configuration */
|
|
__HAL_RTC_SSRU_EXTI_ENABLE_IT();
|
|
8004592: 4b0d ldr r3, [pc, #52] @ (80045c8 <HAL_RTCEx_SetSSRU_IT+0x74>)
|
|
8004594: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8004598: 4a0b ldr r2, [pc, #44] @ (80045c8 <HAL_RTCEx_SetSSRU_IT+0x74>)
|
|
800459a: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
800459e: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
80045a2: 4b08 ldr r3, [pc, #32] @ (80045c4 <HAL_RTCEx_SetSSRU_IT+0x70>)
|
|
80045a4: 22ff movs r2, #255 @ 0xff
|
|
80045a6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
80045a8: 687b ldr r3, [r7, #4]
|
|
80045aa: 2201 movs r2, #1
|
|
80045ac: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
80045b0: 687b ldr r3, [r7, #4]
|
|
80045b2: 2200 movs r2, #0
|
|
80045b4: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
80045b8: 2300 movs r3, #0
|
|
}
|
|
80045ba: 4618 mov r0, r3
|
|
80045bc: 370c adds r7, #12
|
|
80045be: 46bd mov sp, r7
|
|
80045c0: bc80 pop {r7}
|
|
80045c2: 4770 bx lr
|
|
80045c4: 40002800 .word 0x40002800
|
|
80045c8: 58000800 .word 0x58000800
|
|
|
|
080045cc <HAL_RTCEx_SSRUIRQHandler>:
|
|
* @brief Handle SSR underflow interrupt request.
|
|
* @param hrtc RTC handle
|
|
* @retval None
|
|
*/
|
|
void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
80045cc: b580 push {r7, lr}
|
|
80045ce: b082 sub sp, #8
|
|
80045d0: af00 add r7, sp, #0
|
|
80045d2: 6078 str r0, [r7, #4]
|
|
if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u)
|
|
80045d4: 4b09 ldr r3, [pc, #36] @ (80045fc <HAL_RTCEx_SSRUIRQHandler+0x30>)
|
|
80045d6: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80045d8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80045dc: 2b00 cmp r3, #0
|
|
80045de: d005 beq.n 80045ec <HAL_RTCEx_SSRUIRQHandler+0x20>
|
|
{
|
|
/* Immediately clear flags */
|
|
RTC->SCR = RTC_SCR_CSSRUF;
|
|
80045e0: 4b06 ldr r3, [pc, #24] @ (80045fc <HAL_RTCEx_SSRUIRQHandler+0x30>)
|
|
80045e2: 2240 movs r2, #64 @ 0x40
|
|
80045e4: 65da str r2, [r3, #92] @ 0x5c
|
|
/* SSRU callback */
|
|
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
/* Call SSRUEvent registered Callback */
|
|
hrtc->SSRUEventCallback(hrtc);
|
|
#else
|
|
HAL_RTCEx_SSRUEventCallback(hrtc);
|
|
80045e6: 6878 ldr r0, [r7, #4]
|
|
80045e8: f7fc fcc5 bl 8000f76 <HAL_RTCEx_SSRUEventCallback>
|
|
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
80045ec: 687b ldr r3, [r7, #4]
|
|
80045ee: 2201 movs r2, #1
|
|
80045f0: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
}
|
|
80045f4: bf00 nop
|
|
80045f6: 3708 adds r7, #8
|
|
80045f8: 46bd mov sp, r7
|
|
80045fa: bd80 pop {r7, pc}
|
|
80045fc: 40002800 .word 0x40002800
|
|
|
|
08004600 <HAL_RTCEx_AlarmBEventCallback>:
|
|
* @brief Alarm B callback.
|
|
* @param hrtc RTC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8004600: b480 push {r7}
|
|
8004602: b083 sub sp, #12
|
|
8004604: af00 add r7, sp, #0
|
|
8004606: 6078 str r0, [r7, #4]
|
|
UNUSED(hrtc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004608: bf00 nop
|
|
800460a: 370c adds r7, #12
|
|
800460c: 46bd mov sp, r7
|
|
800460e: bc80 pop {r7}
|
|
8004610: 4770 bx lr
|
|
...
|
|
|
|
08004614 <HAL_RTCEx_BKUPWrite>:
|
|
* This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
|
|
* @param Data Data to be written in the specified Backup data register.
|
|
* @retval None
|
|
*/
|
|
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
|
|
{
|
|
8004614: b480 push {r7}
|
|
8004616: b087 sub sp, #28
|
|
8004618: af00 add r7, sp, #0
|
|
800461a: 60f8 str r0, [r7, #12]
|
|
800461c: 60b9 str r1, [r7, #8]
|
|
800461e: 607a str r2, [r7, #4]
|
|
|
|
UNUSED(hrtc);
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_BKP(BackupRegister));
|
|
|
|
tmp = (uint32_t) &(TAMP->BKP0R);
|
|
8004620: 4b07 ldr r3, [pc, #28] @ (8004640 <HAL_RTCEx_BKUPWrite+0x2c>)
|
|
8004622: 617b str r3, [r7, #20]
|
|
tmp += (BackupRegister * 4U);
|
|
8004624: 68bb ldr r3, [r7, #8]
|
|
8004626: 009b lsls r3, r3, #2
|
|
8004628: 697a ldr r2, [r7, #20]
|
|
800462a: 4413 add r3, r2
|
|
800462c: 617b str r3, [r7, #20]
|
|
|
|
/* Write the specified register */
|
|
*(__IO uint32_t *)tmp = (uint32_t)Data;
|
|
800462e: 697b ldr r3, [r7, #20]
|
|
8004630: 687a ldr r2, [r7, #4]
|
|
8004632: 601a str r2, [r3, #0]
|
|
}
|
|
8004634: bf00 nop
|
|
8004636: 371c adds r7, #28
|
|
8004638: 46bd mov sp, r7
|
|
800463a: bc80 pop {r7}
|
|
800463c: 4770 bx lr
|
|
800463e: bf00 nop
|
|
8004640: 4000b100 .word 0x4000b100
|
|
|
|
08004644 <HAL_RTCEx_BKUPRead>:
|
|
* @param BackupRegister RTC Backup data Register number.
|
|
* This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
|
|
* @retval Read value
|
|
*/
|
|
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
|
|
{
|
|
8004644: b480 push {r7}
|
|
8004646: b085 sub sp, #20
|
|
8004648: af00 add r7, sp, #0
|
|
800464a: 6078 str r0, [r7, #4]
|
|
800464c: 6039 str r1, [r7, #0]
|
|
|
|
UNUSED(hrtc);
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_BKP(BackupRegister));
|
|
|
|
tmp = (uint32_t) &(TAMP->BKP0R);
|
|
800464e: 4b07 ldr r3, [pc, #28] @ (800466c <HAL_RTCEx_BKUPRead+0x28>)
|
|
8004650: 60fb str r3, [r7, #12]
|
|
tmp += (BackupRegister * 4U);
|
|
8004652: 683b ldr r3, [r7, #0]
|
|
8004654: 009b lsls r3, r3, #2
|
|
8004656: 68fa ldr r2, [r7, #12]
|
|
8004658: 4413 add r3, r2
|
|
800465a: 60fb str r3, [r7, #12]
|
|
|
|
/* Read the specified register */
|
|
return (*(__IO uint32_t *)tmp);
|
|
800465c: 68fb ldr r3, [r7, #12]
|
|
800465e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004660: 4618 mov r0, r3
|
|
8004662: 3714 adds r7, #20
|
|
8004664: 46bd mov sp, r7
|
|
8004666: bc80 pop {r7}
|
|
8004668: 4770 bx lr
|
|
800466a: bf00 nop
|
|
800466c: 4000b100 .word 0x4000b100
|
|
|
|
08004670 <LL_PWR_SetRadioBusyTrigger>:
|
|
{
|
|
8004670: b480 push {r7}
|
|
8004672: b083 sub sp, #12
|
|
8004674: af00 add r7, sp, #0
|
|
8004676: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger);
|
|
8004678: 4b06 ldr r3, [pc, #24] @ (8004694 <LL_PWR_SetRadioBusyTrigger+0x24>)
|
|
800467a: 689b ldr r3, [r3, #8]
|
|
800467c: f423 6200 bic.w r2, r3, #2048 @ 0x800
|
|
8004680: 4904 ldr r1, [pc, #16] @ (8004694 <LL_PWR_SetRadioBusyTrigger+0x24>)
|
|
8004682: 687b ldr r3, [r7, #4]
|
|
8004684: 4313 orrs r3, r2
|
|
8004686: 608b str r3, [r1, #8]
|
|
}
|
|
8004688: bf00 nop
|
|
800468a: 370c adds r7, #12
|
|
800468c: 46bd mov sp, r7
|
|
800468e: bc80 pop {r7}
|
|
8004690: 4770 bx lr
|
|
8004692: bf00 nop
|
|
8004694: 58000400 .word 0x58000400
|
|
|
|
08004698 <LL_PWR_UnselectSUBGHZSPI_NSS>:
|
|
{
|
|
8004698: b480 push {r7}
|
|
800469a: af00 add r7, sp, #0
|
|
SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS);
|
|
800469c: 4b05 ldr r3, [pc, #20] @ (80046b4 <LL_PWR_UnselectSUBGHZSPI_NSS+0x1c>)
|
|
800469e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80046a2: 4a04 ldr r2, [pc, #16] @ (80046b4 <LL_PWR_UnselectSUBGHZSPI_NSS+0x1c>)
|
|
80046a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80046a8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
80046ac: bf00 nop
|
|
80046ae: 46bd mov sp, r7
|
|
80046b0: bc80 pop {r7}
|
|
80046b2: 4770 bx lr
|
|
80046b4: 58000400 .word 0x58000400
|
|
|
|
080046b8 <LL_PWR_SelectSUBGHZSPI_NSS>:
|
|
{
|
|
80046b8: b480 push {r7}
|
|
80046ba: af00 add r7, sp, #0
|
|
CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS);
|
|
80046bc: 4b05 ldr r3, [pc, #20] @ (80046d4 <LL_PWR_SelectSUBGHZSPI_NSS+0x1c>)
|
|
80046be: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80046c2: 4a04 ldr r2, [pc, #16] @ (80046d4 <LL_PWR_SelectSUBGHZSPI_NSS+0x1c>)
|
|
80046c4: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
80046c8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
80046cc: bf00 nop
|
|
80046ce: 46bd mov sp, r7
|
|
80046d0: bc80 pop {r7}
|
|
80046d2: 4770 bx lr
|
|
80046d4: 58000400 .word 0x58000400
|
|
|
|
080046d8 <LL_PWR_ClearFlag_RFBUSY>:
|
|
{
|
|
80046d8: b480 push {r7}
|
|
80046da: af00 add r7, sp, #0
|
|
WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF);
|
|
80046dc: 4b03 ldr r3, [pc, #12] @ (80046ec <LL_PWR_ClearFlag_RFBUSY+0x14>)
|
|
80046de: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
80046e2: 619a str r2, [r3, #24]
|
|
}
|
|
80046e4: bf00 nop
|
|
80046e6: 46bd mov sp, r7
|
|
80046e8: bc80 pop {r7}
|
|
80046ea: 4770 bx lr
|
|
80046ec: 58000400 .word 0x58000400
|
|
|
|
080046f0 <LL_PWR_IsActiveFlag_RFBUSYS>:
|
|
{
|
|
80046f0: b480 push {r7}
|
|
80046f2: af00 add r7, sp, #0
|
|
return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL);
|
|
80046f4: 4b06 ldr r3, [pc, #24] @ (8004710 <LL_PWR_IsActiveFlag_RFBUSYS+0x20>)
|
|
80046f6: 695b ldr r3, [r3, #20]
|
|
80046f8: f003 0302 and.w r3, r3, #2
|
|
80046fc: 2b02 cmp r3, #2
|
|
80046fe: d101 bne.n 8004704 <LL_PWR_IsActiveFlag_RFBUSYS+0x14>
|
|
8004700: 2301 movs r3, #1
|
|
8004702: e000 b.n 8004706 <LL_PWR_IsActiveFlag_RFBUSYS+0x16>
|
|
8004704: 2300 movs r3, #0
|
|
}
|
|
8004706: 4618 mov r0, r3
|
|
8004708: 46bd mov sp, r7
|
|
800470a: bc80 pop {r7}
|
|
800470c: 4770 bx lr
|
|
800470e: bf00 nop
|
|
8004710: 58000400 .word 0x58000400
|
|
|
|
08004714 <LL_PWR_IsActiveFlag_RFBUSYMS>:
|
|
{
|
|
8004714: b480 push {r7}
|
|
8004716: af00 add r7, sp, #0
|
|
return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL);
|
|
8004718: 4b06 ldr r3, [pc, #24] @ (8004734 <LL_PWR_IsActiveFlag_RFBUSYMS+0x20>)
|
|
800471a: 695b ldr r3, [r3, #20]
|
|
800471c: f003 0304 and.w r3, r3, #4
|
|
8004720: 2b04 cmp r3, #4
|
|
8004722: d101 bne.n 8004728 <LL_PWR_IsActiveFlag_RFBUSYMS+0x14>
|
|
8004724: 2301 movs r3, #1
|
|
8004726: e000 b.n 800472a <LL_PWR_IsActiveFlag_RFBUSYMS+0x16>
|
|
8004728: 2300 movs r3, #0
|
|
}
|
|
800472a: 4618 mov r0, r3
|
|
800472c: 46bd mov sp, r7
|
|
800472e: bc80 pop {r7}
|
|
8004730: 4770 bx lr
|
|
8004732: bf00 nop
|
|
8004734: 58000400 .word 0x58000400
|
|
|
|
08004738 <LL_RCC_RF_DisableReset>:
|
|
{
|
|
8004738: b480 push {r7}
|
|
800473a: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST);
|
|
800473c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8004740: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004744: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8004748: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
800474c: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
8004750: bf00 nop
|
|
8004752: 46bd mov sp, r7
|
|
8004754: bc80 pop {r7}
|
|
8004756: 4770 bx lr
|
|
|
|
08004758 <LL_RCC_IsRFUnderReset>:
|
|
{
|
|
8004758: b480 push {r7}
|
|
800475a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL);
|
|
800475c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8004760: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004764: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8004768: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
800476c: d101 bne.n 8004772 <LL_RCC_IsRFUnderReset+0x1a>
|
|
800476e: 2301 movs r3, #1
|
|
8004770: e000 b.n 8004774 <LL_RCC_IsRFUnderReset+0x1c>
|
|
8004772: 2300 movs r3, #0
|
|
}
|
|
8004774: 4618 mov r0, r3
|
|
8004776: 46bd mov sp, r7
|
|
8004778: bc80 pop {r7}
|
|
800477a: 4770 bx lr
|
|
|
|
0800477c <LL_EXTI_EnableIT_32_63>:
|
|
{
|
|
800477c: b480 push {r7}
|
|
800477e: b083 sub sp, #12
|
|
8004780: af00 add r7, sp, #0
|
|
8004782: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->IMR2, ExtiLine);
|
|
8004784: 4b06 ldr r3, [pc, #24] @ (80047a0 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
8004786: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90
|
|
800478a: 4905 ldr r1, [pc, #20] @ (80047a0 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 4313 orrs r3, r2
|
|
8004790: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
8004794: bf00 nop
|
|
8004796: 370c adds r7, #12
|
|
8004798: 46bd mov sp, r7
|
|
800479a: bc80 pop {r7}
|
|
800479c: 4770 bx lr
|
|
800479e: bf00 nop
|
|
80047a0: 58000800 .word 0x58000800
|
|
|
|
080047a4 <HAL_SUBGHZ_Init>:
|
|
* set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY
|
|
* to avoid the reset of Radio peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
80047a4: b580 push {r7, lr}
|
|
80047a6: b084 sub sp, #16
|
|
80047a8: af00 add r7, sp, #0
|
|
80047aa: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status;
|
|
__IO uint32_t count;
|
|
HAL_SUBGHZ_StateTypeDef subghz_state;
|
|
|
|
/* Check the hsubghz handle allocation */
|
|
if (hsubghz == NULL)
|
|
80047ac: 687b ldr r3, [r7, #4]
|
|
80047ae: 2b00 cmp r3, #0
|
|
80047b0: d103 bne.n 80047ba <HAL_SUBGHZ_Init+0x16>
|
|
{
|
|
status = HAL_ERROR;
|
|
80047b2: 2301 movs r3, #1
|
|
80047b4: 73fb strb r3, [r7, #15]
|
|
return status;
|
|
80047b6: 7bfb ldrb r3, [r7, #15]
|
|
80047b8: e052 b.n 8004860 <HAL_SUBGHZ_Init+0xbc>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
80047ba: 2300 movs r3, #0
|
|
80047bc: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler));
|
|
|
|
subghz_state = hsubghz->State;
|
|
80047be: 687b ldr r3, [r7, #4]
|
|
80047c0: 799b ldrb r3, [r3, #6]
|
|
80047c2: 73bb strb r3, [r7, #14]
|
|
if ((subghz_state == HAL_SUBGHZ_STATE_RESET) ||
|
|
80047c4: 7bbb ldrb r3, [r7, #14]
|
|
80047c6: 2b00 cmp r3, #0
|
|
80047c8: d002 beq.n 80047d0 <HAL_SUBGHZ_Init+0x2c>
|
|
80047ca: 7bbb ldrb r3, [r7, #14]
|
|
80047cc: 2b03 cmp r3, #3
|
|
80047ce: d109 bne.n 80047e4 <HAL_SUBGHZ_Init+0x40>
|
|
(subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY))
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hsubghz->Lock = HAL_UNLOCKED;
|
|
80047d0: 687b ldr r3, [r7, #4]
|
|
80047d2: 2200 movs r2, #0
|
|
80047d4: 715a strb r2, [r3, #5]
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hsubghz->MspInitCallback(hsubghz);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SUBGHZ_MspInit(hsubghz);
|
|
80047d6: 6878 ldr r0, [r7, #4]
|
|
80047d8: f7fc f932 bl 8000a40 <HAL_SUBGHZ_MspInit>
|
|
#if defined(CORE_CM0PLUS)
|
|
/* Enable EXTI 44 : Radio IRQ ITs for CPU2 */
|
|
LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
|
|
#else
|
|
/* Enable EXTI 44 : Radio IRQ ITs for CPU1 */
|
|
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
|
|
80047dc: f44f 5080 mov.w r0, #4096 @ 0x1000
|
|
80047e0: f7ff ffcc bl 800477c <LL_EXTI_EnableIT_32_63>
|
|
#endif /* CORE_CM0PLUS */
|
|
}
|
|
|
|
if (subghz_state == HAL_SUBGHZ_STATE_RESET)
|
|
80047e4: 7bbb ldrb r3, [r7, #14]
|
|
80047e6: 2b00 cmp r3, #0
|
|
80047e8: d126 bne.n 8004838 <HAL_SUBGHZ_Init+0x94>
|
|
{
|
|
/* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */
|
|
hsubghz->State = HAL_SUBGHZ_STATE_BUSY;
|
|
80047ea: 687b ldr r3, [r7, #4]
|
|
80047ec: 2202 movs r2, #2
|
|
80047ee: 719a strb r2, [r3, #6]
|
|
|
|
/* De-asserts the reset signal of the Radio peripheral */
|
|
LL_RCC_RF_DisableReset();
|
|
80047f0: f7ff ffa2 bl 8004738 <LL_RCC_RF_DisableReset>
|
|
|
|
/* Verify that Radio in reset status flag is set */
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
|
|
80047f4: 4b1c ldr r3, [pc, #112] @ (8004868 <HAL_SUBGHZ_Init+0xc4>)
|
|
80047f6: 681a ldr r2, [r3, #0]
|
|
80047f8: 4613 mov r3, r2
|
|
80047fa: 00db lsls r3, r3, #3
|
|
80047fc: 1a9b subs r3, r3, r2
|
|
80047fe: 009b lsls r3, r3, #2
|
|
8004800: 0cdb lsrs r3, r3, #19
|
|
8004802: 2264 movs r2, #100 @ 0x64
|
|
8004804: fb02 f303 mul.w r3, r2, r3
|
|
8004808: 60bb str r3, [r7, #8]
|
|
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800480a: 68bb ldr r3, [r7, #8]
|
|
800480c: 2b00 cmp r3, #0
|
|
800480e: d105 bne.n 800481c <HAL_SUBGHZ_Init+0x78>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004810: 2301 movs r3, #1
|
|
8004812: 73fb strb r3, [r7, #15]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
|
|
8004814: 687b ldr r3, [r7, #4]
|
|
8004816: 2201 movs r2, #1
|
|
8004818: 609a str r2, [r3, #8]
|
|
break;
|
|
800481a: e007 b.n 800482c <HAL_SUBGHZ_Init+0x88>
|
|
}
|
|
count--;
|
|
800481c: 68bb ldr r3, [r7, #8]
|
|
800481e: 3b01 subs r3, #1
|
|
8004820: 60bb str r3, [r7, #8]
|
|
} while (LL_RCC_IsRFUnderReset() != 0UL);
|
|
8004822: f7ff ff99 bl 8004758 <LL_RCC_IsRFUnderReset>
|
|
8004826: 4603 mov r3, r0
|
|
8004828: 2b00 cmp r3, #0
|
|
800482a: d1ee bne.n 800480a <HAL_SUBGHZ_Init+0x66>
|
|
|
|
/* Asserts the reset signal of the Radio peripheral */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
800482c: f7ff ff34 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
#if defined(CORE_CM0PLUS)
|
|
/* Enable wakeup signal of the Radio peripheral */
|
|
LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
|
|
#else
|
|
/* Enable wakeup signal of the Radio peripheral */
|
|
LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
|
|
8004830: f44f 6000 mov.w r0, #2048 @ 0x800
|
|
8004834: f7ff ff1c bl 8004670 <LL_PWR_SetRadioBusyTrigger>
|
|
#endif /* CORE_CM0PLUS */
|
|
}
|
|
|
|
/* Clear Pending Flag */
|
|
LL_PWR_ClearFlag_RFBUSY();
|
|
8004838: f7ff ff4e bl 80046d8 <LL_PWR_ClearFlag_RFBUSY>
|
|
|
|
if (status == HAL_OK)
|
|
800483c: 7bfb ldrb r3, [r7, #15]
|
|
800483e: 2b00 cmp r3, #0
|
|
8004840: d10a bne.n 8004858 <HAL_SUBGHZ_Init+0xb4>
|
|
{
|
|
/* Initialize SUBGHZSPI Peripheral */
|
|
SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler);
|
|
8004842: 687b ldr r3, [r7, #4]
|
|
8004844: 681b ldr r3, [r3, #0]
|
|
8004846: 4618 mov r0, r3
|
|
8004848: f000 fac2 bl 8004dd0 <SUBGHZSPI_Init>
|
|
|
|
hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE;
|
|
800484c: 687b ldr r3, [r7, #4]
|
|
800484e: 2201 movs r2, #1
|
|
8004850: 711a strb r2, [r3, #4]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE;
|
|
8004852: 687b ldr r3, [r7, #4]
|
|
8004854: 2200 movs r2, #0
|
|
8004856: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 2201 movs r2, #1
|
|
800485c: 719a strb r2, [r3, #6]
|
|
|
|
return status;
|
|
800485e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004860: 4618 mov r0, r3
|
|
8004862: 3710 adds r7, #16
|
|
8004864: 46bd mov sp, r7
|
|
8004866: bd80 pop {r7, pc}
|
|
8004868: 20000000 .word 0x20000000
|
|
|
|
0800486c <HAL_SUBGHZ_WriteRegisters>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint16_t Address,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
800486c: b580 push {r7, lr}
|
|
800486e: b086 sub sp, #24
|
|
8004870: af00 add r7, sp, #0
|
|
8004872: 60f8 str r0, [r7, #12]
|
|
8004874: 607a str r2, [r7, #4]
|
|
8004876: 461a mov r2, r3
|
|
8004878: 460b mov r3, r1
|
|
800487a: 817b strh r3, [r7, #10]
|
|
800487c: 4613 mov r3, r2
|
|
800487e: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004880: 68fb ldr r3, [r7, #12]
|
|
8004882: 799b ldrb r3, [r3, #6]
|
|
8004884: b2db uxtb r3, r3
|
|
8004886: 2b01 cmp r3, #1
|
|
8004888: d14a bne.n 8004920 <HAL_SUBGHZ_WriteRegisters+0xb4>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
800488a: 68fb ldr r3, [r7, #12]
|
|
800488c: 795b ldrb r3, [r3, #5]
|
|
800488e: 2b01 cmp r3, #1
|
|
8004890: d101 bne.n 8004896 <HAL_SUBGHZ_WriteRegisters+0x2a>
|
|
8004892: 2302 movs r3, #2
|
|
8004894: e045 b.n 8004922 <HAL_SUBGHZ_WriteRegisters+0xb6>
|
|
8004896: 68fb ldr r3, [r7, #12]
|
|
8004898: 2201 movs r2, #1
|
|
800489a: 715a strb r2, [r3, #5]
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_BUSY;
|
|
800489c: 68fb ldr r3, [r7, #12]
|
|
800489e: 2202 movs r2, #2
|
|
80048a0: 719a strb r2, [r3, #6]
|
|
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
80048a2: 68f8 ldr r0, [r7, #12]
|
|
80048a4: f000 fb62 bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
80048a8: f7ff ff06 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER);
|
|
80048ac: 210d movs r1, #13
|
|
80048ae: 68f8 ldr r0, [r7, #12]
|
|
80048b0: f000 faae bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U));
|
|
80048b4: 897b ldrh r3, [r7, #10]
|
|
80048b6: 0a1b lsrs r3, r3, #8
|
|
80048b8: b29b uxth r3, r3
|
|
80048ba: b2db uxtb r3, r3
|
|
80048bc: 4619 mov r1, r3
|
|
80048be: 68f8 ldr r0, [r7, #12]
|
|
80048c0: f000 faa6 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU));
|
|
80048c4: 897b ldrh r3, [r7, #10]
|
|
80048c6: b2db uxtb r3, r3
|
|
80048c8: 4619 mov r1, r3
|
|
80048ca: 68f8 ldr r0, [r7, #12]
|
|
80048cc: f000 faa0 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
80048d0: 2300 movs r3, #0
|
|
80048d2: 82bb strh r3, [r7, #20]
|
|
80048d4: e00a b.n 80048ec <HAL_SUBGHZ_WriteRegisters+0x80>
|
|
{
|
|
(void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]);
|
|
80048d6: 8abb ldrh r3, [r7, #20]
|
|
80048d8: 687a ldr r2, [r7, #4]
|
|
80048da: 4413 add r3, r2
|
|
80048dc: 781b ldrb r3, [r3, #0]
|
|
80048de: 4619 mov r1, r3
|
|
80048e0: 68f8 ldr r0, [r7, #12]
|
|
80048e2: f000 fa95 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
80048e6: 8abb ldrh r3, [r7, #20]
|
|
80048e8: 3301 adds r3, #1
|
|
80048ea: 82bb strh r3, [r7, #20]
|
|
80048ec: 8aba ldrh r2, [r7, #20]
|
|
80048ee: 893b ldrh r3, [r7, #8]
|
|
80048f0: 429a cmp r2, r3
|
|
80048f2: d3f0 bcc.n 80048d6 <HAL_SUBGHZ_WriteRegisters+0x6a>
|
|
}
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
80048f4: f7ff fed0 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
80048f8: 68f8 ldr r0, [r7, #12]
|
|
80048fa: f000 fb57 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
80048fe: 68fb ldr r3, [r7, #12]
|
|
8004900: 689b ldr r3, [r3, #8]
|
|
8004902: 2b00 cmp r3, #0
|
|
8004904: d002 beq.n 800490c <HAL_SUBGHZ_WriteRegisters+0xa0>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004906: 2301 movs r3, #1
|
|
8004908: 75fb strb r3, [r7, #23]
|
|
800490a: e001 b.n 8004910 <HAL_SUBGHZ_WriteRegisters+0xa4>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
800490c: 2300 movs r3, #0
|
|
800490e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004910: 68fb ldr r3, [r7, #12]
|
|
8004912: 2201 movs r2, #1
|
|
8004914: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
8004916: 68fb ldr r3, [r7, #12]
|
|
8004918: 2200 movs r2, #0
|
|
800491a: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
800491c: 7dfb ldrb r3, [r7, #23]
|
|
800491e: e000 b.n 8004922 <HAL_SUBGHZ_WriteRegisters+0xb6>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004920: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004922: 4618 mov r0, r3
|
|
8004924: 3718 adds r7, #24
|
|
8004926: 46bd mov sp, r7
|
|
8004928: bd80 pop {r7, pc}
|
|
|
|
0800492a <HAL_SUBGHZ_ReadRegisters>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint16_t Address,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
800492a: b580 push {r7, lr}
|
|
800492c: b088 sub sp, #32
|
|
800492e: af00 add r7, sp, #0
|
|
8004930: 60f8 str r0, [r7, #12]
|
|
8004932: 607a str r2, [r7, #4]
|
|
8004934: 461a mov r2, r3
|
|
8004936: 460b mov r3, r1
|
|
8004938: 817b strh r3, [r7, #10]
|
|
800493a: 4613 mov r3, r2
|
|
800493c: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
uint8_t *pData = pBuffer;
|
|
800493e: 687b ldr r3, [r7, #4]
|
|
8004940: 61bb str r3, [r7, #24]
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004942: 68fb ldr r3, [r7, #12]
|
|
8004944: 799b ldrb r3, [r3, #6]
|
|
8004946: b2db uxtb r3, r3
|
|
8004948: 2b01 cmp r3, #1
|
|
800494a: d14a bne.n 80049e2 <HAL_SUBGHZ_ReadRegisters+0xb8>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
800494c: 68fb ldr r3, [r7, #12]
|
|
800494e: 795b ldrb r3, [r3, #5]
|
|
8004950: 2b01 cmp r3, #1
|
|
8004952: d101 bne.n 8004958 <HAL_SUBGHZ_ReadRegisters+0x2e>
|
|
8004954: 2302 movs r3, #2
|
|
8004956: e045 b.n 80049e4 <HAL_SUBGHZ_ReadRegisters+0xba>
|
|
8004958: 68fb ldr r3, [r7, #12]
|
|
800495a: 2201 movs r2, #1
|
|
800495c: 715a strb r2, [r3, #5]
|
|
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
800495e: 68f8 ldr r0, [r7, #12]
|
|
8004960: f000 fb04 bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004964: f7ff fea8 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER);
|
|
8004968: 211d movs r1, #29
|
|
800496a: 68f8 ldr r0, [r7, #12]
|
|
800496c: f000 fa50 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U));
|
|
8004970: 897b ldrh r3, [r7, #10]
|
|
8004972: 0a1b lsrs r3, r3, #8
|
|
8004974: b29b uxth r3, r3
|
|
8004976: b2db uxtb r3, r3
|
|
8004978: 4619 mov r1, r3
|
|
800497a: 68f8 ldr r0, [r7, #12]
|
|
800497c: f000 fa48 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU));
|
|
8004980: 897b ldrh r3, [r7, #10]
|
|
8004982: b2db uxtb r3, r3
|
|
8004984: 4619 mov r1, r3
|
|
8004986: 68f8 ldr r0, [r7, #12]
|
|
8004988: f000 fa42 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, 0U);
|
|
800498c: 2100 movs r1, #0
|
|
800498e: 68f8 ldr r0, [r7, #12]
|
|
8004990: f000 fa3e bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004994: 2300 movs r3, #0
|
|
8004996: 82fb strh r3, [r7, #22]
|
|
8004998: e009 b.n 80049ae <HAL_SUBGHZ_ReadRegisters+0x84>
|
|
{
|
|
(void)SUBGHZSPI_Receive(hsubghz, (pData));
|
|
800499a: 69b9 ldr r1, [r7, #24]
|
|
800499c: 68f8 ldr r0, [r7, #12]
|
|
800499e: f000 fa8d bl 8004ebc <SUBGHZSPI_Receive>
|
|
pData++;
|
|
80049a2: 69bb ldr r3, [r7, #24]
|
|
80049a4: 3301 adds r3, #1
|
|
80049a6: 61bb str r3, [r7, #24]
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
80049a8: 8afb ldrh r3, [r7, #22]
|
|
80049aa: 3301 adds r3, #1
|
|
80049ac: 82fb strh r3, [r7, #22]
|
|
80049ae: 8afa ldrh r2, [r7, #22]
|
|
80049b0: 893b ldrh r3, [r7, #8]
|
|
80049b2: 429a cmp r2, r3
|
|
80049b4: d3f1 bcc.n 800499a <HAL_SUBGHZ_ReadRegisters+0x70>
|
|
}
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
80049b6: f7ff fe6f bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
80049ba: 68f8 ldr r0, [r7, #12]
|
|
80049bc: f000 faf6 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
80049c0: 68fb ldr r3, [r7, #12]
|
|
80049c2: 689b ldr r3, [r3, #8]
|
|
80049c4: 2b00 cmp r3, #0
|
|
80049c6: d002 beq.n 80049ce <HAL_SUBGHZ_ReadRegisters+0xa4>
|
|
{
|
|
status = HAL_ERROR;
|
|
80049c8: 2301 movs r3, #1
|
|
80049ca: 77fb strb r3, [r7, #31]
|
|
80049cc: e001 b.n 80049d2 <HAL_SUBGHZ_ReadRegisters+0xa8>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
80049ce: 2300 movs r3, #0
|
|
80049d0: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
80049d2: 68fb ldr r3, [r7, #12]
|
|
80049d4: 2201 movs r2, #1
|
|
80049d6: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
80049d8: 68fb ldr r3, [r7, #12]
|
|
80049da: 2200 movs r2, #0
|
|
80049dc: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
80049de: 7ffb ldrb r3, [r7, #31]
|
|
80049e0: e000 b.n 80049e4 <HAL_SUBGHZ_ReadRegisters+0xba>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80049e2: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80049e4: 4618 mov r0, r3
|
|
80049e6: 3720 adds r7, #32
|
|
80049e8: 46bd mov sp, r7
|
|
80049ea: bd80 pop {r7, pc}
|
|
|
|
080049ec <HAL_SUBGHZ_ExecSetCmd>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz,
|
|
SUBGHZ_RadioSetCmd_t Command,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
80049ec: b580 push {r7, lr}
|
|
80049ee: b086 sub sp, #24
|
|
80049f0: af00 add r7, sp, #0
|
|
80049f2: 60f8 str r0, [r7, #12]
|
|
80049f4: 607a str r2, [r7, #4]
|
|
80049f6: 461a mov r2, r3
|
|
80049f8: 460b mov r3, r1
|
|
80049fa: 72fb strb r3, [r7, #11]
|
|
80049fc: 4613 mov r3, r2
|
|
80049fe: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* LORA Modulation not available on STM32WLx4xx devices */
|
|
assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U]));
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004a00: 68fb ldr r3, [r7, #12]
|
|
8004a02: 799b ldrb r3, [r3, #6]
|
|
8004a04: b2db uxtb r3, r3
|
|
8004a06: 2b01 cmp r3, #1
|
|
8004a08: d14a bne.n 8004aa0 <HAL_SUBGHZ_ExecSetCmd+0xb4>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
8004a0a: 68fb ldr r3, [r7, #12]
|
|
8004a0c: 795b ldrb r3, [r3, #5]
|
|
8004a0e: 2b01 cmp r3, #1
|
|
8004a10: d101 bne.n 8004a16 <HAL_SUBGHZ_ExecSetCmd+0x2a>
|
|
8004a12: 2302 movs r3, #2
|
|
8004a14: e045 b.n 8004aa2 <HAL_SUBGHZ_ExecSetCmd+0xb6>
|
|
8004a16: 68fb ldr r3, [r7, #12]
|
|
8004a18: 2201 movs r2, #1
|
|
8004a1a: 715a strb r2, [r3, #5]
|
|
|
|
/* Need to wakeup Radio if already in Sleep at startup */
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
8004a1c: 68f8 ldr r0, [r7, #12]
|
|
8004a1e: f000 faa5 bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE))
|
|
8004a22: 7afb ldrb r3, [r7, #11]
|
|
8004a24: 2b84 cmp r3, #132 @ 0x84
|
|
8004a26: d002 beq.n 8004a2e <HAL_SUBGHZ_ExecSetCmd+0x42>
|
|
8004a28: 7afb ldrb r3, [r7, #11]
|
|
8004a2a: 2b94 cmp r3, #148 @ 0x94
|
|
8004a2c: d103 bne.n 8004a36 <HAL_SUBGHZ_ExecSetCmd+0x4a>
|
|
{
|
|
hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE;
|
|
8004a2e: 68fb ldr r3, [r7, #12]
|
|
8004a30: 2201 movs r2, #1
|
|
8004a32: 711a strb r2, [r3, #4]
|
|
8004a34: e002 b.n 8004a3c <HAL_SUBGHZ_ExecSetCmd+0x50>
|
|
}
|
|
else
|
|
{
|
|
hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE;
|
|
8004a36: 68fb ldr r3, [r7, #12]
|
|
8004a38: 2200 movs r2, #0
|
|
8004a3a: 711a strb r2, [r3, #4]
|
|
}
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004a3c: f7ff fe3c bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command);
|
|
8004a40: 7afb ldrb r3, [r7, #11]
|
|
8004a42: 4619 mov r1, r3
|
|
8004a44: 68f8 ldr r0, [r7, #12]
|
|
8004a46: f000 f9e3 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004a4a: 2300 movs r3, #0
|
|
8004a4c: 82bb strh r3, [r7, #20]
|
|
8004a4e: e00a b.n 8004a66 <HAL_SUBGHZ_ExecSetCmd+0x7a>
|
|
{
|
|
(void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]);
|
|
8004a50: 8abb ldrh r3, [r7, #20]
|
|
8004a52: 687a ldr r2, [r7, #4]
|
|
8004a54: 4413 add r3, r2
|
|
8004a56: 781b ldrb r3, [r3, #0]
|
|
8004a58: 4619 mov r1, r3
|
|
8004a5a: 68f8 ldr r0, [r7, #12]
|
|
8004a5c: f000 f9d8 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004a60: 8abb ldrh r3, [r7, #20]
|
|
8004a62: 3301 adds r3, #1
|
|
8004a64: 82bb strh r3, [r7, #20]
|
|
8004a66: 8aba ldrh r2, [r7, #20]
|
|
8004a68: 893b ldrh r3, [r7, #8]
|
|
8004a6a: 429a cmp r2, r3
|
|
8004a6c: d3f0 bcc.n 8004a50 <HAL_SUBGHZ_ExecSetCmd+0x64>
|
|
}
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
8004a6e: f7ff fe13 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
if (Command != RADIO_SET_SLEEP)
|
|
8004a72: 7afb ldrb r3, [r7, #11]
|
|
8004a74: 2b84 cmp r3, #132 @ 0x84
|
|
8004a76: d002 beq.n 8004a7e <HAL_SUBGHZ_ExecSetCmd+0x92>
|
|
{
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
8004a78: 68f8 ldr r0, [r7, #12]
|
|
8004a7a: f000 fa97 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
}
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
8004a7e: 68fb ldr r3, [r7, #12]
|
|
8004a80: 689b ldr r3, [r3, #8]
|
|
8004a82: 2b00 cmp r3, #0
|
|
8004a84: d002 beq.n 8004a8c <HAL_SUBGHZ_ExecSetCmd+0xa0>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004a86: 2301 movs r3, #1
|
|
8004a88: 75fb strb r3, [r7, #23]
|
|
8004a8a: e001 b.n 8004a90 <HAL_SUBGHZ_ExecSetCmd+0xa4>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
8004a8c: 2300 movs r3, #0
|
|
8004a8e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004a90: 68fb ldr r3, [r7, #12]
|
|
8004a92: 2201 movs r2, #1
|
|
8004a94: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
8004a96: 68fb ldr r3, [r7, #12]
|
|
8004a98: 2200 movs r2, #0
|
|
8004a9a: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
8004a9c: 7dfb ldrb r3, [r7, #23]
|
|
8004a9e: e000 b.n 8004aa2 <HAL_SUBGHZ_ExecSetCmd+0xb6>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004aa0: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004aa2: 4618 mov r0, r3
|
|
8004aa4: 3718 adds r7, #24
|
|
8004aa6: 46bd mov sp, r7
|
|
8004aa8: bd80 pop {r7, pc}
|
|
|
|
08004aaa <HAL_SUBGHZ_ExecGetCmd>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz,
|
|
SUBGHZ_RadioGetCmd_t Command,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
8004aaa: b580 push {r7, lr}
|
|
8004aac: b088 sub sp, #32
|
|
8004aae: af00 add r7, sp, #0
|
|
8004ab0: 60f8 str r0, [r7, #12]
|
|
8004ab2: 607a str r2, [r7, #4]
|
|
8004ab4: 461a mov r2, r3
|
|
8004ab6: 460b mov r3, r1
|
|
8004ab8: 72fb strb r3, [r7, #11]
|
|
8004aba: 4613 mov r3, r2
|
|
8004abc: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
uint8_t *pData = pBuffer;
|
|
8004abe: 687b ldr r3, [r7, #4]
|
|
8004ac0: 61bb str r3, [r7, #24]
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004ac2: 68fb ldr r3, [r7, #12]
|
|
8004ac4: 799b ldrb r3, [r3, #6]
|
|
8004ac6: b2db uxtb r3, r3
|
|
8004ac8: 2b01 cmp r3, #1
|
|
8004aca: d13d bne.n 8004b48 <HAL_SUBGHZ_ExecGetCmd+0x9e>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
8004acc: 68fb ldr r3, [r7, #12]
|
|
8004ace: 795b ldrb r3, [r3, #5]
|
|
8004ad0: 2b01 cmp r3, #1
|
|
8004ad2: d101 bne.n 8004ad8 <HAL_SUBGHZ_ExecGetCmd+0x2e>
|
|
8004ad4: 2302 movs r3, #2
|
|
8004ad6: e038 b.n 8004b4a <HAL_SUBGHZ_ExecGetCmd+0xa0>
|
|
8004ad8: 68fb ldr r3, [r7, #12]
|
|
8004ada: 2201 movs r2, #1
|
|
8004adc: 715a strb r2, [r3, #5]
|
|
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
8004ade: 68f8 ldr r0, [r7, #12]
|
|
8004ae0: f000 fa44 bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004ae4: f7ff fde8 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command);
|
|
8004ae8: 7afb ldrb r3, [r7, #11]
|
|
8004aea: 4619 mov r1, r3
|
|
8004aec: 68f8 ldr r0, [r7, #12]
|
|
8004aee: f000 f98f bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
/* Use to flush the Status (First byte) receive from SUBGHZ as not use */
|
|
(void)SUBGHZSPI_Transmit(hsubghz, 0x00U);
|
|
8004af2: 2100 movs r1, #0
|
|
8004af4: 68f8 ldr r0, [r7, #12]
|
|
8004af6: f000 f98b bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004afa: 2300 movs r3, #0
|
|
8004afc: 82fb strh r3, [r7, #22]
|
|
8004afe: e009 b.n 8004b14 <HAL_SUBGHZ_ExecGetCmd+0x6a>
|
|
{
|
|
(void)SUBGHZSPI_Receive(hsubghz, (pData));
|
|
8004b00: 69b9 ldr r1, [r7, #24]
|
|
8004b02: 68f8 ldr r0, [r7, #12]
|
|
8004b04: f000 f9da bl 8004ebc <SUBGHZSPI_Receive>
|
|
pData++;
|
|
8004b08: 69bb ldr r3, [r7, #24]
|
|
8004b0a: 3301 adds r3, #1
|
|
8004b0c: 61bb str r3, [r7, #24]
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004b0e: 8afb ldrh r3, [r7, #22]
|
|
8004b10: 3301 adds r3, #1
|
|
8004b12: 82fb strh r3, [r7, #22]
|
|
8004b14: 8afa ldrh r2, [r7, #22]
|
|
8004b16: 893b ldrh r3, [r7, #8]
|
|
8004b18: 429a cmp r2, r3
|
|
8004b1a: d3f1 bcc.n 8004b00 <HAL_SUBGHZ_ExecGetCmd+0x56>
|
|
}
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
8004b1c: f7ff fdbc bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
8004b20: 68f8 ldr r0, [r7, #12]
|
|
8004b22: f000 fa43 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
8004b26: 68fb ldr r3, [r7, #12]
|
|
8004b28: 689b ldr r3, [r3, #8]
|
|
8004b2a: 2b00 cmp r3, #0
|
|
8004b2c: d002 beq.n 8004b34 <HAL_SUBGHZ_ExecGetCmd+0x8a>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004b2e: 2301 movs r3, #1
|
|
8004b30: 77fb strb r3, [r7, #31]
|
|
8004b32: e001 b.n 8004b38 <HAL_SUBGHZ_ExecGetCmd+0x8e>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
8004b34: 2300 movs r3, #0
|
|
8004b36: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004b38: 68fb ldr r3, [r7, #12]
|
|
8004b3a: 2201 movs r2, #1
|
|
8004b3c: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
8004b3e: 68fb ldr r3, [r7, #12]
|
|
8004b40: 2200 movs r2, #0
|
|
8004b42: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
8004b44: 7ffb ldrb r3, [r7, #31]
|
|
8004b46: e000 b.n 8004b4a <HAL_SUBGHZ_ExecGetCmd+0xa0>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004b48: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004b4a: 4618 mov r0, r3
|
|
8004b4c: 3720 adds r7, #32
|
|
8004b4e: 46bd mov sp, r7
|
|
8004b50: bd80 pop {r7, pc}
|
|
|
|
08004b52 <HAL_SUBGHZ_WriteBuffer>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint8_t Offset,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
8004b52: b580 push {r7, lr}
|
|
8004b54: b086 sub sp, #24
|
|
8004b56: af00 add r7, sp, #0
|
|
8004b58: 60f8 str r0, [r7, #12]
|
|
8004b5a: 607a str r2, [r7, #4]
|
|
8004b5c: 461a mov r2, r3
|
|
8004b5e: 460b mov r3, r1
|
|
8004b60: 72fb strb r3, [r7, #11]
|
|
8004b62: 4613 mov r3, r2
|
|
8004b64: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004b66: 68fb ldr r3, [r7, #12]
|
|
8004b68: 799b ldrb r3, [r3, #6]
|
|
8004b6a: b2db uxtb r3, r3
|
|
8004b6c: 2b01 cmp r3, #1
|
|
8004b6e: d13e bne.n 8004bee <HAL_SUBGHZ_WriteBuffer+0x9c>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
8004b70: 68fb ldr r3, [r7, #12]
|
|
8004b72: 795b ldrb r3, [r3, #5]
|
|
8004b74: 2b01 cmp r3, #1
|
|
8004b76: d101 bne.n 8004b7c <HAL_SUBGHZ_WriteBuffer+0x2a>
|
|
8004b78: 2302 movs r3, #2
|
|
8004b7a: e039 b.n 8004bf0 <HAL_SUBGHZ_WriteBuffer+0x9e>
|
|
8004b7c: 68fb ldr r3, [r7, #12]
|
|
8004b7e: 2201 movs r2, #1
|
|
8004b80: 715a strb r2, [r3, #5]
|
|
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
8004b82: 68f8 ldr r0, [r7, #12]
|
|
8004b84: f000 f9f2 bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004b88: f7ff fd96 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER);
|
|
8004b8c: 210e movs r1, #14
|
|
8004b8e: 68f8 ldr r0, [r7, #12]
|
|
8004b90: f000 f93e bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, Offset);
|
|
8004b94: 7afb ldrb r3, [r7, #11]
|
|
8004b96: 4619 mov r1, r3
|
|
8004b98: 68f8 ldr r0, [r7, #12]
|
|
8004b9a: f000 f939 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004b9e: 2300 movs r3, #0
|
|
8004ba0: 82bb strh r3, [r7, #20]
|
|
8004ba2: e00a b.n 8004bba <HAL_SUBGHZ_WriteBuffer+0x68>
|
|
{
|
|
(void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]);
|
|
8004ba4: 8abb ldrh r3, [r7, #20]
|
|
8004ba6: 687a ldr r2, [r7, #4]
|
|
8004ba8: 4413 add r3, r2
|
|
8004baa: 781b ldrb r3, [r3, #0]
|
|
8004bac: 4619 mov r1, r3
|
|
8004bae: 68f8 ldr r0, [r7, #12]
|
|
8004bb0: f000 f92e bl 8004e10 <SUBGHZSPI_Transmit>
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004bb4: 8abb ldrh r3, [r7, #20]
|
|
8004bb6: 3301 adds r3, #1
|
|
8004bb8: 82bb strh r3, [r7, #20]
|
|
8004bba: 8aba ldrh r2, [r7, #20]
|
|
8004bbc: 893b ldrh r3, [r7, #8]
|
|
8004bbe: 429a cmp r2, r3
|
|
8004bc0: d3f0 bcc.n 8004ba4 <HAL_SUBGHZ_WriteBuffer+0x52>
|
|
}
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
8004bc2: f7ff fd69 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
8004bc6: 68f8 ldr r0, [r7, #12]
|
|
8004bc8: f000 f9f0 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
8004bcc: 68fb ldr r3, [r7, #12]
|
|
8004bce: 689b ldr r3, [r3, #8]
|
|
8004bd0: 2b00 cmp r3, #0
|
|
8004bd2: d002 beq.n 8004bda <HAL_SUBGHZ_WriteBuffer+0x88>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004bd4: 2301 movs r3, #1
|
|
8004bd6: 75fb strb r3, [r7, #23]
|
|
8004bd8: e001 b.n 8004bde <HAL_SUBGHZ_WriteBuffer+0x8c>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
8004bda: 2300 movs r3, #0
|
|
8004bdc: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004bde: 68fb ldr r3, [r7, #12]
|
|
8004be0: 2201 movs r2, #1
|
|
8004be2: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
8004be4: 68fb ldr r3, [r7, #12]
|
|
8004be6: 2200 movs r2, #0
|
|
8004be8: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
8004bea: 7dfb ldrb r3, [r7, #23]
|
|
8004bec: e000 b.n 8004bf0 <HAL_SUBGHZ_WriteBuffer+0x9e>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004bee: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004bf0: 4618 mov r0, r3
|
|
8004bf2: 3718 adds r7, #24
|
|
8004bf4: 46bd mov sp, r7
|
|
8004bf6: bd80 pop {r7, pc}
|
|
|
|
08004bf8 <HAL_SUBGHZ_ReadBuffer>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint8_t Offset,
|
|
uint8_t *pBuffer,
|
|
uint16_t Size)
|
|
{
|
|
8004bf8: b580 push {r7, lr}
|
|
8004bfa: b088 sub sp, #32
|
|
8004bfc: af00 add r7, sp, #0
|
|
8004bfe: 60f8 str r0, [r7, #12]
|
|
8004c00: 607a str r2, [r7, #4]
|
|
8004c02: 461a mov r2, r3
|
|
8004c04: 460b mov r3, r1
|
|
8004c06: 72fb strb r3, [r7, #11]
|
|
8004c08: 4613 mov r3, r2
|
|
8004c0a: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef status;
|
|
uint8_t *pData = pBuffer;
|
|
8004c0c: 687b ldr r3, [r7, #4]
|
|
8004c0e: 61bb str r3, [r7, #24]
|
|
|
|
if (hsubghz->State == HAL_SUBGHZ_STATE_READY)
|
|
8004c10: 68fb ldr r3, [r7, #12]
|
|
8004c12: 799b ldrb r3, [r3, #6]
|
|
8004c14: b2db uxtb r3, r3
|
|
8004c16: 2b01 cmp r3, #1
|
|
8004c18: d141 bne.n 8004c9e <HAL_SUBGHZ_ReadBuffer+0xa6>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsubghz);
|
|
8004c1a: 68fb ldr r3, [r7, #12]
|
|
8004c1c: 795b ldrb r3, [r3, #5]
|
|
8004c1e: 2b01 cmp r3, #1
|
|
8004c20: d101 bne.n 8004c26 <HAL_SUBGHZ_ReadBuffer+0x2e>
|
|
8004c22: 2302 movs r3, #2
|
|
8004c24: e03c b.n 8004ca0 <HAL_SUBGHZ_ReadBuffer+0xa8>
|
|
8004c26: 68fb ldr r3, [r7, #12]
|
|
8004c28: 2201 movs r2, #1
|
|
8004c2a: 715a strb r2, [r3, #5]
|
|
|
|
(void)SUBGHZ_CheckDeviceReady(hsubghz);
|
|
8004c2c: 68f8 ldr r0, [r7, #12]
|
|
8004c2e: f000 f99d bl 8004f6c <SUBGHZ_CheckDeviceReady>
|
|
|
|
/* NSS = 0 */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004c32: f7ff fd41 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER);
|
|
8004c36: 211e movs r1, #30
|
|
8004c38: 68f8 ldr r0, [r7, #12]
|
|
8004c3a: f000 f8e9 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, Offset);
|
|
8004c3e: 7afb ldrb r3, [r7, #11]
|
|
8004c40: 4619 mov r1, r3
|
|
8004c42: 68f8 ldr r0, [r7, #12]
|
|
8004c44: f000 f8e4 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
(void)SUBGHZSPI_Transmit(hsubghz, 0x00U);
|
|
8004c48: 2100 movs r1, #0
|
|
8004c4a: 68f8 ldr r0, [r7, #12]
|
|
8004c4c: f000 f8e0 bl 8004e10 <SUBGHZSPI_Transmit>
|
|
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004c50: 2300 movs r3, #0
|
|
8004c52: 82fb strh r3, [r7, #22]
|
|
8004c54: e009 b.n 8004c6a <HAL_SUBGHZ_ReadBuffer+0x72>
|
|
{
|
|
(void)SUBGHZSPI_Receive(hsubghz, (pData));
|
|
8004c56: 69b9 ldr r1, [r7, #24]
|
|
8004c58: 68f8 ldr r0, [r7, #12]
|
|
8004c5a: f000 f92f bl 8004ebc <SUBGHZSPI_Receive>
|
|
pData++;
|
|
8004c5e: 69bb ldr r3, [r7, #24]
|
|
8004c60: 3301 adds r3, #1
|
|
8004c62: 61bb str r3, [r7, #24]
|
|
for (uint16_t i = 0U; i < Size; i++)
|
|
8004c64: 8afb ldrh r3, [r7, #22]
|
|
8004c66: 3301 adds r3, #1
|
|
8004c68: 82fb strh r3, [r7, #22]
|
|
8004c6a: 8afa ldrh r2, [r7, #22]
|
|
8004c6c: 893b ldrh r3, [r7, #8]
|
|
8004c6e: 429a cmp r2, r3
|
|
8004c70: d3f1 bcc.n 8004c56 <HAL_SUBGHZ_ReadBuffer+0x5e>
|
|
}
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
8004c72: f7ff fd11 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
|
|
(void)SUBGHZ_WaitOnBusy(hsubghz);
|
|
8004c76: 68f8 ldr r0, [r7, #12]
|
|
8004c78: f000 f998 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
|
|
if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE)
|
|
8004c7c: 68fb ldr r3, [r7, #12]
|
|
8004c7e: 689b ldr r3, [r3, #8]
|
|
8004c80: 2b00 cmp r3, #0
|
|
8004c82: d002 beq.n 8004c8a <HAL_SUBGHZ_ReadBuffer+0x92>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004c84: 2301 movs r3, #1
|
|
8004c86: 77fb strb r3, [r7, #31]
|
|
8004c88: e001 b.n 8004c8e <HAL_SUBGHZ_ReadBuffer+0x96>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_OK;
|
|
8004c8a: 2300 movs r3, #0
|
|
8004c8c: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
hsubghz->State = HAL_SUBGHZ_STATE_READY;
|
|
8004c8e: 68fb ldr r3, [r7, #12]
|
|
8004c90: 2201 movs r2, #1
|
|
8004c92: 719a strb r2, [r3, #6]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsubghz);
|
|
8004c94: 68fb ldr r3, [r7, #12]
|
|
8004c96: 2200 movs r2, #0
|
|
8004c98: 715a strb r2, [r3, #5]
|
|
|
|
return status;
|
|
8004c9a: 7ffb ldrb r3, [r7, #31]
|
|
8004c9c: e000 b.n 8004ca0 <HAL_SUBGHZ_ReadBuffer+0xa8>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004c9e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004ca0: 4618 mov r0, r3
|
|
8004ca2: 3720 adds r7, #32
|
|
8004ca4: 46bd mov sp, r7
|
|
8004ca6: bd80 pop {r7, pc}
|
|
|
|
08004ca8 <HAL_SUBGHZ_IRQHandler>:
|
|
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
|
|
* the configuration information for the specified SUBGHZ module.
|
|
* @retval None
|
|
*/
|
|
void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
8004ca8: b580 push {r7, lr}
|
|
8004caa: b084 sub sp, #16
|
|
8004cac: af00 add r7, sp, #0
|
|
8004cae: 6078 str r0, [r7, #4]
|
|
uint8_t tmpisr[2U] = {0U};
|
|
8004cb0: 2300 movs r3, #0
|
|
8004cb2: 81bb strh r3, [r7, #12]
|
|
uint16_t itsource;
|
|
|
|
/* Retrieve Interrupts from SUBGHZ Irq Register */
|
|
(void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U);
|
|
8004cb4: f107 020c add.w r2, r7, #12
|
|
8004cb8: 2302 movs r3, #2
|
|
8004cba: 2112 movs r1, #18
|
|
8004cbc: 6878 ldr r0, [r7, #4]
|
|
8004cbe: f7ff fef4 bl 8004aaa <HAL_SUBGHZ_ExecGetCmd>
|
|
itsource = tmpisr[0U];
|
|
8004cc2: 7b3b ldrb r3, [r7, #12]
|
|
8004cc4: 81fb strh r3, [r7, #14]
|
|
itsource = (itsource << 8U) | tmpisr[1U];
|
|
8004cc6: f9b7 300e ldrsh.w r3, [r7, #14]
|
|
8004cca: 021b lsls r3, r3, #8
|
|
8004ccc: b21a sxth r2, r3
|
|
8004cce: 7b7b ldrb r3, [r7, #13]
|
|
8004cd0: b21b sxth r3, r3
|
|
8004cd2: 4313 orrs r3, r2
|
|
8004cd4: b21b sxth r3, r3
|
|
8004cd6: 81fb strh r3, [r7, #14]
|
|
|
|
/* Clear SUBGHZ Irq Register */
|
|
(void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U);
|
|
8004cd8: f107 020c add.w r2, r7, #12
|
|
8004cdc: 2302 movs r3, #2
|
|
8004cde: 2102 movs r1, #2
|
|
8004ce0: 6878 ldr r0, [r7, #4]
|
|
8004ce2: f7ff fe83 bl 80049ec <HAL_SUBGHZ_ExecSetCmd>
|
|
|
|
/* Packet transmission completed Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET)
|
|
8004ce6: 89fb ldrh r3, [r7, #14]
|
|
8004ce8: f003 0301 and.w r3, r3, #1
|
|
8004cec: 2b00 cmp r3, #0
|
|
8004cee: d002 beq.n 8004cf6 <HAL_SUBGHZ_IRQHandler+0x4e>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->TxCpltCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_TxCpltCallback(hsubghz);
|
|
8004cf0: 6878 ldr r0, [r7, #4]
|
|
8004cf2: f005 fc83 bl 800a5fc <HAL_SUBGHZ_TxCpltCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Packet received Interrupt */
|
|
if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET))
|
|
8004cf6: 89fb ldrh r3, [r7, #14]
|
|
8004cf8: 085b lsrs r3, r3, #1
|
|
8004cfa: f003 0301 and.w r3, r3, #1
|
|
8004cfe: 2b00 cmp r3, #0
|
|
8004d00: d00e beq.n 8004d20 <HAL_SUBGHZ_IRQHandler+0x78>
|
|
{
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET)
|
|
8004d02: 89fb ldrh r3, [r7, #14]
|
|
8004d04: 099b lsrs r3, r3, #6
|
|
8004d06: f003 0301 and.w r3, r3, #1
|
|
8004d0a: 2b00 cmp r3, #0
|
|
8004d0c: d005 beq.n 8004d1a <HAL_SUBGHZ_IRQHandler+0x72>
|
|
{
|
|
hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_CRC_MISMATCH;
|
|
8004d0e: 687b ldr r3, [r7, #4]
|
|
8004d10: 689b ldr r3, [r3, #8]
|
|
8004d12: f043 0204 orr.w r2, r3, #4
|
|
8004d16: 687b ldr r3, [r7, #4]
|
|
8004d18: 609a str r2, [r3, #8]
|
|
}
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->RxCpltCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_RxCpltCallback(hsubghz);
|
|
8004d1a: 6878 ldr r0, [r7, #4]
|
|
8004d1c: f005 fc7c bl 800a618 <HAL_SUBGHZ_RxCpltCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Preamble Detected Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET)
|
|
8004d20: 89fb ldrh r3, [r7, #14]
|
|
8004d22: 089b lsrs r3, r3, #2
|
|
8004d24: f003 0301 and.w r3, r3, #1
|
|
8004d28: 2b00 cmp r3, #0
|
|
8004d2a: d002 beq.n 8004d32 <HAL_SUBGHZ_IRQHandler+0x8a>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->PreambleDetectedCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_PreambleDetectedCallback(hsubghz);
|
|
8004d2c: 6878 ldr r0, [r7, #4]
|
|
8004d2e: f005 fccb bl 800a6c8 <HAL_SUBGHZ_PreambleDetectedCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Valid sync word detected Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET)
|
|
8004d32: 89fb ldrh r3, [r7, #14]
|
|
8004d34: 08db lsrs r3, r3, #3
|
|
8004d36: f003 0301 and.w r3, r3, #1
|
|
8004d3a: 2b00 cmp r3, #0
|
|
8004d3c: d002 beq.n 8004d44 <HAL_SUBGHZ_IRQHandler+0x9c>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->SyncWordValidCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_SyncWordValidCallback(hsubghz);
|
|
8004d3e: 6878 ldr r0, [r7, #4]
|
|
8004d40: f005 fcd0 bl 800a6e4 <HAL_SUBGHZ_SyncWordValidCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Valid LoRa header received Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET)
|
|
8004d44: 89fb ldrh r3, [r7, #14]
|
|
8004d46: 091b lsrs r3, r3, #4
|
|
8004d48: f003 0301 and.w r3, r3, #1
|
|
8004d4c: 2b00 cmp r3, #0
|
|
8004d4e: d002 beq.n 8004d56 <HAL_SUBGHZ_IRQHandler+0xae>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->HeaderValidCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_HeaderValidCallback(hsubghz);
|
|
8004d50: 6878 ldr r0, [r7, #4]
|
|
8004d52: f005 fcd5 bl 800a700 <HAL_SUBGHZ_HeaderValidCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* LoRa header CRC error Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET)
|
|
8004d56: 89fb ldrh r3, [r7, #14]
|
|
8004d58: 095b lsrs r3, r3, #5
|
|
8004d5a: f003 0301 and.w r3, r3, #1
|
|
8004d5e: 2b00 cmp r3, #0
|
|
8004d60: d002 beq.n 8004d68 <HAL_SUBGHZ_IRQHandler+0xc0>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->HeaderErrorCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_HeaderErrorCallback(hsubghz);
|
|
8004d62: 6878 ldr r0, [r7, #4]
|
|
8004d64: f005 fca2 bl 800a6ac <HAL_SUBGHZ_HeaderErrorCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Wrong CRC received Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET)
|
|
8004d68: 89fb ldrh r3, [r7, #14]
|
|
8004d6a: 099b lsrs r3, r3, #6
|
|
8004d6c: f003 0301 and.w r3, r3, #1
|
|
8004d70: 2b00 cmp r3, #0
|
|
8004d72: d002 beq.n 8004d7a <HAL_SUBGHZ_IRQHandler+0xd2>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->CRCErrorCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_CRCErrorCallback(hsubghz);
|
|
8004d74: 6878 ldr r0, [r7, #4]
|
|
8004d76: f005 fc5d bl 800a634 <HAL_SUBGHZ_CRCErrorCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Channel activity detection finished Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET)
|
|
8004d7a: 89fb ldrh r3, [r7, #14]
|
|
8004d7c: 09db lsrs r3, r3, #7
|
|
8004d7e: f003 0301 and.w r3, r3, #1
|
|
8004d82: 2b00 cmp r3, #0
|
|
8004d84: d00e beq.n 8004da4 <HAL_SUBGHZ_IRQHandler+0xfc>
|
|
{
|
|
hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR);
|
|
}
|
|
#else
|
|
/* Channel activity Detected Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET)
|
|
8004d86: 89fb ldrh r3, [r7, #14]
|
|
8004d88: 0a1b lsrs r3, r3, #8
|
|
8004d8a: f003 0301 and.w r3, r3, #1
|
|
8004d8e: 2b00 cmp r3, #0
|
|
8004d90: d004 beq.n 8004d9c <HAL_SUBGHZ_IRQHandler+0xf4>
|
|
{
|
|
HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED);
|
|
8004d92: 2101 movs r1, #1
|
|
8004d94: 6878 ldr r0, [r7, #4]
|
|
8004d96: f005 fc5b bl 800a650 <HAL_SUBGHZ_CADStatusCallback>
|
|
8004d9a: e003 b.n 8004da4 <HAL_SUBGHZ_IRQHandler+0xfc>
|
|
}
|
|
else
|
|
{
|
|
HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR);
|
|
8004d9c: 2100 movs r1, #0
|
|
8004d9e: 6878 ldr r0, [r7, #4]
|
|
8004da0: f005 fc56 bl 800a650 <HAL_SUBGHZ_CADStatusCallback>
|
|
}
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Rx or Tx Timeout Interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET)
|
|
8004da4: 89fb ldrh r3, [r7, #14]
|
|
8004da6: 0a5b lsrs r3, r3, #9
|
|
8004da8: f003 0301 and.w r3, r3, #1
|
|
8004dac: 2b00 cmp r3, #0
|
|
8004dae: d002 beq.n 8004db6 <HAL_SUBGHZ_IRQHandler+0x10e>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->RxTxTimeoutCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz);
|
|
8004db0: 6878 ldr r0, [r7, #4]
|
|
8004db2: f005 fc6b bl 800a68c <HAL_SUBGHZ_RxTxTimeoutCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* LR_FHSS Hop interrupt */
|
|
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET)
|
|
8004db6: 89fb ldrh r3, [r7, #14]
|
|
8004db8: 0b9b lsrs r3, r3, #14
|
|
8004dba: f003 0301 and.w r3, r3, #1
|
|
8004dbe: 2b00 cmp r3, #0
|
|
8004dc0: d002 beq.n 8004dc8 <HAL_SUBGHZ_IRQHandler+0x120>
|
|
{
|
|
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
|
|
hsubghz->LrFhssHopCallback(hsubghz);
|
|
#else
|
|
HAL_SUBGHZ_LrFhssHopCallback(hsubghz);
|
|
8004dc2: 6878 ldr r0, [r7, #4]
|
|
8004dc4: f005 fcaa bl 800a71c <HAL_SUBGHZ_LrFhssHopCallback>
|
|
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8004dc8: bf00 nop
|
|
8004dca: 3710 adds r7, #16
|
|
8004dcc: 46bd mov sp, r7
|
|
8004dce: bd80 pop {r7, pc}
|
|
|
|
08004dd0 <SUBGHZSPI_Init>:
|
|
* @brief Initializes the SUBGHZSPI peripheral
|
|
* @param BaudratePrescaler SPI Baudrate prescaler
|
|
* @retval None
|
|
*/
|
|
void SUBGHZSPI_Init(uint32_t BaudratePrescaler)
|
|
{
|
|
8004dd0: b480 push {r7}
|
|
8004dd2: b083 sub sp, #12
|
|
8004dd4: af00 add r7, sp, #0
|
|
8004dd6: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI));
|
|
|
|
/* Disable SUBGHZSPI Peripheral */
|
|
CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE);
|
|
8004dd8: 4b0c ldr r3, [pc, #48] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004dda: 681b ldr r3, [r3, #0]
|
|
8004ddc: 4a0b ldr r2, [pc, #44] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004dde: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004de2: 6013 str r3, [r2, #0]
|
|
* NSS management: Internal (Done with External bit inside PWR *
|
|
* Communication speed: BaudratePrescaler *
|
|
* First bit: MSB *
|
|
* CRC calculation: Disable *
|
|
*--------------------------------------------------------------------------*/
|
|
WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM));
|
|
8004de4: 4a09 ldr r2, [pc, #36] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004de6: 687b ldr r3, [r7, #4]
|
|
8004de8: f443 7341 orr.w r3, r3, #772 @ 0x304
|
|
8004dec: 6013 str r3, [r2, #0]
|
|
* Data Size: 8bits *
|
|
* TI Mode: Disable *
|
|
* NSS Pulse: Disable *
|
|
* Rx FIFO Threshold: 8bits *
|
|
*--------------------------------------------------------------------------*/
|
|
WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2));
|
|
8004dee: 4b07 ldr r3, [pc, #28] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004df0: f44f 52b8 mov.w r2, #5888 @ 0x1700
|
|
8004df4: 605a str r2, [r3, #4]
|
|
|
|
/* Enable SUBGHZSPI Peripheral */
|
|
SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE);
|
|
8004df6: 4b05 ldr r3, [pc, #20] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004df8: 681b ldr r3, [r3, #0]
|
|
8004dfa: 4a04 ldr r2, [pc, #16] @ (8004e0c <SUBGHZSPI_Init+0x3c>)
|
|
8004dfc: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8004e00: 6013 str r3, [r2, #0]
|
|
}
|
|
8004e02: bf00 nop
|
|
8004e04: 370c adds r7, #12
|
|
8004e06: 46bd mov sp, r7
|
|
8004e08: bc80 pop {r7}
|
|
8004e0a: 4770 bx lr
|
|
8004e0c: 58010000 .word 0x58010000
|
|
|
|
08004e10 <SUBGHZSPI_Transmit>:
|
|
* @param Data data to transmit
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint8_t Data)
|
|
{
|
|
8004e10: b480 push {r7}
|
|
8004e12: b087 sub sp, #28
|
|
8004e14: af00 add r7, sp, #0
|
|
8004e16: 6078 str r0, [r7, #4]
|
|
8004e18: 460b mov r3, r1
|
|
8004e1a: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004e1c: 2300 movs r3, #0
|
|
8004e1e: 75fb strb r3, [r7, #23]
|
|
__IO uint32_t count;
|
|
|
|
/* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/
|
|
/* Initialize Timeout */
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
|
|
8004e20: 4b23 ldr r3, [pc, #140] @ (8004eb0 <SUBGHZSPI_Transmit+0xa0>)
|
|
8004e22: 681a ldr r2, [r3, #0]
|
|
8004e24: 4613 mov r3, r2
|
|
8004e26: 00db lsls r3, r3, #3
|
|
8004e28: 1a9b subs r3, r3, r2
|
|
8004e2a: 009b lsls r3, r3, #2
|
|
8004e2c: 0cdb lsrs r3, r3, #19
|
|
8004e2e: 2264 movs r2, #100 @ 0x64
|
|
8004e30: fb02 f303 mul.w r3, r2, r3
|
|
8004e34: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until TXE flag is set */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
8004e36: 68fb ldr r3, [r7, #12]
|
|
8004e38: 2b00 cmp r3, #0
|
|
8004e3a: d105 bne.n 8004e48 <SUBGHZSPI_Transmit+0x38>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004e3c: 2301 movs r3, #1
|
|
8004e3e: 75fb strb r3, [r7, #23]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
|
|
8004e40: 687b ldr r3, [r7, #4]
|
|
8004e42: 2201 movs r2, #1
|
|
8004e44: 609a str r2, [r3, #8]
|
|
break;
|
|
8004e46: e008 b.n 8004e5a <SUBGHZSPI_Transmit+0x4a>
|
|
}
|
|
count--;
|
|
8004e48: 68fb ldr r3, [r7, #12]
|
|
8004e4a: 3b01 subs r3, #1
|
|
8004e4c: 60fb str r3, [r7, #12]
|
|
} while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE));
|
|
8004e4e: 4b19 ldr r3, [pc, #100] @ (8004eb4 <SUBGHZSPI_Transmit+0xa4>)
|
|
8004e50: 689b ldr r3, [r3, #8]
|
|
8004e52: f003 0302 and.w r3, r3, #2
|
|
8004e56: 2b02 cmp r3, #2
|
|
8004e58: d1ed bne.n 8004e36 <SUBGHZSPI_Transmit+0x26>
|
|
|
|
/* Transmit Data*/
|
|
#if defined (__GNUC__)
|
|
__IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR);
|
|
8004e5a: 4b17 ldr r3, [pc, #92] @ (8004eb8 <SUBGHZSPI_Transmit+0xa8>)
|
|
8004e5c: 613b str r3, [r7, #16]
|
|
*spidr = Data;
|
|
8004e5e: 693b ldr r3, [r7, #16]
|
|
8004e60: 78fa ldrb r2, [r7, #3]
|
|
8004e62: 701a strb r2, [r3, #0]
|
|
*((__IO uint8_t *)&SUBGHZSPI->DR) = Data;
|
|
#endif /* __GNUC__ */
|
|
|
|
/* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/
|
|
/* Initialize Timeout */
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
|
|
8004e64: 4b12 ldr r3, [pc, #72] @ (8004eb0 <SUBGHZSPI_Transmit+0xa0>)
|
|
8004e66: 681a ldr r2, [r3, #0]
|
|
8004e68: 4613 mov r3, r2
|
|
8004e6a: 00db lsls r3, r3, #3
|
|
8004e6c: 1a9b subs r3, r3, r2
|
|
8004e6e: 009b lsls r3, r3, #2
|
|
8004e70: 0cdb lsrs r3, r3, #19
|
|
8004e72: 2264 movs r2, #100 @ 0x64
|
|
8004e74: fb02 f303 mul.w r3, r2, r3
|
|
8004e78: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until RXNE flag is set */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
8004e7a: 68fb ldr r3, [r7, #12]
|
|
8004e7c: 2b00 cmp r3, #0
|
|
8004e7e: d105 bne.n 8004e8c <SUBGHZSPI_Transmit+0x7c>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004e80: 2301 movs r3, #1
|
|
8004e82: 75fb strb r3, [r7, #23]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
|
|
8004e84: 687b ldr r3, [r7, #4]
|
|
8004e86: 2201 movs r2, #1
|
|
8004e88: 609a str r2, [r3, #8]
|
|
break;
|
|
8004e8a: e008 b.n 8004e9e <SUBGHZSPI_Transmit+0x8e>
|
|
}
|
|
count--;
|
|
8004e8c: 68fb ldr r3, [r7, #12]
|
|
8004e8e: 3b01 subs r3, #1
|
|
8004e90: 60fb str r3, [r7, #12]
|
|
} while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE));
|
|
8004e92: 4b08 ldr r3, [pc, #32] @ (8004eb4 <SUBGHZSPI_Transmit+0xa4>)
|
|
8004e94: 689b ldr r3, [r3, #8]
|
|
8004e96: f003 0301 and.w r3, r3, #1
|
|
8004e9a: 2b01 cmp r3, #1
|
|
8004e9c: d1ed bne.n 8004e7a <SUBGHZSPI_Transmit+0x6a>
|
|
|
|
/* Flush Rx data */
|
|
READ_REG(SUBGHZSPI->DR);
|
|
8004e9e: 4b05 ldr r3, [pc, #20] @ (8004eb4 <SUBGHZSPI_Transmit+0xa4>)
|
|
8004ea0: 68db ldr r3, [r3, #12]
|
|
|
|
return status;
|
|
8004ea2: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004ea4: 4618 mov r0, r3
|
|
8004ea6: 371c adds r7, #28
|
|
8004ea8: 46bd mov sp, r7
|
|
8004eaa: bc80 pop {r7}
|
|
8004eac: 4770 bx lr
|
|
8004eae: bf00 nop
|
|
8004eb0: 20000000 .word 0x20000000
|
|
8004eb4: 58010000 .word 0x58010000
|
|
8004eb8: 5801000c .word 0x5801000c
|
|
|
|
08004ebc <SUBGHZSPI_Receive>:
|
|
* @param pData pointer on data to receive
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz,
|
|
uint8_t *pData)
|
|
{
|
|
8004ebc: b480 push {r7}
|
|
8004ebe: b087 sub sp, #28
|
|
8004ec0: af00 add r7, sp, #0
|
|
8004ec2: 6078 str r0, [r7, #4]
|
|
8004ec4: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004ec6: 2300 movs r3, #0
|
|
8004ec8: 75fb strb r3, [r7, #23]
|
|
__IO uint32_t count;
|
|
|
|
/* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/
|
|
/* Initialize Timeout */
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
|
|
8004eca: 4b25 ldr r3, [pc, #148] @ (8004f60 <SUBGHZSPI_Receive+0xa4>)
|
|
8004ecc: 681a ldr r2, [r3, #0]
|
|
8004ece: 4613 mov r3, r2
|
|
8004ed0: 00db lsls r3, r3, #3
|
|
8004ed2: 1a9b subs r3, r3, r2
|
|
8004ed4: 009b lsls r3, r3, #2
|
|
8004ed6: 0cdb lsrs r3, r3, #19
|
|
8004ed8: 2264 movs r2, #100 @ 0x64
|
|
8004eda: fb02 f303 mul.w r3, r2, r3
|
|
8004ede: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until TXE flag is set */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
8004ee0: 68fb ldr r3, [r7, #12]
|
|
8004ee2: 2b00 cmp r3, #0
|
|
8004ee4: d105 bne.n 8004ef2 <SUBGHZSPI_Receive+0x36>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004ee6: 2301 movs r3, #1
|
|
8004ee8: 75fb strb r3, [r7, #23]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
|
|
8004eea: 687b ldr r3, [r7, #4]
|
|
8004eec: 2201 movs r2, #1
|
|
8004eee: 609a str r2, [r3, #8]
|
|
break;
|
|
8004ef0: e008 b.n 8004f04 <SUBGHZSPI_Receive+0x48>
|
|
}
|
|
count--;
|
|
8004ef2: 68fb ldr r3, [r7, #12]
|
|
8004ef4: 3b01 subs r3, #1
|
|
8004ef6: 60fb str r3, [r7, #12]
|
|
} while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE));
|
|
8004ef8: 4b1a ldr r3, [pc, #104] @ (8004f64 <SUBGHZSPI_Receive+0xa8>)
|
|
8004efa: 689b ldr r3, [r3, #8]
|
|
8004efc: f003 0302 and.w r3, r3, #2
|
|
8004f00: 2b02 cmp r3, #2
|
|
8004f02: d1ed bne.n 8004ee0 <SUBGHZSPI_Receive+0x24>
|
|
|
|
/* Transmit Data*/
|
|
#if defined (__GNUC__)
|
|
__IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR);
|
|
8004f04: 4b18 ldr r3, [pc, #96] @ (8004f68 <SUBGHZSPI_Receive+0xac>)
|
|
8004f06: 613b str r3, [r7, #16]
|
|
*spidr = SUBGHZ_DUMMY_DATA;
|
|
8004f08: 693b ldr r3, [r7, #16]
|
|
8004f0a: 22ff movs r2, #255 @ 0xff
|
|
8004f0c: 701a strb r2, [r3, #0]
|
|
*((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA;
|
|
#endif /* __GNUC__ */
|
|
|
|
/* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/
|
|
/* Initialize Timeout */
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
|
|
8004f0e: 4b14 ldr r3, [pc, #80] @ (8004f60 <SUBGHZSPI_Receive+0xa4>)
|
|
8004f10: 681a ldr r2, [r3, #0]
|
|
8004f12: 4613 mov r3, r2
|
|
8004f14: 00db lsls r3, r3, #3
|
|
8004f16: 1a9b subs r3, r3, r2
|
|
8004f18: 009b lsls r3, r3, #2
|
|
8004f1a: 0cdb lsrs r3, r3, #19
|
|
8004f1c: 2264 movs r2, #100 @ 0x64
|
|
8004f1e: fb02 f303 mul.w r3, r2, r3
|
|
8004f22: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until RXNE flag is set */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
8004f24: 68fb ldr r3, [r7, #12]
|
|
8004f26: 2b00 cmp r3, #0
|
|
8004f28: d105 bne.n 8004f36 <SUBGHZSPI_Receive+0x7a>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004f2a: 2301 movs r3, #1
|
|
8004f2c: 75fb strb r3, [r7, #23]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
|
|
8004f2e: 687b ldr r3, [r7, #4]
|
|
8004f30: 2201 movs r2, #1
|
|
8004f32: 609a str r2, [r3, #8]
|
|
break;
|
|
8004f34: e008 b.n 8004f48 <SUBGHZSPI_Receive+0x8c>
|
|
}
|
|
count--;
|
|
8004f36: 68fb ldr r3, [r7, #12]
|
|
8004f38: 3b01 subs r3, #1
|
|
8004f3a: 60fb str r3, [r7, #12]
|
|
} while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE));
|
|
8004f3c: 4b09 ldr r3, [pc, #36] @ (8004f64 <SUBGHZSPI_Receive+0xa8>)
|
|
8004f3e: 689b ldr r3, [r3, #8]
|
|
8004f40: f003 0301 and.w r3, r3, #1
|
|
8004f44: 2b01 cmp r3, #1
|
|
8004f46: d1ed bne.n 8004f24 <SUBGHZSPI_Receive+0x68>
|
|
|
|
/* Retrieve pData */
|
|
*pData = (uint8_t)(READ_REG(SUBGHZSPI->DR));
|
|
8004f48: 4b06 ldr r3, [pc, #24] @ (8004f64 <SUBGHZSPI_Receive+0xa8>)
|
|
8004f4a: 68db ldr r3, [r3, #12]
|
|
8004f4c: b2da uxtb r2, r3
|
|
8004f4e: 683b ldr r3, [r7, #0]
|
|
8004f50: 701a strb r2, [r3, #0]
|
|
|
|
return status;
|
|
8004f52: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004f54: 4618 mov r0, r3
|
|
8004f56: 371c adds r7, #28
|
|
8004f58: 46bd mov sp, r7
|
|
8004f5a: bc80 pop {r7}
|
|
8004f5c: 4770 bx lr
|
|
8004f5e: bf00 nop
|
|
8004f60: 20000000 .word 0x20000000
|
|
8004f64: 58010000 .word 0x58010000
|
|
8004f68: 5801000c .word 0x5801000c
|
|
|
|
08004f6c <SUBGHZ_CheckDeviceReady>:
|
|
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
|
|
* the handle information for SUBGHZ module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
8004f6c: b580 push {r7, lr}
|
|
8004f6e: b084 sub sp, #16
|
|
8004f70: af00 add r7, sp, #0
|
|
8004f72: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count;
|
|
|
|
/* Wakeup radio in case of sleep mode: Select-Unselect radio */
|
|
if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE)
|
|
8004f74: 687b ldr r3, [r7, #4]
|
|
8004f76: 791b ldrb r3, [r3, #4]
|
|
8004f78: 2b01 cmp r3, #1
|
|
8004f7a: d10d bne.n 8004f98 <SUBGHZ_CheckDeviceReady+0x2c>
|
|
{
|
|
/* Initialize NSS switch Delay */
|
|
count = SUBGHZ_NSS_LOOP_TIME;
|
|
8004f7c: 4b0a ldr r3, [pc, #40] @ (8004fa8 <SUBGHZ_CheckDeviceReady+0x3c>)
|
|
8004f7e: 681b ldr r3, [r3, #0]
|
|
8004f80: 0c1b lsrs r3, r3, #16
|
|
8004f82: 60fb str r3, [r7, #12]
|
|
|
|
/* NSS = 0; */
|
|
LL_PWR_SelectSUBGHZSPI_NSS();
|
|
8004f84: f7ff fb98 bl 80046b8 <LL_PWR_SelectSUBGHZSPI_NSS>
|
|
|
|
/* Wait Radio wakeup */
|
|
do
|
|
{
|
|
count--;
|
|
8004f88: 68fb ldr r3, [r7, #12]
|
|
8004f8a: 3b01 subs r3, #1
|
|
8004f8c: 60fb str r3, [r7, #12]
|
|
} while (count != 0UL);
|
|
8004f8e: 68fb ldr r3, [r7, #12]
|
|
8004f90: 2b00 cmp r3, #0
|
|
8004f92: d1f9 bne.n 8004f88 <SUBGHZ_CheckDeviceReady+0x1c>
|
|
|
|
/* NSS = 1 */
|
|
LL_PWR_UnselectSUBGHZSPI_NSS();
|
|
8004f94: f7ff fb80 bl 8004698 <LL_PWR_UnselectSUBGHZSPI_NSS>
|
|
}
|
|
return (SUBGHZ_WaitOnBusy(hsubghz));
|
|
8004f98: 6878 ldr r0, [r7, #4]
|
|
8004f9a: f000 f807 bl 8004fac <SUBGHZ_WaitOnBusy>
|
|
8004f9e: 4603 mov r3, r0
|
|
}
|
|
8004fa0: 4618 mov r0, r3
|
|
8004fa2: 3710 adds r7, #16
|
|
8004fa4: 46bd mov sp, r7
|
|
8004fa6: bd80 pop {r7, pc}
|
|
8004fa8: 20000000 .word 0x20000000
|
|
|
|
08004fac <SUBGHZ_WaitOnBusy>:
|
|
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
|
|
* the handle information for SUBGHZ module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
8004fac: b580 push {r7, lr}
|
|
8004fae: b086 sub sp, #24
|
|
8004fb0: af00 add r7, sp, #0
|
|
8004fb2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status;
|
|
__IO uint32_t count;
|
|
uint32_t mask;
|
|
|
|
status = HAL_OK;
|
|
8004fb4: 2300 movs r3, #0
|
|
8004fb6: 75fb strb r3, [r7, #23]
|
|
count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME;
|
|
8004fb8: 4b12 ldr r3, [pc, #72] @ (8005004 <SUBGHZ_WaitOnBusy+0x58>)
|
|
8004fba: 681a ldr r2, [r3, #0]
|
|
8004fbc: 4613 mov r3, r2
|
|
8004fbe: 005b lsls r3, r3, #1
|
|
8004fc0: 4413 add r3, r2
|
|
8004fc2: 00db lsls r3, r3, #3
|
|
8004fc4: 0d1b lsrs r3, r3, #20
|
|
8004fc6: 2264 movs r2, #100 @ 0x64
|
|
8004fc8: fb02 f303 mul.w r3, r2, r3
|
|
8004fcc: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until Busy signal is set */
|
|
do
|
|
{
|
|
mask = LL_PWR_IsActiveFlag_RFBUSYMS();
|
|
8004fce: f7ff fba1 bl 8004714 <LL_PWR_IsActiveFlag_RFBUSYMS>
|
|
8004fd2: 6138 str r0, [r7, #16]
|
|
|
|
if (count == 0U)
|
|
8004fd4: 68fb ldr r3, [r7, #12]
|
|
8004fd6: 2b00 cmp r3, #0
|
|
8004fd8: d105 bne.n 8004fe6 <SUBGHZ_WaitOnBusy+0x3a>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004fda: 2301 movs r3, #1
|
|
8004fdc: 75fb strb r3, [r7, #23]
|
|
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY;
|
|
8004fde: 687b ldr r3, [r7, #4]
|
|
8004fe0: 2202 movs r2, #2
|
|
8004fe2: 609a str r2, [r3, #8]
|
|
break;
|
|
8004fe4: e009 b.n 8004ffa <SUBGHZ_WaitOnBusy+0x4e>
|
|
}
|
|
count--;
|
|
8004fe6: 68fb ldr r3, [r7, #12]
|
|
8004fe8: 3b01 subs r3, #1
|
|
8004fea: 60fb str r3, [r7, #12]
|
|
} while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL);
|
|
8004fec: f7ff fb80 bl 80046f0 <LL_PWR_IsActiveFlag_RFBUSYS>
|
|
8004ff0: 4602 mov r2, r0
|
|
8004ff2: 693b ldr r3, [r7, #16]
|
|
8004ff4: 4013 ands r3, r2
|
|
8004ff6: 2b01 cmp r3, #1
|
|
8004ff8: d0e9 beq.n 8004fce <SUBGHZ_WaitOnBusy+0x22>
|
|
|
|
return status;
|
|
8004ffa: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004ffc: 4618 mov r0, r3
|
|
8004ffe: 3718 adds r7, #24
|
|
8005000: 46bd mov sp, r7
|
|
8005002: bd80 pop {r7, pc}
|
|
8005004: 20000000 .word 0x20000000
|
|
|
|
08005008 <LL_RCC_GetUSARTClockSource>:
|
|
{
|
|
8005008: b480 push {r7}
|
|
800500a: b083 sub sp, #12
|
|
800500c: af00 add r7, sp, #0
|
|
800500e: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16));
|
|
8005010: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005014: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
8005018: 687b ldr r3, [r7, #4]
|
|
800501a: 401a ands r2, r3
|
|
800501c: 687b ldr r3, [r7, #4]
|
|
800501e: 041b lsls r3, r3, #16
|
|
8005020: 4313 orrs r3, r2
|
|
}
|
|
8005022: 4618 mov r0, r3
|
|
8005024: 370c adds r7, #12
|
|
8005026: 46bd mov sp, r7
|
|
8005028: bc80 pop {r7}
|
|
800502a: 4770 bx lr
|
|
|
|
0800502c <LL_RCC_GetLPUARTClockSource>:
|
|
{
|
|
800502c: b480 push {r7}
|
|
800502e: b083 sub sp, #12
|
|
8005030: af00 add r7, sp, #0
|
|
8005032: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
|
|
8005034: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005038: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
800503c: 687b ldr r3, [r7, #4]
|
|
800503e: 4013 ands r3, r2
|
|
}
|
|
8005040: 4618 mov r0, r3
|
|
8005042: 370c adds r7, #12
|
|
8005044: 46bd mov sp, r7
|
|
8005046: bc80 pop {r7}
|
|
8005048: 4770 bx lr
|
|
|
|
0800504a <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
800504a: b580 push {r7, lr}
|
|
800504c: b082 sub sp, #8
|
|
800504e: af00 add r7, sp, #0
|
|
8005050: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005052: 687b ldr r3, [r7, #4]
|
|
8005054: 2b00 cmp r3, #0
|
|
8005056: d101 bne.n 800505c <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005058: 2301 movs r3, #1
|
|
800505a: e042 b.n 80050e2 <HAL_UART_Init+0x98>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
800505c: 687b ldr r3, [r7, #4]
|
|
800505e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005062: 2b00 cmp r3, #0
|
|
8005064: d106 bne.n 8005074 <HAL_UART_Init+0x2a>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005066: 687b ldr r3, [r7, #4]
|
|
8005068: 2200 movs r2, #0
|
|
800506a: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
800506e: 6878 ldr r0, [r7, #4]
|
|
8005070: f7fc f8e6 bl 8001240 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005074: 687b ldr r3, [r7, #4]
|
|
8005076: 2224 movs r2, #36 @ 0x24
|
|
8005078: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
800507c: 687b ldr r3, [r7, #4]
|
|
800507e: 681b ldr r3, [r3, #0]
|
|
8005080: 681a ldr r2, [r3, #0]
|
|
8005082: 687b ldr r3, [r7, #4]
|
|
8005084: 681b ldr r3, [r3, #0]
|
|
8005086: f022 0201 bic.w r2, r2, #1
|
|
800508a: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
800508c: 687b ldr r3, [r7, #4]
|
|
800508e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005090: 2b00 cmp r3, #0
|
|
8005092: d002 beq.n 800509a <HAL_UART_Init+0x50>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8005094: 6878 ldr r0, [r7, #4]
|
|
8005096: f000 fec9 bl 8005e2c <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
800509a: 6878 ldr r0, [r7, #4]
|
|
800509c: f000 fc52 bl 8005944 <UART_SetConfig>
|
|
80050a0: 4603 mov r3, r0
|
|
80050a2: 2b01 cmp r3, #1
|
|
80050a4: d101 bne.n 80050aa <HAL_UART_Init+0x60>
|
|
{
|
|
return HAL_ERROR;
|
|
80050a6: 2301 movs r3, #1
|
|
80050a8: e01b b.n 80050e2 <HAL_UART_Init+0x98>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
80050aa: 687b ldr r3, [r7, #4]
|
|
80050ac: 681b ldr r3, [r3, #0]
|
|
80050ae: 685a ldr r2, [r3, #4]
|
|
80050b0: 687b ldr r3, [r7, #4]
|
|
80050b2: 681b ldr r3, [r3, #0]
|
|
80050b4: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
80050b8: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
80050ba: 687b ldr r3, [r7, #4]
|
|
80050bc: 681b ldr r3, [r3, #0]
|
|
80050be: 689a ldr r2, [r3, #8]
|
|
80050c0: 687b ldr r3, [r7, #4]
|
|
80050c2: 681b ldr r3, [r3, #0]
|
|
80050c4: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
80050c8: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
80050ca: 687b ldr r3, [r7, #4]
|
|
80050cc: 681b ldr r3, [r3, #0]
|
|
80050ce: 681a ldr r2, [r3, #0]
|
|
80050d0: 687b ldr r3, [r7, #4]
|
|
80050d2: 681b ldr r3, [r3, #0]
|
|
80050d4: f042 0201 orr.w r2, r2, #1
|
|
80050d8: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
80050da: 6878 ldr r0, [r7, #4]
|
|
80050dc: f000 ff47 bl 8005f6e <UART_CheckIdleState>
|
|
80050e0: 4603 mov r3, r0
|
|
}
|
|
80050e2: 4618 mov r0, r3
|
|
80050e4: 3708 adds r7, #8
|
|
80050e6: 46bd mov sp, r7
|
|
80050e8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080050ec <HAL_UART_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
80050ec: b580 push {r7, lr}
|
|
80050ee: b08a sub sp, #40 @ 0x28
|
|
80050f0: af00 add r7, sp, #0
|
|
80050f2: 60f8 str r0, [r7, #12]
|
|
80050f4: 60b9 str r1, [r7, #8]
|
|
80050f6: 4613 mov r3, r2
|
|
80050f8: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
80050fa: 68fb ldr r3, [r7, #12]
|
|
80050fc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8005100: 2b20 cmp r3, #32
|
|
8005102: d137 bne.n 8005174 <HAL_UART_Receive_IT+0x88>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005104: 68bb ldr r3, [r7, #8]
|
|
8005106: 2b00 cmp r3, #0
|
|
8005108: d002 beq.n 8005110 <HAL_UART_Receive_IT+0x24>
|
|
800510a: 88fb ldrh r3, [r7, #6]
|
|
800510c: 2b00 cmp r3, #0
|
|
800510e: d101 bne.n 8005114 <HAL_UART_Receive_IT+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8005110: 2301 movs r3, #1
|
|
8005112: e030 b.n 8005176 <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
}
|
|
|
|
#endif /* CORE_CM0PLUS */
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005114: 68fb ldr r3, [r7, #12]
|
|
8005116: 2200 movs r2, #0
|
|
8005118: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
800511a: 68fb ldr r3, [r7, #12]
|
|
800511c: 681b ldr r3, [r3, #0]
|
|
800511e: 4a18 ldr r2, [pc, #96] @ (8005180 <HAL_UART_Receive_IT+0x94>)
|
|
8005120: 4293 cmp r3, r2
|
|
8005122: d01f beq.n 8005164 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8005124: 68fb ldr r3, [r7, #12]
|
|
8005126: 681b ldr r3, [r3, #0]
|
|
8005128: 685b ldr r3, [r3, #4]
|
|
800512a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
800512e: 2b00 cmp r3, #0
|
|
8005130: d018 beq.n 8005164 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8005132: 68fb ldr r3, [r7, #12]
|
|
8005134: 681b ldr r3, [r3, #0]
|
|
8005136: 617b str r3, [r7, #20]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005138: 697b ldr r3, [r7, #20]
|
|
800513a: e853 3f00 ldrex r3, [r3]
|
|
800513e: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005140: 693b ldr r3, [r7, #16]
|
|
8005142: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8005146: 627b str r3, [r7, #36] @ 0x24
|
|
8005148: 68fb ldr r3, [r7, #12]
|
|
800514a: 681b ldr r3, [r3, #0]
|
|
800514c: 461a mov r2, r3
|
|
800514e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005150: 623b str r3, [r7, #32]
|
|
8005152: 61fa str r2, [r7, #28]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005154: 69f9 ldr r1, [r7, #28]
|
|
8005156: 6a3a ldr r2, [r7, #32]
|
|
8005158: e841 2300 strex r3, r2, [r1]
|
|
800515c: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
800515e: 69bb ldr r3, [r7, #24]
|
|
8005160: 2b00 cmp r3, #0
|
|
8005162: d1e6 bne.n 8005132 <HAL_UART_Receive_IT+0x46>
|
|
}
|
|
}
|
|
|
|
return (UART_Start_Receive_IT(huart, pData, Size));
|
|
8005164: 88fb ldrh r3, [r7, #6]
|
|
8005166: 461a mov r2, r3
|
|
8005168: 68b9 ldr r1, [r7, #8]
|
|
800516a: 68f8 ldr r0, [r7, #12]
|
|
800516c: f001 f816 bl 800619c <UART_Start_Receive_IT>
|
|
8005170: 4603 mov r3, r0
|
|
8005172: e000 b.n 8005176 <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005174: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005176: 4618 mov r0, r3
|
|
8005178: 3728 adds r7, #40 @ 0x28
|
|
800517a: 46bd mov sp, r7
|
|
800517c: bd80 pop {r7, pc}
|
|
800517e: bf00 nop
|
|
8005180: 40008000 .word 0x40008000
|
|
|
|
08005184 <HAL_UART_Transmit_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005184: b580 push {r7, lr}
|
|
8005186: b08a sub sp, #40 @ 0x28
|
|
8005188: af00 add r7, sp, #0
|
|
800518a: 60f8 str r0, [r7, #12]
|
|
800518c: 60b9 str r1, [r7, #8]
|
|
800518e: 4613 mov r3, r2
|
|
8005190: 80fb strh r3, [r7, #6]
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8005192: 68fb ldr r3, [r7, #12]
|
|
8005194: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005198: 2b20 cmp r3, #32
|
|
800519a: d167 bne.n 800526c <HAL_UART_Transmit_DMA+0xe8>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
800519c: 68bb ldr r3, [r7, #8]
|
|
800519e: 2b00 cmp r3, #0
|
|
80051a0: d002 beq.n 80051a8 <HAL_UART_Transmit_DMA+0x24>
|
|
80051a2: 88fb ldrh r3, [r7, #6]
|
|
80051a4: 2b00 cmp r3, #0
|
|
80051a6: d101 bne.n 80051ac <HAL_UART_Transmit_DMA+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
80051a8: 2301 movs r3, #1
|
|
80051aa: e060 b.n 800526e <HAL_UART_Transmit_DMA+0xea>
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
#endif /* CORE_CM0PLUS */
|
|
huart->pTxBuffPtr = pData;
|
|
80051ac: 68fb ldr r3, [r7, #12]
|
|
80051ae: 68ba ldr r2, [r7, #8]
|
|
80051b0: 651a str r2, [r3, #80] @ 0x50
|
|
huart->TxXferSize = Size;
|
|
80051b2: 68fb ldr r3, [r7, #12]
|
|
80051b4: 88fa ldrh r2, [r7, #6]
|
|
80051b6: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
|
|
huart->TxXferCount = Size;
|
|
80051ba: 68fb ldr r3, [r7, #12]
|
|
80051bc: 88fa ldrh r2, [r7, #6]
|
|
80051be: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80051c2: 68fb ldr r3, [r7, #12]
|
|
80051c4: 2200 movs r2, #0
|
|
80051c6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
80051ca: 68fb ldr r3, [r7, #12]
|
|
80051cc: 2221 movs r2, #33 @ 0x21
|
|
80051ce: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
if (huart->hdmatx != NULL)
|
|
80051d2: 68fb ldr r3, [r7, #12]
|
|
80051d4: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80051d6: 2b00 cmp r3, #0
|
|
80051d8: d028 beq.n 800522c <HAL_UART_Transmit_DMA+0xa8>
|
|
{
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
|
|
80051da: 68fb ldr r3, [r7, #12]
|
|
80051dc: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80051de: 4a26 ldr r2, [pc, #152] @ (8005278 <HAL_UART_Transmit_DMA+0xf4>)
|
|
80051e0: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
|
|
80051e2: 68fb ldr r3, [r7, #12]
|
|
80051e4: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80051e6: 4a25 ldr r2, [pc, #148] @ (800527c <HAL_UART_Transmit_DMA+0xf8>)
|
|
80051e8: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmatx->XferErrorCallback = UART_DMAError;
|
|
80051ea: 68fb ldr r3, [r7, #12]
|
|
80051ec: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80051ee: 4a24 ldr r2, [pc, #144] @ (8005280 <HAL_UART_Transmit_DMA+0xfc>)
|
|
80051f0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmatx->XferAbortCallback = NULL;
|
|
80051f2: 68fb ldr r3, [r7, #12]
|
|
80051f4: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80051f6: 2200 movs r2, #0
|
|
80051f8: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Enable the UART transmit DMA channel */
|
|
if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
|
|
80051fa: 68fb ldr r3, [r7, #12]
|
|
80051fc: 6fd8 ldr r0, [r3, #124] @ 0x7c
|
|
80051fe: 68fb ldr r3, [r7, #12]
|
|
8005200: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8005202: 4619 mov r1, r3
|
|
8005204: 68fb ldr r3, [r7, #12]
|
|
8005206: 681b ldr r3, [r3, #0]
|
|
8005208: 3328 adds r3, #40 @ 0x28
|
|
800520a: 461a mov r2, r3
|
|
800520c: 88fb ldrh r3, [r7, #6]
|
|
800520e: f7fc fd91 bl 8001d34 <HAL_DMA_Start_IT>
|
|
8005212: 4603 mov r3, r0
|
|
8005214: 2b00 cmp r3, #0
|
|
8005216: d009 beq.n 800522c <HAL_UART_Transmit_DMA+0xa8>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8005218: 68fb ldr r3, [r7, #12]
|
|
800521a: 2210 movs r2, #16
|
|
800521c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Restore huart->gState to ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005220: 68fb ldr r3, [r7, #12]
|
|
8005222: 2220 movs r2, #32
|
|
8005224: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
return HAL_ERROR;
|
|
8005228: 2301 movs r3, #1
|
|
800522a: e020 b.n 800526e <HAL_UART_Transmit_DMA+0xea>
|
|
}
|
|
}
|
|
/* Clear the TC flag in the ICR register */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
|
|
800522c: 68fb ldr r3, [r7, #12]
|
|
800522e: 681b ldr r3, [r3, #0]
|
|
8005230: 2240 movs r2, #64 @ 0x40
|
|
8005232: 621a str r2, [r3, #32]
|
|
|
|
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8005234: 68fb ldr r3, [r7, #12]
|
|
8005236: 681b ldr r3, [r3, #0]
|
|
8005238: 3308 adds r3, #8
|
|
800523a: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800523c: 697b ldr r3, [r7, #20]
|
|
800523e: e853 3f00 ldrex r3, [r3]
|
|
8005242: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005244: 693b ldr r3, [r7, #16]
|
|
8005246: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800524a: 627b str r3, [r7, #36] @ 0x24
|
|
800524c: 68fb ldr r3, [r7, #12]
|
|
800524e: 681b ldr r3, [r3, #0]
|
|
8005250: 3308 adds r3, #8
|
|
8005252: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8005254: 623a str r2, [r7, #32]
|
|
8005256: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005258: 69f9 ldr r1, [r7, #28]
|
|
800525a: 6a3a ldr r2, [r7, #32]
|
|
800525c: e841 2300 strex r3, r2, [r1]
|
|
8005260: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8005262: 69bb ldr r3, [r7, #24]
|
|
8005264: 2b00 cmp r3, #0
|
|
8005266: d1e5 bne.n 8005234 <HAL_UART_Transmit_DMA+0xb0>
|
|
|
|
return HAL_OK;
|
|
8005268: 2300 movs r3, #0
|
|
800526a: e000 b.n 800526e <HAL_UART_Transmit_DMA+0xea>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800526c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800526e: 4618 mov r0, r3
|
|
8005270: 3728 adds r7, #40 @ 0x28
|
|
8005272: 46bd mov sp, r7
|
|
8005274: bd80 pop {r7, pc}
|
|
8005276: bf00 nop
|
|
8005278: 08006527 .word 0x08006527
|
|
800527c: 080065b9 .word 0x080065b9
|
|
8005280: 080065d5 .word 0x080065d5
|
|
|
|
08005284 <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8005284: b580 push {r7, lr}
|
|
8005286: b0ba sub sp, #232 @ 0xe8
|
|
8005288: af00 add r7, sp, #0
|
|
800528a: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
800528c: 687b ldr r3, [r7, #4]
|
|
800528e: 681b ldr r3, [r3, #0]
|
|
8005290: 69db ldr r3, [r3, #28]
|
|
8005292: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8005296: 687b ldr r3, [r7, #4]
|
|
8005298: 681b ldr r3, [r3, #0]
|
|
800529a: 681b ldr r3, [r3, #0]
|
|
800529c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
80052a0: 687b ldr r3, [r7, #4]
|
|
80052a2: 681b ldr r3, [r3, #0]
|
|
80052a4: 689b ldr r3, [r3, #8]
|
|
80052a6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
80052aa: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
|
|
80052ae: f640 030f movw r3, #2063 @ 0x80f
|
|
80052b2: 4013 ands r3, r2
|
|
80052b4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == 0U)
|
|
80052b8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80052bc: 2b00 cmp r3, #0
|
|
80052be: d11b bne.n 80052f8 <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
/* UART in mode Receiver ---------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
80052c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80052c4: f003 0320 and.w r3, r3, #32
|
|
80052c8: 2b00 cmp r3, #0
|
|
80052ca: d015 beq.n 80052f8 <HAL_UART_IRQHandler+0x74>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
80052cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80052d0: f003 0320 and.w r3, r3, #32
|
|
80052d4: 2b00 cmp r3, #0
|
|
80052d6: d105 bne.n 80052e4 <HAL_UART_IRQHandler+0x60>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
80052d8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80052dc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80052e0: 2b00 cmp r3, #0
|
|
80052e2: d009 beq.n 80052f8 <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
80052e4: 687b ldr r3, [r7, #4]
|
|
80052e6: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80052e8: 2b00 cmp r3, #0
|
|
80052ea: f000 8300 beq.w 80058ee <HAL_UART_IRQHandler+0x66a>
|
|
{
|
|
huart->RxISR(huart);
|
|
80052ee: 687b ldr r3, [r7, #4]
|
|
80052f0: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80052f2: 6878 ldr r0, [r7, #4]
|
|
80052f4: 4798 blx r3
|
|
}
|
|
return;
|
|
80052f6: e2fa b.n 80058ee <HAL_UART_IRQHandler+0x66a>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != 0U)
|
|
80052f8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80052fc: 2b00 cmp r3, #0
|
|
80052fe: f000 8123 beq.w 8005548 <HAL_UART_IRQHandler+0x2c4>
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
8005302: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
8005306: 4b8d ldr r3, [pc, #564] @ (800553c <HAL_UART_IRQHandler+0x2b8>)
|
|
8005308: 4013 ands r3, r2
|
|
800530a: 2b00 cmp r3, #0
|
|
800530c: d106 bne.n 800531c <HAL_UART_IRQHandler+0x98>
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
800530e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
|
|
8005312: 4b8b ldr r3, [pc, #556] @ (8005540 <HAL_UART_IRQHandler+0x2bc>)
|
|
8005314: 4013 ands r3, r2
|
|
8005316: 2b00 cmp r3, #0
|
|
8005318: f000 8116 beq.w 8005548 <HAL_UART_IRQHandler+0x2c4>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
800531c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005320: f003 0301 and.w r3, r3, #1
|
|
8005324: 2b00 cmp r3, #0
|
|
8005326: d011 beq.n 800534c <HAL_UART_IRQHandler+0xc8>
|
|
8005328: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800532c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005330: 2b00 cmp r3, #0
|
|
8005332: d00b beq.n 800534c <HAL_UART_IRQHandler+0xc8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8005334: 687b ldr r3, [r7, #4]
|
|
8005336: 681b ldr r3, [r3, #0]
|
|
8005338: 2201 movs r2, #1
|
|
800533a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
800533c: 687b ldr r3, [r7, #4]
|
|
800533e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005342: f043 0201 orr.w r2, r3, #1
|
|
8005346: 687b ldr r3, [r7, #4]
|
|
8005348: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800534c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005350: f003 0302 and.w r3, r3, #2
|
|
8005354: 2b00 cmp r3, #0
|
|
8005356: d011 beq.n 800537c <HAL_UART_IRQHandler+0xf8>
|
|
8005358: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800535c: f003 0301 and.w r3, r3, #1
|
|
8005360: 2b00 cmp r3, #0
|
|
8005362: d00b beq.n 800537c <HAL_UART_IRQHandler+0xf8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8005364: 687b ldr r3, [r7, #4]
|
|
8005366: 681b ldr r3, [r3, #0]
|
|
8005368: 2202 movs r2, #2
|
|
800536a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
800536c: 687b ldr r3, [r7, #4]
|
|
800536e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005372: f043 0204 orr.w r2, r3, #4
|
|
8005376: 687b ldr r3, [r7, #4]
|
|
8005378: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800537c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005380: f003 0304 and.w r3, r3, #4
|
|
8005384: 2b00 cmp r3, #0
|
|
8005386: d011 beq.n 80053ac <HAL_UART_IRQHandler+0x128>
|
|
8005388: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800538c: f003 0301 and.w r3, r3, #1
|
|
8005390: 2b00 cmp r3, #0
|
|
8005392: d00b beq.n 80053ac <HAL_UART_IRQHandler+0x128>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8005394: 687b ldr r3, [r7, #4]
|
|
8005396: 681b ldr r3, [r3, #0]
|
|
8005398: 2204 movs r2, #4
|
|
800539a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
800539c: 687b ldr r3, [r7, #4]
|
|
800539e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80053a2: f043 0202 orr.w r2, r3, #2
|
|
80053a6: 687b ldr r3, [r7, #4]
|
|
80053a8: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred -----------------------------------------*/
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
80053ac: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80053b0: f003 0308 and.w r3, r3, #8
|
|
80053b4: 2b00 cmp r3, #0
|
|
80053b6: d017 beq.n 80053e8 <HAL_UART_IRQHandler+0x164>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
80053b8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80053bc: f003 0320 and.w r3, r3, #32
|
|
80053c0: 2b00 cmp r3, #0
|
|
80053c2: d105 bne.n 80053d0 <HAL_UART_IRQHandler+0x14c>
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
80053c4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
80053c8: 4b5c ldr r3, [pc, #368] @ (800553c <HAL_UART_IRQHandler+0x2b8>)
|
|
80053ca: 4013 ands r3, r2
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
80053cc: 2b00 cmp r3, #0
|
|
80053ce: d00b beq.n 80053e8 <HAL_UART_IRQHandler+0x164>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
80053d0: 687b ldr r3, [r7, #4]
|
|
80053d2: 681b ldr r3, [r3, #0]
|
|
80053d4: 2208 movs r2, #8
|
|
80053d6: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
80053d8: 687b ldr r3, [r7, #4]
|
|
80053da: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80053de: f043 0208 orr.w r2, r3, #8
|
|
80053e2: 687b ldr r3, [r7, #4]
|
|
80053e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
80053e8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80053ec: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80053f0: 2b00 cmp r3, #0
|
|
80053f2: d012 beq.n 800541a <HAL_UART_IRQHandler+0x196>
|
|
80053f4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80053f8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
80053fc: 2b00 cmp r3, #0
|
|
80053fe: d00c beq.n 800541a <HAL_UART_IRQHandler+0x196>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8005400: 687b ldr r3, [r7, #4]
|
|
8005402: 681b ldr r3, [r3, #0]
|
|
8005404: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8005408: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
800540a: 687b ldr r3, [r7, #4]
|
|
800540c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005410: f043 0220 orr.w r2, r3, #32
|
|
8005414: 687b ldr r3, [r7, #4]
|
|
8005416: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800541a: 687b ldr r3, [r7, #4]
|
|
800541c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005420: 2b00 cmp r3, #0
|
|
8005422: f000 8266 beq.w 80058f2 <HAL_UART_IRQHandler+0x66e>
|
|
{
|
|
/* UART in mode Receiver --------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
8005426: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800542a: f003 0320 and.w r3, r3, #32
|
|
800542e: 2b00 cmp r3, #0
|
|
8005430: d013 beq.n 800545a <HAL_UART_IRQHandler+0x1d6>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
8005432: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005436: f003 0320 and.w r3, r3, #32
|
|
800543a: 2b00 cmp r3, #0
|
|
800543c: d105 bne.n 800544a <HAL_UART_IRQHandler+0x1c6>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
800543e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005442: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005446: 2b00 cmp r3, #0
|
|
8005448: d007 beq.n 800545a <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
800544a: 687b ldr r3, [r7, #4]
|
|
800544c: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800544e: 2b00 cmp r3, #0
|
|
8005450: d003 beq.n 800545a <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
huart->RxISR(huart);
|
|
8005452: 687b ldr r3, [r7, #4]
|
|
8005454: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005456: 6878 ldr r0, [r7, #4]
|
|
8005458: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
800545a: 687b ldr r3, [r7, #4]
|
|
800545c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005460: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8005464: 687b ldr r3, [r7, #4]
|
|
8005466: 681b ldr r3, [r3, #0]
|
|
8005468: 689b ldr r3, [r3, #8]
|
|
800546a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800546e: 2b40 cmp r3, #64 @ 0x40
|
|
8005470: d005 beq.n 800547e <HAL_UART_IRQHandler+0x1fa>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
8005472: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
8005476: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800547a: 2b00 cmp r3, #0
|
|
800547c: d054 beq.n 8005528 <HAL_UART_IRQHandler+0x2a4>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
800547e: 6878 ldr r0, [r7, #4]
|
|
8005480: f000 ffec bl 800645c <UART_EndRxTransfer>
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005484: 687b ldr r3, [r7, #4]
|
|
8005486: 681b ldr r3, [r3, #0]
|
|
8005488: 689b ldr r3, [r3, #8]
|
|
800548a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800548e: 2b40 cmp r3, #64 @ 0x40
|
|
8005490: d146 bne.n 8005520 <HAL_UART_IRQHandler+0x29c>
|
|
{
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005492: 687b ldr r3, [r7, #4]
|
|
8005494: 681b ldr r3, [r3, #0]
|
|
8005496: 3308 adds r3, #8
|
|
8005498: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800549c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80054a0: e853 3f00 ldrex r3, [r3]
|
|
80054a4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
80054a8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80054ac: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80054b0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80054b4: 687b ldr r3, [r7, #4]
|
|
80054b6: 681b ldr r3, [r3, #0]
|
|
80054b8: 3308 adds r3, #8
|
|
80054ba: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
80054be: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
80054c2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054c6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
80054ca: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
80054ce: e841 2300 strex r3, r2, [r1]
|
|
80054d2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
80054d6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
80054da: 2b00 cmp r3, #0
|
|
80054dc: d1d9 bne.n 8005492 <HAL_UART_IRQHandler+0x20e>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
80054de: 687b ldr r3, [r7, #4]
|
|
80054e0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80054e4: 2b00 cmp r3, #0
|
|
80054e6: d017 beq.n 8005518 <HAL_UART_IRQHandler+0x294>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
80054e8: 687b ldr r3, [r7, #4]
|
|
80054ea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80054ee: 4a15 ldr r2, [pc, #84] @ (8005544 <HAL_UART_IRQHandler+0x2c0>)
|
|
80054f0: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
80054f2: 687b ldr r3, [r7, #4]
|
|
80054f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80054f8: 4618 mov r0, r3
|
|
80054fa: f7fc fcf7 bl 8001eec <HAL_DMA_Abort_IT>
|
|
80054fe: 4603 mov r3, r0
|
|
8005500: 2b00 cmp r3, #0
|
|
8005502: d019 beq.n 8005538 <HAL_UART_IRQHandler+0x2b4>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8005504: 687b ldr r3, [r7, #4]
|
|
8005506: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800550a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800550c: 687a ldr r2, [r7, #4]
|
|
800550e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
|
|
8005512: 4610 mov r0, r2
|
|
8005514: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005516: e00f b.n 8005538 <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005518: 6878 ldr r0, [r7, #4]
|
|
800551a: f000 f9fe bl 800591a <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800551e: e00b b.n 8005538 <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005520: 6878 ldr r0, [r7, #4]
|
|
8005522: f000 f9fa bl 800591a <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005526: e007 b.n 8005538 <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005528: 6878 ldr r0, [r7, #4]
|
|
800552a: f000 f9f6 bl 800591a <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800552e: 687b ldr r3, [r7, #4]
|
|
8005530: 2200 movs r2, #0
|
|
8005532: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
return;
|
|
8005536: e1dc b.n 80058f2 <HAL_UART_IRQHandler+0x66e>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005538: bf00 nop
|
|
return;
|
|
800553a: e1da b.n 80058f2 <HAL_UART_IRQHandler+0x66e>
|
|
800553c: 10000001 .word 0x10000001
|
|
8005540: 04000120 .word 0x04000120
|
|
8005544: 08006645 .word 0x08006645
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005548: 687b ldr r3, [r7, #4]
|
|
800554a: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
800554c: 2b01 cmp r3, #1
|
|
800554e: f040 8170 bne.w 8005832 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
8005552: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005556: f003 0310 and.w r3, r3, #16
|
|
800555a: 2b00 cmp r3, #0
|
|
800555c: f000 8169 beq.w 8005832 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
8005560: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005564: f003 0310 and.w r3, r3, #16
|
|
8005568: 2b00 cmp r3, #0
|
|
800556a: f000 8162 beq.w 8005832 <HAL_UART_IRQHandler+0x5ae>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800556e: 687b ldr r3, [r7, #4]
|
|
8005570: 681b ldr r3, [r3, #0]
|
|
8005572: 2210 movs r2, #16
|
|
8005574: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005576: 687b ldr r3, [r7, #4]
|
|
8005578: 681b ldr r3, [r3, #0]
|
|
800557a: 689b ldr r3, [r3, #8]
|
|
800557c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005580: 2b40 cmp r3, #64 @ 0x40
|
|
8005582: f040 80d8 bne.w 8005736 <HAL_UART_IRQHandler+0x4b2>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8005586: 687b ldr r3, [r7, #4]
|
|
8005588: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800558c: 681b ldr r3, [r3, #0]
|
|
800558e: 685b ldr r3, [r3, #4]
|
|
8005590: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8005594: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
8005598: 2b00 cmp r3, #0
|
|
800559a: f000 80af beq.w 80056fc <HAL_UART_IRQHandler+0x478>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
800559e: 687b ldr r3, [r7, #4]
|
|
80055a0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80055a4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80055a8: 429a cmp r2, r3
|
|
80055aa: f080 80a7 bcs.w 80056fc <HAL_UART_IRQHandler+0x478>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
80055ae: 687b ldr r3, [r7, #4]
|
|
80055b0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80055b4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
80055b8: 687b ldr r3, [r7, #4]
|
|
80055ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80055be: 681b ldr r3, [r3, #0]
|
|
80055c0: 681b ldr r3, [r3, #0]
|
|
80055c2: f003 0320 and.w r3, r3, #32
|
|
80055c6: 2b00 cmp r3, #0
|
|
80055c8: f040 8087 bne.w 80056da <HAL_UART_IRQHandler+0x456>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80055cc: 687b ldr r3, [r7, #4]
|
|
80055ce: 681b ldr r3, [r3, #0]
|
|
80055d0: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80055d4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
80055d8: e853 3f00 ldrex r3, [r3]
|
|
80055dc: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
80055e0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
80055e4: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80055e8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
80055ec: 687b ldr r3, [r7, #4]
|
|
80055ee: 681b ldr r3, [r3, #0]
|
|
80055f0: 461a mov r2, r3
|
|
80055f2: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80055f6: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80055fa: f8c7 2090 str.w r2, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80055fe: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8005602: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8005606: e841 2300 strex r3, r2, [r1]
|
|
800560a: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
800560e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8005612: 2b00 cmp r3, #0
|
|
8005614: d1da bne.n 80055cc <HAL_UART_IRQHandler+0x348>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005616: 687b ldr r3, [r7, #4]
|
|
8005618: 681b ldr r3, [r3, #0]
|
|
800561a: 3308 adds r3, #8
|
|
800561c: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800561e: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8005620: e853 3f00 ldrex r3, [r3]
|
|
8005624: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8005626: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8005628: f023 0301 bic.w r3, r3, #1
|
|
800562c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8005630: 687b ldr r3, [r7, #4]
|
|
8005632: 681b ldr r3, [r3, #0]
|
|
8005634: 3308 adds r3, #8
|
|
8005636: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
800563a: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
800563e: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005640: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8005642: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8005646: e841 2300 strex r3, r2, [r1]
|
|
800564a: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
800564c: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800564e: 2b00 cmp r3, #0
|
|
8005650: d1e1 bne.n 8005616 <HAL_UART_IRQHandler+0x392>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005652: 687b ldr r3, [r7, #4]
|
|
8005654: 681b ldr r3, [r3, #0]
|
|
8005656: 3308 adds r3, #8
|
|
8005658: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800565a: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800565c: e853 3f00 ldrex r3, [r3]
|
|
8005660: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8005662: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005664: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005668: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
800566c: 687b ldr r3, [r7, #4]
|
|
800566e: 681b ldr r3, [r3, #0]
|
|
8005670: 3308 adds r3, #8
|
|
8005672: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
8005676: 66fa str r2, [r7, #108] @ 0x6c
|
|
8005678: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800567a: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
800567c: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
800567e: e841 2300 strex r3, r2, [r1]
|
|
8005682: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8005684: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8005686: 2b00 cmp r3, #0
|
|
8005688: d1e3 bne.n 8005652 <HAL_UART_IRQHandler+0x3ce>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800568a: 687b ldr r3, [r7, #4]
|
|
800568c: 2220 movs r2, #32
|
|
800568e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005692: 687b ldr r3, [r7, #4]
|
|
8005694: 2200 movs r2, #0
|
|
8005696: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005698: 687b ldr r3, [r7, #4]
|
|
800569a: 681b ldr r3, [r3, #0]
|
|
800569c: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800569e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80056a0: e853 3f00 ldrex r3, [r3]
|
|
80056a4: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80056a6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80056a8: f023 0310 bic.w r3, r3, #16
|
|
80056ac: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
80056b0: 687b ldr r3, [r7, #4]
|
|
80056b2: 681b ldr r3, [r3, #0]
|
|
80056b4: 461a mov r2, r3
|
|
80056b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80056ba: 65bb str r3, [r7, #88] @ 0x58
|
|
80056bc: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80056be: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80056c0: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80056c2: e841 2300 strex r3, r2, [r1]
|
|
80056c6: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80056c8: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80056ca: 2b00 cmp r3, #0
|
|
80056cc: d1e4 bne.n 8005698 <HAL_UART_IRQHandler+0x414>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
80056ce: 687b ldr r3, [r7, #4]
|
|
80056d0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80056d4: 4618 mov r0, r3
|
|
80056d6: f7fc fbab bl 8001e30 <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80056da: 687b ldr r3, [r7, #4]
|
|
80056dc: 2202 movs r2, #2
|
|
80056de: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
80056e0: 687b ldr r3, [r7, #4]
|
|
80056e2: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
80056e6: 687b ldr r3, [r7, #4]
|
|
80056e8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80056ec: b29b uxth r3, r3
|
|
80056ee: 1ad3 subs r3, r2, r3
|
|
80056f0: b29b uxth r3, r3
|
|
80056f2: 4619 mov r1, r3
|
|
80056f4: 6878 ldr r0, [r7, #4]
|
|
80056f6: f000 f919 bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
80056fa: e0fc b.n 80058f6 <HAL_UART_IRQHandler+0x672>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
80056fc: 687b ldr r3, [r7, #4]
|
|
80056fe: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8005702: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005706: 429a cmp r2, r3
|
|
8005708: f040 80f5 bne.w 80058f6 <HAL_UART_IRQHandler+0x672>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
800570c: 687b ldr r3, [r7, #4]
|
|
800570e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8005712: 681b ldr r3, [r3, #0]
|
|
8005714: 681b ldr r3, [r3, #0]
|
|
8005716: f003 0320 and.w r3, r3, #32
|
|
800571a: 2b20 cmp r3, #32
|
|
800571c: f040 80eb bne.w 80058f6 <HAL_UART_IRQHandler+0x672>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8005720: 687b ldr r3, [r7, #4]
|
|
8005722: 2202 movs r2, #2
|
|
8005724: 671a str r2, [r3, #112] @ 0x70
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8005726: 687b ldr r3, [r7, #4]
|
|
8005728: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
800572c: 4619 mov r1, r3
|
|
800572e: 6878 ldr r0, [r7, #4]
|
|
8005730: f000 f8fc bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
8005734: e0df b.n 80058f6 <HAL_UART_IRQHandler+0x672>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
8005736: 687b ldr r3, [r7, #4]
|
|
8005738: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
800573c: 687b ldr r3, [r7, #4]
|
|
800573e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8005742: b29b uxth r3, r3
|
|
8005744: 1ad3 subs r3, r2, r3
|
|
8005746: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
800574a: 687b ldr r3, [r7, #4]
|
|
800574c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8005750: b29b uxth r3, r3
|
|
8005752: 2b00 cmp r3, #0
|
|
8005754: f000 80d1 beq.w 80058fa <HAL_UART_IRQHandler+0x676>
|
|
&& (nb_rx_data > 0U))
|
|
8005758: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
800575c: 2b00 cmp r3, #0
|
|
800575e: f000 80cc beq.w 80058fa <HAL_UART_IRQHandler+0x676>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8005762: 687b ldr r3, [r7, #4]
|
|
8005764: 681b ldr r3, [r3, #0]
|
|
8005766: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005768: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800576a: e853 3f00 ldrex r3, [r3]
|
|
800576e: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8005770: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8005772: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8005776: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
800577a: 687b ldr r3, [r7, #4]
|
|
800577c: 681b ldr r3, [r3, #0]
|
|
800577e: 461a mov r2, r3
|
|
8005780: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8005784: 647b str r3, [r7, #68] @ 0x44
|
|
8005786: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005788: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
800578a: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800578c: e841 2300 strex r3, r2, [r1]
|
|
8005790: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8005792: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8005794: 2b00 cmp r3, #0
|
|
8005796: d1e4 bne.n 8005762 <HAL_UART_IRQHandler+0x4de>
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8005798: 687b ldr r3, [r7, #4]
|
|
800579a: 681b ldr r3, [r3, #0]
|
|
800579c: 3308 adds r3, #8
|
|
800579e: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80057a0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80057a2: e853 3f00 ldrex r3, [r3]
|
|
80057a6: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80057a8: 6a3b ldr r3, [r7, #32]
|
|
80057aa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80057ae: f023 0301 bic.w r3, r3, #1
|
|
80057b2: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
80057b6: 687b ldr r3, [r7, #4]
|
|
80057b8: 681b ldr r3, [r3, #0]
|
|
80057ba: 3308 adds r3, #8
|
|
80057bc: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
80057c0: 633a str r2, [r7, #48] @ 0x30
|
|
80057c2: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80057c4: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80057c6: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80057c8: e841 2300 strex r3, r2, [r1]
|
|
80057cc: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80057ce: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80057d0: 2b00 cmp r3, #0
|
|
80057d2: d1e1 bne.n 8005798 <HAL_UART_IRQHandler+0x514>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80057d4: 687b ldr r3, [r7, #4]
|
|
80057d6: 2220 movs r2, #32
|
|
80057d8: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80057dc: 687b ldr r3, [r7, #4]
|
|
80057de: 2200 movs r2, #0
|
|
80057e0: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
80057e2: 687b ldr r3, [r7, #4]
|
|
80057e4: 2200 movs r2, #0
|
|
80057e6: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80057e8: 687b ldr r3, [r7, #4]
|
|
80057ea: 681b ldr r3, [r3, #0]
|
|
80057ec: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80057ee: 693b ldr r3, [r7, #16]
|
|
80057f0: e853 3f00 ldrex r3, [r3]
|
|
80057f4: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80057f6: 68fb ldr r3, [r7, #12]
|
|
80057f8: f023 0310 bic.w r3, r3, #16
|
|
80057fc: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8005800: 687b ldr r3, [r7, #4]
|
|
8005802: 681b ldr r3, [r3, #0]
|
|
8005804: 461a mov r2, r3
|
|
8005806: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
800580a: 61fb str r3, [r7, #28]
|
|
800580c: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800580e: 69b9 ldr r1, [r7, #24]
|
|
8005810: 69fa ldr r2, [r7, #28]
|
|
8005812: e841 2300 strex r3, r2, [r1]
|
|
8005816: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005818: 697b ldr r3, [r7, #20]
|
|
800581a: 2b00 cmp r3, #0
|
|
800581c: d1e4 bne.n 80057e8 <HAL_UART_IRQHandler+0x564>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800581e: 687b ldr r3, [r7, #4]
|
|
8005820: 2202 movs r2, #2
|
|
8005822: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
8005824: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8005828: 4619 mov r1, r3
|
|
800582a: 6878 ldr r0, [r7, #4]
|
|
800582c: f000 f87e bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
return;
|
|
8005830: e063 b.n 80058fa <HAL_UART_IRQHandler+0x676>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
8005832: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005836: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800583a: 2b00 cmp r3, #0
|
|
800583c: d00e beq.n 800585c <HAL_UART_IRQHandler+0x5d8>
|
|
800583e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005842: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8005846: 2b00 cmp r3, #0
|
|
8005848: d008 beq.n 800585c <HAL_UART_IRQHandler+0x5d8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
800584a: 687b ldr r3, [r7, #4]
|
|
800584c: 681b ldr r3, [r3, #0]
|
|
800584e: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
8005852: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
8005854: 6878 ldr r0, [r7, #4]
|
|
8005856: f001 fc4f bl 80070f8 <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
800585a: e051 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
800585c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005860: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005864: 2b00 cmp r3, #0
|
|
8005866: d014 beq.n 8005892 <HAL_UART_IRQHandler+0x60e>
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
8005868: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800586c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005870: 2b00 cmp r3, #0
|
|
8005872: d105 bne.n 8005880 <HAL_UART_IRQHandler+0x5fc>
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
8005874: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005878: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
800587c: 2b00 cmp r3, #0
|
|
800587e: d008 beq.n 8005892 <HAL_UART_IRQHandler+0x60e>
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
8005880: 687b ldr r3, [r7, #4]
|
|
8005882: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8005884: 2b00 cmp r3, #0
|
|
8005886: d03a beq.n 80058fe <HAL_UART_IRQHandler+0x67a>
|
|
{
|
|
huart->TxISR(huart);
|
|
8005888: 687b ldr r3, [r7, #4]
|
|
800588a: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
800588c: 6878 ldr r0, [r7, #4]
|
|
800588e: 4798 blx r3
|
|
}
|
|
return;
|
|
8005890: e035 b.n 80058fe <HAL_UART_IRQHandler+0x67a>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
8005892: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005896: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800589a: 2b00 cmp r3, #0
|
|
800589c: d009 beq.n 80058b2 <HAL_UART_IRQHandler+0x62e>
|
|
800589e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80058a2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80058a6: 2b00 cmp r3, #0
|
|
80058a8: d003 beq.n 80058b2 <HAL_UART_IRQHandler+0x62e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
80058aa: 6878 ldr r0, [r7, #4]
|
|
80058ac: f000 fed8 bl 8006660 <UART_EndTransmit_IT>
|
|
return;
|
|
80058b0: e026 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART TX Fifo Empty occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
|
|
80058b2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80058b6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80058ba: 2b00 cmp r3, #0
|
|
80058bc: d009 beq.n 80058d2 <HAL_UART_IRQHandler+0x64e>
|
|
80058be: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80058c2: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
80058c6: 2b00 cmp r3, #0
|
|
80058c8: d003 beq.n 80058d2 <HAL_UART_IRQHandler+0x64e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Tx Fifo Empty Callback */
|
|
huart->TxFifoEmptyCallback(huart);
|
|
#else
|
|
/* Call legacy weak Tx Fifo Empty Callback */
|
|
HAL_UARTEx_TxFifoEmptyCallback(huart);
|
|
80058ca: 6878 ldr r0, [r7, #4]
|
|
80058cc: f001 fc26 bl 800711c <HAL_UARTEx_TxFifoEmptyCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
80058d0: e016 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART RX Fifo Full occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
|
|
80058d2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80058d6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80058da: 2b00 cmp r3, #0
|
|
80058dc: d010 beq.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
80058de: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80058e2: 2b00 cmp r3, #0
|
|
80058e4: da0c bge.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Rx Fifo Full Callback */
|
|
huart->RxFifoFullCallback(huart);
|
|
#else
|
|
/* Call legacy weak Rx Fifo Full Callback */
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
80058e6: 6878 ldr r0, [r7, #4]
|
|
80058e8: f001 fc0f bl 800710a <HAL_UARTEx_RxFifoFullCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
80058ec: e008 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
80058ee: bf00 nop
|
|
80058f0: e006 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
80058f2: bf00 nop
|
|
80058f4: e004 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
80058f6: bf00 nop
|
|
80058f8: e002 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
80058fa: bf00 nop
|
|
80058fc: e000 b.n 8005900 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
80058fe: bf00 nop
|
|
}
|
|
}
|
|
8005900: 37e8 adds r7, #232 @ 0xe8
|
|
8005902: 46bd mov sp, r7
|
|
8005904: bd80 pop {r7, pc}
|
|
8005906: bf00 nop
|
|
|
|
08005908 <HAL_UART_TxHalfCpltCallback>:
|
|
* @brief Tx Half Transfer completed callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005908: b480 push {r7}
|
|
800590a: b083 sub sp, #12
|
|
800590c: af00 add r7, sp, #0
|
|
800590e: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005910: bf00 nop
|
|
8005912: 370c adds r7, #12
|
|
8005914: 46bd mov sp, r7
|
|
8005916: bc80 pop {r7}
|
|
8005918: 4770 bx lr
|
|
|
|
0800591a <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800591a: b480 push {r7}
|
|
800591c: b083 sub sp, #12
|
|
800591e: af00 add r7, sp, #0
|
|
8005920: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005922: bf00 nop
|
|
8005924: 370c adds r7, #12
|
|
8005926: 46bd mov sp, r7
|
|
8005928: bc80 pop {r7}
|
|
800592a: 4770 bx lr
|
|
|
|
0800592c <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
800592c: b480 push {r7}
|
|
800592e: b083 sub sp, #12
|
|
8005930: af00 add r7, sp, #0
|
|
8005932: 6078 str r0, [r7, #4]
|
|
8005934: 460b mov r3, r1
|
|
8005936: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005938: bf00 nop
|
|
800593a: 370c adds r7, #12
|
|
800593c: 46bd mov sp, r7
|
|
800593e: bc80 pop {r7}
|
|
8005940: 4770 bx lr
|
|
...
|
|
|
|
08005944 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005944: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8005948: b08c sub sp, #48 @ 0x30
|
|
800594a: af00 add r7, sp, #0
|
|
800594c: 6178 str r0, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800594e: 2300 movs r3, #0
|
|
8005950: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8005954: 697b ldr r3, [r7, #20]
|
|
8005956: 689a ldr r2, [r3, #8]
|
|
8005958: 697b ldr r3, [r7, #20]
|
|
800595a: 691b ldr r3, [r3, #16]
|
|
800595c: 431a orrs r2, r3
|
|
800595e: 697b ldr r3, [r7, #20]
|
|
8005960: 695b ldr r3, [r3, #20]
|
|
8005962: 431a orrs r2, r3
|
|
8005964: 697b ldr r3, [r7, #20]
|
|
8005966: 69db ldr r3, [r3, #28]
|
|
8005968: 4313 orrs r3, r2
|
|
800596a: 62fb str r3, [r7, #44] @ 0x2c
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
800596c: 697b ldr r3, [r7, #20]
|
|
800596e: 681b ldr r3, [r3, #0]
|
|
8005970: 681a ldr r2, [r3, #0]
|
|
8005972: 4b94 ldr r3, [pc, #592] @ (8005bc4 <UART_SetConfig+0x280>)
|
|
8005974: 4013 ands r3, r2
|
|
8005976: 697a ldr r2, [r7, #20]
|
|
8005978: 6812 ldr r2, [r2, #0]
|
|
800597a: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800597c: 430b orrs r3, r1
|
|
800597e: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8005980: 697b ldr r3, [r7, #20]
|
|
8005982: 681b ldr r3, [r3, #0]
|
|
8005984: 685b ldr r3, [r3, #4]
|
|
8005986: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
800598a: 697b ldr r3, [r7, #20]
|
|
800598c: 68da ldr r2, [r3, #12]
|
|
800598e: 697b ldr r3, [r7, #20]
|
|
8005990: 681b ldr r3, [r3, #0]
|
|
8005992: 430a orrs r2, r1
|
|
8005994: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
8005996: 697b ldr r3, [r7, #20]
|
|
8005998: 699b ldr r3, [r3, #24]
|
|
800599a: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
800599c: 697b ldr r3, [r7, #20]
|
|
800599e: 681b ldr r3, [r3, #0]
|
|
80059a0: 4a89 ldr r2, [pc, #548] @ (8005bc8 <UART_SetConfig+0x284>)
|
|
80059a2: 4293 cmp r3, r2
|
|
80059a4: d004 beq.n 80059b0 <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
80059a6: 697b ldr r3, [r7, #20]
|
|
80059a8: 6a1b ldr r3, [r3, #32]
|
|
80059aa: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80059ac: 4313 orrs r3, r2
|
|
80059ae: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
80059b0: 697b ldr r3, [r7, #20]
|
|
80059b2: 681b ldr r3, [r3, #0]
|
|
80059b4: 689b ldr r3, [r3, #8]
|
|
80059b6: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
|
|
80059ba: f423 6330 bic.w r3, r3, #2816 @ 0xb00
|
|
80059be: 697a ldr r2, [r7, #20]
|
|
80059c0: 6812 ldr r2, [r2, #0]
|
|
80059c2: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80059c4: 430b orrs r3, r1
|
|
80059c6: 6093 str r3, [r2, #8]
|
|
|
|
/*-------------------------- USART PRESC Configuration -----------------------*/
|
|
/* Configure
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
80059c8: 697b ldr r3, [r7, #20]
|
|
80059ca: 681b ldr r3, [r3, #0]
|
|
80059cc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80059ce: f023 010f bic.w r1, r3, #15
|
|
80059d2: 697b ldr r3, [r7, #20]
|
|
80059d4: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80059d6: 697b ldr r3, [r7, #20]
|
|
80059d8: 681b ldr r3, [r3, #0]
|
|
80059da: 430a orrs r2, r1
|
|
80059dc: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
80059de: 697b ldr r3, [r7, #20]
|
|
80059e0: 681b ldr r3, [r3, #0]
|
|
80059e2: 4a7a ldr r2, [pc, #488] @ (8005bcc <UART_SetConfig+0x288>)
|
|
80059e4: 4293 cmp r3, r2
|
|
80059e6: d127 bne.n 8005a38 <UART_SetConfig+0xf4>
|
|
80059e8: 2003 movs r0, #3
|
|
80059ea: f7ff fb0d bl 8005008 <LL_RCC_GetUSARTClockSource>
|
|
80059ee: 4603 mov r3, r0
|
|
80059f0: f5a3 3340 sub.w r3, r3, #196608 @ 0x30000
|
|
80059f4: 2b03 cmp r3, #3
|
|
80059f6: d81b bhi.n 8005a30 <UART_SetConfig+0xec>
|
|
80059f8: a201 add r2, pc, #4 @ (adr r2, 8005a00 <UART_SetConfig+0xbc>)
|
|
80059fa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80059fe: bf00 nop
|
|
8005a00: 08005a11 .word 0x08005a11
|
|
8005a04: 08005a21 .word 0x08005a21
|
|
8005a08: 08005a19 .word 0x08005a19
|
|
8005a0c: 08005a29 .word 0x08005a29
|
|
8005a10: 2301 movs r3, #1
|
|
8005a12: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a16: e080 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a18: 2302 movs r3, #2
|
|
8005a1a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a1e: e07c b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a20: 2304 movs r3, #4
|
|
8005a22: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a26: e078 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a28: 2308 movs r3, #8
|
|
8005a2a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a2e: e074 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a30: 2310 movs r3, #16
|
|
8005a32: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a36: e070 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a38: 697b ldr r3, [r7, #20]
|
|
8005a3a: 681b ldr r3, [r3, #0]
|
|
8005a3c: 4a64 ldr r2, [pc, #400] @ (8005bd0 <UART_SetConfig+0x28c>)
|
|
8005a3e: 4293 cmp r3, r2
|
|
8005a40: d138 bne.n 8005ab4 <UART_SetConfig+0x170>
|
|
8005a42: 200c movs r0, #12
|
|
8005a44: f7ff fae0 bl 8005008 <LL_RCC_GetUSARTClockSource>
|
|
8005a48: 4603 mov r3, r0
|
|
8005a4a: f5a3 2340 sub.w r3, r3, #786432 @ 0xc0000
|
|
8005a4e: 2b0c cmp r3, #12
|
|
8005a50: d82c bhi.n 8005aac <UART_SetConfig+0x168>
|
|
8005a52: a201 add r2, pc, #4 @ (adr r2, 8005a58 <UART_SetConfig+0x114>)
|
|
8005a54: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005a58: 08005a8d .word 0x08005a8d
|
|
8005a5c: 08005aad .word 0x08005aad
|
|
8005a60: 08005aad .word 0x08005aad
|
|
8005a64: 08005aad .word 0x08005aad
|
|
8005a68: 08005a9d .word 0x08005a9d
|
|
8005a6c: 08005aad .word 0x08005aad
|
|
8005a70: 08005aad .word 0x08005aad
|
|
8005a74: 08005aad .word 0x08005aad
|
|
8005a78: 08005a95 .word 0x08005a95
|
|
8005a7c: 08005aad .word 0x08005aad
|
|
8005a80: 08005aad .word 0x08005aad
|
|
8005a84: 08005aad .word 0x08005aad
|
|
8005a88: 08005aa5 .word 0x08005aa5
|
|
8005a8c: 2300 movs r3, #0
|
|
8005a8e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a92: e042 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a94: 2302 movs r3, #2
|
|
8005a96: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005a9a: e03e b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005a9c: 2304 movs r3, #4
|
|
8005a9e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005aa2: e03a b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005aa4: 2308 movs r3, #8
|
|
8005aa6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005aaa: e036 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005aac: 2310 movs r3, #16
|
|
8005aae: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005ab2: e032 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005ab4: 697b ldr r3, [r7, #20]
|
|
8005ab6: 681b ldr r3, [r3, #0]
|
|
8005ab8: 4a43 ldr r2, [pc, #268] @ (8005bc8 <UART_SetConfig+0x284>)
|
|
8005aba: 4293 cmp r3, r2
|
|
8005abc: d12a bne.n 8005b14 <UART_SetConfig+0x1d0>
|
|
8005abe: f44f 6040 mov.w r0, #3072 @ 0xc00
|
|
8005ac2: f7ff fab3 bl 800502c <LL_RCC_GetLPUARTClockSource>
|
|
8005ac6: 4603 mov r3, r0
|
|
8005ac8: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8005acc: d01a beq.n 8005b04 <UART_SetConfig+0x1c0>
|
|
8005ace: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8005ad2: d81b bhi.n 8005b0c <UART_SetConfig+0x1c8>
|
|
8005ad4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005ad8: d00c beq.n 8005af4 <UART_SetConfig+0x1b0>
|
|
8005ada: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005ade: d815 bhi.n 8005b0c <UART_SetConfig+0x1c8>
|
|
8005ae0: 2b00 cmp r3, #0
|
|
8005ae2: d003 beq.n 8005aec <UART_SetConfig+0x1a8>
|
|
8005ae4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8005ae8: d008 beq.n 8005afc <UART_SetConfig+0x1b8>
|
|
8005aea: e00f b.n 8005b0c <UART_SetConfig+0x1c8>
|
|
8005aec: 2300 movs r3, #0
|
|
8005aee: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005af2: e012 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005af4: 2302 movs r3, #2
|
|
8005af6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005afa: e00e b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005afc: 2304 movs r3, #4
|
|
8005afe: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005b02: e00a b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005b04: 2308 movs r3, #8
|
|
8005b06: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005b0a: e006 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005b0c: 2310 movs r3, #16
|
|
8005b0e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8005b12: e002 b.n 8005b1a <UART_SetConfig+0x1d6>
|
|
8005b14: 2310 movs r3, #16
|
|
8005b16: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
8005b1a: 697b ldr r3, [r7, #20]
|
|
8005b1c: 681b ldr r3, [r3, #0]
|
|
8005b1e: 4a2a ldr r2, [pc, #168] @ (8005bc8 <UART_SetConfig+0x284>)
|
|
8005b20: 4293 cmp r3, r2
|
|
8005b22: f040 80a4 bne.w 8005c6e <UART_SetConfig+0x32a>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
8005b26: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8005b2a: 2b08 cmp r3, #8
|
|
8005b2c: d823 bhi.n 8005b76 <UART_SetConfig+0x232>
|
|
8005b2e: a201 add r2, pc, #4 @ (adr r2, 8005b34 <UART_SetConfig+0x1f0>)
|
|
8005b30: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005b34: 08005b59 .word 0x08005b59
|
|
8005b38: 08005b77 .word 0x08005b77
|
|
8005b3c: 08005b61 .word 0x08005b61
|
|
8005b40: 08005b77 .word 0x08005b77
|
|
8005b44: 08005b67 .word 0x08005b67
|
|
8005b48: 08005b77 .word 0x08005b77
|
|
8005b4c: 08005b77 .word 0x08005b77
|
|
8005b50: 08005b77 .word 0x08005b77
|
|
8005b54: 08005b6f .word 0x08005b6f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005b58: f7fd ff10 bl 800397c <HAL_RCC_GetPCLK1Freq>
|
|
8005b5c: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005b5e: e010 b.n 8005b82 <UART_SetConfig+0x23e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8005b60: 4b1c ldr r3, [pc, #112] @ (8005bd4 <UART_SetConfig+0x290>)
|
|
8005b62: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005b64: e00d b.n 8005b82 <UART_SetConfig+0x23e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8005b66: f7fd fe55 bl 8003814 <HAL_RCC_GetSysClockFreq>
|
|
8005b6a: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005b6c: e009 b.n 8005b82 <UART_SetConfig+0x23e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8005b6e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8005b72: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005b74: e005 b.n 8005b82 <UART_SetConfig+0x23e>
|
|
default:
|
|
pclk = 0U;
|
|
8005b76: 2300 movs r3, #0
|
|
8005b78: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8005b7a: 2301 movs r3, #1
|
|
8005b7c: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8005b80: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
8005b82: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005b84: 2b00 cmp r3, #0
|
|
8005b86: f000 8137 beq.w 8005df8 <UART_SetConfig+0x4b4>
|
|
{
|
|
/* Compute clock after Prescaler */
|
|
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
|
|
8005b8a: 697b ldr r3, [r7, #20]
|
|
8005b8c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005b8e: 4a12 ldr r2, [pc, #72] @ (8005bd8 <UART_SetConfig+0x294>)
|
|
8005b90: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8005b94: 461a mov r2, r3
|
|
8005b96: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005b98: fbb3 f3f2 udiv r3, r3, r2
|
|
8005b9c: 61bb str r3, [r7, #24]
|
|
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
8005b9e: 697b ldr r3, [r7, #20]
|
|
8005ba0: 685a ldr r2, [r3, #4]
|
|
8005ba2: 4613 mov r3, r2
|
|
8005ba4: 005b lsls r3, r3, #1
|
|
8005ba6: 4413 add r3, r2
|
|
8005ba8: 69ba ldr r2, [r7, #24]
|
|
8005baa: 429a cmp r2, r3
|
|
8005bac: d305 bcc.n 8005bba <UART_SetConfig+0x276>
|
|
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
|
|
8005bae: 697b ldr r3, [r7, #20]
|
|
8005bb0: 685b ldr r3, [r3, #4]
|
|
8005bb2: 031b lsls r3, r3, #12
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
8005bb4: 69ba ldr r2, [r7, #24]
|
|
8005bb6: 429a cmp r2, r3
|
|
8005bb8: d910 bls.n 8005bdc <UART_SetConfig+0x298>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005bba: 2301 movs r3, #1
|
|
8005bbc: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8005bc0: e11a b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
8005bc2: bf00 nop
|
|
8005bc4: cfff69f3 .word 0xcfff69f3
|
|
8005bc8: 40008000 .word 0x40008000
|
|
8005bcc: 40013800 .word 0x40013800
|
|
8005bd0: 40004400 .word 0x40004400
|
|
8005bd4: 00f42400 .word 0x00f42400
|
|
8005bd8: 0800d9b8 .word 0x0800d9b8
|
|
}
|
|
else
|
|
{
|
|
/* Check computed UsartDiv value is in allocated range
|
|
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8005bdc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005bde: 2200 movs r2, #0
|
|
8005be0: 60bb str r3, [r7, #8]
|
|
8005be2: 60fa str r2, [r7, #12]
|
|
8005be4: 697b ldr r3, [r7, #20]
|
|
8005be6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005be8: 4a8e ldr r2, [pc, #568] @ (8005e24 <UART_SetConfig+0x4e0>)
|
|
8005bea: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8005bee: b29b uxth r3, r3
|
|
8005bf0: 2200 movs r2, #0
|
|
8005bf2: 603b str r3, [r7, #0]
|
|
8005bf4: 607a str r2, [r7, #4]
|
|
8005bf6: e9d7 2300 ldrd r2, r3, [r7]
|
|
8005bfa: e9d7 0102 ldrd r0, r1, [r7, #8]
|
|
8005bfe: f7fa fac3 bl 8000188 <__aeabi_uldivmod>
|
|
8005c02: 4602 mov r2, r0
|
|
8005c04: 460b mov r3, r1
|
|
8005c06: 4610 mov r0, r2
|
|
8005c08: 4619 mov r1, r3
|
|
8005c0a: f04f 0200 mov.w r2, #0
|
|
8005c0e: f04f 0300 mov.w r3, #0
|
|
8005c12: 020b lsls r3, r1, #8
|
|
8005c14: ea43 6310 orr.w r3, r3, r0, lsr #24
|
|
8005c18: 0202 lsls r2, r0, #8
|
|
8005c1a: 6979 ldr r1, [r7, #20]
|
|
8005c1c: 6849 ldr r1, [r1, #4]
|
|
8005c1e: 0849 lsrs r1, r1, #1
|
|
8005c20: 2000 movs r0, #0
|
|
8005c22: 460c mov r4, r1
|
|
8005c24: 4605 mov r5, r0
|
|
8005c26: eb12 0804 adds.w r8, r2, r4
|
|
8005c2a: eb43 0905 adc.w r9, r3, r5
|
|
8005c2e: 697b ldr r3, [r7, #20]
|
|
8005c30: 685b ldr r3, [r3, #4]
|
|
8005c32: 2200 movs r2, #0
|
|
8005c34: 469a mov sl, r3
|
|
8005c36: 4693 mov fp, r2
|
|
8005c38: 4652 mov r2, sl
|
|
8005c3a: 465b mov r3, fp
|
|
8005c3c: 4640 mov r0, r8
|
|
8005c3e: 4649 mov r1, r9
|
|
8005c40: f7fa faa2 bl 8000188 <__aeabi_uldivmod>
|
|
8005c44: 4602 mov r2, r0
|
|
8005c46: 460b mov r3, r1
|
|
8005c48: 4613 mov r3, r2
|
|
8005c4a: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8005c4c: 6a3b ldr r3, [r7, #32]
|
|
8005c4e: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8005c52: d308 bcc.n 8005c66 <UART_SetConfig+0x322>
|
|
8005c54: 6a3b ldr r3, [r7, #32]
|
|
8005c56: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8005c5a: d204 bcs.n 8005c66 <UART_SetConfig+0x322>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8005c5c: 697b ldr r3, [r7, #20]
|
|
8005c5e: 681b ldr r3, [r3, #0]
|
|
8005c60: 6a3a ldr r2, [r7, #32]
|
|
8005c62: 60da str r2, [r3, #12]
|
|
8005c64: e0c8 b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005c66: 2301 movs r3, #1
|
|
8005c68: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8005c6c: e0c4 b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8005c6e: 697b ldr r3, [r7, #20]
|
|
8005c70: 69db ldr r3, [r3, #28]
|
|
8005c72: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8005c76: d167 bne.n 8005d48 <UART_SetConfig+0x404>
|
|
{
|
|
switch (clocksource)
|
|
8005c78: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8005c7c: 2b08 cmp r3, #8
|
|
8005c7e: d828 bhi.n 8005cd2 <UART_SetConfig+0x38e>
|
|
8005c80: a201 add r2, pc, #4 @ (adr r2, 8005c88 <UART_SetConfig+0x344>)
|
|
8005c82: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005c86: bf00 nop
|
|
8005c88: 08005cad .word 0x08005cad
|
|
8005c8c: 08005cb5 .word 0x08005cb5
|
|
8005c90: 08005cbd .word 0x08005cbd
|
|
8005c94: 08005cd3 .word 0x08005cd3
|
|
8005c98: 08005cc3 .word 0x08005cc3
|
|
8005c9c: 08005cd3 .word 0x08005cd3
|
|
8005ca0: 08005cd3 .word 0x08005cd3
|
|
8005ca4: 08005cd3 .word 0x08005cd3
|
|
8005ca8: 08005ccb .word 0x08005ccb
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005cac: f7fd fe66 bl 800397c <HAL_RCC_GetPCLK1Freq>
|
|
8005cb0: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005cb2: e014 b.n 8005cde <UART_SetConfig+0x39a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005cb4: f7fd fe74 bl 80039a0 <HAL_RCC_GetPCLK2Freq>
|
|
8005cb8: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005cba: e010 b.n 8005cde <UART_SetConfig+0x39a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8005cbc: 4b5a ldr r3, [pc, #360] @ (8005e28 <UART_SetConfig+0x4e4>)
|
|
8005cbe: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005cc0: e00d b.n 8005cde <UART_SetConfig+0x39a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8005cc2: f7fd fda7 bl 8003814 <HAL_RCC_GetSysClockFreq>
|
|
8005cc6: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005cc8: e009 b.n 8005cde <UART_SetConfig+0x39a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8005cca: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8005cce: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005cd0: e005 b.n 8005cde <UART_SetConfig+0x39a>
|
|
default:
|
|
pclk = 0U;
|
|
8005cd2: 2300 movs r3, #0
|
|
8005cd4: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8005cd6: 2301 movs r3, #1
|
|
8005cd8: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8005cdc: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8005cde: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005ce0: 2b00 cmp r3, #0
|
|
8005ce2: f000 8089 beq.w 8005df8 <UART_SetConfig+0x4b4>
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8005ce6: 697b ldr r3, [r7, #20]
|
|
8005ce8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005cea: 4a4e ldr r2, [pc, #312] @ (8005e24 <UART_SetConfig+0x4e0>)
|
|
8005cec: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8005cf0: 461a mov r2, r3
|
|
8005cf2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005cf4: fbb3 f3f2 udiv r3, r3, r2
|
|
8005cf8: 005a lsls r2, r3, #1
|
|
8005cfa: 697b ldr r3, [r7, #20]
|
|
8005cfc: 685b ldr r3, [r3, #4]
|
|
8005cfe: 085b lsrs r3, r3, #1
|
|
8005d00: 441a add r2, r3
|
|
8005d02: 697b ldr r3, [r7, #20]
|
|
8005d04: 685b ldr r3, [r3, #4]
|
|
8005d06: fbb2 f3f3 udiv r3, r2, r3
|
|
8005d0a: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8005d0c: 6a3b ldr r3, [r7, #32]
|
|
8005d0e: 2b0f cmp r3, #15
|
|
8005d10: d916 bls.n 8005d40 <UART_SetConfig+0x3fc>
|
|
8005d12: 6a3b ldr r3, [r7, #32]
|
|
8005d14: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005d18: d212 bcs.n 8005d40 <UART_SetConfig+0x3fc>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8005d1a: 6a3b ldr r3, [r7, #32]
|
|
8005d1c: b29b uxth r3, r3
|
|
8005d1e: f023 030f bic.w r3, r3, #15
|
|
8005d22: 83fb strh r3, [r7, #30]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8005d24: 6a3b ldr r3, [r7, #32]
|
|
8005d26: 085b lsrs r3, r3, #1
|
|
8005d28: b29b uxth r3, r3
|
|
8005d2a: f003 0307 and.w r3, r3, #7
|
|
8005d2e: b29a uxth r2, r3
|
|
8005d30: 8bfb ldrh r3, [r7, #30]
|
|
8005d32: 4313 orrs r3, r2
|
|
8005d34: 83fb strh r3, [r7, #30]
|
|
huart->Instance->BRR = brrtemp;
|
|
8005d36: 697b ldr r3, [r7, #20]
|
|
8005d38: 681b ldr r3, [r3, #0]
|
|
8005d3a: 8bfa ldrh r2, [r7, #30]
|
|
8005d3c: 60da str r2, [r3, #12]
|
|
8005d3e: e05b b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005d40: 2301 movs r3, #1
|
|
8005d42: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8005d46: e057 b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
8005d48: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8005d4c: 2b08 cmp r3, #8
|
|
8005d4e: d828 bhi.n 8005da2 <UART_SetConfig+0x45e>
|
|
8005d50: a201 add r2, pc, #4 @ (adr r2, 8005d58 <UART_SetConfig+0x414>)
|
|
8005d52: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005d56: bf00 nop
|
|
8005d58: 08005d7d .word 0x08005d7d
|
|
8005d5c: 08005d85 .word 0x08005d85
|
|
8005d60: 08005d8d .word 0x08005d8d
|
|
8005d64: 08005da3 .word 0x08005da3
|
|
8005d68: 08005d93 .word 0x08005d93
|
|
8005d6c: 08005da3 .word 0x08005da3
|
|
8005d70: 08005da3 .word 0x08005da3
|
|
8005d74: 08005da3 .word 0x08005da3
|
|
8005d78: 08005d9b .word 0x08005d9b
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005d7c: f7fd fdfe bl 800397c <HAL_RCC_GetPCLK1Freq>
|
|
8005d80: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005d82: e014 b.n 8005dae <UART_SetConfig+0x46a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005d84: f7fd fe0c bl 80039a0 <HAL_RCC_GetPCLK2Freq>
|
|
8005d88: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005d8a: e010 b.n 8005dae <UART_SetConfig+0x46a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8005d8c: 4b26 ldr r3, [pc, #152] @ (8005e28 <UART_SetConfig+0x4e4>)
|
|
8005d8e: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005d90: e00d b.n 8005dae <UART_SetConfig+0x46a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8005d92: f7fd fd3f bl 8003814 <HAL_RCC_GetSysClockFreq>
|
|
8005d96: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8005d98: e009 b.n 8005dae <UART_SetConfig+0x46a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8005d9a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8005d9e: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8005da0: e005 b.n 8005dae <UART_SetConfig+0x46a>
|
|
default:
|
|
pclk = 0U;
|
|
8005da2: 2300 movs r3, #0
|
|
8005da4: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8005da6: 2301 movs r3, #1
|
|
8005da8: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8005dac: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8005dae: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005db0: 2b00 cmp r3, #0
|
|
8005db2: d021 beq.n 8005df8 <UART_SetConfig+0x4b4>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8005db4: 697b ldr r3, [r7, #20]
|
|
8005db6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005db8: 4a1a ldr r2, [pc, #104] @ (8005e24 <UART_SetConfig+0x4e0>)
|
|
8005dba: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8005dbe: 461a mov r2, r3
|
|
8005dc0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005dc2: fbb3 f2f2 udiv r2, r3, r2
|
|
8005dc6: 697b ldr r3, [r7, #20]
|
|
8005dc8: 685b ldr r3, [r3, #4]
|
|
8005dca: 085b lsrs r3, r3, #1
|
|
8005dcc: 441a add r2, r3
|
|
8005dce: 697b ldr r3, [r7, #20]
|
|
8005dd0: 685b ldr r3, [r3, #4]
|
|
8005dd2: fbb2 f3f3 udiv r3, r2, r3
|
|
8005dd6: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8005dd8: 6a3b ldr r3, [r7, #32]
|
|
8005dda: 2b0f cmp r3, #15
|
|
8005ddc: d909 bls.n 8005df2 <UART_SetConfig+0x4ae>
|
|
8005dde: 6a3b ldr r3, [r7, #32]
|
|
8005de0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005de4: d205 bcs.n 8005df2 <UART_SetConfig+0x4ae>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8005de6: 6a3b ldr r3, [r7, #32]
|
|
8005de8: b29a uxth r2, r3
|
|
8005dea: 697b ldr r3, [r7, #20]
|
|
8005dec: 681b ldr r3, [r3, #0]
|
|
8005dee: 60da str r2, [r3, #12]
|
|
8005df0: e002 b.n 8005df8 <UART_SetConfig+0x4b4>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005df2: 2301 movs r3, #1
|
|
8005df4: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Initialize the number of data to process during RX/TX ISR execution */
|
|
huart->NbTxDataToProcess = 1;
|
|
8005df8: 697b ldr r3, [r7, #20]
|
|
8005dfa: 2201 movs r2, #1
|
|
8005dfc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1;
|
|
8005e00: 697b ldr r3, [r7, #20]
|
|
8005e02: 2201 movs r2, #1
|
|
8005e04: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
8005e08: 697b ldr r3, [r7, #20]
|
|
8005e0a: 2200 movs r2, #0
|
|
8005e0c: 675a str r2, [r3, #116] @ 0x74
|
|
huart->TxISR = NULL;
|
|
8005e0e: 697b ldr r3, [r7, #20]
|
|
8005e10: 2200 movs r2, #0
|
|
8005e12: 679a str r2, [r3, #120] @ 0x78
|
|
|
|
return ret;
|
|
8005e14: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
8005e18: 4618 mov r0, r3
|
|
8005e1a: 3730 adds r7, #48 @ 0x30
|
|
8005e1c: 46bd mov sp, r7
|
|
8005e1e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005e22: bf00 nop
|
|
8005e24: 0800d9b8 .word 0x0800d9b8
|
|
8005e28: 00f42400 .word 0x00f42400
|
|
|
|
08005e2c <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005e2c: b480 push {r7}
|
|
8005e2e: b083 sub sp, #12
|
|
8005e30: af00 add r7, sp, #0
|
|
8005e32: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8005e34: 687b ldr r3, [r7, #4]
|
|
8005e36: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005e38: f003 0308 and.w r3, r3, #8
|
|
8005e3c: 2b00 cmp r3, #0
|
|
8005e3e: d00a beq.n 8005e56 <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8005e40: 687b ldr r3, [r7, #4]
|
|
8005e42: 681b ldr r3, [r3, #0]
|
|
8005e44: 685b ldr r3, [r3, #4]
|
|
8005e46: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8005e4a: 687b ldr r3, [r7, #4]
|
|
8005e4c: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8005e4e: 687b ldr r3, [r7, #4]
|
|
8005e50: 681b ldr r3, [r3, #0]
|
|
8005e52: 430a orrs r2, r1
|
|
8005e54: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8005e56: 687b ldr r3, [r7, #4]
|
|
8005e58: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005e5a: f003 0301 and.w r3, r3, #1
|
|
8005e5e: 2b00 cmp r3, #0
|
|
8005e60: d00a beq.n 8005e78 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8005e62: 687b ldr r3, [r7, #4]
|
|
8005e64: 681b ldr r3, [r3, #0]
|
|
8005e66: 685b ldr r3, [r3, #4]
|
|
8005e68: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8005e6c: 687b ldr r3, [r7, #4]
|
|
8005e6e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8005e70: 687b ldr r3, [r7, #4]
|
|
8005e72: 681b ldr r3, [r3, #0]
|
|
8005e74: 430a orrs r2, r1
|
|
8005e76: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8005e78: 687b ldr r3, [r7, #4]
|
|
8005e7a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005e7c: f003 0302 and.w r3, r3, #2
|
|
8005e80: 2b00 cmp r3, #0
|
|
8005e82: d00a beq.n 8005e9a <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8005e84: 687b ldr r3, [r7, #4]
|
|
8005e86: 681b ldr r3, [r3, #0]
|
|
8005e88: 685b ldr r3, [r3, #4]
|
|
8005e8a: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8005e8e: 687b ldr r3, [r7, #4]
|
|
8005e90: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8005e92: 687b ldr r3, [r7, #4]
|
|
8005e94: 681b ldr r3, [r3, #0]
|
|
8005e96: 430a orrs r2, r1
|
|
8005e98: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8005e9a: 687b ldr r3, [r7, #4]
|
|
8005e9c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005e9e: f003 0304 and.w r3, r3, #4
|
|
8005ea2: 2b00 cmp r3, #0
|
|
8005ea4: d00a beq.n 8005ebc <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8005ea6: 687b ldr r3, [r7, #4]
|
|
8005ea8: 681b ldr r3, [r3, #0]
|
|
8005eaa: 685b ldr r3, [r3, #4]
|
|
8005eac: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8005eb0: 687b ldr r3, [r7, #4]
|
|
8005eb2: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8005eb4: 687b ldr r3, [r7, #4]
|
|
8005eb6: 681b ldr r3, [r3, #0]
|
|
8005eb8: 430a orrs r2, r1
|
|
8005eba: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8005ebc: 687b ldr r3, [r7, #4]
|
|
8005ebe: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005ec0: f003 0310 and.w r3, r3, #16
|
|
8005ec4: 2b00 cmp r3, #0
|
|
8005ec6: d00a beq.n 8005ede <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8005ec8: 687b ldr r3, [r7, #4]
|
|
8005eca: 681b ldr r3, [r3, #0]
|
|
8005ecc: 689b ldr r3, [r3, #8]
|
|
8005ece: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8005ed2: 687b ldr r3, [r7, #4]
|
|
8005ed4: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8005ed6: 687b ldr r3, [r7, #4]
|
|
8005ed8: 681b ldr r3, [r3, #0]
|
|
8005eda: 430a orrs r2, r1
|
|
8005edc: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8005ede: 687b ldr r3, [r7, #4]
|
|
8005ee0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005ee2: f003 0320 and.w r3, r3, #32
|
|
8005ee6: 2b00 cmp r3, #0
|
|
8005ee8: d00a beq.n 8005f00 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8005eea: 687b ldr r3, [r7, #4]
|
|
8005eec: 681b ldr r3, [r3, #0]
|
|
8005eee: 689b ldr r3, [r3, #8]
|
|
8005ef0: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8005ef4: 687b ldr r3, [r7, #4]
|
|
8005ef6: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8005ef8: 687b ldr r3, [r7, #4]
|
|
8005efa: 681b ldr r3, [r3, #0]
|
|
8005efc: 430a orrs r2, r1
|
|
8005efe: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8005f00: 687b ldr r3, [r7, #4]
|
|
8005f02: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005f04: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005f08: 2b00 cmp r3, #0
|
|
8005f0a: d01a beq.n 8005f42 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8005f0c: 687b ldr r3, [r7, #4]
|
|
8005f0e: 681b ldr r3, [r3, #0]
|
|
8005f10: 685b ldr r3, [r3, #4]
|
|
8005f12: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8005f16: 687b ldr r3, [r7, #4]
|
|
8005f18: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8005f1a: 687b ldr r3, [r7, #4]
|
|
8005f1c: 681b ldr r3, [r3, #0]
|
|
8005f1e: 430a orrs r2, r1
|
|
8005f20: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8005f22: 687b ldr r3, [r7, #4]
|
|
8005f24: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005f26: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8005f2a: d10a bne.n 8005f42 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8005f2c: 687b ldr r3, [r7, #4]
|
|
8005f2e: 681b ldr r3, [r3, #0]
|
|
8005f30: 685b ldr r3, [r3, #4]
|
|
8005f32: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8005f36: 687b ldr r3, [r7, #4]
|
|
8005f38: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8005f3a: 687b ldr r3, [r7, #4]
|
|
8005f3c: 681b ldr r3, [r3, #0]
|
|
8005f3e: 430a orrs r2, r1
|
|
8005f40: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8005f42: 687b ldr r3, [r7, #4]
|
|
8005f44: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005f46: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005f4a: 2b00 cmp r3, #0
|
|
8005f4c: d00a beq.n 8005f64 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8005f4e: 687b ldr r3, [r7, #4]
|
|
8005f50: 681b ldr r3, [r3, #0]
|
|
8005f52: 685b ldr r3, [r3, #4]
|
|
8005f54: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8005f58: 687b ldr r3, [r7, #4]
|
|
8005f5a: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8005f5c: 687b ldr r3, [r7, #4]
|
|
8005f5e: 681b ldr r3, [r3, #0]
|
|
8005f60: 430a orrs r2, r1
|
|
8005f62: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8005f64: bf00 nop
|
|
8005f66: 370c adds r7, #12
|
|
8005f68: 46bd mov sp, r7
|
|
8005f6a: bc80 pop {r7}
|
|
8005f6c: 4770 bx lr
|
|
|
|
08005f6e <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8005f6e: b580 push {r7, lr}
|
|
8005f70: b098 sub sp, #96 @ 0x60
|
|
8005f72: af02 add r7, sp, #8
|
|
8005f74: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005f76: 687b ldr r3, [r7, #4]
|
|
8005f78: 2200 movs r2, #0
|
|
8005f7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8005f7e: f7fa fdff bl 8000b80 <HAL_GetTick>
|
|
8005f82: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8005f84: 687b ldr r3, [r7, #4]
|
|
8005f86: 681b ldr r3, [r3, #0]
|
|
8005f88: 681b ldr r3, [r3, #0]
|
|
8005f8a: f003 0308 and.w r3, r3, #8
|
|
8005f8e: 2b08 cmp r3, #8
|
|
8005f90: d12f bne.n 8005ff2 <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8005f92: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8005f96: 9300 str r3, [sp, #0]
|
|
8005f98: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8005f9a: 2200 movs r2, #0
|
|
8005f9c: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8005fa0: 6878 ldr r0, [r7, #4]
|
|
8005fa2: f000 f88e bl 80060c2 <UART_WaitOnFlagUntilTimeout>
|
|
8005fa6: 4603 mov r3, r0
|
|
8005fa8: 2b00 cmp r3, #0
|
|
8005faa: d022 beq.n 8005ff2 <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
8005fac: 687b ldr r3, [r7, #4]
|
|
8005fae: 681b ldr r3, [r3, #0]
|
|
8005fb0: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005fb2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005fb4: e853 3f00 ldrex r3, [r3]
|
|
8005fb8: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8005fba: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8005fbc: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005fc0: 653b str r3, [r7, #80] @ 0x50
|
|
8005fc2: 687b ldr r3, [r7, #4]
|
|
8005fc4: 681b ldr r3, [r3, #0]
|
|
8005fc6: 461a mov r2, r3
|
|
8005fc8: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8005fca: 647b str r3, [r7, #68] @ 0x44
|
|
8005fcc: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005fce: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8005fd0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8005fd2: e841 2300 strex r3, r2, [r1]
|
|
8005fd6: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8005fd8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8005fda: 2b00 cmp r3, #0
|
|
8005fdc: d1e6 bne.n 8005fac <UART_CheckIdleState+0x3e>
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005fde: 687b ldr r3, [r7, #4]
|
|
8005fe0: 2220 movs r2, #32
|
|
8005fe2: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8005fe6: 687b ldr r3, [r7, #4]
|
|
8005fe8: 2200 movs r2, #0
|
|
8005fea: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8005fee: 2303 movs r3, #3
|
|
8005ff0: e063 b.n 80060ba <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8005ff2: 687b ldr r3, [r7, #4]
|
|
8005ff4: 681b ldr r3, [r3, #0]
|
|
8005ff6: 681b ldr r3, [r3, #0]
|
|
8005ff8: f003 0304 and.w r3, r3, #4
|
|
8005ffc: 2b04 cmp r3, #4
|
|
8005ffe: d149 bne.n 8006094 <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006000: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006004: 9300 str r3, [sp, #0]
|
|
8006006: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006008: 2200 movs r2, #0
|
|
800600a: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
800600e: 6878 ldr r0, [r7, #4]
|
|
8006010: f000 f857 bl 80060c2 <UART_WaitOnFlagUntilTimeout>
|
|
8006014: 4603 mov r3, r0
|
|
8006016: 2b00 cmp r3, #0
|
|
8006018: d03c beq.n 8006094 <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
800601a: 687b ldr r3, [r7, #4]
|
|
800601c: 681b ldr r3, [r3, #0]
|
|
800601e: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006020: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006022: e853 3f00 ldrex r3, [r3]
|
|
8006026: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006028: 6a3b ldr r3, [r7, #32]
|
|
800602a: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800602e: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006030: 687b ldr r3, [r7, #4]
|
|
8006032: 681b ldr r3, [r3, #0]
|
|
8006034: 461a mov r2, r3
|
|
8006036: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006038: 633b str r3, [r7, #48] @ 0x30
|
|
800603a: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800603c: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800603e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006040: e841 2300 strex r3, r2, [r1]
|
|
8006044: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006046: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006048: 2b00 cmp r3, #0
|
|
800604a: d1e6 bne.n 800601a <UART_CheckIdleState+0xac>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800604c: 687b ldr r3, [r7, #4]
|
|
800604e: 681b ldr r3, [r3, #0]
|
|
8006050: 3308 adds r3, #8
|
|
8006052: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006054: 693b ldr r3, [r7, #16]
|
|
8006056: e853 3f00 ldrex r3, [r3]
|
|
800605a: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800605c: 68fb ldr r3, [r7, #12]
|
|
800605e: f023 0301 bic.w r3, r3, #1
|
|
8006062: 64bb str r3, [r7, #72] @ 0x48
|
|
8006064: 687b ldr r3, [r7, #4]
|
|
8006066: 681b ldr r3, [r3, #0]
|
|
8006068: 3308 adds r3, #8
|
|
800606a: 6cba ldr r2, [r7, #72] @ 0x48
|
|
800606c: 61fa str r2, [r7, #28]
|
|
800606e: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006070: 69b9 ldr r1, [r7, #24]
|
|
8006072: 69fa ldr r2, [r7, #28]
|
|
8006074: e841 2300 strex r3, r2, [r1]
|
|
8006078: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800607a: 697b ldr r3, [r7, #20]
|
|
800607c: 2b00 cmp r3, #0
|
|
800607e: d1e5 bne.n 800604c <UART_CheckIdleState+0xde>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006080: 687b ldr r3, [r7, #4]
|
|
8006082: 2220 movs r2, #32
|
|
8006084: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006088: 687b ldr r3, [r7, #4]
|
|
800608a: 2200 movs r2, #0
|
|
800608c: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006090: 2303 movs r3, #3
|
|
8006092: e012 b.n 80060ba <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006094: 687b ldr r3, [r7, #4]
|
|
8006096: 2220 movs r2, #32
|
|
8006098: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800609c: 687b ldr r3, [r7, #4]
|
|
800609e: 2220 movs r2, #32
|
|
80060a0: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80060a4: 687b ldr r3, [r7, #4]
|
|
80060a6: 2200 movs r2, #0
|
|
80060a8: 66da str r2, [r3, #108] @ 0x6c
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80060aa: 687b ldr r3, [r7, #4]
|
|
80060ac: 2200 movs r2, #0
|
|
80060ae: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
__HAL_UNLOCK(huart);
|
|
80060b0: 687b ldr r3, [r7, #4]
|
|
80060b2: 2200 movs r2, #0
|
|
80060b4: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
80060b8: 2300 movs r3, #0
|
|
}
|
|
80060ba: 4618 mov r0, r3
|
|
80060bc: 3758 adds r7, #88 @ 0x58
|
|
80060be: 46bd mov sp, r7
|
|
80060c0: bd80 pop {r7, pc}
|
|
|
|
080060c2 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
80060c2: b580 push {r7, lr}
|
|
80060c4: b084 sub sp, #16
|
|
80060c6: af00 add r7, sp, #0
|
|
80060c8: 60f8 str r0, [r7, #12]
|
|
80060ca: 60b9 str r1, [r7, #8]
|
|
80060cc: 603b str r3, [r7, #0]
|
|
80060ce: 4613 mov r3, r2
|
|
80060d0: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
80060d2: e04f b.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80060d4: 69bb ldr r3, [r7, #24]
|
|
80060d6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80060da: d04b beq.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80060dc: f7fa fd50 bl 8000b80 <HAL_GetTick>
|
|
80060e0: 4602 mov r2, r0
|
|
80060e2: 683b ldr r3, [r7, #0]
|
|
80060e4: 1ad3 subs r3, r2, r3
|
|
80060e6: 69ba ldr r2, [r7, #24]
|
|
80060e8: 429a cmp r2, r3
|
|
80060ea: d302 bcc.n 80060f2 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
80060ec: 69bb ldr r3, [r7, #24]
|
|
80060ee: 2b00 cmp r3, #0
|
|
80060f0: d101 bne.n 80060f6 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
80060f2: 2303 movs r3, #3
|
|
80060f4: e04e b.n 8006194 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
80060f6: 68fb ldr r3, [r7, #12]
|
|
80060f8: 681b ldr r3, [r3, #0]
|
|
80060fa: 681b ldr r3, [r3, #0]
|
|
80060fc: f003 0304 and.w r3, r3, #4
|
|
8006100: 2b00 cmp r3, #0
|
|
8006102: d037 beq.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8006104: 68bb ldr r3, [r7, #8]
|
|
8006106: 2b80 cmp r3, #128 @ 0x80
|
|
8006108: d034 beq.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
800610a: 68bb ldr r3, [r7, #8]
|
|
800610c: 2b40 cmp r3, #64 @ 0x40
|
|
800610e: d031 beq.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8006110: 68fb ldr r3, [r7, #12]
|
|
8006112: 681b ldr r3, [r3, #0]
|
|
8006114: 69db ldr r3, [r3, #28]
|
|
8006116: f003 0308 and.w r3, r3, #8
|
|
800611a: 2b08 cmp r3, #8
|
|
800611c: d110 bne.n 8006140 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
800611e: 68fb ldr r3, [r7, #12]
|
|
8006120: 681b ldr r3, [r3, #0]
|
|
8006122: 2208 movs r2, #8
|
|
8006124: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006126: 68f8 ldr r0, [r7, #12]
|
|
8006128: f000 f998 bl 800645c <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
800612c: 68fb ldr r3, [r7, #12]
|
|
800612e: 2208 movs r2, #8
|
|
8006130: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006134: 68fb ldr r3, [r7, #12]
|
|
8006136: 2200 movs r2, #0
|
|
8006138: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_ERROR;
|
|
800613c: 2301 movs r3, #1
|
|
800613e: e029 b.n 8006194 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8006140: 68fb ldr r3, [r7, #12]
|
|
8006142: 681b ldr r3, [r3, #0]
|
|
8006144: 69db ldr r3, [r3, #28]
|
|
8006146: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800614a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800614e: d111 bne.n 8006174 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8006150: 68fb ldr r3, [r7, #12]
|
|
8006152: 681b ldr r3, [r3, #0]
|
|
8006154: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8006158: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
800615a: 68f8 ldr r0, [r7, #12]
|
|
800615c: f000 f97e bl 800645c <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8006160: 68fb ldr r3, [r7, #12]
|
|
8006162: 2220 movs r2, #32
|
|
8006164: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006168: 68fb ldr r3, [r7, #12]
|
|
800616a: 2200 movs r2, #0
|
|
800616c: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_TIMEOUT;
|
|
8006170: 2303 movs r3, #3
|
|
8006172: e00f b.n 8006194 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8006174: 68fb ldr r3, [r7, #12]
|
|
8006176: 681b ldr r3, [r3, #0]
|
|
8006178: 69da ldr r2, [r3, #28]
|
|
800617a: 68bb ldr r3, [r7, #8]
|
|
800617c: 4013 ands r3, r2
|
|
800617e: 68ba ldr r2, [r7, #8]
|
|
8006180: 429a cmp r2, r3
|
|
8006182: bf0c ite eq
|
|
8006184: 2301 moveq r3, #1
|
|
8006186: 2300 movne r3, #0
|
|
8006188: b2db uxtb r3, r3
|
|
800618a: 461a mov r2, r3
|
|
800618c: 79fb ldrb r3, [r7, #7]
|
|
800618e: 429a cmp r2, r3
|
|
8006190: d0a0 beq.n 80060d4 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006192: 2300 movs r3, #0
|
|
}
|
|
8006194: 4618 mov r0, r3
|
|
8006196: 3710 adds r7, #16
|
|
8006198: 46bd mov sp, r7
|
|
800619a: bd80 pop {r7, pc}
|
|
|
|
0800619c <UART_Start_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
800619c: b480 push {r7}
|
|
800619e: b0a3 sub sp, #140 @ 0x8c
|
|
80061a0: af00 add r7, sp, #0
|
|
80061a2: 60f8 str r0, [r7, #12]
|
|
80061a4: 60b9 str r1, [r7, #8]
|
|
80061a6: 4613 mov r3, r2
|
|
80061a8: 80fb strh r3, [r7, #6]
|
|
huart->pRxBuffPtr = pData;
|
|
80061aa: 68fb ldr r3, [r7, #12]
|
|
80061ac: 68ba ldr r2, [r7, #8]
|
|
80061ae: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferSize = Size;
|
|
80061b0: 68fb ldr r3, [r7, #12]
|
|
80061b2: 88fa ldrh r2, [r7, #6]
|
|
80061b4: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
huart->RxXferCount = Size;
|
|
80061b8: 68fb ldr r3, [r7, #12]
|
|
80061ba: 88fa ldrh r2, [r7, #6]
|
|
80061bc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
huart->RxISR = NULL;
|
|
80061c0: 68fb ldr r3, [r7, #12]
|
|
80061c2: 2200 movs r2, #0
|
|
80061c4: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
80061c6: 68fb ldr r3, [r7, #12]
|
|
80061c8: 689b ldr r3, [r3, #8]
|
|
80061ca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80061ce: d10e bne.n 80061ee <UART_Start_Receive_IT+0x52>
|
|
80061d0: 68fb ldr r3, [r7, #12]
|
|
80061d2: 691b ldr r3, [r3, #16]
|
|
80061d4: 2b00 cmp r3, #0
|
|
80061d6: d105 bne.n 80061e4 <UART_Start_Receive_IT+0x48>
|
|
80061d8: 68fb ldr r3, [r7, #12]
|
|
80061da: f240 12ff movw r2, #511 @ 0x1ff
|
|
80061de: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80061e2: e02d b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
80061e4: 68fb ldr r3, [r7, #12]
|
|
80061e6: 22ff movs r2, #255 @ 0xff
|
|
80061e8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80061ec: e028 b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
80061ee: 68fb ldr r3, [r7, #12]
|
|
80061f0: 689b ldr r3, [r3, #8]
|
|
80061f2: 2b00 cmp r3, #0
|
|
80061f4: d10d bne.n 8006212 <UART_Start_Receive_IT+0x76>
|
|
80061f6: 68fb ldr r3, [r7, #12]
|
|
80061f8: 691b ldr r3, [r3, #16]
|
|
80061fa: 2b00 cmp r3, #0
|
|
80061fc: d104 bne.n 8006208 <UART_Start_Receive_IT+0x6c>
|
|
80061fe: 68fb ldr r3, [r7, #12]
|
|
8006200: 22ff movs r2, #255 @ 0xff
|
|
8006202: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006206: e01b b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
8006208: 68fb ldr r3, [r7, #12]
|
|
800620a: 227f movs r2, #127 @ 0x7f
|
|
800620c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006210: e016 b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
8006212: 68fb ldr r3, [r7, #12]
|
|
8006214: 689b ldr r3, [r3, #8]
|
|
8006216: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
800621a: d10d bne.n 8006238 <UART_Start_Receive_IT+0x9c>
|
|
800621c: 68fb ldr r3, [r7, #12]
|
|
800621e: 691b ldr r3, [r3, #16]
|
|
8006220: 2b00 cmp r3, #0
|
|
8006222: d104 bne.n 800622e <UART_Start_Receive_IT+0x92>
|
|
8006224: 68fb ldr r3, [r7, #12]
|
|
8006226: 227f movs r2, #127 @ 0x7f
|
|
8006228: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
800622c: e008 b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
800622e: 68fb ldr r3, [r7, #12]
|
|
8006230: 223f movs r2, #63 @ 0x3f
|
|
8006232: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006236: e003 b.n 8006240 <UART_Start_Receive_IT+0xa4>
|
|
8006238: 68fb ldr r3, [r7, #12]
|
|
800623a: 2200 movs r2, #0
|
|
800623c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006240: 68fb ldr r3, [r7, #12]
|
|
8006242: 2200 movs r2, #0
|
|
8006244: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8006248: 68fb ldr r3, [r7, #12]
|
|
800624a: 2222 movs r2, #34 @ 0x22
|
|
800624c: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006250: 68fb ldr r3, [r7, #12]
|
|
8006252: 681b ldr r3, [r3, #0]
|
|
8006254: 3308 adds r3, #8
|
|
8006256: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006258: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800625a: e853 3f00 ldrex r3, [r3]
|
|
800625e: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
8006260: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006262: f043 0301 orr.w r3, r3, #1
|
|
8006266: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
800626a: 68fb ldr r3, [r7, #12]
|
|
800626c: 681b ldr r3, [r3, #0]
|
|
800626e: 3308 adds r3, #8
|
|
8006270: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
8006274: 673a str r2, [r7, #112] @ 0x70
|
|
8006276: 66fb str r3, [r7, #108] @ 0x6c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006278: 6ef9 ldr r1, [r7, #108] @ 0x6c
|
|
800627a: 6f3a ldr r2, [r7, #112] @ 0x70
|
|
800627c: e841 2300 strex r3, r2, [r1]
|
|
8006280: 66bb str r3, [r7, #104] @ 0x68
|
|
return(result);
|
|
8006282: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8006284: 2b00 cmp r3, #0
|
|
8006286: d1e3 bne.n 8006250 <UART_Start_Receive_IT+0xb4>
|
|
|
|
/* Configure Rx interrupt processing */
|
|
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
|
|
8006288: 68fb ldr r3, [r7, #12]
|
|
800628a: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
800628c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8006290: d14f bne.n 8006332 <UART_Start_Receive_IT+0x196>
|
|
8006292: 68fb ldr r3, [r7, #12]
|
|
8006294: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8006298: 88fa ldrh r2, [r7, #6]
|
|
800629a: 429a cmp r2, r3
|
|
800629c: d349 bcc.n 8006332 <UART_Start_Receive_IT+0x196>
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800629e: 68fb ldr r3, [r7, #12]
|
|
80062a0: 689b ldr r3, [r3, #8]
|
|
80062a2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80062a6: d107 bne.n 80062b8 <UART_Start_Receive_IT+0x11c>
|
|
80062a8: 68fb ldr r3, [r7, #12]
|
|
80062aa: 691b ldr r3, [r3, #16]
|
|
80062ac: 2b00 cmp r3, #0
|
|
80062ae: d103 bne.n 80062b8 <UART_Start_Receive_IT+0x11c>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
|
|
80062b0: 68fb ldr r3, [r7, #12]
|
|
80062b2: 4a46 ldr r2, [pc, #280] @ (80063cc <UART_Start_Receive_IT+0x230>)
|
|
80062b4: 675a str r2, [r3, #116] @ 0x74
|
|
80062b6: e002 b.n 80062be <UART_Start_Receive_IT+0x122>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
|
|
80062b8: 68fb ldr r3, [r7, #12]
|
|
80062ba: 4a45 ldr r2, [pc, #276] @ (80063d0 <UART_Start_Receive_IT+0x234>)
|
|
80062bc: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
80062be: 68fb ldr r3, [r7, #12]
|
|
80062c0: 691b ldr r3, [r3, #16]
|
|
80062c2: 2b00 cmp r3, #0
|
|
80062c4: d01a beq.n 80062fc <UART_Start_Receive_IT+0x160>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80062c6: 68fb ldr r3, [r7, #12]
|
|
80062c8: 681b ldr r3, [r3, #0]
|
|
80062ca: 653b str r3, [r7, #80] @ 0x50
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80062cc: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80062ce: e853 3f00 ldrex r3, [r3]
|
|
80062d2: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
80062d4: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80062d6: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80062da: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
80062de: 68fb ldr r3, [r7, #12]
|
|
80062e0: 681b ldr r3, [r3, #0]
|
|
80062e2: 461a mov r2, r3
|
|
80062e4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80062e8: 65fb str r3, [r7, #92] @ 0x5c
|
|
80062ea: 65ba str r2, [r7, #88] @ 0x58
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062ec: 6db9 ldr r1, [r7, #88] @ 0x58
|
|
80062ee: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
80062f0: e841 2300 strex r3, r2, [r1]
|
|
80062f4: 657b str r3, [r7, #84] @ 0x54
|
|
return(result);
|
|
80062f6: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80062f8: 2b00 cmp r3, #0
|
|
80062fa: d1e4 bne.n 80062c6 <UART_Start_Receive_IT+0x12a>
|
|
}
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
80062fc: 68fb ldr r3, [r7, #12]
|
|
80062fe: 681b ldr r3, [r3, #0]
|
|
8006300: 3308 adds r3, #8
|
|
8006302: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006304: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006306: e853 3f00 ldrex r3, [r3]
|
|
800630a: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
800630c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800630e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006312: 67fb str r3, [r7, #124] @ 0x7c
|
|
8006314: 68fb ldr r3, [r7, #12]
|
|
8006316: 681b ldr r3, [r3, #0]
|
|
8006318: 3308 adds r3, #8
|
|
800631a: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
800631c: 64ba str r2, [r7, #72] @ 0x48
|
|
800631e: 647b str r3, [r7, #68] @ 0x44
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006320: 6c79 ldr r1, [r7, #68] @ 0x44
|
|
8006322: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006324: e841 2300 strex r3, r2, [r1]
|
|
8006328: 643b str r3, [r7, #64] @ 0x40
|
|
return(result);
|
|
800632a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800632c: 2b00 cmp r3, #0
|
|
800632e: d1e5 bne.n 80062fc <UART_Start_Receive_IT+0x160>
|
|
8006330: e046 b.n 80063c0 <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006332: 68fb ldr r3, [r7, #12]
|
|
8006334: 689b ldr r3, [r3, #8]
|
|
8006336: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800633a: d107 bne.n 800634c <UART_Start_Receive_IT+0x1b0>
|
|
800633c: 68fb ldr r3, [r7, #12]
|
|
800633e: 691b ldr r3, [r3, #16]
|
|
8006340: 2b00 cmp r3, #0
|
|
8006342: d103 bne.n 800634c <UART_Start_Receive_IT+0x1b0>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
8006344: 68fb ldr r3, [r7, #12]
|
|
8006346: 4a23 ldr r2, [pc, #140] @ (80063d4 <UART_Start_Receive_IT+0x238>)
|
|
8006348: 675a str r2, [r3, #116] @ 0x74
|
|
800634a: e002 b.n 8006352 <UART_Start_Receive_IT+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
800634c: 68fb ldr r3, [r7, #12]
|
|
800634e: 4a22 ldr r2, [pc, #136] @ (80063d8 <UART_Start_Receive_IT+0x23c>)
|
|
8006350: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8006352: 68fb ldr r3, [r7, #12]
|
|
8006354: 691b ldr r3, [r3, #16]
|
|
8006356: 2b00 cmp r3, #0
|
|
8006358: d019 beq.n 800638e <UART_Start_Receive_IT+0x1f2>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
|
|
800635a: 68fb ldr r3, [r7, #12]
|
|
800635c: 681b ldr r3, [r3, #0]
|
|
800635e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006360: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006362: e853 3f00 ldrex r3, [r3]
|
|
8006366: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006368: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800636a: f443 7390 orr.w r3, r3, #288 @ 0x120
|
|
800636e: 677b str r3, [r7, #116] @ 0x74
|
|
8006370: 68fb ldr r3, [r7, #12]
|
|
8006372: 681b ldr r3, [r3, #0]
|
|
8006374: 461a mov r2, r3
|
|
8006376: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8006378: 637b str r3, [r7, #52] @ 0x34
|
|
800637a: 633a str r2, [r7, #48] @ 0x30
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800637c: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
800637e: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8006380: e841 2300 strex r3, r2, [r1]
|
|
8006384: 62fb str r3, [r7, #44] @ 0x2c
|
|
return(result);
|
|
8006386: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006388: 2b00 cmp r3, #0
|
|
800638a: d1e6 bne.n 800635a <UART_Start_Receive_IT+0x1be>
|
|
800638c: e018 b.n 80063c0 <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
800638e: 68fb ldr r3, [r7, #12]
|
|
8006390: 681b ldr r3, [r3, #0]
|
|
8006392: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006394: 697b ldr r3, [r7, #20]
|
|
8006396: e853 3f00 ldrex r3, [r3]
|
|
800639a: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800639c: 693b ldr r3, [r7, #16]
|
|
800639e: f043 0320 orr.w r3, r3, #32
|
|
80063a2: 67bb str r3, [r7, #120] @ 0x78
|
|
80063a4: 68fb ldr r3, [r7, #12]
|
|
80063a6: 681b ldr r3, [r3, #0]
|
|
80063a8: 461a mov r2, r3
|
|
80063aa: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80063ac: 623b str r3, [r7, #32]
|
|
80063ae: 61fa str r2, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80063b0: 69f9 ldr r1, [r7, #28]
|
|
80063b2: 6a3a ldr r2, [r7, #32]
|
|
80063b4: e841 2300 strex r3, r2, [r1]
|
|
80063b8: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
80063ba: 69bb ldr r3, [r7, #24]
|
|
80063bc: 2b00 cmp r3, #0
|
|
80063be: d1e6 bne.n 800638e <UART_Start_Receive_IT+0x1f2>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80063c0: 2300 movs r3, #0
|
|
}
|
|
80063c2: 4618 mov r0, r3
|
|
80063c4: 378c adds r7, #140 @ 0x8c
|
|
80063c6: 46bd mov sp, r7
|
|
80063c8: bc80 pop {r7}
|
|
80063ca: 4770 bx lr
|
|
80063cc: 08006d8d .word 0x08006d8d
|
|
80063d0: 08006a29 .word 0x08006a29
|
|
80063d4: 08006871 .word 0x08006871
|
|
80063d8: 080066b9 .word 0x080066b9
|
|
|
|
080063dc <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80063dc: b480 push {r7}
|
|
80063de: b08f sub sp, #60 @ 0x3c
|
|
80063e0: af00 add r7, sp, #0
|
|
80063e2: 6078 str r0, [r7, #4]
|
|
/* Disable TXEIE, TCIE, TXFT interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
|
80063e4: 687b ldr r3, [r7, #4]
|
|
80063e6: 681b ldr r3, [r3, #0]
|
|
80063e8: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80063ea: 6a3b ldr r3, [r7, #32]
|
|
80063ec: e853 3f00 ldrex r3, [r3]
|
|
80063f0: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80063f2: 69fb ldr r3, [r7, #28]
|
|
80063f4: f023 03c0 bic.w r3, r3, #192 @ 0xc0
|
|
80063f8: 637b str r3, [r7, #52] @ 0x34
|
|
80063fa: 687b ldr r3, [r7, #4]
|
|
80063fc: 681b ldr r3, [r3, #0]
|
|
80063fe: 461a mov r2, r3
|
|
8006400: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006402: 62fb str r3, [r7, #44] @ 0x2c
|
|
8006404: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006406: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8006408: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800640a: e841 2300 strex r3, r2, [r1]
|
|
800640e: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006410: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006412: 2b00 cmp r3, #0
|
|
8006414: d1e6 bne.n 80063e4 <UART_EndTxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
|
|
8006416: 687b ldr r3, [r7, #4]
|
|
8006418: 681b ldr r3, [r3, #0]
|
|
800641a: 3308 adds r3, #8
|
|
800641c: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800641e: 68fb ldr r3, [r7, #12]
|
|
8006420: e853 3f00 ldrex r3, [r3]
|
|
8006424: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006426: 68bb ldr r3, [r7, #8]
|
|
8006428: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
|
|
800642c: 633b str r3, [r7, #48] @ 0x30
|
|
800642e: 687b ldr r3, [r7, #4]
|
|
8006430: 681b ldr r3, [r3, #0]
|
|
8006432: 3308 adds r3, #8
|
|
8006434: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006436: 61ba str r2, [r7, #24]
|
|
8006438: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800643a: 6979 ldr r1, [r7, #20]
|
|
800643c: 69ba ldr r2, [r7, #24]
|
|
800643e: e841 2300 strex r3, r2, [r1]
|
|
8006442: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006444: 693b ldr r3, [r7, #16]
|
|
8006446: 2b00 cmp r3, #0
|
|
8006448: d1e5 bne.n 8006416 <UART_EndTxTransfer+0x3a>
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800644a: 687b ldr r3, [r7, #4]
|
|
800644c: 2220 movs r2, #32
|
|
800644e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
}
|
|
8006452: bf00 nop
|
|
8006454: 373c adds r7, #60 @ 0x3c
|
|
8006456: 46bd mov sp, r7
|
|
8006458: bc80 pop {r7}
|
|
800645a: 4770 bx lr
|
|
|
|
0800645c <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
800645c: b480 push {r7}
|
|
800645e: b095 sub sp, #84 @ 0x54
|
|
8006460: af00 add r7, sp, #0
|
|
8006462: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8006464: 687b ldr r3, [r7, #4]
|
|
8006466: 681b ldr r3, [r3, #0]
|
|
8006468: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800646a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800646c: e853 3f00 ldrex r3, [r3]
|
|
8006470: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006472: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006474: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006478: 64fb str r3, [r7, #76] @ 0x4c
|
|
800647a: 687b ldr r3, [r7, #4]
|
|
800647c: 681b ldr r3, [r3, #0]
|
|
800647e: 461a mov r2, r3
|
|
8006480: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006482: 643b str r3, [r7, #64] @ 0x40
|
|
8006484: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006486: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006488: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
800648a: e841 2300 strex r3, r2, [r1]
|
|
800648e: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006490: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006492: 2b00 cmp r3, #0
|
|
8006494: d1e6 bne.n 8006464 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8006496: 687b ldr r3, [r7, #4]
|
|
8006498: 681b ldr r3, [r3, #0]
|
|
800649a: 3308 adds r3, #8
|
|
800649c: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800649e: 6a3b ldr r3, [r7, #32]
|
|
80064a0: e853 3f00 ldrex r3, [r3]
|
|
80064a4: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80064a6: 69fb ldr r3, [r7, #28]
|
|
80064a8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80064ac: f023 0301 bic.w r3, r3, #1
|
|
80064b0: 64bb str r3, [r7, #72] @ 0x48
|
|
80064b2: 687b ldr r3, [r7, #4]
|
|
80064b4: 681b ldr r3, [r3, #0]
|
|
80064b6: 3308 adds r3, #8
|
|
80064b8: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80064ba: 62fa str r2, [r7, #44] @ 0x2c
|
|
80064bc: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064be: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
80064c0: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80064c2: e841 2300 strex r3, r2, [r1]
|
|
80064c6: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
80064c8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80064ca: 2b00 cmp r3, #0
|
|
80064cc: d1e3 bne.n 8006496 <UART_EndRxTransfer+0x3a>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80064ce: 687b ldr r3, [r7, #4]
|
|
80064d0: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80064d2: 2b01 cmp r3, #1
|
|
80064d4: d118 bne.n 8006508 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80064d6: 687b ldr r3, [r7, #4]
|
|
80064d8: 681b ldr r3, [r3, #0]
|
|
80064da: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80064dc: 68fb ldr r3, [r7, #12]
|
|
80064de: e853 3f00 ldrex r3, [r3]
|
|
80064e2: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80064e4: 68bb ldr r3, [r7, #8]
|
|
80064e6: f023 0310 bic.w r3, r3, #16
|
|
80064ea: 647b str r3, [r7, #68] @ 0x44
|
|
80064ec: 687b ldr r3, [r7, #4]
|
|
80064ee: 681b ldr r3, [r3, #0]
|
|
80064f0: 461a mov r2, r3
|
|
80064f2: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80064f4: 61bb str r3, [r7, #24]
|
|
80064f6: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064f8: 6979 ldr r1, [r7, #20]
|
|
80064fa: 69ba ldr r2, [r7, #24]
|
|
80064fc: e841 2300 strex r3, r2, [r1]
|
|
8006500: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006502: 693b ldr r3, [r7, #16]
|
|
8006504: 2b00 cmp r3, #0
|
|
8006506: d1e6 bne.n 80064d6 <UART_EndRxTransfer+0x7a>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006508: 687b ldr r3, [r7, #4]
|
|
800650a: 2220 movs r2, #32
|
|
800650c: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006510: 687b ldr r3, [r7, #4]
|
|
8006512: 2200 movs r2, #0
|
|
8006514: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8006516: 687b ldr r3, [r7, #4]
|
|
8006518: 2200 movs r2, #0
|
|
800651a: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
800651c: bf00 nop
|
|
800651e: 3754 adds r7, #84 @ 0x54
|
|
8006520: 46bd mov sp, r7
|
|
8006522: bc80 pop {r7}
|
|
8006524: 4770 bx lr
|
|
|
|
08006526 <UART_DMATransmitCplt>:
|
|
* @brief DMA UART transmit process complete callback.
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006526: b580 push {r7, lr}
|
|
8006528: b090 sub sp, #64 @ 0x40
|
|
800652a: af00 add r7, sp, #0
|
|
800652c: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
800652e: 687b ldr r3, [r7, #4]
|
|
8006530: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006532: 63fb str r3, [r7, #60] @ 0x3c
|
|
|
|
/* DMA Normal mode */
|
|
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
|
|
8006534: 687b ldr r3, [r7, #4]
|
|
8006536: 681b ldr r3, [r3, #0]
|
|
8006538: 681b ldr r3, [r3, #0]
|
|
800653a: f003 0320 and.w r3, r3, #32
|
|
800653e: 2b00 cmp r3, #0
|
|
8006540: d133 bne.n 80065aa <UART_DMATransmitCplt+0x84>
|
|
{
|
|
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8006542: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006544: 681b ldr r3, [r3, #0]
|
|
8006546: 3308 adds r3, #8
|
|
8006548: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800654a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800654c: e853 3f00 ldrex r3, [r3]
|
|
8006550: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006552: 6a3b ldr r3, [r7, #32]
|
|
8006554: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006558: 63bb str r3, [r7, #56] @ 0x38
|
|
800655a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800655c: 681b ldr r3, [r3, #0]
|
|
800655e: 3308 adds r3, #8
|
|
8006560: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8006562: 633a str r2, [r7, #48] @ 0x30
|
|
8006564: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006566: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006568: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800656a: e841 2300 strex r3, r2, [r1]
|
|
800656e: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006570: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006572: 2b00 cmp r3, #0
|
|
8006574: d1e5 bne.n 8006542 <UART_DMATransmitCplt+0x1c>
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8006576: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006578: 681b ldr r3, [r3, #0]
|
|
800657a: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800657c: 693b ldr r3, [r7, #16]
|
|
800657e: e853 3f00 ldrex r3, [r3]
|
|
8006582: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006584: 68fb ldr r3, [r7, #12]
|
|
8006586: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
800658a: 637b str r3, [r7, #52] @ 0x34
|
|
800658c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800658e: 681b ldr r3, [r3, #0]
|
|
8006590: 461a mov r2, r3
|
|
8006592: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006594: 61fb str r3, [r7, #28]
|
|
8006596: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006598: 69b9 ldr r1, [r7, #24]
|
|
800659a: 69fa ldr r2, [r7, #28]
|
|
800659c: e841 2300 strex r3, r2, [r1]
|
|
80065a0: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80065a2: 697b ldr r3, [r7, #20]
|
|
80065a4: 2b00 cmp r3, #0
|
|
80065a6: d1e6 bne.n 8006576 <UART_DMATransmitCplt+0x50>
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80065a8: e002 b.n 80065b0 <UART_DMATransmitCplt+0x8a>
|
|
HAL_UART_TxCpltCallback(huart);
|
|
80065aa: 6bf8 ldr r0, [r7, #60] @ 0x3c
|
|
80065ac: f7fa ffba bl 8001524 <HAL_UART_TxCpltCallback>
|
|
}
|
|
80065b0: bf00 nop
|
|
80065b2: 3740 adds r7, #64 @ 0x40
|
|
80065b4: 46bd mov sp, r7
|
|
80065b6: bd80 pop {r7, pc}
|
|
|
|
080065b8 <UART_DMATxHalfCplt>:
|
|
* @brief DMA UART transmit process half complete callback.
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80065b8: b580 push {r7, lr}
|
|
80065ba: b084 sub sp, #16
|
|
80065bc: af00 add r7, sp, #0
|
|
80065be: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
80065c0: 687b ldr r3, [r7, #4]
|
|
80065c2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80065c4: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx Half complete callback*/
|
|
huart->TxHalfCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx Half complete callback*/
|
|
HAL_UART_TxHalfCpltCallback(huart);
|
|
80065c6: 68f8 ldr r0, [r7, #12]
|
|
80065c8: f7ff f99e bl 8005908 <HAL_UART_TxHalfCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80065cc: bf00 nop
|
|
80065ce: 3710 adds r7, #16
|
|
80065d0: 46bd mov sp, r7
|
|
80065d2: bd80 pop {r7, pc}
|
|
|
|
080065d4 <UART_DMAError>:
|
|
* @brief DMA UART communication error callback.
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80065d4: b580 push {r7, lr}
|
|
80065d6: b086 sub sp, #24
|
|
80065d8: af00 add r7, sp, #0
|
|
80065da: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
80065dc: 687b ldr r3, [r7, #4]
|
|
80065de: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80065e0: 617b str r3, [r7, #20]
|
|
|
|
const HAL_UART_StateTypeDef gstate = huart->gState;
|
|
80065e2: 697b ldr r3, [r7, #20]
|
|
80065e4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80065e8: 613b str r3, [r7, #16]
|
|
const HAL_UART_StateTypeDef rxstate = huart->RxState;
|
|
80065ea: 697b ldr r3, [r7, #20]
|
|
80065ec: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80065f0: 60fb str r3, [r7, #12]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
|
|
80065f2: 697b ldr r3, [r7, #20]
|
|
80065f4: 681b ldr r3, [r3, #0]
|
|
80065f6: 689b ldr r3, [r3, #8]
|
|
80065f8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80065fc: 2b80 cmp r3, #128 @ 0x80
|
|
80065fe: d105 bne.n 800660c <UART_DMAError+0x38>
|
|
8006600: 693b ldr r3, [r7, #16]
|
|
8006602: 2b21 cmp r3, #33 @ 0x21
|
|
8006604: d102 bne.n 800660c <UART_DMAError+0x38>
|
|
(gstate == HAL_UART_STATE_BUSY_TX))
|
|
{
|
|
UART_EndTxTransfer(huart);
|
|
8006606: 6978 ldr r0, [r7, #20]
|
|
8006608: f7ff fee8 bl 80063dc <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
|
|
800660c: 697b ldr r3, [r7, #20]
|
|
800660e: 681b ldr r3, [r3, #0]
|
|
8006610: 689b ldr r3, [r3, #8]
|
|
8006612: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006616: 2b40 cmp r3, #64 @ 0x40
|
|
8006618: d105 bne.n 8006626 <UART_DMAError+0x52>
|
|
800661a: 68fb ldr r3, [r7, #12]
|
|
800661c: 2b22 cmp r3, #34 @ 0x22
|
|
800661e: d102 bne.n 8006626 <UART_DMAError+0x52>
|
|
(rxstate == HAL_UART_STATE_BUSY_RX))
|
|
{
|
|
UART_EndRxTransfer(huart);
|
|
8006620: 6978 ldr r0, [r7, #20]
|
|
8006622: f7ff ff1b bl 800645c <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
8006626: 697b ldr r3, [r7, #20]
|
|
8006628: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800662c: f043 0210 orr.w r2, r3, #16
|
|
8006630: 697b ldr r3, [r7, #20]
|
|
8006632: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006636: 6978 ldr r0, [r7, #20]
|
|
8006638: f7ff f96f bl 800591a <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800663c: bf00 nop
|
|
800663e: 3718 adds r7, #24
|
|
8006640: 46bd mov sp, r7
|
|
8006642: bd80 pop {r7, pc}
|
|
|
|
08006644 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006644: b580 push {r7, lr}
|
|
8006646: b084 sub sp, #16
|
|
8006648: af00 add r7, sp, #0
|
|
800664a: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
800664c: 687b ldr r3, [r7, #4]
|
|
800664e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006650: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006652: 68f8 ldr r0, [r7, #12]
|
|
8006654: f7ff f961 bl 800591a <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8006658: bf00 nop
|
|
800665a: 3710 adds r7, #16
|
|
800665c: 46bd mov sp, r7
|
|
800665e: bd80 pop {r7, pc}
|
|
|
|
08006660 <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006660: b580 push {r7, lr}
|
|
8006662: b088 sub sp, #32
|
|
8006664: af00 add r7, sp, #0
|
|
8006666: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8006668: 687b ldr r3, [r7, #4]
|
|
800666a: 681b ldr r3, [r3, #0]
|
|
800666c: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800666e: 68fb ldr r3, [r7, #12]
|
|
8006670: e853 3f00 ldrex r3, [r3]
|
|
8006674: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006676: 68bb ldr r3, [r7, #8]
|
|
8006678: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800667c: 61fb str r3, [r7, #28]
|
|
800667e: 687b ldr r3, [r7, #4]
|
|
8006680: 681b ldr r3, [r3, #0]
|
|
8006682: 461a mov r2, r3
|
|
8006684: 69fb ldr r3, [r7, #28]
|
|
8006686: 61bb str r3, [r7, #24]
|
|
8006688: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800668a: 6979 ldr r1, [r7, #20]
|
|
800668c: 69ba ldr r2, [r7, #24]
|
|
800668e: e841 2300 strex r3, r2, [r1]
|
|
8006692: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006694: 693b ldr r3, [r7, #16]
|
|
8006696: 2b00 cmp r3, #0
|
|
8006698: d1e6 bne.n 8006668 <UART_EndTransmit_IT+0x8>
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800669a: 687b ldr r3, [r7, #4]
|
|
800669c: 2220 movs r2, #32
|
|
800669e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
80066a2: 687b ldr r3, [r7, #4]
|
|
80066a4: 2200 movs r2, #0
|
|
80066a6: 679a str r2, [r3, #120] @ 0x78
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
80066a8: 6878 ldr r0, [r7, #4]
|
|
80066aa: f7fa ff3b bl 8001524 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80066ae: bf00 nop
|
|
80066b0: 3720 adds r7, #32
|
|
80066b2: 46bd mov sp, r7
|
|
80066b4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080066b8 <UART_RxISR_8BIT>:
|
|
* @brief RX interrupt handler for 7 or 8 bits data word length .
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
80066b8: b580 push {r7, lr}
|
|
80066ba: b09c sub sp, #112 @ 0x70
|
|
80066bc: af00 add r7, sp, #0
|
|
80066be: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
80066c0: 687b ldr r3, [r7, #4]
|
|
80066c2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
80066c6: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80066ca: 687b ldr r3, [r7, #4]
|
|
80066cc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80066d0: 2b22 cmp r3, #34 @ 0x22
|
|
80066d2: f040 80be bne.w 8006852 <UART_RxISR_8BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
80066d6: 687b ldr r3, [r7, #4]
|
|
80066d8: 681b ldr r3, [r3, #0]
|
|
80066da: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80066dc: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
80066e0: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
80066e4: b2d9 uxtb r1, r3
|
|
80066e6: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
80066ea: b2da uxtb r2, r3
|
|
80066ec: 687b ldr r3, [r7, #4]
|
|
80066ee: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80066f0: 400a ands r2, r1
|
|
80066f2: b2d2 uxtb r2, r2
|
|
80066f4: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
80066f6: 687b ldr r3, [r7, #4]
|
|
80066f8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80066fa: 1c5a adds r2, r3, #1
|
|
80066fc: 687b ldr r3, [r7, #4]
|
|
80066fe: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8006700: 687b ldr r3, [r7, #4]
|
|
8006702: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006706: b29b uxth r3, r3
|
|
8006708: 3b01 subs r3, #1
|
|
800670a: b29a uxth r2, r3
|
|
800670c: 687b ldr r3, [r7, #4]
|
|
800670e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8006712: 687b ldr r3, [r7, #4]
|
|
8006714: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006718: b29b uxth r3, r3
|
|
800671a: 2b00 cmp r3, #0
|
|
800671c: f040 80a1 bne.w 8006862 <UART_RxISR_8BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8006720: 687b ldr r3, [r7, #4]
|
|
8006722: 681b ldr r3, [r3, #0]
|
|
8006724: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006726: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006728: e853 3f00 ldrex r3, [r3]
|
|
800672c: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
800672e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8006730: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006734: 66bb str r3, [r7, #104] @ 0x68
|
|
8006736: 687b ldr r3, [r7, #4]
|
|
8006738: 681b ldr r3, [r3, #0]
|
|
800673a: 461a mov r2, r3
|
|
800673c: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800673e: 65bb str r3, [r7, #88] @ 0x58
|
|
8006740: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006742: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8006744: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8006746: e841 2300 strex r3, r2, [r1]
|
|
800674a: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
800674c: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800674e: 2b00 cmp r3, #0
|
|
8006750: d1e6 bne.n 8006720 <UART_RxISR_8BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006752: 687b ldr r3, [r7, #4]
|
|
8006754: 681b ldr r3, [r3, #0]
|
|
8006756: 3308 adds r3, #8
|
|
8006758: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800675a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800675c: e853 3f00 ldrex r3, [r3]
|
|
8006760: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006762: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006764: f023 0301 bic.w r3, r3, #1
|
|
8006768: 667b str r3, [r7, #100] @ 0x64
|
|
800676a: 687b ldr r3, [r7, #4]
|
|
800676c: 681b ldr r3, [r3, #0]
|
|
800676e: 3308 adds r3, #8
|
|
8006770: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
8006772: 647a str r2, [r7, #68] @ 0x44
|
|
8006774: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006776: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006778: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800677a: e841 2300 strex r3, r2, [r1]
|
|
800677e: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006780: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006782: 2b00 cmp r3, #0
|
|
8006784: d1e5 bne.n 8006752 <UART_RxISR_8BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006786: 687b ldr r3, [r7, #4]
|
|
8006788: 2220 movs r2, #32
|
|
800678a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
800678e: 687b ldr r3, [r7, #4]
|
|
8006790: 2200 movs r2, #0
|
|
8006792: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006794: 687b ldr r3, [r7, #4]
|
|
8006796: 2200 movs r2, #0
|
|
8006798: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
800679a: 687b ldr r3, [r7, #4]
|
|
800679c: 681b ldr r3, [r3, #0]
|
|
800679e: 4a33 ldr r2, [pc, #204] @ (800686c <UART_RxISR_8BIT+0x1b4>)
|
|
80067a0: 4293 cmp r3, r2
|
|
80067a2: d01f beq.n 80067e4 <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
80067a4: 687b ldr r3, [r7, #4]
|
|
80067a6: 681b ldr r3, [r3, #0]
|
|
80067a8: 685b ldr r3, [r3, #4]
|
|
80067aa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80067ae: 2b00 cmp r3, #0
|
|
80067b0: d018 beq.n 80067e4 <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
80067b2: 687b ldr r3, [r7, #4]
|
|
80067b4: 681b ldr r3, [r3, #0]
|
|
80067b6: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80067b8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80067ba: e853 3f00 ldrex r3, [r3]
|
|
80067be: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80067c0: 6a3b ldr r3, [r7, #32]
|
|
80067c2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
80067c6: 663b str r3, [r7, #96] @ 0x60
|
|
80067c8: 687b ldr r3, [r7, #4]
|
|
80067ca: 681b ldr r3, [r3, #0]
|
|
80067cc: 461a mov r2, r3
|
|
80067ce: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
80067d0: 633b str r3, [r7, #48] @ 0x30
|
|
80067d2: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80067d4: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80067d6: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80067d8: e841 2300 strex r3, r2, [r1]
|
|
80067dc: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80067de: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80067e0: 2b00 cmp r3, #0
|
|
80067e2: d1e6 bne.n 80067b2 <UART_RxISR_8BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80067e4: 687b ldr r3, [r7, #4]
|
|
80067e6: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80067e8: 2b01 cmp r3, #1
|
|
80067ea: d12e bne.n 800684a <UART_RxISR_8BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80067ec: 687b ldr r3, [r7, #4]
|
|
80067ee: 2200 movs r2, #0
|
|
80067f0: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80067f2: 687b ldr r3, [r7, #4]
|
|
80067f4: 681b ldr r3, [r3, #0]
|
|
80067f6: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80067f8: 693b ldr r3, [r7, #16]
|
|
80067fa: e853 3f00 ldrex r3, [r3]
|
|
80067fe: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006800: 68fb ldr r3, [r7, #12]
|
|
8006802: f023 0310 bic.w r3, r3, #16
|
|
8006806: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006808: 687b ldr r3, [r7, #4]
|
|
800680a: 681b ldr r3, [r3, #0]
|
|
800680c: 461a mov r2, r3
|
|
800680e: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006810: 61fb str r3, [r7, #28]
|
|
8006812: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006814: 69b9 ldr r1, [r7, #24]
|
|
8006816: 69fa ldr r2, [r7, #28]
|
|
8006818: e841 2300 strex r3, r2, [r1]
|
|
800681c: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800681e: 697b ldr r3, [r7, #20]
|
|
8006820: 2b00 cmp r3, #0
|
|
8006822: d1e6 bne.n 80067f2 <UART_RxISR_8BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8006824: 687b ldr r3, [r7, #4]
|
|
8006826: 681b ldr r3, [r3, #0]
|
|
8006828: 69db ldr r3, [r3, #28]
|
|
800682a: f003 0310 and.w r3, r3, #16
|
|
800682e: 2b10 cmp r3, #16
|
|
8006830: d103 bne.n 800683a <UART_RxISR_8BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8006832: 687b ldr r3, [r7, #4]
|
|
8006834: 681b ldr r3, [r3, #0]
|
|
8006836: 2210 movs r2, #16
|
|
8006838: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800683a: 687b ldr r3, [r7, #4]
|
|
800683c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8006840: 4619 mov r1, r3
|
|
8006842: 6878 ldr r0, [r7, #4]
|
|
8006844: f7ff f872 bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8006848: e00b b.n 8006862 <UART_RxISR_8BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
800684a: 6878 ldr r0, [r7, #4]
|
|
800684c: f7fa fe80 bl 8001550 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8006850: e007 b.n 8006862 <UART_RxISR_8BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8006852: 687b ldr r3, [r7, #4]
|
|
8006854: 681b ldr r3, [r3, #0]
|
|
8006856: 699a ldr r2, [r3, #24]
|
|
8006858: 687b ldr r3, [r7, #4]
|
|
800685a: 681b ldr r3, [r3, #0]
|
|
800685c: f042 0208 orr.w r2, r2, #8
|
|
8006860: 619a str r2, [r3, #24]
|
|
}
|
|
8006862: bf00 nop
|
|
8006864: 3770 adds r7, #112 @ 0x70
|
|
8006866: 46bd mov sp, r7
|
|
8006868: bd80 pop {r7, pc}
|
|
800686a: bf00 nop
|
|
800686c: 40008000 .word 0x40008000
|
|
|
|
08006870 <UART_RxISR_16BIT>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006870: b580 push {r7, lr}
|
|
8006872: b09c sub sp, #112 @ 0x70
|
|
8006874: af00 add r7, sp, #0
|
|
8006876: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
8006878: 687b ldr r3, [r7, #4]
|
|
800687a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
800687e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006882: 687b ldr r3, [r7, #4]
|
|
8006884: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8006888: 2b22 cmp r3, #34 @ 0x22
|
|
800688a: f040 80be bne.w 8006a0a <UART_RxISR_16BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
800688e: 687b ldr r3, [r7, #4]
|
|
8006890: 681b ldr r3, [r3, #0]
|
|
8006892: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006894: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
8006898: 687b ldr r3, [r7, #4]
|
|
800689a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800689c: 66bb str r3, [r7, #104] @ 0x68
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
800689e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
|
|
80068a2: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
80068a6: 4013 ands r3, r2
|
|
80068a8: b29a uxth r2, r3
|
|
80068aa: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80068ac: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
80068ae: 687b ldr r3, [r7, #4]
|
|
80068b0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80068b2: 1c9a adds r2, r3, #2
|
|
80068b4: 687b ldr r3, [r7, #4]
|
|
80068b6: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
80068b8: 687b ldr r3, [r7, #4]
|
|
80068ba: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80068be: b29b uxth r3, r3
|
|
80068c0: 3b01 subs r3, #1
|
|
80068c2: b29a uxth r2, r3
|
|
80068c4: 687b ldr r3, [r7, #4]
|
|
80068c6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
80068ca: 687b ldr r3, [r7, #4]
|
|
80068cc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80068d0: b29b uxth r3, r3
|
|
80068d2: 2b00 cmp r3, #0
|
|
80068d4: f040 80a1 bne.w 8006a1a <UART_RxISR_16BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
80068d8: 687b ldr r3, [r7, #4]
|
|
80068da: 681b ldr r3, [r3, #0]
|
|
80068dc: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80068de: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80068e0: e853 3f00 ldrex r3, [r3]
|
|
80068e4: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
80068e6: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80068e8: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80068ec: 667b str r3, [r7, #100] @ 0x64
|
|
80068ee: 687b ldr r3, [r7, #4]
|
|
80068f0: 681b ldr r3, [r3, #0]
|
|
80068f2: 461a mov r2, r3
|
|
80068f4: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80068f6: 657b str r3, [r7, #84] @ 0x54
|
|
80068f8: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80068fa: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
80068fc: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
80068fe: e841 2300 strex r3, r2, [r1]
|
|
8006902: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
8006904: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006906: 2b00 cmp r3, #0
|
|
8006908: d1e6 bne.n 80068d8 <UART_RxISR_16BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800690a: 687b ldr r3, [r7, #4]
|
|
800690c: 681b ldr r3, [r3, #0]
|
|
800690e: 3308 adds r3, #8
|
|
8006910: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006912: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006914: e853 3f00 ldrex r3, [r3]
|
|
8006918: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
800691a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800691c: f023 0301 bic.w r3, r3, #1
|
|
8006920: 663b str r3, [r7, #96] @ 0x60
|
|
8006922: 687b ldr r3, [r7, #4]
|
|
8006924: 681b ldr r3, [r3, #0]
|
|
8006926: 3308 adds r3, #8
|
|
8006928: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
800692a: 643a str r2, [r7, #64] @ 0x40
|
|
800692c: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800692e: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006930: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006932: e841 2300 strex r3, r2, [r1]
|
|
8006936: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006938: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800693a: 2b00 cmp r3, #0
|
|
800693c: d1e5 bne.n 800690a <UART_RxISR_16BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800693e: 687b ldr r3, [r7, #4]
|
|
8006940: 2220 movs r2, #32
|
|
8006942: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8006946: 687b ldr r3, [r7, #4]
|
|
8006948: 2200 movs r2, #0
|
|
800694a: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800694c: 687b ldr r3, [r7, #4]
|
|
800694e: 2200 movs r2, #0
|
|
8006950: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8006952: 687b ldr r3, [r7, #4]
|
|
8006954: 681b ldr r3, [r3, #0]
|
|
8006956: 4a33 ldr r2, [pc, #204] @ (8006a24 <UART_RxISR_16BIT+0x1b4>)
|
|
8006958: 4293 cmp r3, r2
|
|
800695a: d01f beq.n 800699c <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
800695c: 687b ldr r3, [r7, #4]
|
|
800695e: 681b ldr r3, [r3, #0]
|
|
8006960: 685b ldr r3, [r3, #4]
|
|
8006962: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8006966: 2b00 cmp r3, #0
|
|
8006968: d018 beq.n 800699c <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
800696a: 687b ldr r3, [r7, #4]
|
|
800696c: 681b ldr r3, [r3, #0]
|
|
800696e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006970: 6a3b ldr r3, [r7, #32]
|
|
8006972: e853 3f00 ldrex r3, [r3]
|
|
8006976: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006978: 69fb ldr r3, [r7, #28]
|
|
800697a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
800697e: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006980: 687b ldr r3, [r7, #4]
|
|
8006982: 681b ldr r3, [r3, #0]
|
|
8006984: 461a mov r2, r3
|
|
8006986: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006988: 62fb str r3, [r7, #44] @ 0x2c
|
|
800698a: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800698c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800698e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8006990: e841 2300 strex r3, r2, [r1]
|
|
8006994: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006996: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006998: 2b00 cmp r3, #0
|
|
800699a: d1e6 bne.n 800696a <UART_RxISR_16BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800699c: 687b ldr r3, [r7, #4]
|
|
800699e: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80069a0: 2b01 cmp r3, #1
|
|
80069a2: d12e bne.n 8006a02 <UART_RxISR_16BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80069a4: 687b ldr r3, [r7, #4]
|
|
80069a6: 2200 movs r2, #0
|
|
80069a8: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80069aa: 687b ldr r3, [r7, #4]
|
|
80069ac: 681b ldr r3, [r3, #0]
|
|
80069ae: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80069b0: 68fb ldr r3, [r7, #12]
|
|
80069b2: e853 3f00 ldrex r3, [r3]
|
|
80069b6: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80069b8: 68bb ldr r3, [r7, #8]
|
|
80069ba: f023 0310 bic.w r3, r3, #16
|
|
80069be: 65bb str r3, [r7, #88] @ 0x58
|
|
80069c0: 687b ldr r3, [r7, #4]
|
|
80069c2: 681b ldr r3, [r3, #0]
|
|
80069c4: 461a mov r2, r3
|
|
80069c6: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80069c8: 61bb str r3, [r7, #24]
|
|
80069ca: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80069cc: 6979 ldr r1, [r7, #20]
|
|
80069ce: 69ba ldr r2, [r7, #24]
|
|
80069d0: e841 2300 strex r3, r2, [r1]
|
|
80069d4: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80069d6: 693b ldr r3, [r7, #16]
|
|
80069d8: 2b00 cmp r3, #0
|
|
80069da: d1e6 bne.n 80069aa <UART_RxISR_16BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
80069dc: 687b ldr r3, [r7, #4]
|
|
80069de: 681b ldr r3, [r3, #0]
|
|
80069e0: 69db ldr r3, [r3, #28]
|
|
80069e2: f003 0310 and.w r3, r3, #16
|
|
80069e6: 2b10 cmp r3, #16
|
|
80069e8: d103 bne.n 80069f2 <UART_RxISR_16BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80069ea: 687b ldr r3, [r7, #4]
|
|
80069ec: 681b ldr r3, [r3, #0]
|
|
80069ee: 2210 movs r2, #16
|
|
80069f0: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80069f2: 687b ldr r3, [r7, #4]
|
|
80069f4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80069f8: 4619 mov r1, r3
|
|
80069fa: 6878 ldr r0, [r7, #4]
|
|
80069fc: f7fe ff96 bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8006a00: e00b b.n 8006a1a <UART_RxISR_16BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8006a02: 6878 ldr r0, [r7, #4]
|
|
8006a04: f7fa fda4 bl 8001550 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8006a08: e007 b.n 8006a1a <UART_RxISR_16BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8006a0a: 687b ldr r3, [r7, #4]
|
|
8006a0c: 681b ldr r3, [r3, #0]
|
|
8006a0e: 699a ldr r2, [r3, #24]
|
|
8006a10: 687b ldr r3, [r7, #4]
|
|
8006a12: 681b ldr r3, [r3, #0]
|
|
8006a14: f042 0208 orr.w r2, r2, #8
|
|
8006a18: 619a str r2, [r3, #24]
|
|
}
|
|
8006a1a: bf00 nop
|
|
8006a1c: 3770 adds r7, #112 @ 0x70
|
|
8006a1e: 46bd mov sp, r7
|
|
8006a20: bd80 pop {r7, pc}
|
|
8006a22: bf00 nop
|
|
8006a24: 40008000 .word 0x40008000
|
|
|
|
08006a28 <UART_RxISR_8BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
8006a28: b580 push {r7, lr}
|
|
8006a2a: b0ac sub sp, #176 @ 0xb0
|
|
8006a2c: af00 add r7, sp, #0
|
|
8006a2e: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8006a30: 687b ldr r3, [r7, #4]
|
|
8006a32: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
8006a36: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8006a3a: 687b ldr r3, [r7, #4]
|
|
8006a3c: 681b ldr r3, [r3, #0]
|
|
8006a3e: 69db ldr r3, [r3, #28]
|
|
8006a40: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8006a44: 687b ldr r3, [r7, #4]
|
|
8006a46: 681b ldr r3, [r3, #0]
|
|
8006a48: 681b ldr r3, [r3, #0]
|
|
8006a4a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8006a4e: 687b ldr r3, [r7, #4]
|
|
8006a50: 681b ldr r3, [r3, #0]
|
|
8006a52: 689b ldr r3, [r3, #8]
|
|
8006a54: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006a58: 687b ldr r3, [r7, #4]
|
|
8006a5a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8006a5e: 2b22 cmp r3, #34 @ 0x22
|
|
8006a60: f040 8183 bne.w 8006d6a <UART_RxISR_8BIT_FIFOEN+0x342>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
8006a64: 687b ldr r3, [r7, #4]
|
|
8006a66: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8006a6a: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8006a6e: e126 b.n 8006cbe <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8006a70: 687b ldr r3, [r7, #4]
|
|
8006a72: 681b ldr r3, [r3, #0]
|
|
8006a74: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006a76: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
8006a7a: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
|
|
8006a7e: b2d9 uxtb r1, r3
|
|
8006a80: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
|
|
8006a84: b2da uxtb r2, r3
|
|
8006a86: 687b ldr r3, [r7, #4]
|
|
8006a88: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006a8a: 400a ands r2, r1
|
|
8006a8c: b2d2 uxtb r2, r2
|
|
8006a8e: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
8006a90: 687b ldr r3, [r7, #4]
|
|
8006a92: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006a94: 1c5a adds r2, r3, #1
|
|
8006a96: 687b ldr r3, [r7, #4]
|
|
8006a98: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8006a9a: 687b ldr r3, [r7, #4]
|
|
8006a9c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006aa0: b29b uxth r3, r3
|
|
8006aa2: 3b01 subs r3, #1
|
|
8006aa4: b29a uxth r2, r3
|
|
8006aa6: 687b ldr r3, [r7, #4]
|
|
8006aa8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
8006aac: 687b ldr r3, [r7, #4]
|
|
8006aae: 681b ldr r3, [r3, #0]
|
|
8006ab0: 69db ldr r3, [r3, #28]
|
|
8006ab2: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
8006ab6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006aba: f003 0307 and.w r3, r3, #7
|
|
8006abe: 2b00 cmp r3, #0
|
|
8006ac0: d053 beq.n 8006b6a <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8006ac2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006ac6: f003 0301 and.w r3, r3, #1
|
|
8006aca: 2b00 cmp r3, #0
|
|
8006acc: d011 beq.n 8006af2 <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
8006ace: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8006ad2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8006ad6: 2b00 cmp r3, #0
|
|
8006ad8: d00b beq.n 8006af2 <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8006ada: 687b ldr r3, [r7, #4]
|
|
8006adc: 681b ldr r3, [r3, #0]
|
|
8006ade: 2201 movs r2, #1
|
|
8006ae0: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8006ae2: 687b ldr r3, [r7, #4]
|
|
8006ae4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006ae8: f043 0201 orr.w r2, r3, #1
|
|
8006aec: 687b ldr r3, [r7, #4]
|
|
8006aee: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8006af2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006af6: f003 0302 and.w r3, r3, #2
|
|
8006afa: 2b00 cmp r3, #0
|
|
8006afc: d011 beq.n 8006b22 <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
8006afe: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8006b02: f003 0301 and.w r3, r3, #1
|
|
8006b06: 2b00 cmp r3, #0
|
|
8006b08: d00b beq.n 8006b22 <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8006b0a: 687b ldr r3, [r7, #4]
|
|
8006b0c: 681b ldr r3, [r3, #0]
|
|
8006b0e: 2202 movs r2, #2
|
|
8006b10: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8006b12: 687b ldr r3, [r7, #4]
|
|
8006b14: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006b18: f043 0204 orr.w r2, r3, #4
|
|
8006b1c: 687b ldr r3, [r7, #4]
|
|
8006b1e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8006b22: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006b26: f003 0304 and.w r3, r3, #4
|
|
8006b2a: 2b00 cmp r3, #0
|
|
8006b2c: d011 beq.n 8006b52 <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
8006b2e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8006b32: f003 0301 and.w r3, r3, #1
|
|
8006b36: 2b00 cmp r3, #0
|
|
8006b38: d00b beq.n 8006b52 <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8006b3a: 687b ldr r3, [r7, #4]
|
|
8006b3c: 681b ldr r3, [r3, #0]
|
|
8006b3e: 2204 movs r2, #4
|
|
8006b40: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8006b42: 687b ldr r3, [r7, #4]
|
|
8006b44: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006b48: f043 0202 orr.w r2, r3, #2
|
|
8006b4c: 687b ldr r3, [r7, #4]
|
|
8006b4e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8006b52: 687b ldr r3, [r7, #4]
|
|
8006b54: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006b58: 2b00 cmp r3, #0
|
|
8006b5a: d006 beq.n 8006b6a <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006b5c: 6878 ldr r0, [r7, #4]
|
|
8006b5e: f7fe fedc bl 800591a <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006b62: 687b ldr r3, [r7, #4]
|
|
8006b64: 2200 movs r2, #0
|
|
8006b66: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8006b6a: 687b ldr r3, [r7, #4]
|
|
8006b6c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006b70: b29b uxth r3, r3
|
|
8006b72: 2b00 cmp r3, #0
|
|
8006b74: f040 80a3 bne.w 8006cbe <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8006b78: 687b ldr r3, [r7, #4]
|
|
8006b7a: 681b ldr r3, [r3, #0]
|
|
8006b7c: 673b str r3, [r7, #112] @ 0x70
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006b7e: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8006b80: e853 3f00 ldrex r3, [r3]
|
|
8006b84: 66fb str r3, [r7, #108] @ 0x6c
|
|
return(result);
|
|
8006b86: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006b88: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8006b8c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8006b90: 687b ldr r3, [r7, #4]
|
|
8006b92: 681b ldr r3, [r3, #0]
|
|
8006b94: 461a mov r2, r3
|
|
8006b96: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006b9a: 67fb str r3, [r7, #124] @ 0x7c
|
|
8006b9c: 67ba str r2, [r7, #120] @ 0x78
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006b9e: 6fb9 ldr r1, [r7, #120] @ 0x78
|
|
8006ba0: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
8006ba2: e841 2300 strex r3, r2, [r1]
|
|
8006ba6: 677b str r3, [r7, #116] @ 0x74
|
|
return(result);
|
|
8006ba8: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8006baa: 2b00 cmp r3, #0
|
|
8006bac: d1e4 bne.n 8006b78 <UART_RxISR_8BIT_FIFOEN+0x150>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8006bae: 687b ldr r3, [r7, #4]
|
|
8006bb0: 681b ldr r3, [r3, #0]
|
|
8006bb2: 3308 adds r3, #8
|
|
8006bb4: 65fb str r3, [r7, #92] @ 0x5c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006bb6: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006bb8: e853 3f00 ldrex r3, [r3]
|
|
8006bbc: 65bb str r3, [r7, #88] @ 0x58
|
|
return(result);
|
|
8006bbe: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8006bc0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8006bc4: f023 0301 bic.w r3, r3, #1
|
|
8006bc8: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8006bcc: 687b ldr r3, [r7, #4]
|
|
8006bce: 681b ldr r3, [r3, #0]
|
|
8006bd0: 3308 adds r3, #8
|
|
8006bd2: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8006bd6: 66ba str r2, [r7, #104] @ 0x68
|
|
8006bd8: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006bda: 6e79 ldr r1, [r7, #100] @ 0x64
|
|
8006bdc: 6eba ldr r2, [r7, #104] @ 0x68
|
|
8006bde: e841 2300 strex r3, r2, [r1]
|
|
8006be2: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
8006be4: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006be6: 2b00 cmp r3, #0
|
|
8006be8: d1e1 bne.n 8006bae <UART_RxISR_8BIT_FIFOEN+0x186>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006bea: 687b ldr r3, [r7, #4]
|
|
8006bec: 2220 movs r2, #32
|
|
8006bee: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8006bf2: 687b ldr r3, [r7, #4]
|
|
8006bf4: 2200 movs r2, #0
|
|
8006bf6: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006bf8: 687b ldr r3, [r7, #4]
|
|
8006bfa: 2200 movs r2, #0
|
|
8006bfc: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8006bfe: 687b ldr r3, [r7, #4]
|
|
8006c00: 681b ldr r3, [r3, #0]
|
|
8006c02: 4a60 ldr r2, [pc, #384] @ (8006d84 <UART_RxISR_8BIT_FIFOEN+0x35c>)
|
|
8006c04: 4293 cmp r3, r2
|
|
8006c06: d021 beq.n 8006c4c <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8006c08: 687b ldr r3, [r7, #4]
|
|
8006c0a: 681b ldr r3, [r3, #0]
|
|
8006c0c: 685b ldr r3, [r3, #4]
|
|
8006c0e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8006c12: 2b00 cmp r3, #0
|
|
8006c14: d01a beq.n 8006c4c <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8006c16: 687b ldr r3, [r7, #4]
|
|
8006c18: 681b ldr r3, [r3, #0]
|
|
8006c1a: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006c1c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8006c1e: e853 3f00 ldrex r3, [r3]
|
|
8006c22: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8006c24: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006c26: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8006c2a: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8006c2e: 687b ldr r3, [r7, #4]
|
|
8006c30: 681b ldr r3, [r3, #0]
|
|
8006c32: 461a mov r2, r3
|
|
8006c34: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8006c38: 657b str r3, [r7, #84] @ 0x54
|
|
8006c3a: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006c3c: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8006c3e: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8006c40: e841 2300 strex r3, r2, [r1]
|
|
8006c44: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
8006c46: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006c48: 2b00 cmp r3, #0
|
|
8006c4a: d1e4 bne.n 8006c16 <UART_RxISR_8BIT_FIFOEN+0x1ee>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006c4c: 687b ldr r3, [r7, #4]
|
|
8006c4e: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006c50: 2b01 cmp r3, #1
|
|
8006c52: d130 bne.n 8006cb6 <UART_RxISR_8BIT_FIFOEN+0x28e>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006c54: 687b ldr r3, [r7, #4]
|
|
8006c56: 2200 movs r2, #0
|
|
8006c58: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006c5a: 687b ldr r3, [r7, #4]
|
|
8006c5c: 681b ldr r3, [r3, #0]
|
|
8006c5e: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006c60: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006c62: e853 3f00 ldrex r3, [r3]
|
|
8006c66: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006c68: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006c6a: f023 0310 bic.w r3, r3, #16
|
|
8006c6e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
8006c72: 687b ldr r3, [r7, #4]
|
|
8006c74: 681b ldr r3, [r3, #0]
|
|
8006c76: 461a mov r2, r3
|
|
8006c78: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c7c: 643b str r3, [r7, #64] @ 0x40
|
|
8006c7e: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006c80: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006c82: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006c84: e841 2300 strex r3, r2, [r1]
|
|
8006c88: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006c8a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006c8c: 2b00 cmp r3, #0
|
|
8006c8e: d1e4 bne.n 8006c5a <UART_RxISR_8BIT_FIFOEN+0x232>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8006c90: 687b ldr r3, [r7, #4]
|
|
8006c92: 681b ldr r3, [r3, #0]
|
|
8006c94: 69db ldr r3, [r3, #28]
|
|
8006c96: f003 0310 and.w r3, r3, #16
|
|
8006c9a: 2b10 cmp r3, #16
|
|
8006c9c: d103 bne.n 8006ca6 <UART_RxISR_8BIT_FIFOEN+0x27e>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8006c9e: 687b ldr r3, [r7, #4]
|
|
8006ca0: 681b ldr r3, [r3, #0]
|
|
8006ca2: 2210 movs r2, #16
|
|
8006ca4: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8006ca6: 687b ldr r3, [r7, #4]
|
|
8006ca8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8006cac: 4619 mov r1, r3
|
|
8006cae: 6878 ldr r0, [r7, #4]
|
|
8006cb0: f7fe fe3c bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
8006cb4: e00e b.n 8006cd4 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8006cb6: 6878 ldr r0, [r7, #4]
|
|
8006cb8: f7fa fc4a bl 8001550 <HAL_UART_RxCpltCallback>
|
|
break;
|
|
8006cbc: e00a b.n 8006cd4 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8006cbe: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
|
|
8006cc2: 2b00 cmp r3, #0
|
|
8006cc4: d006 beq.n 8006cd4 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
8006cc6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006cca: f003 0320 and.w r3, r3, #32
|
|
8006cce: 2b00 cmp r3, #0
|
|
8006cd0: f47f aece bne.w 8006a70 <UART_RxISR_8BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
8006cd4: 687b ldr r3, [r7, #4]
|
|
8006cd6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006cda: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
8006cde: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
8006ce2: 2b00 cmp r3, #0
|
|
8006ce4: d049 beq.n 8006d7a <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
8006ce6: 687b ldr r3, [r7, #4]
|
|
8006ce8: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8006cec: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
|
|
8006cf0: 429a cmp r2, r3
|
|
8006cf2: d242 bcs.n 8006d7a <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
8006cf4: 687b ldr r3, [r7, #4]
|
|
8006cf6: 681b ldr r3, [r3, #0]
|
|
8006cf8: 3308 adds r3, #8
|
|
8006cfa: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006cfc: 6a3b ldr r3, [r7, #32]
|
|
8006cfe: e853 3f00 ldrex r3, [r3]
|
|
8006d02: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006d04: 69fb ldr r3, [r7, #28]
|
|
8006d06: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8006d0a: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006d0e: 687b ldr r3, [r7, #4]
|
|
8006d10: 681b ldr r3, [r3, #0]
|
|
8006d12: 3308 adds r3, #8
|
|
8006d14: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
8006d18: 62fa str r2, [r7, #44] @ 0x2c
|
|
8006d1a: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006d1c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8006d1e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8006d20: e841 2300 strex r3, r2, [r1]
|
|
8006d24: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006d26: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006d28: 2b00 cmp r3, #0
|
|
8006d2a: d1e3 bne.n 8006cf4 <UART_RxISR_8BIT_FIFOEN+0x2cc>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
8006d2c: 687b ldr r3, [r7, #4]
|
|
8006d2e: 4a16 ldr r2, [pc, #88] @ (8006d88 <UART_RxISR_8BIT_FIFOEN+0x360>)
|
|
8006d30: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
8006d32: 687b ldr r3, [r7, #4]
|
|
8006d34: 681b ldr r3, [r3, #0]
|
|
8006d36: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006d38: 68fb ldr r3, [r7, #12]
|
|
8006d3a: e853 3f00 ldrex r3, [r3]
|
|
8006d3e: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006d40: 68bb ldr r3, [r7, #8]
|
|
8006d42: f043 0320 orr.w r3, r3, #32
|
|
8006d46: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8006d4a: 687b ldr r3, [r7, #4]
|
|
8006d4c: 681b ldr r3, [r3, #0]
|
|
8006d4e: 461a mov r2, r3
|
|
8006d50: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8006d54: 61bb str r3, [r7, #24]
|
|
8006d56: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006d58: 6979 ldr r1, [r7, #20]
|
|
8006d5a: 69ba ldr r2, [r7, #24]
|
|
8006d5c: e841 2300 strex r3, r2, [r1]
|
|
8006d60: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006d62: 693b ldr r3, [r7, #16]
|
|
8006d64: 2b00 cmp r3, #0
|
|
8006d66: d1e4 bne.n 8006d32 <UART_RxISR_8BIT_FIFOEN+0x30a>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8006d68: e007 b.n 8006d7a <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8006d6a: 687b ldr r3, [r7, #4]
|
|
8006d6c: 681b ldr r3, [r3, #0]
|
|
8006d6e: 699a ldr r2, [r3, #24]
|
|
8006d70: 687b ldr r3, [r7, #4]
|
|
8006d72: 681b ldr r3, [r3, #0]
|
|
8006d74: f042 0208 orr.w r2, r2, #8
|
|
8006d78: 619a str r2, [r3, #24]
|
|
}
|
|
8006d7a: bf00 nop
|
|
8006d7c: 37b0 adds r7, #176 @ 0xb0
|
|
8006d7e: 46bd mov sp, r7
|
|
8006d80: bd80 pop {r7, pc}
|
|
8006d82: bf00 nop
|
|
8006d84: 40008000 .word 0x40008000
|
|
8006d88: 080066b9 .word 0x080066b9
|
|
|
|
08006d8c <UART_RxISR_16BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
8006d8c: b580 push {r7, lr}
|
|
8006d8e: b0ae sub sp, #184 @ 0xb8
|
|
8006d90: af00 add r7, sp, #0
|
|
8006d92: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
8006d94: 687b ldr r3, [r7, #4]
|
|
8006d96: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
8006d9a: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8006d9e: 687b ldr r3, [r7, #4]
|
|
8006da0: 681b ldr r3, [r3, #0]
|
|
8006da2: 69db ldr r3, [r3, #28]
|
|
8006da4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8006da8: 687b ldr r3, [r7, #4]
|
|
8006daa: 681b ldr r3, [r3, #0]
|
|
8006dac: 681b ldr r3, [r3, #0]
|
|
8006dae: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8006db2: 687b ldr r3, [r7, #4]
|
|
8006db4: 681b ldr r3, [r3, #0]
|
|
8006db6: 689b ldr r3, [r3, #8]
|
|
8006db8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006dbc: 687b ldr r3, [r7, #4]
|
|
8006dbe: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8006dc2: 2b22 cmp r3, #34 @ 0x22
|
|
8006dc4: f040 8187 bne.w 80070d6 <UART_RxISR_16BIT_FIFOEN+0x34a>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
8006dc8: 687b ldr r3, [r7, #4]
|
|
8006dca: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8006dce: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8006dd2: e12a b.n 800702a <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8006dd4: 687b ldr r3, [r7, #4]
|
|
8006dd6: 681b ldr r3, [r3, #0]
|
|
8006dd8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006dda: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
8006dde: 687b ldr r3, [r7, #4]
|
|
8006de0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006de2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
8006de6: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
|
|
8006dea: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
|
|
8006dee: 4013 ands r3, r2
|
|
8006df0: b29a uxth r2, r3
|
|
8006df2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8006df6: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
8006df8: 687b ldr r3, [r7, #4]
|
|
8006dfa: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006dfc: 1c9a adds r2, r3, #2
|
|
8006dfe: 687b ldr r3, [r7, #4]
|
|
8006e00: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8006e02: 687b ldr r3, [r7, #4]
|
|
8006e04: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006e08: b29b uxth r3, r3
|
|
8006e0a: 3b01 subs r3, #1
|
|
8006e0c: b29a uxth r2, r3
|
|
8006e0e: 687b ldr r3, [r7, #4]
|
|
8006e10: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
8006e14: 687b ldr r3, [r7, #4]
|
|
8006e16: 681b ldr r3, [r3, #0]
|
|
8006e18: 69db ldr r3, [r3, #28]
|
|
8006e1a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
8006e1e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e22: f003 0307 and.w r3, r3, #7
|
|
8006e26: 2b00 cmp r3, #0
|
|
8006e28: d053 beq.n 8006ed2 <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8006e2a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e2e: f003 0301 and.w r3, r3, #1
|
|
8006e32: 2b00 cmp r3, #0
|
|
8006e34: d011 beq.n 8006e5a <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
8006e36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006e3a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8006e3e: 2b00 cmp r3, #0
|
|
8006e40: d00b beq.n 8006e5a <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8006e42: 687b ldr r3, [r7, #4]
|
|
8006e44: 681b ldr r3, [r3, #0]
|
|
8006e46: 2201 movs r2, #1
|
|
8006e48: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8006e4a: 687b ldr r3, [r7, #4]
|
|
8006e4c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006e50: f043 0201 orr.w r2, r3, #1
|
|
8006e54: 687b ldr r3, [r7, #4]
|
|
8006e56: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8006e5a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e5e: f003 0302 and.w r3, r3, #2
|
|
8006e62: 2b00 cmp r3, #0
|
|
8006e64: d011 beq.n 8006e8a <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
8006e66: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006e6a: f003 0301 and.w r3, r3, #1
|
|
8006e6e: 2b00 cmp r3, #0
|
|
8006e70: d00b beq.n 8006e8a <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8006e72: 687b ldr r3, [r7, #4]
|
|
8006e74: 681b ldr r3, [r3, #0]
|
|
8006e76: 2202 movs r2, #2
|
|
8006e78: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8006e7a: 687b ldr r3, [r7, #4]
|
|
8006e7c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006e80: f043 0204 orr.w r2, r3, #4
|
|
8006e84: 687b ldr r3, [r7, #4]
|
|
8006e86: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8006e8a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e8e: f003 0304 and.w r3, r3, #4
|
|
8006e92: 2b00 cmp r3, #0
|
|
8006e94: d011 beq.n 8006eba <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
8006e96: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006e9a: f003 0301 and.w r3, r3, #1
|
|
8006e9e: 2b00 cmp r3, #0
|
|
8006ea0: d00b beq.n 8006eba <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8006ea2: 687b ldr r3, [r7, #4]
|
|
8006ea4: 681b ldr r3, [r3, #0]
|
|
8006ea6: 2204 movs r2, #4
|
|
8006ea8: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8006eaa: 687b ldr r3, [r7, #4]
|
|
8006eac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006eb0: f043 0202 orr.w r2, r3, #2
|
|
8006eb4: 687b ldr r3, [r7, #4]
|
|
8006eb6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8006eba: 687b ldr r3, [r7, #4]
|
|
8006ebc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006ec0: 2b00 cmp r3, #0
|
|
8006ec2: d006 beq.n 8006ed2 <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006ec4: 6878 ldr r0, [r7, #4]
|
|
8006ec6: f7fe fd28 bl 800591a <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006eca: 687b ldr r3, [r7, #4]
|
|
8006ecc: 2200 movs r2, #0
|
|
8006ece: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8006ed2: 687b ldr r3, [r7, #4]
|
|
8006ed4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006ed8: b29b uxth r3, r3
|
|
8006eda: 2b00 cmp r3, #0
|
|
8006edc: f040 80a5 bne.w 800702a <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8006ee0: 687b ldr r3, [r7, #4]
|
|
8006ee2: 681b ldr r3, [r3, #0]
|
|
8006ee4: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006ee6: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8006ee8: e853 3f00 ldrex r3, [r3]
|
|
8006eec: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8006eee: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8006ef0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8006ef4: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8006ef8: 687b ldr r3, [r7, #4]
|
|
8006efa: 681b ldr r3, [r3, #0]
|
|
8006efc: 461a mov r2, r3
|
|
8006efe: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8006f02: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8006f06: 67fa str r2, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006f08: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8006f0a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8006f0e: e841 2300 strex r3, r2, [r1]
|
|
8006f12: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8006f14: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006f16: 2b00 cmp r3, #0
|
|
8006f18: d1e2 bne.n 8006ee0 <UART_RxISR_16BIT_FIFOEN+0x154>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8006f1a: 687b ldr r3, [r7, #4]
|
|
8006f1c: 681b ldr r3, [r3, #0]
|
|
8006f1e: 3308 adds r3, #8
|
|
8006f20: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006f22: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006f24: e853 3f00 ldrex r3, [r3]
|
|
8006f28: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8006f2a: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006f2c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8006f30: f023 0301 bic.w r3, r3, #1
|
|
8006f34: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8006f38: 687b ldr r3, [r7, #4]
|
|
8006f3a: 681b ldr r3, [r3, #0]
|
|
8006f3c: 3308 adds r3, #8
|
|
8006f3e: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
|
|
8006f42: 66fa str r2, [r7, #108] @ 0x6c
|
|
8006f44: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006f46: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8006f48: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8006f4a: e841 2300 strex r3, r2, [r1]
|
|
8006f4e: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8006f50: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8006f52: 2b00 cmp r3, #0
|
|
8006f54: d1e1 bne.n 8006f1a <UART_RxISR_16BIT_FIFOEN+0x18e>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006f56: 687b ldr r3, [r7, #4]
|
|
8006f58: 2220 movs r2, #32
|
|
8006f5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8006f5e: 687b ldr r3, [r7, #4]
|
|
8006f60: 2200 movs r2, #0
|
|
8006f62: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006f64: 687b ldr r3, [r7, #4]
|
|
8006f66: 2200 movs r2, #0
|
|
8006f68: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8006f6a: 687b ldr r3, [r7, #4]
|
|
8006f6c: 681b ldr r3, [r3, #0]
|
|
8006f6e: 4a60 ldr r2, [pc, #384] @ (80070f0 <UART_RxISR_16BIT_FIFOEN+0x364>)
|
|
8006f70: 4293 cmp r3, r2
|
|
8006f72: d021 beq.n 8006fb8 <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8006f74: 687b ldr r3, [r7, #4]
|
|
8006f76: 681b ldr r3, [r3, #0]
|
|
8006f78: 685b ldr r3, [r3, #4]
|
|
8006f7a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8006f7e: 2b00 cmp r3, #0
|
|
8006f80: d01a beq.n 8006fb8 <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8006f82: 687b ldr r3, [r7, #4]
|
|
8006f84: 681b ldr r3, [r3, #0]
|
|
8006f86: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006f88: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006f8a: e853 3f00 ldrex r3, [r3]
|
|
8006f8e: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8006f90: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8006f92: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8006f96: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8006f9a: 687b ldr r3, [r7, #4]
|
|
8006f9c: 681b ldr r3, [r3, #0]
|
|
8006f9e: 461a mov r2, r3
|
|
8006fa0: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
8006fa4: 65bb str r3, [r7, #88] @ 0x58
|
|
8006fa6: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fa8: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8006faa: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8006fac: e841 2300 strex r3, r2, [r1]
|
|
8006fb0: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8006fb2: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8006fb4: 2b00 cmp r3, #0
|
|
8006fb6: d1e4 bne.n 8006f82 <UART_RxISR_16BIT_FIFOEN+0x1f6>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006fb8: 687b ldr r3, [r7, #4]
|
|
8006fba: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006fbc: 2b01 cmp r3, #1
|
|
8006fbe: d130 bne.n 8007022 <UART_RxISR_16BIT_FIFOEN+0x296>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006fc0: 687b ldr r3, [r7, #4]
|
|
8006fc2: 2200 movs r2, #0
|
|
8006fc4: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006fc6: 687b ldr r3, [r7, #4]
|
|
8006fc8: 681b ldr r3, [r3, #0]
|
|
8006fca: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006fcc: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006fce: e853 3f00 ldrex r3, [r3]
|
|
8006fd2: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006fd4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006fd6: f023 0310 bic.w r3, r3, #16
|
|
8006fda: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8006fde: 687b ldr r3, [r7, #4]
|
|
8006fe0: 681b ldr r3, [r3, #0]
|
|
8006fe2: 461a mov r2, r3
|
|
8006fe4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8006fe8: 647b str r3, [r7, #68] @ 0x44
|
|
8006fea: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fec: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006fee: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006ff0: e841 2300 strex r3, r2, [r1]
|
|
8006ff4: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006ff6: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006ff8: 2b00 cmp r3, #0
|
|
8006ffa: d1e4 bne.n 8006fc6 <UART_RxISR_16BIT_FIFOEN+0x23a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8006ffc: 687b ldr r3, [r7, #4]
|
|
8006ffe: 681b ldr r3, [r3, #0]
|
|
8007000: 69db ldr r3, [r3, #28]
|
|
8007002: f003 0310 and.w r3, r3, #16
|
|
8007006: 2b10 cmp r3, #16
|
|
8007008: d103 bne.n 8007012 <UART_RxISR_16BIT_FIFOEN+0x286>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800700a: 687b ldr r3, [r7, #4]
|
|
800700c: 681b ldr r3, [r3, #0]
|
|
800700e: 2210 movs r2, #16
|
|
8007010: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8007012: 687b ldr r3, [r7, #4]
|
|
8007014: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8007018: 4619 mov r1, r3
|
|
800701a: 6878 ldr r0, [r7, #4]
|
|
800701c: f7fe fc86 bl 800592c <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
8007020: e00e b.n 8007040 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8007022: 6878 ldr r0, [r7, #4]
|
|
8007024: f7fa fa94 bl 8001550 <HAL_UART_RxCpltCallback>
|
|
break;
|
|
8007028: e00a b.n 8007040 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
800702a: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
|
|
800702e: 2b00 cmp r3, #0
|
|
8007030: d006 beq.n 8007040 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
8007032: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007036: f003 0320 and.w r3, r3, #32
|
|
800703a: 2b00 cmp r3, #0
|
|
800703c: f47f aeca bne.w 8006dd4 <UART_RxISR_16BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
8007040: 687b ldr r3, [r7, #4]
|
|
8007042: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007046: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
800704a: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
|
|
800704e: 2b00 cmp r3, #0
|
|
8007050: d049 beq.n 80070e6 <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
8007052: 687b ldr r3, [r7, #4]
|
|
8007054: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8007058: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
|
|
800705c: 429a cmp r2, r3
|
|
800705e: d242 bcs.n 80070e6 <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
8007060: 687b ldr r3, [r7, #4]
|
|
8007062: 681b ldr r3, [r3, #0]
|
|
8007064: 3308 adds r3, #8
|
|
8007066: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007068: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800706a: e853 3f00 ldrex r3, [r3]
|
|
800706e: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8007070: 6a3b ldr r3, [r7, #32]
|
|
8007072: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8007076: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800707a: 687b ldr r3, [r7, #4]
|
|
800707c: 681b ldr r3, [r3, #0]
|
|
800707e: 3308 adds r3, #8
|
|
8007080: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
|
|
8007084: 633a str r2, [r7, #48] @ 0x30
|
|
8007086: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007088: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800708a: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800708c: e841 2300 strex r3, r2, [r1]
|
|
8007090: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8007092: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8007094: 2b00 cmp r3, #0
|
|
8007096: d1e3 bne.n 8007060 <UART_RxISR_16BIT_FIFOEN+0x2d4>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
8007098: 687b ldr r3, [r7, #4]
|
|
800709a: 4a16 ldr r2, [pc, #88] @ (80070f4 <UART_RxISR_16BIT_FIFOEN+0x368>)
|
|
800709c: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
800709e: 687b ldr r3, [r7, #4]
|
|
80070a0: 681b ldr r3, [r3, #0]
|
|
80070a2: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80070a4: 693b ldr r3, [r7, #16]
|
|
80070a6: e853 3f00 ldrex r3, [r3]
|
|
80070aa: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80070ac: 68fb ldr r3, [r7, #12]
|
|
80070ae: f043 0320 orr.w r3, r3, #32
|
|
80070b2: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
80070b6: 687b ldr r3, [r7, #4]
|
|
80070b8: 681b ldr r3, [r3, #0]
|
|
80070ba: 461a mov r2, r3
|
|
80070bc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
80070c0: 61fb str r3, [r7, #28]
|
|
80070c2: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80070c4: 69b9 ldr r1, [r7, #24]
|
|
80070c6: 69fa ldr r2, [r7, #28]
|
|
80070c8: e841 2300 strex r3, r2, [r1]
|
|
80070cc: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80070ce: 697b ldr r3, [r7, #20]
|
|
80070d0: 2b00 cmp r3, #0
|
|
80070d2: d1e4 bne.n 800709e <UART_RxISR_16BIT_FIFOEN+0x312>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
80070d4: e007 b.n 80070e6 <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
80070d6: 687b ldr r3, [r7, #4]
|
|
80070d8: 681b ldr r3, [r3, #0]
|
|
80070da: 699a ldr r2, [r3, #24]
|
|
80070dc: 687b ldr r3, [r7, #4]
|
|
80070de: 681b ldr r3, [r3, #0]
|
|
80070e0: f042 0208 orr.w r2, r2, #8
|
|
80070e4: 619a str r2, [r3, #24]
|
|
}
|
|
80070e6: bf00 nop
|
|
80070e8: 37b8 adds r7, #184 @ 0xb8
|
|
80070ea: 46bd mov sp, r7
|
|
80070ec: bd80 pop {r7, pc}
|
|
80070ee: bf00 nop
|
|
80070f0: 40008000 .word 0x40008000
|
|
80070f4: 08006871 .word 0x08006871
|
|
|
|
080070f8 <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
80070f8: b480 push {r7}
|
|
80070fa: b083 sub sp, #12
|
|
80070fc: af00 add r7, sp, #0
|
|
80070fe: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007100: bf00 nop
|
|
8007102: 370c adds r7, #12
|
|
8007104: 46bd mov sp, r7
|
|
8007106: bc80 pop {r7}
|
|
8007108: 4770 bx lr
|
|
|
|
0800710a <HAL_UARTEx_RxFifoFullCallback>:
|
|
* @brief UART RX Fifo full callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800710a: b480 push {r7}
|
|
800710c: b083 sub sp, #12
|
|
800710e: af00 add r7, sp, #0
|
|
8007110: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007112: bf00 nop
|
|
8007114: 370c adds r7, #12
|
|
8007116: 46bd mov sp, r7
|
|
8007118: bc80 pop {r7}
|
|
800711a: 4770 bx lr
|
|
|
|
0800711c <HAL_UARTEx_TxFifoEmptyCallback>:
|
|
* @brief UART TX Fifo empty callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800711c: b480 push {r7}
|
|
800711e: b083 sub sp, #12
|
|
8007120: af00 add r7, sp, #0
|
|
8007122: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007124: bf00 nop
|
|
8007126: 370c adds r7, #12
|
|
8007128: 46bd mov sp, r7
|
|
800712a: bc80 pop {r7}
|
|
800712c: 4770 bx lr
|
|
|
|
0800712e <HAL_UARTEx_StopModeWakeUpSourceConfig>:
|
|
* @arg @ref UART_WAKEUP_ON_STARTBIT
|
|
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
|
{
|
|
800712e: b580 push {r7, lr}
|
|
8007130: b088 sub sp, #32
|
|
8007132: af02 add r7, sp, #8
|
|
8007134: 60f8 str r0, [r7, #12]
|
|
8007136: 1d3b adds r3, r7, #4
|
|
8007138: e883 0006 stmia.w r3, {r1, r2}
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800713c: 2300 movs r3, #0
|
|
800713e: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
|
/* check the wake-up selection parameter */
|
|
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007140: 68fb ldr r3, [r7, #12]
|
|
8007142: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8007146: 2b01 cmp r3, #1
|
|
8007148: d101 bne.n 800714e <HAL_UARTEx_StopModeWakeUpSourceConfig+0x20>
|
|
800714a: 2302 movs r3, #2
|
|
800714c: e046 b.n 80071dc <HAL_UARTEx_StopModeWakeUpSourceConfig+0xae>
|
|
800714e: 68fb ldr r3, [r7, #12]
|
|
8007150: 2201 movs r2, #1
|
|
8007152: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8007156: 68fb ldr r3, [r7, #12]
|
|
8007158: 2224 movs r2, #36 @ 0x24
|
|
800715a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
800715e: 68fb ldr r3, [r7, #12]
|
|
8007160: 681b ldr r3, [r3, #0]
|
|
8007162: 681a ldr r2, [r3, #0]
|
|
8007164: 68fb ldr r3, [r7, #12]
|
|
8007166: 681b ldr r3, [r3, #0]
|
|
8007168: f022 0201 bic.w r2, r2, #1
|
|
800716c: 601a str r2, [r3, #0]
|
|
|
|
/* Set the wake-up selection scheme */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
|
800716e: 68fb ldr r3, [r7, #12]
|
|
8007170: 681b ldr r3, [r3, #0]
|
|
8007172: 689b ldr r3, [r3, #8]
|
|
8007174: f423 1140 bic.w r1, r3, #3145728 @ 0x300000
|
|
8007178: 687a ldr r2, [r7, #4]
|
|
800717a: 68fb ldr r3, [r7, #12]
|
|
800717c: 681b ldr r3, [r3, #0]
|
|
800717e: 430a orrs r2, r1
|
|
8007180: 609a str r2, [r3, #8]
|
|
|
|
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
|
8007182: 687b ldr r3, [r7, #4]
|
|
8007184: 2b00 cmp r3, #0
|
|
8007186: d105 bne.n 8007194 <HAL_UARTEx_StopModeWakeUpSourceConfig+0x66>
|
|
{
|
|
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
|
|
8007188: 1d3b adds r3, r7, #4
|
|
800718a: e893 0006 ldmia.w r3, {r1, r2}
|
|
800718e: 68f8 ldr r0, [r7, #12]
|
|
8007190: f000 f911 bl 80073b6 <UARTEx_Wakeup_AddressConfig>
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8007194: 68fb ldr r3, [r7, #12]
|
|
8007196: 681b ldr r3, [r3, #0]
|
|
8007198: 681a ldr r2, [r3, #0]
|
|
800719a: 68fb ldr r3, [r7, #12]
|
|
800719c: 681b ldr r3, [r3, #0]
|
|
800719e: f042 0201 orr.w r2, r2, #1
|
|
80071a2: 601a str r2, [r3, #0]
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
80071a4: f7f9 fcec bl 8000b80 <HAL_GetTick>
|
|
80071a8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
80071aa: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
80071ae: 9300 str r3, [sp, #0]
|
|
80071b0: 693b ldr r3, [r7, #16]
|
|
80071b2: 2200 movs r2, #0
|
|
80071b4: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
80071b8: 68f8 ldr r0, [r7, #12]
|
|
80071ba: f7fe ff82 bl 80060c2 <UART_WaitOnFlagUntilTimeout>
|
|
80071be: 4603 mov r3, r0
|
|
80071c0: 2b00 cmp r3, #0
|
|
80071c2: d002 beq.n 80071ca <HAL_UARTEx_StopModeWakeUpSourceConfig+0x9c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
80071c4: 2303 movs r3, #3
|
|
80071c6: 75fb strb r3, [r7, #23]
|
|
80071c8: e003 b.n 80071d2 <HAL_UARTEx_StopModeWakeUpSourceConfig+0xa4>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80071ca: 68fb ldr r3, [r7, #12]
|
|
80071cc: 2220 movs r2, #32
|
|
80071ce: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80071d2: 68fb ldr r3, [r7, #12]
|
|
80071d4: 2200 movs r2, #0
|
|
80071d6: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return status;
|
|
80071da: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80071dc: 4618 mov r0, r3
|
|
80071de: 3718 adds r7, #24
|
|
80071e0: 46bd mov sp, r7
|
|
80071e2: bd80 pop {r7, pc}
|
|
|
|
080071e4 <HAL_UARTEx_EnableStopMode>:
|
|
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
|
{
|
|
80071e4: b480 push {r7}
|
|
80071e6: b089 sub sp, #36 @ 0x24
|
|
80071e8: af00 add r7, sp, #0
|
|
80071ea: 6078 str r0, [r7, #4]
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
80071ec: 687b ldr r3, [r7, #4]
|
|
80071ee: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
80071f2: 2b01 cmp r3, #1
|
|
80071f4: d101 bne.n 80071fa <HAL_UARTEx_EnableStopMode+0x16>
|
|
80071f6: 2302 movs r3, #2
|
|
80071f8: e021 b.n 800723e <HAL_UARTEx_EnableStopMode+0x5a>
|
|
80071fa: 687b ldr r3, [r7, #4]
|
|
80071fc: 2201 movs r2, #1
|
|
80071fe: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Set UESM bit */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
|
8007202: 687b ldr r3, [r7, #4]
|
|
8007204: 681b ldr r3, [r3, #0]
|
|
8007206: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007208: 68fb ldr r3, [r7, #12]
|
|
800720a: e853 3f00 ldrex r3, [r3]
|
|
800720e: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007210: 68bb ldr r3, [r7, #8]
|
|
8007212: f043 0302 orr.w r3, r3, #2
|
|
8007216: 61fb str r3, [r7, #28]
|
|
8007218: 687b ldr r3, [r7, #4]
|
|
800721a: 681b ldr r3, [r3, #0]
|
|
800721c: 461a mov r2, r3
|
|
800721e: 69fb ldr r3, [r7, #28]
|
|
8007220: 61bb str r3, [r7, #24]
|
|
8007222: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007224: 6979 ldr r1, [r7, #20]
|
|
8007226: 69ba ldr r2, [r7, #24]
|
|
8007228: e841 2300 strex r3, r2, [r1]
|
|
800722c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800722e: 693b ldr r3, [r7, #16]
|
|
8007230: 2b00 cmp r3, #0
|
|
8007232: d1e6 bne.n 8007202 <HAL_UARTEx_EnableStopMode+0x1e>
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8007234: 687b ldr r3, [r7, #4]
|
|
8007236: 2200 movs r2, #0
|
|
8007238: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
800723c: 2300 movs r3, #0
|
|
}
|
|
800723e: 4618 mov r0, r3
|
|
8007240: 3724 adds r7, #36 @ 0x24
|
|
8007242: 46bd mov sp, r7
|
|
8007244: bc80 pop {r7}
|
|
8007246: 4770 bx lr
|
|
|
|
08007248 <HAL_UARTEx_EnableFifoMode>:
|
|
* @brief Enable the FIFO mode.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
|
|
{
|
|
8007248: b580 push {r7, lr}
|
|
800724a: b084 sub sp, #16
|
|
800724c: af00 add r7, sp, #0
|
|
800724e: 6078 str r0, [r7, #4]
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007250: 687b ldr r3, [r7, #4]
|
|
8007252: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8007256: 2b01 cmp r3, #1
|
|
8007258: d101 bne.n 800725e <HAL_UARTEx_EnableFifoMode+0x16>
|
|
800725a: 2302 movs r3, #2
|
|
800725c: e02b b.n 80072b6 <HAL_UARTEx_EnableFifoMode+0x6e>
|
|
800725e: 687b ldr r3, [r7, #4]
|
|
8007260: 2201 movs r2, #1
|
|
8007262: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8007266: 687b ldr r3, [r7, #4]
|
|
8007268: 2224 movs r2, #36 @ 0x24
|
|
800726a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
800726e: 687b ldr r3, [r7, #4]
|
|
8007270: 681b ldr r3, [r3, #0]
|
|
8007272: 681b ldr r3, [r3, #0]
|
|
8007274: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8007276: 687b ldr r3, [r7, #4]
|
|
8007278: 681b ldr r3, [r3, #0]
|
|
800727a: 681a ldr r2, [r3, #0]
|
|
800727c: 687b ldr r3, [r7, #4]
|
|
800727e: 681b ldr r3, [r3, #0]
|
|
8007280: f022 0201 bic.w r2, r2, #1
|
|
8007284: 601a str r2, [r3, #0]
|
|
|
|
/* Enable FIFO mode */
|
|
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
|
|
8007286: 68fb ldr r3, [r7, #12]
|
|
8007288: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
800728c: 60fb str r3, [r7, #12]
|
|
huart->FifoMode = UART_FIFOMODE_ENABLE;
|
|
800728e: 687b ldr r3, [r7, #4]
|
|
8007290: f04f 5200 mov.w r2, #536870912 @ 0x20000000
|
|
8007294: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007296: 687b ldr r3, [r7, #4]
|
|
8007298: 681b ldr r3, [r3, #0]
|
|
800729a: 68fa ldr r2, [r7, #12]
|
|
800729c: 601a str r2, [r3, #0]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
800729e: 6878 ldr r0, [r7, #4]
|
|
80072a0: f000 f8ac bl 80073fc <UARTEx_SetNbDataToProcess>
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80072a4: 687b ldr r3, [r7, #4]
|
|
80072a6: 2220 movs r2, #32
|
|
80072a8: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80072ac: 687b ldr r3, [r7, #4]
|
|
80072ae: 2200 movs r2, #0
|
|
80072b0: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
80072b4: 2300 movs r3, #0
|
|
}
|
|
80072b6: 4618 mov r0, r3
|
|
80072b8: 3710 adds r7, #16
|
|
80072ba: 46bd mov sp, r7
|
|
80072bc: bd80 pop {r7, pc}
|
|
|
|
080072be <HAL_UARTEx_SetTxFifoThreshold>:
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
80072be: b580 push {r7, lr}
|
|
80072c0: b084 sub sp, #16
|
|
80072c2: af00 add r7, sp, #0
|
|
80072c4: 6078 str r0, [r7, #4]
|
|
80072c6: 6039 str r1, [r7, #0]
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
80072c8: 687b ldr r3, [r7, #4]
|
|
80072ca: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
80072ce: 2b01 cmp r3, #1
|
|
80072d0: d101 bne.n 80072d6 <HAL_UARTEx_SetTxFifoThreshold+0x18>
|
|
80072d2: 2302 movs r3, #2
|
|
80072d4: e02d b.n 8007332 <HAL_UARTEx_SetTxFifoThreshold+0x74>
|
|
80072d6: 687b ldr r3, [r7, #4]
|
|
80072d8: 2201 movs r2, #1
|
|
80072da: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80072de: 687b ldr r3, [r7, #4]
|
|
80072e0: 2224 movs r2, #36 @ 0x24
|
|
80072e2: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
80072e6: 687b ldr r3, [r7, #4]
|
|
80072e8: 681b ldr r3, [r3, #0]
|
|
80072ea: 681b ldr r3, [r3, #0]
|
|
80072ec: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
80072ee: 687b ldr r3, [r7, #4]
|
|
80072f0: 681b ldr r3, [r3, #0]
|
|
80072f2: 681a ldr r2, [r3, #0]
|
|
80072f4: 687b ldr r3, [r7, #4]
|
|
80072f6: 681b ldr r3, [r3, #0]
|
|
80072f8: f022 0201 bic.w r2, r2, #1
|
|
80072fc: 601a str r2, [r3, #0]
|
|
|
|
/* Update TX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
|
80072fe: 687b ldr r3, [r7, #4]
|
|
8007300: 681b ldr r3, [r3, #0]
|
|
8007302: 689b ldr r3, [r3, #8]
|
|
8007304: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
|
|
8007308: 687b ldr r3, [r7, #4]
|
|
800730a: 681b ldr r3, [r3, #0]
|
|
800730c: 683a ldr r2, [r7, #0]
|
|
800730e: 430a orrs r2, r1
|
|
8007310: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
8007312: 6878 ldr r0, [r7, #4]
|
|
8007314: f000 f872 bl 80073fc <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007318: 687b ldr r3, [r7, #4]
|
|
800731a: 681b ldr r3, [r3, #0]
|
|
800731c: 68fa ldr r2, [r7, #12]
|
|
800731e: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8007320: 687b ldr r3, [r7, #4]
|
|
8007322: 2220 movs r2, #32
|
|
8007324: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8007328: 687b ldr r3, [r7, #4]
|
|
800732a: 2200 movs r2, #0
|
|
800732c: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8007330: 2300 movs r3, #0
|
|
}
|
|
8007332: 4618 mov r0, r3
|
|
8007334: 3710 adds r7, #16
|
|
8007336: 46bd mov sp, r7
|
|
8007338: bd80 pop {r7, pc}
|
|
|
|
0800733a <HAL_UARTEx_SetRxFifoThreshold>:
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
800733a: b580 push {r7, lr}
|
|
800733c: b084 sub sp, #16
|
|
800733e: af00 add r7, sp, #0
|
|
8007340: 6078 str r0, [r7, #4]
|
|
8007342: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007344: 687b ldr r3, [r7, #4]
|
|
8007346: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
800734a: 2b01 cmp r3, #1
|
|
800734c: d101 bne.n 8007352 <HAL_UARTEx_SetRxFifoThreshold+0x18>
|
|
800734e: 2302 movs r3, #2
|
|
8007350: e02d b.n 80073ae <HAL_UARTEx_SetRxFifoThreshold+0x74>
|
|
8007352: 687b ldr r3, [r7, #4]
|
|
8007354: 2201 movs r2, #1
|
|
8007356: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800735a: 687b ldr r3, [r7, #4]
|
|
800735c: 2224 movs r2, #36 @ 0x24
|
|
800735e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8007362: 687b ldr r3, [r7, #4]
|
|
8007364: 681b ldr r3, [r3, #0]
|
|
8007366: 681b ldr r3, [r3, #0]
|
|
8007368: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
800736a: 687b ldr r3, [r7, #4]
|
|
800736c: 681b ldr r3, [r3, #0]
|
|
800736e: 681a ldr r2, [r3, #0]
|
|
8007370: 687b ldr r3, [r7, #4]
|
|
8007372: 681b ldr r3, [r3, #0]
|
|
8007374: f022 0201 bic.w r2, r2, #1
|
|
8007378: 601a str r2, [r3, #0]
|
|
|
|
/* Update RX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
|
800737a: 687b ldr r3, [r7, #4]
|
|
800737c: 681b ldr r3, [r3, #0]
|
|
800737e: 689b ldr r3, [r3, #8]
|
|
8007380: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
|
|
8007384: 687b ldr r3, [r7, #4]
|
|
8007386: 681b ldr r3, [r3, #0]
|
|
8007388: 683a ldr r2, [r7, #0]
|
|
800738a: 430a orrs r2, r1
|
|
800738c: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
800738e: 6878 ldr r0, [r7, #4]
|
|
8007390: f000 f834 bl 80073fc <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007394: 687b ldr r3, [r7, #4]
|
|
8007396: 681b ldr r3, [r3, #0]
|
|
8007398: 68fa ldr r2, [r7, #12]
|
|
800739a: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800739c: 687b ldr r3, [r7, #4]
|
|
800739e: 2220 movs r2, #32
|
|
80073a0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80073a4: 687b ldr r3, [r7, #4]
|
|
80073a6: 2200 movs r2, #0
|
|
80073a8: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
80073ac: 2300 movs r3, #0
|
|
}
|
|
80073ae: 4618 mov r0, r3
|
|
80073b0: 3710 adds r7, #16
|
|
80073b2: 46bd mov sp, r7
|
|
80073b4: bd80 pop {r7, pc}
|
|
|
|
080073b6 <UARTEx_Wakeup_AddressConfig>:
|
|
* @param huart UART handle.
|
|
* @param WakeUpSelection UART wake up from stop mode parameters.
|
|
* @retval None
|
|
*/
|
|
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
|
{
|
|
80073b6: b480 push {r7}
|
|
80073b8: b085 sub sp, #20
|
|
80073ba: af00 add r7, sp, #0
|
|
80073bc: 60f8 str r0, [r7, #12]
|
|
80073be: 1d3b adds r3, r7, #4
|
|
80073c0: e883 0006 stmia.w r3, {r1, r2}
|
|
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
|
|
|
|
/* Set the USART address length */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
|
|
80073c4: 68fb ldr r3, [r7, #12]
|
|
80073c6: 681b ldr r3, [r3, #0]
|
|
80073c8: 685b ldr r3, [r3, #4]
|
|
80073ca: f023 0210 bic.w r2, r3, #16
|
|
80073ce: 893b ldrh r3, [r7, #8]
|
|
80073d0: 4619 mov r1, r3
|
|
80073d2: 68fb ldr r3, [r7, #12]
|
|
80073d4: 681b ldr r3, [r3, #0]
|
|
80073d6: 430a orrs r2, r1
|
|
80073d8: 605a str r2, [r3, #4]
|
|
|
|
/* Set the USART address node */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
|
|
80073da: 68fb ldr r3, [r7, #12]
|
|
80073dc: 681b ldr r3, [r3, #0]
|
|
80073de: 685b ldr r3, [r3, #4]
|
|
80073e0: f023 417f bic.w r1, r3, #4278190080 @ 0xff000000
|
|
80073e4: 7abb ldrb r3, [r7, #10]
|
|
80073e6: 061a lsls r2, r3, #24
|
|
80073e8: 68fb ldr r3, [r7, #12]
|
|
80073ea: 681b ldr r3, [r3, #0]
|
|
80073ec: 430a orrs r2, r1
|
|
80073ee: 605a str r2, [r3, #4]
|
|
}
|
|
80073f0: bf00 nop
|
|
80073f2: 3714 adds r7, #20
|
|
80073f4: 46bd mov sp, r7
|
|
80073f6: bc80 pop {r7}
|
|
80073f8: 4770 bx lr
|
|
...
|
|
|
|
080073fc <UARTEx_SetNbDataToProcess>:
|
|
* the UART configuration registers.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
|
{
|
|
80073fc: b480 push {r7}
|
|
80073fe: b085 sub sp, #20
|
|
8007400: af00 add r7, sp, #0
|
|
8007402: 6078 str r0, [r7, #4]
|
|
uint8_t rx_fifo_threshold;
|
|
uint8_t tx_fifo_threshold;
|
|
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
|
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
|
|
|
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
|
8007404: 687b ldr r3, [r7, #4]
|
|
8007406: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8007408: 2b00 cmp r3, #0
|
|
800740a: d108 bne.n 800741e <UARTEx_SetNbDataToProcess+0x22>
|
|
{
|
|
huart->NbTxDataToProcess = 1U;
|
|
800740c: 687b ldr r3, [r7, #4]
|
|
800740e: 2201 movs r2, #1
|
|
8007410: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1U;
|
|
8007414: 687b ldr r3, [r7, #4]
|
|
8007416: 2201 movs r2, #1
|
|
8007418: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
}
|
|
}
|
|
800741c: e031 b.n 8007482 <UARTEx_SetNbDataToProcess+0x86>
|
|
rx_fifo_depth = RX_FIFO_DEPTH;
|
|
800741e: 2308 movs r3, #8
|
|
8007420: 73fb strb r3, [r7, #15]
|
|
tx_fifo_depth = TX_FIFO_DEPTH;
|
|
8007422: 2308 movs r3, #8
|
|
8007424: 73bb strb r3, [r7, #14]
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8007426: 687b ldr r3, [r7, #4]
|
|
8007428: 681b ldr r3, [r3, #0]
|
|
800742a: 689b ldr r3, [r3, #8]
|
|
800742c: 0e5b lsrs r3, r3, #25
|
|
800742e: b2db uxtb r3, r3
|
|
8007430: f003 0307 and.w r3, r3, #7
|
|
8007434: 737b strb r3, [r7, #13]
|
|
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
|
8007436: 687b ldr r3, [r7, #4]
|
|
8007438: 681b ldr r3, [r3, #0]
|
|
800743a: 689b ldr r3, [r3, #8]
|
|
800743c: 0f5b lsrs r3, r3, #29
|
|
800743e: b2db uxtb r3, r3
|
|
8007440: f003 0307 and.w r3, r3, #7
|
|
8007444: 733b strb r3, [r7, #12]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8007446: 7bbb ldrb r3, [r7, #14]
|
|
8007448: 7b3a ldrb r2, [r7, #12]
|
|
800744a: 4910 ldr r1, [pc, #64] @ (800748c <UARTEx_SetNbDataToProcess+0x90>)
|
|
800744c: 5c8a ldrb r2, [r1, r2]
|
|
800744e: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
8007452: 7b3a ldrb r2, [r7, #12]
|
|
8007454: 490e ldr r1, [pc, #56] @ (8007490 <UARTEx_SetNbDataToProcess+0x94>)
|
|
8007456: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8007458: fb93 f3f2 sdiv r3, r3, r2
|
|
800745c: b29a uxth r2, r3
|
|
800745e: 687b ldr r3, [r7, #4]
|
|
8007460: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8007464: 7bfb ldrb r3, [r7, #15]
|
|
8007466: 7b7a ldrb r2, [r7, #13]
|
|
8007468: 4908 ldr r1, [pc, #32] @ (800748c <UARTEx_SetNbDataToProcess+0x90>)
|
|
800746a: 5c8a ldrb r2, [r1, r2]
|
|
800746c: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
8007470: 7b7a ldrb r2, [r7, #13]
|
|
8007472: 4907 ldr r1, [pc, #28] @ (8007490 <UARTEx_SetNbDataToProcess+0x94>)
|
|
8007474: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8007476: fb93 f3f2 sdiv r3, r3, r2
|
|
800747a: b29a uxth r2, r3
|
|
800747c: 687b ldr r3, [r7, #4]
|
|
800747e: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
}
|
|
8007482: bf00 nop
|
|
8007484: 3714 adds r7, #20
|
|
8007486: 46bd mov sp, r7
|
|
8007488: bc80 pop {r7}
|
|
800748a: 4770 bx lr
|
|
800748c: 0800d9d0 .word 0x0800d9d0
|
|
8007490: 0800d9d8 .word 0x0800d9d8
|
|
|
|
08007494 <LL_GPIO_SetOutputPin>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
8007494: b480 push {r7}
|
|
8007496: b083 sub sp, #12
|
|
8007498: af00 add r7, sp, #0
|
|
800749a: 6078 str r0, [r7, #4]
|
|
800749c: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BSRR, PinMask);
|
|
800749e: 687b ldr r3, [r7, #4]
|
|
80074a0: 683a ldr r2, [r7, #0]
|
|
80074a2: 619a str r2, [r3, #24]
|
|
}
|
|
80074a4: bf00 nop
|
|
80074a6: 370c adds r7, #12
|
|
80074a8: 46bd mov sp, r7
|
|
80074aa: bc80 pop {r7}
|
|
80074ac: 4770 bx lr
|
|
|
|
080074ae <LL_GPIO_ResetOutputPin>:
|
|
* @arg @ref LL_GPIO_PIN_15
|
|
* @arg @ref LL_GPIO_PIN_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
|
{
|
|
80074ae: b480 push {r7}
|
|
80074b0: b083 sub sp, #12
|
|
80074b2: af00 add r7, sp, #0
|
|
80074b4: 6078 str r0, [r7, #4]
|
|
80074b6: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BRR, PinMask);
|
|
80074b8: 687b ldr r3, [r7, #4]
|
|
80074ba: 683a ldr r2, [r7, #0]
|
|
80074bc: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
80074be: bf00 nop
|
|
80074c0: 370c adds r7, #12
|
|
80074c2: 46bd mov sp, r7
|
|
80074c4: bc80 pop {r7}
|
|
80074c6: 4770 bx lr
|
|
|
|
080074c8 <RadioInit>:
|
|
TimerEvent_t RxTimeoutTimer;
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
|
|
static void RadioInit( RadioEvents_t *events )
|
|
{
|
|
80074c8: b580 push {r7, lr}
|
|
80074ca: b084 sub sp, #16
|
|
80074cc: af02 add r7, sp, #8
|
|
80074ce: 6078 str r0, [r7, #4]
|
|
RadioEvents = events;
|
|
80074d0: 4a24 ldr r2, [pc, #144] @ (8007564 <RadioInit+0x9c>)
|
|
80074d2: 687b ldr r3, [r7, #4]
|
|
80074d4: 6013 str r3, [r2, #0]
|
|
|
|
SubgRf.RxContinuous = false;
|
|
80074d6: 4b24 ldr r3, [pc, #144] @ (8007568 <RadioInit+0xa0>)
|
|
80074d8: 2200 movs r2, #0
|
|
80074da: 705a strb r2, [r3, #1]
|
|
SubgRf.TxTimeout = 0;
|
|
80074dc: 4b22 ldr r3, [pc, #136] @ (8007568 <RadioInit+0xa0>)
|
|
80074de: 2200 movs r2, #0
|
|
80074e0: 605a str r2, [r3, #4]
|
|
SubgRf.RxTimeout = 0;
|
|
80074e2: 4b21 ldr r3, [pc, #132] @ (8007568 <RadioInit+0xa0>)
|
|
80074e4: 2200 movs r2, #0
|
|
80074e6: 609a str r2, [r3, #8]
|
|
/*See STM32WL Errata: RadioSetRxDutyCycle*/
|
|
SubgRf.RxDcPreambleDetectTimeout = 0;
|
|
80074e8: 4b1f ldr r3, [pc, #124] @ (8007568 <RadioInit+0xa0>)
|
|
80074ea: 2200 movs r2, #0
|
|
80074ec: 659a str r2, [r3, #88] @ 0x58
|
|
#if( RADIO_LR_FHSS_IS_ON == 1 )
|
|
SubgRf.lr_fhss.is_lr_fhss_on = false;
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
SUBGRF_Init( RadioOnDioIrq );
|
|
80074ee: 481f ldr r0, [pc, #124] @ (800756c <RadioInit+0xa4>)
|
|
80074f0: f001 fffa bl 80094e8 <SUBGRF_Init>
|
|
/*SubgRf.publicNetwork set to false*/
|
|
SubgRf.PublicNetwork.Current = false;
|
|
80074f4: 4b1c ldr r3, [pc, #112] @ (8007568 <RadioInit+0xa0>)
|
|
80074f6: 2200 movs r2, #0
|
|
80074f8: 735a strb r2, [r3, #13]
|
|
SubgRf.PublicNetwork.Previous = false;
|
|
80074fa: 4b1b ldr r3, [pc, #108] @ (8007568 <RadioInit+0xa0>)
|
|
80074fc: 2200 movs r2, #0
|
|
80074fe: 731a strb r2, [r3, #12]
|
|
|
|
RADIO_IRQ_PROCESS_INIT();
|
|
|
|
SUBGRF_SetRegulatorMode( );
|
|
8007500: f002 fa90 bl 8009a24 <SUBGRF_SetRegulatorMode>
|
|
|
|
SUBGRF_SetBufferBaseAddress( 0x00, 0x00 );
|
|
8007504: 2100 movs r1, #0
|
|
8007506: 2000 movs r0, #0
|
|
8007508: f002 fe5c bl 800a1c4 <SUBGRF_SetBufferBaseAddress>
|
|
SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US );
|
|
800750c: 2204 movs r2, #4
|
|
800750e: 2100 movs r1, #0
|
|
8007510: 2001 movs r0, #1
|
|
8007512: f002 fc1f bl 8009d54 <SUBGRF_SetTxParams>
|
|
SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE );
|
|
8007516: 2300 movs r3, #0
|
|
8007518: 2200 movs r2, #0
|
|
800751a: f64f 71ff movw r1, #65535 @ 0xffff
|
|
800751e: f64f 70ff movw r0, #65535 @ 0xffff
|
|
8007522: f002 fb4f bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
|
|
RadioSleep();
|
|
8007526: f000 fe9f bl 8008268 <RadioSleep>
|
|
// Initialize driver timeout timers
|
|
TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq );
|
|
800752a: 2300 movs r3, #0
|
|
800752c: 9300 str r3, [sp, #0]
|
|
800752e: 4b10 ldr r3, [pc, #64] @ (8007570 <RadioInit+0xa8>)
|
|
8007530: 2200 movs r2, #0
|
|
8007532: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8007536: 480f ldr r0, [pc, #60] @ (8007574 <RadioInit+0xac>)
|
|
8007538: f005 fa88 bl 800ca4c <UTIL_TIMER_Create>
|
|
TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq );
|
|
800753c: 2300 movs r3, #0
|
|
800753e: 9300 str r3, [sp, #0]
|
|
8007540: 4b0d ldr r3, [pc, #52] @ (8007578 <RadioInit+0xb0>)
|
|
8007542: 2200 movs r2, #0
|
|
8007544: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8007548: 480c ldr r0, [pc, #48] @ (800757c <RadioInit+0xb4>)
|
|
800754a: f005 fa7f bl 800ca4c <UTIL_TIMER_Create>
|
|
TimerStop( &TxTimeoutTimer );
|
|
800754e: 4809 ldr r0, [pc, #36] @ (8007574 <RadioInit+0xac>)
|
|
8007550: f005 fb20 bl 800cb94 <UTIL_TIMER_Stop>
|
|
TimerStop( &RxTimeoutTimer );
|
|
8007554: 4809 ldr r0, [pc, #36] @ (800757c <RadioInit+0xb4>)
|
|
8007556: f005 fb1d bl 800cb94 <UTIL_TIMER_Stop>
|
|
}
|
|
800755a: bf00 nop
|
|
800755c: 3708 adds r7, #8
|
|
800755e: 46bd mov sp, r7
|
|
8007560: bd80 pop {r7, pc}
|
|
8007562: bf00 nop
|
|
8007564: 2000028c .word 0x2000028c
|
|
8007568: 20000290 .word 0x20000290
|
|
800756c: 0800868d .word 0x0800868d
|
|
8007570: 080085fd .word 0x080085fd
|
|
8007574: 200002ec .word 0x200002ec
|
|
8007578: 08008611 .word 0x08008611
|
|
800757c: 20000304 .word 0x20000304
|
|
|
|
08007580 <RadioGetStatus>:
|
|
|
|
static RadioState_t RadioGetStatus( void )
|
|
{
|
|
8007580: b580 push {r7, lr}
|
|
8007582: af00 add r7, sp, #0
|
|
switch( SUBGRF_GetOperatingMode( ) )
|
|
8007584: f001 fff8 bl 8009578 <SUBGRF_GetOperatingMode>
|
|
8007588: 4603 mov r3, r0
|
|
800758a: 2b07 cmp r3, #7
|
|
800758c: d00a beq.n 80075a4 <RadioGetStatus+0x24>
|
|
800758e: 2b07 cmp r3, #7
|
|
8007590: dc0a bgt.n 80075a8 <RadioGetStatus+0x28>
|
|
8007592: 2b04 cmp r3, #4
|
|
8007594: d002 beq.n 800759c <RadioGetStatus+0x1c>
|
|
8007596: 2b05 cmp r3, #5
|
|
8007598: d002 beq.n 80075a0 <RadioGetStatus+0x20>
|
|
800759a: e005 b.n 80075a8 <RadioGetStatus+0x28>
|
|
{
|
|
case MODE_TX:
|
|
return RF_TX_RUNNING;
|
|
800759c: 2302 movs r3, #2
|
|
800759e: e004 b.n 80075aa <RadioGetStatus+0x2a>
|
|
case MODE_RX:
|
|
return RF_RX_RUNNING;
|
|
80075a0: 2301 movs r3, #1
|
|
80075a2: e002 b.n 80075aa <RadioGetStatus+0x2a>
|
|
case MODE_CAD:
|
|
return RF_CAD;
|
|
80075a4: 2303 movs r3, #3
|
|
80075a6: e000 b.n 80075aa <RadioGetStatus+0x2a>
|
|
default:
|
|
return RF_IDLE;
|
|
80075a8: 2300 movs r3, #0
|
|
}
|
|
}
|
|
80075aa: 4618 mov r0, r3
|
|
80075ac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080075b0 <RadioSetModem>:
|
|
|
|
static void RadioSetModem( RadioModems_t modem )
|
|
{
|
|
80075b0: b580 push {r7, lr}
|
|
80075b2: b082 sub sp, #8
|
|
80075b4: af00 add r7, sp, #0
|
|
80075b6: 4603 mov r3, r0
|
|
80075b8: 71fb strb r3, [r7, #7]
|
|
SubgRf.Modem = modem;
|
|
80075ba: 4a2a ldr r2, [pc, #168] @ (8007664 <RadioSetModem+0xb4>)
|
|
80075bc: 79fb ldrb r3, [r7, #7]
|
|
80075be: 7013 strb r3, [r2, #0]
|
|
RFW_SetRadioModem( modem );
|
|
80075c0: 79fb ldrb r3, [r7, #7]
|
|
80075c2: 4618 mov r0, r3
|
|
80075c4: f003 fd82 bl 800b0cc <RFW_SetRadioModem>
|
|
switch( modem )
|
|
80075c8: 79fb ldrb r3, [r7, #7]
|
|
80075ca: 2b05 cmp r3, #5
|
|
80075cc: d80e bhi.n 80075ec <RadioSetModem+0x3c>
|
|
80075ce: a201 add r2, pc, #4 @ (adr r2, 80075d4 <RadioSetModem+0x24>)
|
|
80075d0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80075d4: 080075fb .word 0x080075fb
|
|
80075d8: 08007609 .word 0x08007609
|
|
80075dc: 080075ed .word 0x080075ed
|
|
80075e0: 0800762f .word 0x0800762f
|
|
80075e4: 0800763d .word 0x0800763d
|
|
80075e8: 0800764b .word 0x0800764b
|
|
{
|
|
default:
|
|
case MODEM_MSK:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_GMSK );
|
|
80075ec: 2003 movs r0, #3
|
|
80075ee: f002 fb8b bl 8009d08 <SUBGRF_SetPacketType>
|
|
// When switching to GFSK mode the LoRa SyncWord register value is reset
|
|
// Thus, we also reset the RadioPublicNetwork variable
|
|
SubgRf.PublicNetwork.Current = false;
|
|
80075f2: 4b1c ldr r3, [pc, #112] @ (8007664 <RadioSetModem+0xb4>)
|
|
80075f4: 2200 movs r2, #0
|
|
80075f6: 735a strb r2, [r3, #13]
|
|
break;
|
|
80075f8: e02f b.n 800765a <RadioSetModem+0xaa>
|
|
case MODEM_FSK:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_GFSK );
|
|
80075fa: 2000 movs r0, #0
|
|
80075fc: f002 fb84 bl 8009d08 <SUBGRF_SetPacketType>
|
|
// When switching to GFSK mode the LoRa SyncWord register value is reset
|
|
// Thus, we also reset the RadioPublicNetwork variable
|
|
SubgRf.PublicNetwork.Current = false;
|
|
8007600: 4b18 ldr r3, [pc, #96] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007602: 2200 movs r2, #0
|
|
8007604: 735a strb r2, [r3, #13]
|
|
break;
|
|
8007606: e028 b.n 800765a <RadioSetModem+0xaa>
|
|
case MODEM_LORA:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_LORA );
|
|
8007608: 2001 movs r0, #1
|
|
800760a: f002 fb7d bl 8009d08 <SUBGRF_SetPacketType>
|
|
// Public/Private network register is reset when switching modems
|
|
if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous )
|
|
800760e: 4b15 ldr r3, [pc, #84] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007610: 7b5a ldrb r2, [r3, #13]
|
|
8007612: 4b14 ldr r3, [pc, #80] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007614: 7b1b ldrb r3, [r3, #12]
|
|
8007616: 429a cmp r2, r3
|
|
8007618: d01e beq.n 8007658 <RadioSetModem+0xa8>
|
|
{
|
|
SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous;
|
|
800761a: 4b12 ldr r3, [pc, #72] @ (8007664 <RadioSetModem+0xb4>)
|
|
800761c: 7b1a ldrb r2, [r3, #12]
|
|
800761e: 4b11 ldr r3, [pc, #68] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007620: 735a strb r2, [r3, #13]
|
|
RadioSetPublicNetwork( SubgRf.PublicNetwork.Current );
|
|
8007622: 4b10 ldr r3, [pc, #64] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007624: 7b5b ldrb r3, [r3, #13]
|
|
8007626: 4618 mov r0, r3
|
|
8007628: f000 ffb2 bl 8008590 <RadioSetPublicNetwork>
|
|
}
|
|
break;
|
|
800762c: e014 b.n 8007658 <RadioSetModem+0xa8>
|
|
case MODEM_BPSK:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_BPSK );
|
|
800762e: 2002 movs r0, #2
|
|
8007630: f002 fb6a bl 8009d08 <SUBGRF_SetPacketType>
|
|
// When switching to BPSK mode the LoRa SyncWord register value is reset
|
|
// Thus, we also reset the RadioPublicNetwork variable
|
|
SubgRf.PublicNetwork.Current = false;
|
|
8007634: 4b0b ldr r3, [pc, #44] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007636: 2200 movs r2, #0
|
|
8007638: 735a strb r2, [r3, #13]
|
|
break;
|
|
800763a: e00e b.n 800765a <RadioSetModem+0xaa>
|
|
#if (RADIO_SIGFOX_ENABLE == 1)
|
|
case MODEM_SIGFOX_TX:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_BPSK );
|
|
800763c: 2002 movs r0, #2
|
|
800763e: f002 fb63 bl 8009d08 <SUBGRF_SetPacketType>
|
|
// When switching to BPSK mode the LoRa SyncWord register value is reset
|
|
// Thus, we also reset the RadioPublicNetwork variable
|
|
SubgRf.PublicNetwork.Current = false;
|
|
8007642: 4b08 ldr r3, [pc, #32] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007644: 2200 movs r2, #0
|
|
8007646: 735a strb r2, [r3, #13]
|
|
break;
|
|
8007648: e007 b.n 800765a <RadioSetModem+0xaa>
|
|
case MODEM_SIGFOX_RX:
|
|
SUBGRF_SetPacketType( PACKET_TYPE_GFSK );
|
|
800764a: 2000 movs r0, #0
|
|
800764c: f002 fb5c bl 8009d08 <SUBGRF_SetPacketType>
|
|
// When switching to GFSK mode the LoRa SyncWord register value is reset
|
|
// Thus, we also reset the RadioPublicNetwork variable
|
|
SubgRf.PublicNetwork.Current = false;
|
|
8007650: 4b04 ldr r3, [pc, #16] @ (8007664 <RadioSetModem+0xb4>)
|
|
8007652: 2200 movs r2, #0
|
|
8007654: 735a strb r2, [r3, #13]
|
|
break;
|
|
8007656: e000 b.n 800765a <RadioSetModem+0xaa>
|
|
break;
|
|
8007658: bf00 nop
|
|
#endif /*RADIO_SIGFOX_ENABLE == 1*/
|
|
}
|
|
}
|
|
800765a: bf00 nop
|
|
800765c: 3708 adds r7, #8
|
|
800765e: 46bd mov sp, r7
|
|
8007660: bd80 pop {r7, pc}
|
|
8007662: bf00 nop
|
|
8007664: 20000290 .word 0x20000290
|
|
|
|
08007668 <RadioSetChannel>:
|
|
|
|
static void RadioSetChannel( uint32_t freq )
|
|
{
|
|
8007668: b580 push {r7, lr}
|
|
800766a: b082 sub sp, #8
|
|
800766c: af00 add r7, sp, #0
|
|
800766e: 6078 str r0, [r7, #4]
|
|
SUBGRF_SetRfFrequency( freq );
|
|
8007670: 6878 ldr r0, [r7, #4]
|
|
8007672: f002 fb03 bl 8009c7c <SUBGRF_SetRfFrequency>
|
|
}
|
|
8007676: bf00 nop
|
|
8007678: 3708 adds r7, #8
|
|
800767a: 46bd mov sp, r7
|
|
800767c: bd80 pop {r7, pc}
|
|
|
|
0800767e <RadioIsChannelFree>:
|
|
|
|
static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime )
|
|
{
|
|
800767e: b580 push {r7, lr}
|
|
8007680: b090 sub sp, #64 @ 0x40
|
|
8007682: af0a add r7, sp, #40 @ 0x28
|
|
8007684: 60f8 str r0, [r7, #12]
|
|
8007686: 60b9 str r1, [r7, #8]
|
|
8007688: 603b str r3, [r7, #0]
|
|
800768a: 4613 mov r3, r2
|
|
800768c: 80fb strh r3, [r7, #6]
|
|
bool status = true;
|
|
800768e: 2301 movs r3, #1
|
|
8007690: 75fb strb r3, [r7, #23]
|
|
int16_t rssi = 0;
|
|
8007692: 2300 movs r3, #0
|
|
8007694: 82bb strh r3, [r7, #20]
|
|
uint32_t carrierSenseTime = 0;
|
|
8007696: 2300 movs r3, #0
|
|
8007698: 613b str r3, [r7, #16]
|
|
|
|
RadioStandby( );
|
|
800769a: f000 fdf8 bl 800828e <RadioStandby>
|
|
|
|
RadioSetModem( MODEM_FSK );
|
|
800769e: 2000 movs r0, #0
|
|
80076a0: f7ff ff86 bl 80075b0 <RadioSetModem>
|
|
|
|
RadioSetChannel( freq );
|
|
80076a4: 68f8 ldr r0, [r7, #12]
|
|
80076a6: f7ff ffdf bl 8007668 <RadioSetChannel>
|
|
|
|
// Set Rx bandwidth. Other parameters are not used.
|
|
RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false,
|
|
80076aa: 2301 movs r3, #1
|
|
80076ac: 9309 str r3, [sp, #36] @ 0x24
|
|
80076ae: 2300 movs r3, #0
|
|
80076b0: 9308 str r3, [sp, #32]
|
|
80076b2: 2300 movs r3, #0
|
|
80076b4: 9307 str r3, [sp, #28]
|
|
80076b6: 2300 movs r3, #0
|
|
80076b8: 9306 str r3, [sp, #24]
|
|
80076ba: 2300 movs r3, #0
|
|
80076bc: 9305 str r3, [sp, #20]
|
|
80076be: 2300 movs r3, #0
|
|
80076c0: 9304 str r3, [sp, #16]
|
|
80076c2: 2300 movs r3, #0
|
|
80076c4: 9303 str r3, [sp, #12]
|
|
80076c6: 2300 movs r3, #0
|
|
80076c8: 9302 str r3, [sp, #8]
|
|
80076ca: 2303 movs r3, #3
|
|
80076cc: 9301 str r3, [sp, #4]
|
|
80076ce: 68bb ldr r3, [r7, #8]
|
|
80076d0: 9300 str r3, [sp, #0]
|
|
80076d2: 2300 movs r3, #0
|
|
80076d4: f44f 7216 mov.w r2, #600 @ 0x258
|
|
80076d8: 68b9 ldr r1, [r7, #8]
|
|
80076da: 2000 movs r0, #0
|
|
80076dc: f000 f83c bl 8007758 <RadioSetRxConfig>
|
|
0, false, 0, 0, false, true );
|
|
RadioRx( 0 );
|
|
80076e0: 2000 movs r0, #0
|
|
80076e2: f000 fddb bl 800829c <RadioRx>
|
|
|
|
RADIO_DELAY_MS( RadioGetWakeupTime( ) );
|
|
80076e6: f000 ff81 bl 80085ec <RadioGetWakeupTime>
|
|
80076ea: 4603 mov r3, r0
|
|
80076ec: 4618 mov r0, r3
|
|
80076ee: f7f9 fa5b bl 8000ba8 <HAL_Delay>
|
|
|
|
carrierSenseTime = TimerGetCurrentTime( );
|
|
80076f2: f005 fb69 bl 800cdc8 <UTIL_TIMER_GetCurrentTime>
|
|
80076f6: 6138 str r0, [r7, #16]
|
|
|
|
// Perform carrier sense for maxCarrierSenseTime
|
|
while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime )
|
|
80076f8: e00d b.n 8007716 <RadioIsChannelFree+0x98>
|
|
{
|
|
rssi = RadioRssi( MODEM_FSK );
|
|
80076fa: 2000 movs r0, #0
|
|
80076fc: f000 fec8 bl 8008490 <RadioRssi>
|
|
8007700: 4603 mov r3, r0
|
|
8007702: 82bb strh r3, [r7, #20]
|
|
|
|
if( rssi > rssiThresh )
|
|
8007704: f9b7 2014 ldrsh.w r2, [r7, #20]
|
|
8007708: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800770c: 429a cmp r2, r3
|
|
800770e: dd02 ble.n 8007716 <RadioIsChannelFree+0x98>
|
|
{
|
|
status = false;
|
|
8007710: 2300 movs r3, #0
|
|
8007712: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007714: e006 b.n 8007724 <RadioIsChannelFree+0xa6>
|
|
while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime )
|
|
8007716: 6938 ldr r0, [r7, #16]
|
|
8007718: f005 fb68 bl 800cdec <UTIL_TIMER_GetElapsedTime>
|
|
800771c: 4602 mov r2, r0
|
|
800771e: 683b ldr r3, [r7, #0]
|
|
8007720: 4293 cmp r3, r2
|
|
8007722: d8ea bhi.n 80076fa <RadioIsChannelFree+0x7c>
|
|
}
|
|
}
|
|
RadioStandby( );
|
|
8007724: f000 fdb3 bl 800828e <RadioStandby>
|
|
|
|
return status;
|
|
8007728: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800772a: 4618 mov r0, r3
|
|
800772c: 3718 adds r7, #24
|
|
800772e: 46bd mov sp, r7
|
|
8007730: bd80 pop {r7, pc}
|
|
|
|
08007732 <RadioRandom>:
|
|
|
|
static uint32_t RadioRandom( void )
|
|
{
|
|
8007732: b580 push {r7, lr}
|
|
8007734: b082 sub sp, #8
|
|
8007736: af00 add r7, sp, #0
|
|
uint32_t rnd = 0;
|
|
8007738: 2300 movs r3, #0
|
|
800773a: 607b str r3, [r7, #4]
|
|
|
|
/*
|
|
* Radio setup for random number generation
|
|
*/
|
|
// Disable modem interrupts
|
|
SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE );
|
|
800773c: 2300 movs r3, #0
|
|
800773e: 2200 movs r2, #0
|
|
8007740: 2100 movs r1, #0
|
|
8007742: 2000 movs r0, #0
|
|
8007744: f002 fa3e bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
|
|
rnd = SUBGRF_GetRandom();
|
|
8007748: f001 ffe7 bl 800971a <SUBGRF_GetRandom>
|
|
800774c: 6078 str r0, [r7, #4]
|
|
|
|
return rnd;
|
|
800774e: 687b ldr r3, [r7, #4]
|
|
}
|
|
8007750: 4618 mov r0, r3
|
|
8007752: 3708 adds r7, #8
|
|
8007754: 46bd mov sp, r7
|
|
8007756: bd80 pop {r7, pc}
|
|
|
|
08007758 <RadioSetRxConfig>:
|
|
uint32_t bandwidthAfc, uint16_t preambleLen,
|
|
uint16_t symbTimeout, bool fixLen,
|
|
uint8_t payloadLen,
|
|
bool crcOn, bool freqHopOn, uint8_t hopPeriod,
|
|
bool iqInverted, bool rxContinuous )
|
|
{
|
|
8007758: b580 push {r7, lr}
|
|
800775a: b08a sub sp, #40 @ 0x28
|
|
800775c: af00 add r7, sp, #0
|
|
800775e: 60b9 str r1, [r7, #8]
|
|
8007760: 607a str r2, [r7, #4]
|
|
8007762: 461a mov r2, r3
|
|
8007764: 4603 mov r3, r0
|
|
8007766: 73fb strb r3, [r7, #15]
|
|
8007768: 4613 mov r3, r2
|
|
800776a: 73bb strb r3, [r7, #14]
|
|
#if (RADIO_SIGFOX_ENABLE == 1)
|
|
uint8_t modReg;
|
|
#endif
|
|
SubgRf.RxContinuous = rxContinuous;
|
|
800776c: 4ab9 ldr r2, [pc, #740] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800776e: f897 3054 ldrb.w r3, [r7, #84] @ 0x54
|
|
8007772: 7053 strb r3, [r2, #1]
|
|
RFW_DeInit();
|
|
8007774: f003 fb40 bl 800adf8 <RFW_DeInit>
|
|
if( rxContinuous == true )
|
|
8007778: f897 3054 ldrb.w r3, [r7, #84] @ 0x54
|
|
800777c: 2b00 cmp r3, #0
|
|
800777e: d001 beq.n 8007784 <RadioSetRxConfig+0x2c>
|
|
{
|
|
symbTimeout = 0;
|
|
8007780: 2300 movs r3, #0
|
|
8007782: 873b strh r3, [r7, #56] @ 0x38
|
|
}
|
|
if( fixLen == true )
|
|
8007784: f897 303c ldrb.w r3, [r7, #60] @ 0x3c
|
|
8007788: 2b00 cmp r3, #0
|
|
800778a: d004 beq.n 8007796 <RadioSetRxConfig+0x3e>
|
|
{
|
|
MaxPayloadLength = payloadLen;
|
|
800778c: 4ab2 ldr r2, [pc, #712] @ (8007a58 <RadioSetRxConfig+0x300>)
|
|
800778e: f897 3040 ldrb.w r3, [r7, #64] @ 0x40
|
|
8007792: 7013 strb r3, [r2, #0]
|
|
8007794: e002 b.n 800779c <RadioSetRxConfig+0x44>
|
|
}
|
|
else
|
|
{
|
|
MaxPayloadLength = 0xFF;
|
|
8007796: 4bb0 ldr r3, [pc, #704] @ (8007a58 <RadioSetRxConfig+0x300>)
|
|
8007798: 22ff movs r2, #255 @ 0xff
|
|
800779a: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
switch( modem )
|
|
800779c: 7bfb ldrb r3, [r7, #15]
|
|
800779e: 2b05 cmp r3, #5
|
|
80077a0: d009 beq.n 80077b6 <RadioSetRxConfig+0x5e>
|
|
80077a2: 2b05 cmp r3, #5
|
|
80077a4: f300 81d7 bgt.w 8007b56 <RadioSetRxConfig+0x3fe>
|
|
80077a8: 2b00 cmp r3, #0
|
|
80077aa: f000 80bf beq.w 800792c <RadioSetRxConfig+0x1d4>
|
|
80077ae: 2b01 cmp r3, #1
|
|
80077b0: f000 8124 beq.w 80079fc <RadioSetRxConfig+0x2a4>
|
|
// Timeout Max, Timeout handled directly in SetRx function
|
|
SubgRf.RxTimeout = 0xFFFF;
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
80077b4: e1cf b.n 8007b56 <RadioSetRxConfig+0x3fe>
|
|
SUBGRF_SetStopRxTimerOnPreambleDetect( true );
|
|
80077b6: 2001 movs r0, #1
|
|
80077b8: f002 f8f6 bl 80099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
80077bc: 4ba5 ldr r3, [pc, #660] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077be: 2200 movs r2, #0
|
|
80077c0: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate;
|
|
80077c4: 4aa3 ldr r2, [pc, #652] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077c6: 687b ldr r3, [r7, #4]
|
|
80077c8: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05;
|
|
80077ca: 4ba2 ldr r3, [pc, #648] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077cc: 2209 movs r2, #9
|
|
80077ce: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
SubgRf.ModulationParams.Params.Gfsk.Fdev = 800;
|
|
80077d2: 4ba0 ldr r3, [pc, #640] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077d4: f44f 7248 mov.w r2, #800 @ 0x320
|
|
80077d8: 641a str r2, [r3, #64] @ 0x40
|
|
SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth );
|
|
80077da: 68b8 ldr r0, [r7, #8]
|
|
80077dc: f002 ffd0 bl 800a780 <SUBGRF_GetFskBandwidthRegValue>
|
|
80077e0: 4603 mov r3, r0
|
|
80077e2: 461a mov r2, r3
|
|
80077e4: 4b9b ldr r3, [pc, #620] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077e6: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
80077ea: 4b9a ldr r3, [pc, #616] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077ec: 2200 movs r2, #0
|
|
80077ee: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit
|
|
80077f0: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
80077f2: 00db lsls r3, r3, #3
|
|
80077f4: b29a uxth r2, r3
|
|
80077f6: 4b97 ldr r3, [pc, #604] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077f8: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF;
|
|
80077fa: 4b96 ldr r3, [pc, #600] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80077fc: 2200 movs r2, #0
|
|
80077fe: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit
|
|
8007800: 4b94 ldr r3, [pc, #592] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007802: 2210 movs r2, #16
|
|
8007804: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF;
|
|
8007806: 4b93 ldr r3, [pc, #588] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007808: 2200 movs r2, #0
|
|
800780a: 751a strb r2, [r3, #20]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH;
|
|
800780c: 4b91 ldr r3, [pc, #580] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800780e: 2200 movs r2, #0
|
|
8007810: 755a strb r2, [r3, #21]
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength;
|
|
8007812: 4b91 ldr r3, [pc, #580] @ (8007a58 <RadioSetRxConfig+0x300>)
|
|
8007814: 781a ldrb r2, [r3, #0]
|
|
8007816: 4b8f ldr r3, [pc, #572] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007818: 759a strb r2, [r3, #22]
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF;
|
|
800781a: 4b8e ldr r3, [pc, #568] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800781c: 2201 movs r2, #1
|
|
800781e: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF;
|
|
8007820: 4b8c ldr r3, [pc, #560] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007822: 2200 movs r2, #0
|
|
8007824: 761a strb r2, [r3, #24]
|
|
RadioSetModem( MODEM_SIGFOX_RX );
|
|
8007826: 2005 movs r0, #5
|
|
8007828: f7ff fec2 bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
800782c: 488b ldr r0, [pc, #556] @ (8007a5c <RadioSetRxConfig+0x304>)
|
|
800782e: f002 fb5f bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8007832: 488b ldr r0, [pc, #556] @ (8007a60 <RadioSetRxConfig+0x308>)
|
|
8007834: f002 fc2a bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } );
|
|
8007838: 4a8a ldr r2, [pc, #552] @ (8007a64 <RadioSetRxConfig+0x30c>)
|
|
800783a: f107 031c add.w r3, r7, #28
|
|
800783e: e892 0003 ldmia.w r2, {r0, r1}
|
|
8007842: e883 0003 stmia.w r3, {r0, r1}
|
|
8007846: f107 031c add.w r3, r7, #28
|
|
800784a: 4618 mov r0, r3
|
|
800784c: f001 fee3 bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( 0x01FF );
|
|
8007850: f240 10ff movw r0, #511 @ 0x1ff
|
|
8007854: f001 ff2e bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR);
|
|
8007858: f640 00b8 movw r0, #2232 @ 0x8b8
|
|
800785c: f000 fe36 bl 80084cc <RadioRead>
|
|
8007860: 4603 mov r3, r0
|
|
8007862: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
modReg&=RADIO_BIT_MASK(4);
|
|
8007866: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800786a: f023 0310 bic.w r3, r3, #16
|
|
800786e: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg);
|
|
8007872: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8007876: 4619 mov r1, r3
|
|
8007878: f640 00b8 movw r0, #2232 @ 0x8b8
|
|
800787c: f000 fe14 bl 80084a8 <RadioWrite>
|
|
RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 );
|
|
8007880: 2104 movs r1, #4
|
|
8007882: f640 00b9 movw r0, #2233 @ 0x8b9
|
|
8007886: f000 fe0f bl 80084a8 <RadioWrite>
|
|
modReg= RadioRead(SUBGHZ_AGCRSSICTL0R);
|
|
800788a: f640 009b movw r0, #2203 @ 0x89b
|
|
800788e: f000 fe1d bl 80084cc <RadioRead>
|
|
8007892: 4603 mov r3, r0
|
|
8007894: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) );
|
|
8007898: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800789c: f023 031c bic.w r3, r3, #28
|
|
80078a0: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) );
|
|
80078a4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80078a8: f043 0308 orr.w r3, r3, #8
|
|
80078ac: b2db uxtb r3, r3
|
|
80078ae: 4619 mov r1, r3
|
|
80078b0: f640 009b movw r0, #2203 @ 0x89b
|
|
80078b4: f000 fdf8 bl 80084a8 <RadioWrite>
|
|
modReg= RadioRead(SUBGHZ_GAFCR);
|
|
80078b8: f240 60d1 movw r0, #1745 @ 0x6d1
|
|
80078bc: f000 fe06 bl 80084cc <RadioRead>
|
|
80078c0: 4603 mov r3, r0
|
|
80078c2: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) );
|
|
80078c6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80078ca: f023 0318 bic.w r3, r3, #24
|
|
80078ce: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) ));
|
|
80078d2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80078d6: f043 0318 orr.w r3, r3, #24
|
|
80078da: b2db uxtb r3, r3
|
|
80078dc: 4619 mov r1, r3
|
|
80078de: f240 60d1 movw r0, #1745 @ 0x6d1
|
|
80078e2: f000 fde1 bl 80084a8 <RadioWrite>
|
|
modReg= RadioRead(SUBGHZ_GBSYNCR);
|
|
80078e6: f240 60ac movw r0, #1708 @ 0x6ac
|
|
80078ea: f000 fdef bl 80084cc <RadioRead>
|
|
80078ee: 4603 mov r3, r0
|
|
80078f0: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) );
|
|
80078f4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80078f8: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80078fc: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) ));
|
|
8007900: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8007904: f043 0350 orr.w r3, r3, #80 @ 0x50
|
|
8007908: b2db uxtb r3, r3
|
|
800790a: 4619 mov r1, r3
|
|
800790c: f240 60ac movw r0, #1708 @ 0x6ac
|
|
8007910: f000 fdca bl 80084a8 <RadioWrite>
|
|
SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate);
|
|
8007914: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
8007916: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
800791a: fb02 f303 mul.w r3, r2, r3
|
|
800791e: 461a mov r2, r3
|
|
8007920: 687b ldr r3, [r7, #4]
|
|
8007922: fbb2 f3f3 udiv r3, r2, r3
|
|
8007926: 4a4b ldr r2, [pc, #300] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007928: 6093 str r3, [r2, #8]
|
|
break;
|
|
800792a: e115 b.n 8007b58 <RadioSetRxConfig+0x400>
|
|
SUBGRF_SetStopRxTimerOnPreambleDetect( false );
|
|
800792c: 2000 movs r0, #0
|
|
800792e: f002 f83b bl 80099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
8007932: 4b48 ldr r3, [pc, #288] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007934: 2200 movs r2, #0
|
|
8007936: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate;
|
|
800793a: 4a46 ldr r2, [pc, #280] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800793c: 687b ldr r3, [r7, #4]
|
|
800793e: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1;
|
|
8007940: 4b44 ldr r3, [pc, #272] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007942: 220b movs r2, #11
|
|
8007944: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth );
|
|
8007948: 68b8 ldr r0, [r7, #8]
|
|
800794a: f002 ff19 bl 800a780 <SUBGRF_GetFskBandwidthRegValue>
|
|
800794e: 4603 mov r3, r0
|
|
8007950: 461a mov r2, r3
|
|
8007952: 4b40 ldr r3, [pc, #256] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007954: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
8007958: 4b3e ldr r3, [pc, #248] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800795a: 2200 movs r2, #0
|
|
800795c: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit
|
|
800795e: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
8007960: 00db lsls r3, r3, #3
|
|
8007962: b29a uxth r2, r3
|
|
8007964: 4b3b ldr r3, [pc, #236] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007966: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS;
|
|
8007968: 4b3a ldr r3, [pc, #232] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800796a: 2204 movs r2, #4
|
|
800796c: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit
|
|
800796e: 4b39 ldr r3, [pc, #228] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007970: 2218 movs r2, #24
|
|
8007972: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF;
|
|
8007974: 4b37 ldr r3, [pc, #220] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007976: 2200 movs r2, #0
|
|
8007978: 751a strb r2, [r3, #20]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH;
|
|
800797a: f897 303c ldrb.w r3, [r7, #60] @ 0x3c
|
|
800797e: f083 0301 eor.w r3, r3, #1
|
|
8007982: b2db uxtb r3, r3
|
|
8007984: 461a mov r2, r3
|
|
8007986: 4b33 ldr r3, [pc, #204] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007988: 755a strb r2, [r3, #21]
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength;
|
|
800798a: 4b33 ldr r3, [pc, #204] @ (8007a58 <RadioSetRxConfig+0x300>)
|
|
800798c: 781a ldrb r2, [r3, #0]
|
|
800798e: 4b31 ldr r3, [pc, #196] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007990: 759a strb r2, [r3, #22]
|
|
if( crcOn == true )
|
|
8007992: f897 3044 ldrb.w r3, [r7, #68] @ 0x44
|
|
8007996: 2b00 cmp r3, #0
|
|
8007998: d003 beq.n 80079a2 <RadioSetRxConfig+0x24a>
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT;
|
|
800799a: 4b2e ldr r3, [pc, #184] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
800799c: 22f2 movs r2, #242 @ 0xf2
|
|
800799e: 75da strb r2, [r3, #23]
|
|
80079a0: e002 b.n 80079a8 <RadioSetRxConfig+0x250>
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF;
|
|
80079a2: 4b2c ldr r3, [pc, #176] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80079a4: 2201 movs r2, #1
|
|
80079a6: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING;
|
|
80079a8: 4b2a ldr r3, [pc, #168] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80079aa: 2201 movs r2, #1
|
|
80079ac: 761a strb r2, [r3, #24]
|
|
RadioStandby( );
|
|
80079ae: f000 fc6e bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_FSK );
|
|
80079b2: 2000 movs r0, #0
|
|
80079b4: f7ff fdfc bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
80079b8: 4828 ldr r0, [pc, #160] @ (8007a5c <RadioSetRxConfig+0x304>)
|
|
80079ba: f002 fa99 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
80079be: 4828 ldr r0, [pc, #160] @ (8007a60 <RadioSetRxConfig+0x308>)
|
|
80079c0: f002 fb64 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } );
|
|
80079c4: 4a28 ldr r2, [pc, #160] @ (8007a68 <RadioSetRxConfig+0x310>)
|
|
80079c6: f107 0314 add.w r3, r7, #20
|
|
80079ca: e892 0003 ldmia.w r2, {r0, r1}
|
|
80079ce: e883 0003 stmia.w r3, {r0, r1}
|
|
80079d2: f107 0314 add.w r3, r7, #20
|
|
80079d6: 4618 mov r0, r3
|
|
80079d8: f001 fe1d bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( 0x01FF );
|
|
80079dc: f240 10ff movw r0, #511 @ 0x1ff
|
|
80079e0: f001 fe68 bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate);
|
|
80079e4: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
80079e6: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
80079ea: fb02 f303 mul.w r3, r2, r3
|
|
80079ee: 461a mov r2, r3
|
|
80079f0: 687b ldr r3, [r7, #4]
|
|
80079f2: fbb2 f3f3 udiv r3, r2, r3
|
|
80079f6: 4a17 ldr r2, [pc, #92] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
80079f8: 6093 str r3, [r2, #8]
|
|
break;
|
|
80079fa: e0ad b.n 8007b58 <RadioSetRxConfig+0x400>
|
|
SUBGRF_SetStopRxTimerOnPreambleDetect( false );
|
|
80079fc: 2000 movs r0, #0
|
|
80079fe: f001 ffd3 bl 80099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA;
|
|
8007a02: 4b14 ldr r3, [pc, #80] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007a04: 2201 movs r2, #1
|
|
8007a06: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate;
|
|
8007a0a: 687b ldr r3, [r7, #4]
|
|
8007a0c: b2da uxtb r2, r3
|
|
8007a0e: 4b11 ldr r3, [pc, #68] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007a10: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth];
|
|
8007a14: 4a15 ldr r2, [pc, #84] @ (8007a6c <RadioSetRxConfig+0x314>)
|
|
8007a16: 68bb ldr r3, [r7, #8]
|
|
8007a18: 4413 add r3, r2
|
|
8007a1a: 781a ldrb r2, [r3, #0]
|
|
8007a1c: 4b0d ldr r3, [pc, #52] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007a1e: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate;
|
|
8007a22: 4a0c ldr r2, [pc, #48] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007a24: 7bbb ldrb r3, [r7, #14]
|
|
8007a26: f882 3052 strb.w r3, [r2, #82] @ 0x52
|
|
if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
|
|
8007a2a: 68bb ldr r3, [r7, #8]
|
|
8007a2c: 2b00 cmp r3, #0
|
|
8007a2e: d105 bne.n 8007a3c <RadioSetRxConfig+0x2e4>
|
|
8007a30: 687b ldr r3, [r7, #4]
|
|
8007a32: 2b0b cmp r3, #11
|
|
8007a34: d008 beq.n 8007a48 <RadioSetRxConfig+0x2f0>
|
|
8007a36: 687b ldr r3, [r7, #4]
|
|
8007a38: 2b0c cmp r3, #12
|
|
8007a3a: d005 beq.n 8007a48 <RadioSetRxConfig+0x2f0>
|
|
8007a3c: 68bb ldr r3, [r7, #8]
|
|
8007a3e: 2b01 cmp r3, #1
|
|
8007a40: d116 bne.n 8007a70 <RadioSetRxConfig+0x318>
|
|
( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
|
|
8007a42: 687b ldr r3, [r7, #4]
|
|
8007a44: 2b0c cmp r3, #12
|
|
8007a46: d113 bne.n 8007a70 <RadioSetRxConfig+0x318>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01;
|
|
8007a48: 4b02 ldr r3, [pc, #8] @ (8007a54 <RadioSetRxConfig+0x2fc>)
|
|
8007a4a: 2201 movs r2, #1
|
|
8007a4c: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
8007a50: e012 b.n 8007a78 <RadioSetRxConfig+0x320>
|
|
8007a52: bf00 nop
|
|
8007a54: 20000290 .word 0x20000290
|
|
8007a58: 20000008 .word 0x20000008
|
|
8007a5c: 200002c8 .word 0x200002c8
|
|
8007a60: 2000029e .word 0x2000029e
|
|
8007a64: 0800d528 .word 0x0800d528
|
|
8007a68: 0800d530 .word 0x0800d530
|
|
8007a6c: 0800da6c .word 0x0800da6c
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00;
|
|
8007a70: 4b3b ldr r3, [pc, #236] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007a72: 2200 movs r2, #0
|
|
8007a74: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA;
|
|
8007a78: 4b39 ldr r3, [pc, #228] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007a7a: 2201 movs r2, #1
|
|
8007a7c: 739a strb r2, [r3, #14]
|
|
if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
|
|
8007a7e: 4b38 ldr r3, [pc, #224] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007a80: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
|
|
8007a84: 2b05 cmp r3, #5
|
|
8007a86: d004 beq.n 8007a92 <RadioSetRxConfig+0x33a>
|
|
( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) )
|
|
8007a88: 4b35 ldr r3, [pc, #212] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007a8a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
|
|
if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
|
|
8007a8e: 2b06 cmp r3, #6
|
|
8007a90: d10a bne.n 8007aa8 <RadioSetRxConfig+0x350>
|
|
if( preambleLen < 12 )
|
|
8007a92: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
8007a94: 2b0b cmp r3, #11
|
|
8007a96: d803 bhi.n 8007aa0 <RadioSetRxConfig+0x348>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = 12;
|
|
8007a98: 4b31 ldr r3, [pc, #196] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007a9a: 220c movs r2, #12
|
|
8007a9c: 839a strh r2, [r3, #28]
|
|
if( preambleLen < 12 )
|
|
8007a9e: e006 b.n 8007aae <RadioSetRxConfig+0x356>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen;
|
|
8007aa0: 4a2f ldr r2, [pc, #188] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007aa2: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
8007aa4: 8393 strh r3, [r2, #28]
|
|
if( preambleLen < 12 )
|
|
8007aa6: e002 b.n 8007aae <RadioSetRxConfig+0x356>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen;
|
|
8007aa8: 4a2d ldr r2, [pc, #180] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007aaa: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
8007aac: 8393 strh r3, [r2, #28]
|
|
SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen;
|
|
8007aae: f897 203c ldrb.w r2, [r7, #60] @ 0x3c
|
|
8007ab2: 4b2b ldr r3, [pc, #172] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007ab4: 779a strb r2, [r3, #30]
|
|
SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength;
|
|
8007ab6: 4b2b ldr r3, [pc, #172] @ (8007b64 <RadioSetRxConfig+0x40c>)
|
|
8007ab8: 781a ldrb r2, [r3, #0]
|
|
8007aba: 4b29 ldr r3, [pc, #164] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007abc: 77da strb r2, [r3, #31]
|
|
SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn;
|
|
8007abe: f897 2044 ldrb.w r2, [r7, #68] @ 0x44
|
|
8007ac2: 4b27 ldr r3, [pc, #156] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007ac4: f883 2020 strb.w r2, [r3, #32]
|
|
SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted;
|
|
8007ac8: f897 2050 ldrb.w r2, [r7, #80] @ 0x50
|
|
8007acc: 4b24 ldr r3, [pc, #144] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007ace: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
RadioStandby( );
|
|
8007ad2: f000 fbdc bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_LORA );
|
|
8007ad6: 2001 movs r0, #1
|
|
8007ad8: f7ff fd6a bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8007adc: 4822 ldr r0, [pc, #136] @ (8007b68 <RadioSetRxConfig+0x410>)
|
|
8007ade: f002 fa07 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8007ae2: 4822 ldr r0, [pc, #136] @ (8007b6c <RadioSetRxConfig+0x414>)
|
|
8007ae4: f002 fad2 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetLoRaSymbNumTimeout( symbTimeout );
|
|
8007ae8: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
8007aea: b2db uxtb r3, r3
|
|
8007aec: 4618 mov r0, r3
|
|
8007aee: f001 ff6a bl 80099c6 <SUBGRF_SetLoRaSymbNumTimeout>
|
|
SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1);
|
|
8007af2: f640 00a3 movw r0, #2211 @ 0x8a3
|
|
8007af6: f002 fc31 bl 800a35c <SUBGRF_ReadRegister>
|
|
8007afa: 4603 mov r3, r0
|
|
8007afc: f003 0301 and.w r3, r3, #1
|
|
8007b00: b2db uxtb r3, r3
|
|
8007b02: 4619 mov r1, r3
|
|
8007b04: f640 00a3 movw r0, #2211 @ 0x8a3
|
|
8007b08: f002 fc06 bl 800a318 <SUBGRF_WriteRegister>
|
|
if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED )
|
|
8007b0c: 4b14 ldr r3, [pc, #80] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007b0e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
8007b12: 2b01 cmp r3, #1
|
|
8007b14: d10d bne.n 8007b32 <RadioSetRxConfig+0x3da>
|
|
SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) );
|
|
8007b16: f240 7036 movw r0, #1846 @ 0x736
|
|
8007b1a: f002 fc1f bl 800a35c <SUBGRF_ReadRegister>
|
|
8007b1e: 4603 mov r3, r0
|
|
8007b20: f023 0304 bic.w r3, r3, #4
|
|
8007b24: b2db uxtb r3, r3
|
|
8007b26: 4619 mov r1, r3
|
|
8007b28: f240 7036 movw r0, #1846 @ 0x736
|
|
8007b2c: f002 fbf4 bl 800a318 <SUBGRF_WriteRegister>
|
|
8007b30: e00c b.n 8007b4c <RadioSetRxConfig+0x3f4>
|
|
SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) );
|
|
8007b32: f240 7036 movw r0, #1846 @ 0x736
|
|
8007b36: f002 fc11 bl 800a35c <SUBGRF_ReadRegister>
|
|
8007b3a: 4603 mov r3, r0
|
|
8007b3c: f043 0304 orr.w r3, r3, #4
|
|
8007b40: b2db uxtb r3, r3
|
|
8007b42: 4619 mov r1, r3
|
|
8007b44: f240 7036 movw r0, #1846 @ 0x736
|
|
8007b48: f002 fbe6 bl 800a318 <SUBGRF_WriteRegister>
|
|
SubgRf.RxTimeout = 0xFFFF;
|
|
8007b4c: 4b04 ldr r3, [pc, #16] @ (8007b60 <RadioSetRxConfig+0x408>)
|
|
8007b4e: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8007b52: 609a str r2, [r3, #8]
|
|
break;
|
|
8007b54: e000 b.n 8007b58 <RadioSetRxConfig+0x400>
|
|
break;
|
|
8007b56: bf00 nop
|
|
}
|
|
}
|
|
8007b58: bf00 nop
|
|
8007b5a: 3728 adds r7, #40 @ 0x28
|
|
8007b5c: 46bd mov sp, r7
|
|
8007b5e: bd80 pop {r7, pc}
|
|
8007b60: 20000290 .word 0x20000290
|
|
8007b64: 20000008 .word 0x20000008
|
|
8007b68: 200002c8 .word 0x200002c8
|
|
8007b6c: 2000029e .word 0x2000029e
|
|
|
|
08007b70 <RadioSetTxConfig>:
|
|
static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
|
|
uint32_t bandwidth, uint32_t datarate,
|
|
uint8_t coderate, uint16_t preambleLen,
|
|
bool fixLen, bool crcOn, bool freqHopOn,
|
|
uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
|
|
{
|
|
8007b70: b580 push {r7, lr}
|
|
8007b72: b086 sub sp, #24
|
|
8007b74: af00 add r7, sp, #0
|
|
8007b76: 60ba str r2, [r7, #8]
|
|
8007b78: 607b str r3, [r7, #4]
|
|
8007b7a: 4603 mov r3, r0
|
|
8007b7c: 73fb strb r3, [r7, #15]
|
|
8007b7e: 460b mov r3, r1
|
|
8007b80: 73bb strb r3, [r7, #14]
|
|
#if( RADIO_LR_FHSS_IS_ON == 1 )
|
|
/*disable LrFhss*/
|
|
SubgRf.lr_fhss.is_lr_fhss_on = false;
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
RFW_DeInit();
|
|
8007b82: f003 f939 bl 800adf8 <RFW_DeInit>
|
|
switch( modem )
|
|
8007b86: 7bfb ldrb r3, [r7, #15]
|
|
8007b88: 2b04 cmp r3, #4
|
|
8007b8a: f000 80c7 beq.w 8007d1c <RadioSetTxConfig+0x1ac>
|
|
8007b8e: 2b04 cmp r3, #4
|
|
8007b90: f300 80d6 bgt.w 8007d40 <RadioSetTxConfig+0x1d0>
|
|
8007b94: 2b00 cmp r3, #0
|
|
8007b96: d002 beq.n 8007b9e <RadioSetTxConfig+0x2e>
|
|
8007b98: 2b01 cmp r3, #1
|
|
8007b9a: d059 beq.n 8007c50 <RadioSetTxConfig+0xe0>
|
|
SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK;
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
break;
|
|
#endif /*RADIO_SIGFOX_ENABLE == 1*/
|
|
default:
|
|
break;
|
|
8007b9c: e0d0 b.n 8007d40 <RadioSetTxConfig+0x1d0>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
8007b9e: 4b77 ldr r3, [pc, #476] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007ba0: 2200 movs r2, #0
|
|
8007ba2: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate;
|
|
8007ba6: 4a75 ldr r2, [pc, #468] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007ba8: 6a3b ldr r3, [r7, #32]
|
|
8007baa: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1;
|
|
8007bac: 4b73 ldr r3, [pc, #460] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bae: 220b movs r2, #11
|
|
8007bb0: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth );
|
|
8007bb4: 6878 ldr r0, [r7, #4]
|
|
8007bb6: f002 fde3 bl 800a780 <SUBGRF_GetFskBandwidthRegValue>
|
|
8007bba: 4603 mov r3, r0
|
|
8007bbc: 461a mov r2, r3
|
|
8007bbe: 4b6f ldr r3, [pc, #444] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bc0: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev;
|
|
8007bc4: 4a6d ldr r2, [pc, #436] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bc6: 68bb ldr r3, [r7, #8]
|
|
8007bc8: 6413 str r3, [r2, #64] @ 0x40
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
8007bca: 4b6c ldr r3, [pc, #432] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bcc: 2200 movs r2, #0
|
|
8007bce: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit
|
|
8007bd0: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
8007bd2: 00db lsls r3, r3, #3
|
|
8007bd4: b29a uxth r2, r3
|
|
8007bd6: 4b69 ldr r3, [pc, #420] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bd8: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS;
|
|
8007bda: 4b68 ldr r3, [pc, #416] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bdc: 2204 movs r2, #4
|
|
8007bde: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit
|
|
8007be0: 4b66 ldr r3, [pc, #408] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007be2: 2218 movs r2, #24
|
|
8007be4: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF;
|
|
8007be6: 4b65 ldr r3, [pc, #404] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007be8: 2200 movs r2, #0
|
|
8007bea: 751a strb r2, [r3, #20]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH;
|
|
8007bec: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
8007bf0: f083 0301 eor.w r3, r3, #1
|
|
8007bf4: b2db uxtb r3, r3
|
|
8007bf6: 461a mov r2, r3
|
|
8007bf8: 4b60 ldr r3, [pc, #384] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007bfa: 755a strb r2, [r3, #21]
|
|
if( crcOn == true )
|
|
8007bfc: f897 3030 ldrb.w r3, [r7, #48] @ 0x30
|
|
8007c00: 2b00 cmp r3, #0
|
|
8007c02: d003 beq.n 8007c0c <RadioSetTxConfig+0x9c>
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT;
|
|
8007c04: 4b5d ldr r3, [pc, #372] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c06: 22f2 movs r2, #242 @ 0xf2
|
|
8007c08: 75da strb r2, [r3, #23]
|
|
8007c0a: e002 b.n 8007c12 <RadioSetTxConfig+0xa2>
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF;
|
|
8007c0c: 4b5b ldr r3, [pc, #364] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c0e: 2201 movs r2, #1
|
|
8007c10: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING;
|
|
8007c12: 4b5a ldr r3, [pc, #360] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c14: 2201 movs r2, #1
|
|
8007c16: 761a strb r2, [r3, #24]
|
|
RadioStandby( );
|
|
8007c18: f000 fb39 bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_FSK );
|
|
8007c1c: 2000 movs r0, #0
|
|
8007c1e: f7ff fcc7 bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8007c22: 4857 ldr r0, [pc, #348] @ (8007d80 <RadioSetTxConfig+0x210>)
|
|
8007c24: f002 f964 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8007c28: 4856 ldr r0, [pc, #344] @ (8007d84 <RadioSetTxConfig+0x214>)
|
|
8007c2a: f002 fa2f bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } );
|
|
8007c2e: 4a56 ldr r2, [pc, #344] @ (8007d88 <RadioSetTxConfig+0x218>)
|
|
8007c30: f107 0310 add.w r3, r7, #16
|
|
8007c34: e892 0003 ldmia.w r2, {r0, r1}
|
|
8007c38: e883 0003 stmia.w r3, {r0, r1}
|
|
8007c3c: f107 0310 add.w r3, r7, #16
|
|
8007c40: 4618 mov r0, r3
|
|
8007c42: f001 fce8 bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( 0x01FF );
|
|
8007c46: f240 10ff movw r0, #511 @ 0x1ff
|
|
8007c4a: f001 fd33 bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
break;
|
|
8007c4e: e078 b.n 8007d42 <RadioSetTxConfig+0x1d2>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA;
|
|
8007c50: 4b4a ldr r3, [pc, #296] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c52: 2201 movs r2, #1
|
|
8007c54: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate;
|
|
8007c58: 6a3b ldr r3, [r7, #32]
|
|
8007c5a: b2da uxtb r2, r3
|
|
8007c5c: 4b47 ldr r3, [pc, #284] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c5e: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth];
|
|
8007c62: 4a4a ldr r2, [pc, #296] @ (8007d8c <RadioSetTxConfig+0x21c>)
|
|
8007c64: 687b ldr r3, [r7, #4]
|
|
8007c66: 4413 add r3, r2
|
|
8007c68: 781a ldrb r2, [r3, #0]
|
|
8007c6a: 4b44 ldr r3, [pc, #272] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c6c: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate;
|
|
8007c70: 4a42 ldr r2, [pc, #264] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c72: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8007c76: f882 3052 strb.w r3, [r2, #82] @ 0x52
|
|
if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
|
|
8007c7a: 687b ldr r3, [r7, #4]
|
|
8007c7c: 2b00 cmp r3, #0
|
|
8007c7e: d105 bne.n 8007c8c <RadioSetTxConfig+0x11c>
|
|
8007c80: 6a3b ldr r3, [r7, #32]
|
|
8007c82: 2b0b cmp r3, #11
|
|
8007c84: d008 beq.n 8007c98 <RadioSetTxConfig+0x128>
|
|
8007c86: 6a3b ldr r3, [r7, #32]
|
|
8007c88: 2b0c cmp r3, #12
|
|
8007c8a: d005 beq.n 8007c98 <RadioSetTxConfig+0x128>
|
|
8007c8c: 687b ldr r3, [r7, #4]
|
|
8007c8e: 2b01 cmp r3, #1
|
|
8007c90: d107 bne.n 8007ca2 <RadioSetTxConfig+0x132>
|
|
( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
|
|
8007c92: 6a3b ldr r3, [r7, #32]
|
|
8007c94: 2b0c cmp r3, #12
|
|
8007c96: d104 bne.n 8007ca2 <RadioSetTxConfig+0x132>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01;
|
|
8007c98: 4b38 ldr r3, [pc, #224] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007c9a: 2201 movs r2, #1
|
|
8007c9c: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
8007ca0: e003 b.n 8007caa <RadioSetTxConfig+0x13a>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00;
|
|
8007ca2: 4b36 ldr r3, [pc, #216] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007ca4: 2200 movs r2, #0
|
|
8007ca6: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA;
|
|
8007caa: 4b34 ldr r3, [pc, #208] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cac: 2201 movs r2, #1
|
|
8007cae: 739a strb r2, [r3, #14]
|
|
if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
|
|
8007cb0: 4b32 ldr r3, [pc, #200] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cb2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
|
|
8007cb6: 2b05 cmp r3, #5
|
|
8007cb8: d004 beq.n 8007cc4 <RadioSetTxConfig+0x154>
|
|
( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) )
|
|
8007cba: 4b30 ldr r3, [pc, #192] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cbc: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
|
|
if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
|
|
8007cc0: 2b06 cmp r3, #6
|
|
8007cc2: d10a bne.n 8007cda <RadioSetTxConfig+0x16a>
|
|
if( preambleLen < 12 )
|
|
8007cc4: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
8007cc6: 2b0b cmp r3, #11
|
|
8007cc8: d803 bhi.n 8007cd2 <RadioSetTxConfig+0x162>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = 12;
|
|
8007cca: 4b2c ldr r3, [pc, #176] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007ccc: 220c movs r2, #12
|
|
8007cce: 839a strh r2, [r3, #28]
|
|
if( preambleLen < 12 )
|
|
8007cd0: e006 b.n 8007ce0 <RadioSetTxConfig+0x170>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen;
|
|
8007cd2: 4a2a ldr r2, [pc, #168] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cd4: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
8007cd6: 8393 strh r3, [r2, #28]
|
|
if( preambleLen < 12 )
|
|
8007cd8: e002 b.n 8007ce0 <RadioSetTxConfig+0x170>
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen;
|
|
8007cda: 4a28 ldr r2, [pc, #160] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cdc: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
8007cde: 8393 strh r3, [r2, #28]
|
|
SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen;
|
|
8007ce0: f897 202c ldrb.w r2, [r7, #44] @ 0x2c
|
|
8007ce4: 4b25 ldr r3, [pc, #148] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007ce6: 779a strb r2, [r3, #30]
|
|
SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength;
|
|
8007ce8: 4b29 ldr r3, [pc, #164] @ (8007d90 <RadioSetTxConfig+0x220>)
|
|
8007cea: 781a ldrb r2, [r3, #0]
|
|
8007cec: 4b23 ldr r3, [pc, #140] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cee: 77da strb r2, [r3, #31]
|
|
SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn;
|
|
8007cf0: f897 2030 ldrb.w r2, [r7, #48] @ 0x30
|
|
8007cf4: 4b21 ldr r3, [pc, #132] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007cf6: f883 2020 strb.w r2, [r3, #32]
|
|
SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted;
|
|
8007cfa: f897 203c ldrb.w r2, [r7, #60] @ 0x3c
|
|
8007cfe: 4b1f ldr r3, [pc, #124] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d00: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
RadioStandby( );
|
|
8007d04: f000 fac3 bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_LORA );
|
|
8007d08: 2001 movs r0, #1
|
|
8007d0a: f7ff fc51 bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8007d0e: 481c ldr r0, [pc, #112] @ (8007d80 <RadioSetTxConfig+0x210>)
|
|
8007d10: f002 f8ee bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8007d14: 481b ldr r0, [pc, #108] @ (8007d84 <RadioSetTxConfig+0x214>)
|
|
8007d16: f002 f9b9 bl 800a08c <SUBGRF_SetPacketParams>
|
|
break;
|
|
8007d1a: e012 b.n 8007d42 <RadioSetTxConfig+0x1d2>
|
|
RadioSetModem(MODEM_SIGFOX_TX);
|
|
8007d1c: 2004 movs r0, #4
|
|
8007d1e: f7ff fc47 bl 80075b0 <RadioSetModem>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK;
|
|
8007d22: 4b16 ldr r3, [pc, #88] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d24: 2202 movs r2, #2
|
|
8007d26: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate;
|
|
8007d2a: 4a14 ldr r2, [pc, #80] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d2c: 6a3b ldr r3, [r7, #32]
|
|
8007d2e: 6493 str r3, [r2, #72] @ 0x48
|
|
SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK;
|
|
8007d30: 4b12 ldr r3, [pc, #72] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d32: 2216 movs r2, #22
|
|
8007d34: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8007d38: 4811 ldr r0, [pc, #68] @ (8007d80 <RadioSetTxConfig+0x210>)
|
|
8007d3a: f002 f8d9 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
break;
|
|
8007d3e: e000 b.n 8007d42 <RadioSetTxConfig+0x1d2>
|
|
break;
|
|
8007d40: bf00 nop
|
|
}
|
|
|
|
SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power );
|
|
8007d42: f997 300e ldrsb.w r3, [r7, #14]
|
|
8007d46: 4618 mov r0, r3
|
|
8007d48: f002 fc1c bl 800a584 <SUBGRF_SetRfTxPower>
|
|
8007d4c: 4603 mov r3, r0
|
|
8007d4e: 461a mov r2, r3
|
|
8007d50: 4b0a ldr r3, [pc, #40] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d52: f883 2056 strb.w r2, [r3, #86] @ 0x56
|
|
/* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */
|
|
SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1);
|
|
8007d56: 210e movs r1, #14
|
|
8007d58: f640 101f movw r0, #2335 @ 0x91f
|
|
8007d5c: f002 fadc bl 800a318 <SUBGRF_WriteRegister>
|
|
RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect );
|
|
8007d60: 4b06 ldr r3, [pc, #24] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d62: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
8007d66: 4618 mov r0, r3
|
|
8007d68: f003 f866 bl 800ae38 <RFW_SetAntSwitch>
|
|
SubgRf.TxTimeout = timeout;
|
|
8007d6c: 4a03 ldr r2, [pc, #12] @ (8007d7c <RadioSetTxConfig+0x20c>)
|
|
8007d6e: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8007d70: 6053 str r3, [r2, #4]
|
|
}
|
|
8007d72: bf00 nop
|
|
8007d74: 3718 adds r7, #24
|
|
8007d76: 46bd mov sp, r7
|
|
8007d78: bd80 pop {r7, pc}
|
|
8007d7a: bf00 nop
|
|
8007d7c: 20000290 .word 0x20000290
|
|
8007d80: 200002c8 .word 0x200002c8
|
|
8007d84: 2000029e .word 0x2000029e
|
|
8007d88: 0800d530 .word 0x0800d530
|
|
8007d8c: 0800da6c .word 0x0800da6c
|
|
8007d90: 20000008 .word 0x20000008
|
|
|
|
08007d94 <RadioCheckRfFrequency>:
|
|
|
|
static bool RadioCheckRfFrequency( uint32_t frequency )
|
|
{
|
|
8007d94: b480 push {r7}
|
|
8007d96: b083 sub sp, #12
|
|
8007d98: af00 add r7, sp, #0
|
|
8007d9a: 6078 str r0, [r7, #4]
|
|
return true;
|
|
8007d9c: 2301 movs r3, #1
|
|
}
|
|
8007d9e: 4618 mov r0, r3
|
|
8007da0: 370c adds r7, #12
|
|
8007da2: 46bd mov sp, r7
|
|
8007da4: bc80 pop {r7}
|
|
8007da6: 4770 bx lr
|
|
|
|
08007da8 <RadioGetLoRaBandwidthInHz>:
|
|
|
|
static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw )
|
|
{
|
|
8007da8: b480 push {r7}
|
|
8007daa: b085 sub sp, #20
|
|
8007dac: af00 add r7, sp, #0
|
|
8007dae: 4603 mov r3, r0
|
|
8007db0: 71fb strb r3, [r7, #7]
|
|
uint32_t bandwidthInHz = 0;
|
|
8007db2: 2300 movs r3, #0
|
|
8007db4: 60fb str r3, [r7, #12]
|
|
|
|
switch( bw )
|
|
8007db6: 79fb ldrb r3, [r7, #7]
|
|
8007db8: 2b0a cmp r3, #10
|
|
8007dba: d83e bhi.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
8007dbc: a201 add r2, pc, #4 @ (adr r2, 8007dc4 <RadioGetLoRaBandwidthInHz+0x1c>)
|
|
8007dbe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007dc2: bf00 nop
|
|
8007dc4: 08007df1 .word 0x08007df1
|
|
8007dc8: 08007e01 .word 0x08007e01
|
|
8007dcc: 08007e11 .word 0x08007e11
|
|
8007dd0: 08007e21 .word 0x08007e21
|
|
8007dd4: 08007e29 .word 0x08007e29
|
|
8007dd8: 08007e2f .word 0x08007e2f
|
|
8007ddc: 08007e35 .word 0x08007e35
|
|
8007de0: 08007e3b .word 0x08007e3b
|
|
8007de4: 08007df9 .word 0x08007df9
|
|
8007de8: 08007e09 .word 0x08007e09
|
|
8007dec: 08007e19 .word 0x08007e19
|
|
{
|
|
case LORA_BW_007:
|
|
bandwidthInHz = 7812UL;
|
|
8007df0: f641 6384 movw r3, #7812 @ 0x1e84
|
|
8007df4: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007df6: e020 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_010:
|
|
bandwidthInHz = 10417UL;
|
|
8007df8: f642 03b1 movw r3, #10417 @ 0x28b1
|
|
8007dfc: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007dfe: e01c b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_015:
|
|
bandwidthInHz = 15625UL;
|
|
8007e00: f643 5309 movw r3, #15625 @ 0x3d09
|
|
8007e04: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e06: e018 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_020:
|
|
bandwidthInHz = 20833UL;
|
|
8007e08: f245 1361 movw r3, #20833 @ 0x5161
|
|
8007e0c: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e0e: e014 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_031:
|
|
bandwidthInHz = 31250UL;
|
|
8007e10: f647 2312 movw r3, #31250 @ 0x7a12
|
|
8007e14: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e16: e010 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_041:
|
|
bandwidthInHz = 41667UL;
|
|
8007e18: f24a 23c3 movw r3, #41667 @ 0xa2c3
|
|
8007e1c: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e1e: e00c b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_062:
|
|
bandwidthInHz = 62500UL;
|
|
8007e20: f24f 4324 movw r3, #62500 @ 0xf424
|
|
8007e24: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e26: e008 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_125:
|
|
bandwidthInHz = 125000UL;
|
|
8007e28: 4b07 ldr r3, [pc, #28] @ (8007e48 <RadioGetLoRaBandwidthInHz+0xa0>)
|
|
8007e2a: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e2c: e005 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_250:
|
|
bandwidthInHz = 250000UL;
|
|
8007e2e: 4b07 ldr r3, [pc, #28] @ (8007e4c <RadioGetLoRaBandwidthInHz+0xa4>)
|
|
8007e30: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e32: e002 b.n 8007e3a <RadioGetLoRaBandwidthInHz+0x92>
|
|
case LORA_BW_500:
|
|
bandwidthInHz = 500000UL;
|
|
8007e34: 4b06 ldr r3, [pc, #24] @ (8007e50 <RadioGetLoRaBandwidthInHz+0xa8>)
|
|
8007e36: 60fb str r3, [r7, #12]
|
|
break;
|
|
8007e38: bf00 nop
|
|
}
|
|
|
|
return bandwidthInHz;
|
|
8007e3a: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8007e3c: 4618 mov r0, r3
|
|
8007e3e: 3714 adds r7, #20
|
|
8007e40: 46bd mov sp, r7
|
|
8007e42: bc80 pop {r7}
|
|
8007e44: 4770 bx lr
|
|
8007e46: bf00 nop
|
|
8007e48: 0001e848 .word 0x0001e848
|
|
8007e4c: 0003d090 .word 0x0003d090
|
|
8007e50: 0007a120 .word 0x0007a120
|
|
|
|
08007e54 <RadioGetGfskTimeOnAirNumerator>:
|
|
|
|
static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate,
|
|
uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
|
|
bool crcOn )
|
|
{
|
|
8007e54: b480 push {r7}
|
|
8007e56: b083 sub sp, #12
|
|
8007e58: af00 add r7, sp, #0
|
|
8007e5a: 6078 str r0, [r7, #4]
|
|
8007e5c: 4608 mov r0, r1
|
|
8007e5e: 4611 mov r1, r2
|
|
8007e60: 461a mov r2, r3
|
|
8007e62: 4603 mov r3, r0
|
|
8007e64: 70fb strb r3, [r7, #3]
|
|
8007e66: 460b mov r3, r1
|
|
8007e68: 803b strh r3, [r7, #0]
|
|
8007e6a: 4613 mov r3, r2
|
|
8007e6c: 70bb strb r3, [r7, #2]
|
|
return ( preambleLen << 3 ) +
|
|
8007e6e: 883b ldrh r3, [r7, #0]
|
|
8007e70: 00db lsls r3, r3, #3
|
|
( ( fixLen == false ) ? 8 : 0 ) + 24 +
|
|
8007e72: 78ba ldrb r2, [r7, #2]
|
|
8007e74: f082 0201 eor.w r2, r2, #1
|
|
8007e78: b2d2 uxtb r2, r2
|
|
8007e7a: 2a00 cmp r2, #0
|
|
8007e7c: d001 beq.n 8007e82 <RadioGetGfskTimeOnAirNumerator+0x2e>
|
|
8007e7e: 2208 movs r2, #8
|
|
8007e80: e000 b.n 8007e84 <RadioGetGfskTimeOnAirNumerator+0x30>
|
|
8007e82: 2200 movs r2, #0
|
|
return ( preambleLen << 3 ) +
|
|
8007e84: 4413 add r3, r2
|
|
( ( fixLen == false ) ? 8 : 0 ) + 24 +
|
|
8007e86: f103 0218 add.w r2, r3, #24
|
|
( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 );
|
|
8007e8a: 7c3b ldrb r3, [r7, #16]
|
|
8007e8c: 7d39 ldrb r1, [r7, #20]
|
|
8007e8e: 2900 cmp r1, #0
|
|
8007e90: d001 beq.n 8007e96 <RadioGetGfskTimeOnAirNumerator+0x42>
|
|
8007e92: 2102 movs r1, #2
|
|
8007e94: e000 b.n 8007e98 <RadioGetGfskTimeOnAirNumerator+0x44>
|
|
8007e96: 2100 movs r1, #0
|
|
8007e98: 440b add r3, r1
|
|
8007e9a: 00db lsls r3, r3, #3
|
|
( ( fixLen == false ) ? 8 : 0 ) + 24 +
|
|
8007e9c: 4413 add r3, r2
|
|
}
|
|
8007e9e: 4618 mov r0, r3
|
|
8007ea0: 370c adds r7, #12
|
|
8007ea2: 46bd mov sp, r7
|
|
8007ea4: bc80 pop {r7}
|
|
8007ea6: 4770 bx lr
|
|
|
|
08007ea8 <RadioGetLoRaTimeOnAirNumerator>:
|
|
|
|
static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth,
|
|
uint32_t datarate, uint8_t coderate,
|
|
uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
|
|
bool crcOn )
|
|
{
|
|
8007ea8: b480 push {r7}
|
|
8007eaa: b08b sub sp, #44 @ 0x2c
|
|
8007eac: af00 add r7, sp, #0
|
|
8007eae: 60f8 str r0, [r7, #12]
|
|
8007eb0: 60b9 str r1, [r7, #8]
|
|
8007eb2: 4611 mov r1, r2
|
|
8007eb4: 461a mov r2, r3
|
|
8007eb6: 460b mov r3, r1
|
|
8007eb8: 71fb strb r3, [r7, #7]
|
|
8007eba: 4613 mov r3, r2
|
|
8007ebc: 80bb strh r3, [r7, #4]
|
|
int32_t crDenom = coderate + 4;
|
|
8007ebe: 79fb ldrb r3, [r7, #7]
|
|
8007ec0: 3304 adds r3, #4
|
|
8007ec2: 617b str r3, [r7, #20]
|
|
bool lowDatareOptimize = false;
|
|
8007ec4: 2300 movs r3, #0
|
|
8007ec6: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
// Ensure that the preamble length is at least 12 symbols when using SF5 or SF6
|
|
if( ( datarate == 5 ) || ( datarate == 6 ) )
|
|
8007eca: 68bb ldr r3, [r7, #8]
|
|
8007ecc: 2b05 cmp r3, #5
|
|
8007ece: d002 beq.n 8007ed6 <RadioGetLoRaTimeOnAirNumerator+0x2e>
|
|
8007ed0: 68bb ldr r3, [r7, #8]
|
|
8007ed2: 2b06 cmp r3, #6
|
|
8007ed4: d104 bne.n 8007ee0 <RadioGetLoRaTimeOnAirNumerator+0x38>
|
|
{
|
|
if( preambleLen < 12 )
|
|
8007ed6: 88bb ldrh r3, [r7, #4]
|
|
8007ed8: 2b0b cmp r3, #11
|
|
8007eda: d801 bhi.n 8007ee0 <RadioGetLoRaTimeOnAirNumerator+0x38>
|
|
{
|
|
preambleLen = 12;
|
|
8007edc: 230c movs r3, #12
|
|
8007ede: 80bb strh r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
|
|
8007ee0: 68fb ldr r3, [r7, #12]
|
|
8007ee2: 2b00 cmp r3, #0
|
|
8007ee4: d105 bne.n 8007ef2 <RadioGetLoRaTimeOnAirNumerator+0x4a>
|
|
8007ee6: 68bb ldr r3, [r7, #8]
|
|
8007ee8: 2b0b cmp r3, #11
|
|
8007eea: d008 beq.n 8007efe <RadioGetLoRaTimeOnAirNumerator+0x56>
|
|
8007eec: 68bb ldr r3, [r7, #8]
|
|
8007eee: 2b0c cmp r3, #12
|
|
8007ef0: d005 beq.n 8007efe <RadioGetLoRaTimeOnAirNumerator+0x56>
|
|
8007ef2: 68fb ldr r3, [r7, #12]
|
|
8007ef4: 2b01 cmp r3, #1
|
|
8007ef6: d105 bne.n 8007f04 <RadioGetLoRaTimeOnAirNumerator+0x5c>
|
|
( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
|
|
8007ef8: 68bb ldr r3, [r7, #8]
|
|
8007efa: 2b0c cmp r3, #12
|
|
8007efc: d102 bne.n 8007f04 <RadioGetLoRaTimeOnAirNumerator+0x5c>
|
|
{
|
|
lowDatareOptimize = true;
|
|
8007efe: 2301 movs r3, #1
|
|
8007f00: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
int32_t ceilDenominator;
|
|
int32_t ceilNumerator = ( payloadLen << 3 ) +
|
|
8007f04: f897 3034 ldrb.w r3, [r7, #52] @ 0x34
|
|
8007f08: 00db lsls r3, r3, #3
|
|
( crcOn ? 16 : 0 ) -
|
|
8007f0a: f897 2038 ldrb.w r2, [r7, #56] @ 0x38
|
|
8007f0e: 2a00 cmp r2, #0
|
|
8007f10: d001 beq.n 8007f16 <RadioGetLoRaTimeOnAirNumerator+0x6e>
|
|
8007f12: 2210 movs r2, #16
|
|
8007f14: e000 b.n 8007f18 <RadioGetLoRaTimeOnAirNumerator+0x70>
|
|
8007f16: 2200 movs r2, #0
|
|
int32_t ceilNumerator = ( payloadLen << 3 ) +
|
|
8007f18: 4413 add r3, r2
|
|
8007f1a: 461a mov r2, r3
|
|
( 4 * datarate ) +
|
|
8007f1c: 68bb ldr r3, [r7, #8]
|
|
8007f1e: 009b lsls r3, r3, #2
|
|
( crcOn ? 16 : 0 ) -
|
|
8007f20: 1ad3 subs r3, r2, r3
|
|
( fixLen ? 0 : 20 );
|
|
8007f22: f897 2030 ldrb.w r2, [r7, #48] @ 0x30
|
|
8007f26: 2a00 cmp r2, #0
|
|
8007f28: d001 beq.n 8007f2e <RadioGetLoRaTimeOnAirNumerator+0x86>
|
|
8007f2a: 2200 movs r2, #0
|
|
8007f2c: e000 b.n 8007f30 <RadioGetLoRaTimeOnAirNumerator+0x88>
|
|
8007f2e: 2214 movs r2, #20
|
|
( 4 * datarate ) +
|
|
8007f30: 4413 add r3, r2
|
|
int32_t ceilNumerator = ( payloadLen << 3 ) +
|
|
8007f32: 61fb str r3, [r7, #28]
|
|
|
|
if( datarate <= 6 )
|
|
8007f34: 68bb ldr r3, [r7, #8]
|
|
8007f36: 2b06 cmp r3, #6
|
|
8007f38: d803 bhi.n 8007f42 <RadioGetLoRaTimeOnAirNumerator+0x9a>
|
|
{
|
|
ceilDenominator = 4 * datarate;
|
|
8007f3a: 68bb ldr r3, [r7, #8]
|
|
8007f3c: 009b lsls r3, r3, #2
|
|
8007f3e: 623b str r3, [r7, #32]
|
|
8007f40: e00e b.n 8007f60 <RadioGetLoRaTimeOnAirNumerator+0xb8>
|
|
}
|
|
else
|
|
{
|
|
ceilNumerator += 8;
|
|
8007f42: 69fb ldr r3, [r7, #28]
|
|
8007f44: 3308 adds r3, #8
|
|
8007f46: 61fb str r3, [r7, #28]
|
|
|
|
if( lowDatareOptimize == true )
|
|
8007f48: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8007f4c: 2b00 cmp r3, #0
|
|
8007f4e: d004 beq.n 8007f5a <RadioGetLoRaTimeOnAirNumerator+0xb2>
|
|
{
|
|
ceilDenominator = 4 * ( datarate - 2 );
|
|
8007f50: 68bb ldr r3, [r7, #8]
|
|
8007f52: 3b02 subs r3, #2
|
|
8007f54: 009b lsls r3, r3, #2
|
|
8007f56: 623b str r3, [r7, #32]
|
|
8007f58: e002 b.n 8007f60 <RadioGetLoRaTimeOnAirNumerator+0xb8>
|
|
}
|
|
else
|
|
{
|
|
ceilDenominator = 4 * datarate;
|
|
8007f5a: 68bb ldr r3, [r7, #8]
|
|
8007f5c: 009b lsls r3, r3, #2
|
|
8007f5e: 623b str r3, [r7, #32]
|
|
}
|
|
}
|
|
|
|
if( ceilNumerator < 0 )
|
|
8007f60: 69fb ldr r3, [r7, #28]
|
|
8007f62: 2b00 cmp r3, #0
|
|
8007f64: da01 bge.n 8007f6a <RadioGetLoRaTimeOnAirNumerator+0xc2>
|
|
{
|
|
ceilNumerator = 0;
|
|
8007f66: 2300 movs r3, #0
|
|
8007f68: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
// Perform integral ceil()
|
|
int32_t intermediate =
|
|
( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12;
|
|
8007f6a: 69fa ldr r2, [r7, #28]
|
|
8007f6c: 6a3b ldr r3, [r7, #32]
|
|
8007f6e: 4413 add r3, r2
|
|
8007f70: 1e5a subs r2, r3, #1
|
|
8007f72: 6a3b ldr r3, [r7, #32]
|
|
8007f74: fb92 f3f3 sdiv r3, r2, r3
|
|
8007f78: 697a ldr r2, [r7, #20]
|
|
8007f7a: fb03 f202 mul.w r2, r3, r2
|
|
8007f7e: 88bb ldrh r3, [r7, #4]
|
|
8007f80: 4413 add r3, r2
|
|
int32_t intermediate =
|
|
8007f82: 330c adds r3, #12
|
|
8007f84: 61bb str r3, [r7, #24]
|
|
|
|
if( datarate <= 6 )
|
|
8007f86: 68bb ldr r3, [r7, #8]
|
|
8007f88: 2b06 cmp r3, #6
|
|
8007f8a: d802 bhi.n 8007f92 <RadioGetLoRaTimeOnAirNumerator+0xea>
|
|
{
|
|
intermediate += 2;
|
|
8007f8c: 69bb ldr r3, [r7, #24]
|
|
8007f8e: 3302 adds r3, #2
|
|
8007f90: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) );
|
|
8007f92: 69bb ldr r3, [r7, #24]
|
|
8007f94: 009b lsls r3, r3, #2
|
|
8007f96: 1c5a adds r2, r3, #1
|
|
8007f98: 68bb ldr r3, [r7, #8]
|
|
8007f9a: 3b02 subs r3, #2
|
|
8007f9c: fa02 f303 lsl.w r3, r2, r3
|
|
}
|
|
8007fa0: 4618 mov r0, r3
|
|
8007fa2: 372c adds r7, #44 @ 0x2c
|
|
8007fa4: 46bd mov sp, r7
|
|
8007fa6: bc80 pop {r7}
|
|
8007fa8: 4770 bx lr
|
|
...
|
|
|
|
08007fac <RadioTimeOnAir>:
|
|
|
|
static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth,
|
|
uint32_t datarate, uint8_t coderate,
|
|
uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
|
|
bool crcOn )
|
|
{
|
|
8007fac: b580 push {r7, lr}
|
|
8007fae: b08a sub sp, #40 @ 0x28
|
|
8007fb0: af04 add r7, sp, #16
|
|
8007fb2: 60b9 str r1, [r7, #8]
|
|
8007fb4: 607a str r2, [r7, #4]
|
|
8007fb6: 461a mov r2, r3
|
|
8007fb8: 4603 mov r3, r0
|
|
8007fba: 73fb strb r3, [r7, #15]
|
|
8007fbc: 4613 mov r3, r2
|
|
8007fbe: 73bb strb r3, [r7, #14]
|
|
uint32_t numerator = 0;
|
|
8007fc0: 2300 movs r3, #0
|
|
8007fc2: 617b str r3, [r7, #20]
|
|
uint32_t denominator = 1;
|
|
8007fc4: 2301 movs r3, #1
|
|
8007fc6: 613b str r3, [r7, #16]
|
|
|
|
switch( modem )
|
|
8007fc8: 7bfb ldrb r3, [r7, #15]
|
|
8007fca: 2b00 cmp r3, #0
|
|
8007fcc: d002 beq.n 8007fd4 <RadioTimeOnAir+0x28>
|
|
8007fce: 2b01 cmp r3, #1
|
|
8007fd0: d017 beq.n 8008002 <RadioTimeOnAir+0x56>
|
|
fixLen, payloadLen, crcOn );
|
|
denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] );
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
8007fd2: e035 b.n 8008040 <RadioTimeOnAir+0x94>
|
|
numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate,
|
|
8007fd4: f897 0024 ldrb.w r0, [r7, #36] @ 0x24
|
|
8007fd8: 8c3a ldrh r2, [r7, #32]
|
|
8007fda: 7bb9 ldrb r1, [r7, #14]
|
|
8007fdc: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
8007fe0: 9301 str r3, [sp, #4]
|
|
8007fe2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8007fe6: 9300 str r3, [sp, #0]
|
|
8007fe8: 4603 mov r3, r0
|
|
8007fea: 6878 ldr r0, [r7, #4]
|
|
8007fec: f7ff ff32 bl 8007e54 <RadioGetGfskTimeOnAirNumerator>
|
|
8007ff0: 4603 mov r3, r0
|
|
8007ff2: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8007ff6: fb02 f303 mul.w r3, r2, r3
|
|
8007ffa: 617b str r3, [r7, #20]
|
|
denominator = datarate;
|
|
8007ffc: 687b ldr r3, [r7, #4]
|
|
8007ffe: 613b str r3, [r7, #16]
|
|
break;
|
|
8008000: e01e b.n 8008040 <RadioTimeOnAir+0x94>
|
|
numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate,
|
|
8008002: 8c39 ldrh r1, [r7, #32]
|
|
8008004: 7bba ldrb r2, [r7, #14]
|
|
8008006: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
800800a: 9302 str r3, [sp, #8]
|
|
800800c: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8008010: 9301 str r3, [sp, #4]
|
|
8008012: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8008016: 9300 str r3, [sp, #0]
|
|
8008018: 460b mov r3, r1
|
|
800801a: 6879 ldr r1, [r7, #4]
|
|
800801c: 68b8 ldr r0, [r7, #8]
|
|
800801e: f7ff ff43 bl 8007ea8 <RadioGetLoRaTimeOnAirNumerator>
|
|
8008022: 4603 mov r3, r0
|
|
8008024: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8008028: fb02 f303 mul.w r3, r2, r3
|
|
800802c: 617b str r3, [r7, #20]
|
|
denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] );
|
|
800802e: 4a0a ldr r2, [pc, #40] @ (8008058 <RadioTimeOnAir+0xac>)
|
|
8008030: 68bb ldr r3, [r7, #8]
|
|
8008032: 4413 add r3, r2
|
|
8008034: 781b ldrb r3, [r3, #0]
|
|
8008036: 4618 mov r0, r3
|
|
8008038: f7ff feb6 bl 8007da8 <RadioGetLoRaBandwidthInHz>
|
|
800803c: 6138 str r0, [r7, #16]
|
|
break;
|
|
800803e: bf00 nop
|
|
}
|
|
// Perform integral ceil()
|
|
return DIVC( numerator, denominator );
|
|
8008040: 697a ldr r2, [r7, #20]
|
|
8008042: 693b ldr r3, [r7, #16]
|
|
8008044: 4413 add r3, r2
|
|
8008046: 1e5a subs r2, r3, #1
|
|
8008048: 693b ldr r3, [r7, #16]
|
|
800804a: fbb2 f3f3 udiv r3, r2, r3
|
|
}
|
|
800804e: 4618 mov r0, r3
|
|
8008050: 3718 adds r7, #24
|
|
8008052: 46bd mov sp, r7
|
|
8008054: bd80 pop {r7, pc}
|
|
8008056: bf00 nop
|
|
8008058: 0800da6c .word 0x0800da6c
|
|
|
|
0800805c <RadioSend>:
|
|
|
|
static radio_status_t RadioSend( uint8_t *buffer, uint8_t size )
|
|
{
|
|
800805c: b580 push {r7, lr}
|
|
800805e: b084 sub sp, #16
|
|
8008060: af00 add r7, sp, #0
|
|
8008062: 6078 str r0, [r7, #4]
|
|
8008064: 460b mov r3, r1
|
|
8008066: 70fb strb r3, [r7, #3]
|
|
SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG,
|
|
8008068: 2300 movs r3, #0
|
|
800806a: 2200 movs r2, #0
|
|
800806c: f240 2101 movw r1, #513 @ 0x201
|
|
8008070: f240 2001 movw r0, #513 @ 0x201
|
|
8008074: f001 fda6 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
|
|
/* Set DBG pin */
|
|
DBG_GPIO_RADIO_TX( SET );
|
|
8008078: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
800807c: 4874 ldr r0, [pc, #464] @ (8008250 <RadioSend+0x1f4>)
|
|
800807e: f7ff fa09 bl 8007494 <LL_GPIO_SetOutputPin>
|
|
|
|
/* Set RF switch */
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX );
|
|
8008082: 4b74 ldr r3, [pc, #464] @ (8008254 <RadioSend+0x1f8>)
|
|
8008084: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
8008088: 2101 movs r1, #1
|
|
800808a: 4618 mov r0, r3
|
|
800808c: f002 fa52 bl 800a534 <SUBGRF_SetSwitch>
|
|
/* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/
|
|
/* RegTxModulation = @address 0x0889 */
|
|
if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) )
|
|
8008090: 4b70 ldr r3, [pc, #448] @ (8008254 <RadioSend+0x1f8>)
|
|
8008092: 781b ldrb r3, [r3, #0]
|
|
8008094: 2b01 cmp r3, #1
|
|
8008096: d112 bne.n 80080be <RadioSend+0x62>
|
|
8008098: 4b6e ldr r3, [pc, #440] @ (8008254 <RadioSend+0x1f8>)
|
|
800809a: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
800809e: 2b06 cmp r3, #6
|
|
80080a0: d10d bne.n 80080be <RadioSend+0x62>
|
|
{
|
|
SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) );
|
|
80080a2: f640 0089 movw r0, #2185 @ 0x889
|
|
80080a6: f002 f959 bl 800a35c <SUBGRF_ReadRegister>
|
|
80080aa: 4603 mov r3, r0
|
|
80080ac: f023 0304 bic.w r3, r3, #4
|
|
80080b0: b2db uxtb r3, r3
|
|
80080b2: 4619 mov r1, r3
|
|
80080b4: f640 0089 movw r0, #2185 @ 0x889
|
|
80080b8: f002 f92e bl 800a318 <SUBGRF_WriteRegister>
|
|
80080bc: e00c b.n 80080d8 <RadioSend+0x7c>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) );
|
|
80080be: f640 0089 movw r0, #2185 @ 0x889
|
|
80080c2: f002 f94b bl 800a35c <SUBGRF_ReadRegister>
|
|
80080c6: 4603 mov r3, r0
|
|
80080c8: f043 0304 orr.w r3, r3, #4
|
|
80080cc: b2db uxtb r3, r3
|
|
80080ce: 4619 mov r1, r3
|
|
80080d0: f640 0089 movw r0, #2185 @ 0x889
|
|
80080d4: f002 f920 bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
else
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
{
|
|
/* WORKAROUND END */
|
|
switch( SubgRf.Modem )
|
|
80080d8: 4b5e ldr r3, [pc, #376] @ (8008254 <RadioSend+0x1f8>)
|
|
80080da: 781b ldrb r3, [r3, #0]
|
|
80080dc: 2b04 cmp r3, #4
|
|
80080de: f200 80a7 bhi.w 8008230 <RadioSend+0x1d4>
|
|
80080e2: a201 add r2, pc, #4 @ (adr r2, 80080e8 <RadioSend+0x8c>)
|
|
80080e4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80080e8: 08008117 .word 0x08008117
|
|
80080ec: 080080fd .word 0x080080fd
|
|
80080f0: 08008117 .word 0x08008117
|
|
80080f4: 08008179 .word 0x08008179
|
|
80080f8: 08008199 .word 0x08008199
|
|
{
|
|
case MODEM_LORA:
|
|
{
|
|
SubgRf.PacketParams.Params.LoRa.PayloadLength = size;
|
|
80080fc: 4a55 ldr r2, [pc, #340] @ (8008254 <RadioSend+0x1f8>)
|
|
80080fe: 78fb ldrb r3, [r7, #3]
|
|
8008100: 77d3 strb r3, [r2, #31]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008102: 4855 ldr r0, [pc, #340] @ (8008258 <RadioSend+0x1fc>)
|
|
8008104: f001 ffc2 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SendPayload( buffer, size, 0 );
|
|
8008108: 78fb ldrb r3, [r7, #3]
|
|
800810a: 2200 movs r2, #0
|
|
800810c: 4619 mov r1, r3
|
|
800810e: 6878 ldr r0, [r7, #4]
|
|
8008110: f001 fa6e bl 80095f0 <SUBGRF_SendPayload>
|
|
break;
|
|
8008114: e08d b.n 8008232 <RadioSend+0x1d6>
|
|
}
|
|
case MODEM_MSK:
|
|
case MODEM_FSK:
|
|
{
|
|
if ( 1UL == RFW_Is_Init( ) )
|
|
8008116: f002 fe7b bl 800ae10 <RFW_Is_Init>
|
|
800811a: 4603 mov r3, r0
|
|
800811c: 2b01 cmp r3, #1
|
|
800811e: d11e bne.n 800815e <RadioSend+0x102>
|
|
{
|
|
uint8_t outsize;
|
|
if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) )
|
|
8008120: f107 020d add.w r2, r7, #13
|
|
8008124: 78fb ldrb r3, [r7, #3]
|
|
8008126: 4619 mov r1, r3
|
|
8008128: 6878 ldr r0, [r7, #4]
|
|
800812a: f002 fe95 bl 800ae58 <RFW_TransmitInit>
|
|
800812e: 4603 mov r3, r0
|
|
8008130: 2b00 cmp r3, #0
|
|
8008132: d10c bne.n 800814e <RadioSend+0xf2>
|
|
{
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize;
|
|
8008134: 7b7a ldrb r2, [r7, #13]
|
|
8008136: 4b47 ldr r3, [pc, #284] @ (8008254 <RadioSend+0x1f8>)
|
|
8008138: 759a strb r2, [r3, #22]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
800813a: 4847 ldr r0, [pc, #284] @ (8008258 <RadioSend+0x1fc>)
|
|
800813c: f001 ffa6 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SendPayload( buffer, outsize, 0 );
|
|
8008140: 7b7b ldrb r3, [r7, #13]
|
|
8008142: 2200 movs r2, #0
|
|
8008144: 4619 mov r1, r3
|
|
8008146: 6878 ldr r0, [r7, #4]
|
|
8008148: f001 fa52 bl 80095f0 <SUBGRF_SendPayload>
|
|
{
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = size;
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
SUBGRF_SendPayload( buffer, size, 0 );
|
|
}
|
|
break;
|
|
800814c: e071 b.n 8008232 <RadioSend+0x1d6>
|
|
MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" );
|
|
800814e: 4b43 ldr r3, [pc, #268] @ (800825c <RadioSend+0x200>)
|
|
8008150: 2201 movs r2, #1
|
|
8008152: 2100 movs r1, #0
|
|
8008154: 2002 movs r0, #2
|
|
8008156: f004 ff15 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
return RADIO_STATUS_ERROR;
|
|
800815a: 2303 movs r3, #3
|
|
800815c: e073 b.n 8008246 <RadioSend+0x1ea>
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = size;
|
|
800815e: 4a3d ldr r2, [pc, #244] @ (8008254 <RadioSend+0x1f8>)
|
|
8008160: 78fb ldrb r3, [r7, #3]
|
|
8008162: 7593 strb r3, [r2, #22]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008164: 483c ldr r0, [pc, #240] @ (8008258 <RadioSend+0x1fc>)
|
|
8008166: f001 ff91 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SendPayload( buffer, size, 0 );
|
|
800816a: 78fb ldrb r3, [r7, #3]
|
|
800816c: 2200 movs r2, #0
|
|
800816e: 4619 mov r1, r3
|
|
8008170: 6878 ldr r0, [r7, #4]
|
|
8008172: f001 fa3d bl 80095f0 <SUBGRF_SendPayload>
|
|
break;
|
|
8008176: e05c b.n 8008232 <RadioSend+0x1d6>
|
|
}
|
|
case MODEM_BPSK:
|
|
{
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK;
|
|
8008178: 4b36 ldr r3, [pc, #216] @ (8008254 <RadioSend+0x1f8>)
|
|
800817a: 2202 movs r2, #2
|
|
800817c: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Bpsk.PayloadLength = size;
|
|
800817e: 4a35 ldr r2, [pc, #212] @ (8008254 <RadioSend+0x1f8>)
|
|
8008180: 78fb ldrb r3, [r7, #3]
|
|
8008182: 7693 strb r3, [r2, #26]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008184: 4834 ldr r0, [pc, #208] @ (8008258 <RadioSend+0x1fc>)
|
|
8008186: f001 ff81 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SendPayload( buffer, size, 0 );
|
|
800818a: 78fb ldrb r3, [r7, #3]
|
|
800818c: 2200 movs r2, #0
|
|
800818e: 4619 mov r1, r3
|
|
8008190: 6878 ldr r0, [r7, #4]
|
|
8008192: f001 fa2d bl 80095f0 <SUBGRF_SendPayload>
|
|
break;
|
|
8008196: e04c b.n 8008232 <RadioSend+0x1d6>
|
|
case MODEM_SIGFOX_TX:
|
|
{
|
|
/* from bpsk to dbpsk */
|
|
/* first 1 bit duplicated */
|
|
/* RadioBuffer is 1 bytes more */
|
|
payload_integration( RadioBuffer, buffer, size );
|
|
8008198: 78fb ldrb r3, [r7, #3]
|
|
800819a: 461a mov r2, r3
|
|
800819c: 6879 ldr r1, [r7, #4]
|
|
800819e: 4830 ldr r0, [pc, #192] @ (8008260 <RadioSend+0x204>)
|
|
80081a0: f000 fcfa bl 8008b98 <payload_integration>
|
|
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK;
|
|
80081a4: 4b2b ldr r3, [pc, #172] @ (8008254 <RadioSend+0x1f8>)
|
|
80081a6: 2202 movs r2, #2
|
|
80081a8: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1;
|
|
80081aa: 78fb ldrb r3, [r7, #3]
|
|
80081ac: 3301 adds r3, #1
|
|
80081ae: b2da uxtb r2, r3
|
|
80081b0: 4b28 ldr r3, [pc, #160] @ (8008254 <RadioSend+0x1f8>)
|
|
80081b2: 769a strb r2, [r3, #26]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
80081b4: 4828 ldr r0, [pc, #160] @ (8008258 <RadioSend+0x1fc>)
|
|
80081b6: f001 ff69 bl 800a08c <SUBGRF_SetPacketParams>
|
|
|
|
RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB
|
|
80081ba: 2100 movs r1, #0
|
|
80081bc: 20f1 movs r0, #241 @ 0xf1
|
|
80081be: f000 f973 bl 80084a8 <RadioWrite>
|
|
RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB
|
|
80081c2: 2100 movs r1, #0
|
|
80081c4: 20f0 movs r0, #240 @ 0xf0
|
|
80081c6: f000 f96f bl 80084a8 <RadioWrite>
|
|
if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 )
|
|
80081ca: 4b22 ldr r3, [pc, #136] @ (8008254 <RadioSend+0x1f8>)
|
|
80081cc: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80081ce: 2b64 cmp r3, #100 @ 0x64
|
|
80081d0: d108 bne.n 80081e4 <RadioSend+0x188>
|
|
{
|
|
RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB
|
|
80081d2: 2170 movs r1, #112 @ 0x70
|
|
80081d4: 20f3 movs r0, #243 @ 0xf3
|
|
80081d6: f000 f967 bl 80084a8 <RadioWrite>
|
|
RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB
|
|
80081da: 211d movs r1, #29
|
|
80081dc: 20f2 movs r0, #242 @ 0xf2
|
|
80081de: f000 f963 bl 80084a8 <RadioWrite>
|
|
80081e2: e007 b.n 80081f4 <RadioSend+0x198>
|
|
}
|
|
else // 600 bps
|
|
{
|
|
RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB
|
|
80081e4: 21e1 movs r1, #225 @ 0xe1
|
|
80081e6: 20f3 movs r0, #243 @ 0xf3
|
|
80081e8: f000 f95e bl 80084a8 <RadioWrite>
|
|
RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB
|
|
80081ec: 2104 movs r1, #4
|
|
80081ee: 20f2 movs r0, #242 @ 0xf2
|
|
80081f0: f000 f95a bl 80084a8 <RadioWrite>
|
|
}
|
|
|
|
uint16_t bitNum = ( size * 8 ) + 2;
|
|
80081f4: 78fb ldrb r3, [r7, #3]
|
|
80081f6: b29b uxth r3, r3
|
|
80081f8: 00db lsls r3, r3, #3
|
|
80081fa: b29b uxth r3, r3
|
|
80081fc: 3302 adds r3, #2
|
|
80081fe: 81fb strh r3, [r7, #14]
|
|
RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame
|
|
8008200: 89fb ldrh r3, [r7, #14]
|
|
8008202: 0a1b lsrs r3, r3, #8
|
|
8008204: b29b uxth r3, r3
|
|
8008206: b2db uxtb r3, r3
|
|
8008208: 4619 mov r1, r3
|
|
800820a: 20f4 movs r0, #244 @ 0xf4
|
|
800820c: f000 f94c bl 80084a8 <RadioWrite>
|
|
RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame
|
|
8008210: 89fb ldrh r3, [r7, #14]
|
|
8008212: b2db uxtb r3, r3
|
|
8008214: 4619 mov r1, r3
|
|
8008216: 20f5 movs r0, #245 @ 0xf5
|
|
8008218: f000 f946 bl 80084a8 <RadioWrite>
|
|
SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF );
|
|
800821c: 78fb ldrb r3, [r7, #3]
|
|
800821e: 3301 adds r3, #1
|
|
8008220: b2db uxtb r3, r3
|
|
8008222: f06f 427f mvn.w r2, #4278190080 @ 0xff000000
|
|
8008226: 4619 mov r1, r3
|
|
8008228: 480d ldr r0, [pc, #52] @ (8008260 <RadioSend+0x204>)
|
|
800822a: f001 f9e1 bl 80095f0 <SUBGRF_SendPayload>
|
|
break;
|
|
800822e: e000 b.n 8008232 <RadioSend+0x1d6>
|
|
}
|
|
#endif /*RADIO_SIGFOX_ENABLE == 1*/
|
|
default:
|
|
break;
|
|
8008230: bf00 nop
|
|
}
|
|
|
|
TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout );
|
|
8008232: 4b08 ldr r3, [pc, #32] @ (8008254 <RadioSend+0x1f8>)
|
|
8008234: 685b ldr r3, [r3, #4]
|
|
8008236: 4619 mov r1, r3
|
|
8008238: 480a ldr r0, [pc, #40] @ (8008264 <RadioSend+0x208>)
|
|
800823a: f004 fd1b bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &TxTimeoutTimer );
|
|
800823e: 4809 ldr r0, [pc, #36] @ (8008264 <RadioSend+0x208>)
|
|
8008240: f004 fc3a bl 800cab8 <UTIL_TIMER_Start>
|
|
}
|
|
|
|
return RADIO_STATUS_OK;
|
|
8008244: 2300 movs r3, #0
|
|
}
|
|
8008246: 4618 mov r0, r3
|
|
8008248: 3710 adds r7, #16
|
|
800824a: 46bd mov sp, r7
|
|
800824c: bd80 pop {r7, pc}
|
|
800824e: bf00 nop
|
|
8008250: 48000400 .word 0x48000400
|
|
8008254: 20000290 .word 0x20000290
|
|
8008258: 2000029e .word 0x2000029e
|
|
800825c: 0800d538 .word 0x0800d538
|
|
8008260: 2000018c .word 0x2000018c
|
|
8008264: 200002ec .word 0x200002ec
|
|
|
|
08008268 <RadioSleep>:
|
|
|
|
static void RadioSleep( void )
|
|
{
|
|
8008268: b580 push {r7, lr}
|
|
800826a: b082 sub sp, #8
|
|
800826c: af00 add r7, sp, #0
|
|
SleepParams_t params = { 0 };
|
|
800826e: 2300 movs r3, #0
|
|
8008270: 713b strb r3, [r7, #4]
|
|
|
|
params.Fields.WarmStart = 1;
|
|
8008272: 793b ldrb r3, [r7, #4]
|
|
8008274: f043 0304 orr.w r3, r3, #4
|
|
8008278: 713b strb r3, [r7, #4]
|
|
SUBGRF_SetSleep( params );
|
|
800827a: 7938 ldrb r0, [r7, #4]
|
|
800827c: f001 fa94 bl 80097a8 <SUBGRF_SetSleep>
|
|
|
|
RADIO_DELAY_MS( 2 );
|
|
8008280: 2002 movs r0, #2
|
|
8008282: f7f8 fc91 bl 8000ba8 <HAL_Delay>
|
|
}
|
|
8008286: bf00 nop
|
|
8008288: 3708 adds r7, #8
|
|
800828a: 46bd mov sp, r7
|
|
800828c: bd80 pop {r7, pc}
|
|
|
|
0800828e <RadioStandby>:
|
|
|
|
static void RadioStandby( void )
|
|
{
|
|
800828e: b580 push {r7, lr}
|
|
8008290: af00 add r7, sp, #0
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
8008292: 2000 movs r0, #0
|
|
8008294: f001 fabc bl 8009810 <SUBGRF_SetStandby>
|
|
}
|
|
8008298: bf00 nop
|
|
800829a: bd80 pop {r7, pc}
|
|
|
|
0800829c <RadioRx>:
|
|
|
|
static void RadioRx( uint32_t timeout )
|
|
{
|
|
800829c: b580 push {r7, lr}
|
|
800829e: b082 sub sp, #8
|
|
80082a0: af00 add r7, sp, #0
|
|
80082a2: 6078 str r0, [r7, #4]
|
|
if( SubgRf.lr_fhss.is_lr_fhss_on == true )
|
|
{
|
|
//return LORAMAC_RADIO_STATUS_ERROR;
|
|
}
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
if( 1UL == RFW_Is_Init( ) )
|
|
80082a4: f002 fdb4 bl 800ae10 <RFW_Is_Init>
|
|
80082a8: 4603 mov r3, r0
|
|
80082aa: 2b01 cmp r3, #1
|
|
80082ac: d102 bne.n 80082b4 <RadioRx+0x18>
|
|
{
|
|
RFW_ReceiveInit( );
|
|
80082ae: f002 fe59 bl 800af64 <RFW_ReceiveInit>
|
|
80082b2: e007 b.n 80082c4 <RadioRx+0x28>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG,
|
|
80082b4: 2300 movs r3, #0
|
|
80082b6: 2200 movs r2, #0
|
|
80082b8: f240 2162 movw r1, #610 @ 0x262
|
|
80082bc: f240 2062 movw r0, #610 @ 0x262
|
|
80082c0: f001 fc80 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
}
|
|
|
|
if( timeout != 0 )
|
|
80082c4: 687b ldr r3, [r7, #4]
|
|
80082c6: 2b00 cmp r3, #0
|
|
80082c8: d006 beq.n 80082d8 <RadioRx+0x3c>
|
|
{
|
|
TimerSetValue( &RxTimeoutTimer, timeout );
|
|
80082ca: 6879 ldr r1, [r7, #4]
|
|
80082cc: 4813 ldr r0, [pc, #76] @ (800831c <RadioRx+0x80>)
|
|
80082ce: f004 fcd1 bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RxTimeoutTimer );
|
|
80082d2: 4812 ldr r0, [pc, #72] @ (800831c <RadioRx+0x80>)
|
|
80082d4: f004 fbf0 bl 800cab8 <UTIL_TIMER_Start>
|
|
}
|
|
/* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/
|
|
SubgRf.RxDcPreambleDetectTimeout = 0;
|
|
80082d8: 4b11 ldr r3, [pc, #68] @ (8008320 <RadioRx+0x84>)
|
|
80082da: 2200 movs r2, #0
|
|
80082dc: 659a str r2, [r3, #88] @ 0x58
|
|
/* Set DBG pin */
|
|
DBG_GPIO_RADIO_RX( SET );
|
|
80082de: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
80082e2: 4810 ldr r0, [pc, #64] @ (8008324 <RadioRx+0x88>)
|
|
80082e4: f7ff f8d6 bl 8007494 <LL_GPIO_SetOutputPin>
|
|
/* RF switch configuration */
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX );
|
|
80082e8: 4b0d ldr r3, [pc, #52] @ (8008320 <RadioRx+0x84>)
|
|
80082ea: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
80082ee: 2100 movs r1, #0
|
|
80082f0: 4618 mov r0, r3
|
|
80082f2: f002 f91f bl 800a534 <SUBGRF_SetSwitch>
|
|
|
|
if( SubgRf.RxContinuous == true )
|
|
80082f6: 4b0a ldr r3, [pc, #40] @ (8008320 <RadioRx+0x84>)
|
|
80082f8: 785b ldrb r3, [r3, #1]
|
|
80082fa: 2b00 cmp r3, #0
|
|
80082fc: d004 beq.n 8008308 <RadioRx+0x6c>
|
|
{
|
|
SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous
|
|
80082fe: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
|
|
8008302: f001 fac1 bl 8009888 <SUBGRF_SetRx>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_SetRx( SubgRf.RxTimeout << 6 );
|
|
}
|
|
}
|
|
8008306: e005 b.n 8008314 <RadioRx+0x78>
|
|
SUBGRF_SetRx( SubgRf.RxTimeout << 6 );
|
|
8008308: 4b05 ldr r3, [pc, #20] @ (8008320 <RadioRx+0x84>)
|
|
800830a: 689b ldr r3, [r3, #8]
|
|
800830c: 019b lsls r3, r3, #6
|
|
800830e: 4618 mov r0, r3
|
|
8008310: f001 faba bl 8009888 <SUBGRF_SetRx>
|
|
}
|
|
8008314: bf00 nop
|
|
8008316: 3708 adds r7, #8
|
|
8008318: 46bd mov sp, r7
|
|
800831a: bd80 pop {r7, pc}
|
|
800831c: 20000304 .word 0x20000304
|
|
8008320: 20000290 .word 0x20000290
|
|
8008324: 48000400 .word 0x48000400
|
|
|
|
08008328 <RadioRxBoosted>:
|
|
|
|
static void RadioRxBoosted( uint32_t timeout )
|
|
{
|
|
8008328: b580 push {r7, lr}
|
|
800832a: b082 sub sp, #8
|
|
800832c: af00 add r7, sp, #0
|
|
800832e: 6078 str r0, [r7, #4]
|
|
if( SubgRf.lr_fhss.is_lr_fhss_on == true )
|
|
{
|
|
//return LORAMAC_RADIO_STATUS_ERROR;
|
|
}
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
if( 1UL == RFW_Is_Init() )
|
|
8008330: f002 fd6e bl 800ae10 <RFW_Is_Init>
|
|
8008334: 4603 mov r3, r0
|
|
8008336: 2b01 cmp r3, #1
|
|
8008338: d102 bne.n 8008340 <RadioRxBoosted+0x18>
|
|
{
|
|
RFW_ReceiveInit();
|
|
800833a: f002 fe13 bl 800af64 <RFW_ReceiveInit>
|
|
800833e: e007 b.n 8008350 <RadioRxBoosted+0x28>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG,
|
|
8008340: 2300 movs r3, #0
|
|
8008342: 2200 movs r2, #0
|
|
8008344: f240 2162 movw r1, #610 @ 0x262
|
|
8008348: f240 2062 movw r0, #610 @ 0x262
|
|
800834c: f001 fc3a bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
}
|
|
if( timeout != 0 )
|
|
8008350: 687b ldr r3, [r7, #4]
|
|
8008352: 2b00 cmp r3, #0
|
|
8008354: d006 beq.n 8008364 <RadioRxBoosted+0x3c>
|
|
{
|
|
TimerSetValue( &RxTimeoutTimer, timeout );
|
|
8008356: 6879 ldr r1, [r7, #4]
|
|
8008358: 4813 ldr r0, [pc, #76] @ (80083a8 <RadioRxBoosted+0x80>)
|
|
800835a: f004 fc8b bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RxTimeoutTimer );
|
|
800835e: 4812 ldr r0, [pc, #72] @ (80083a8 <RadioRxBoosted+0x80>)
|
|
8008360: f004 fbaa bl 800cab8 <UTIL_TIMER_Start>
|
|
}
|
|
/* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/
|
|
SubgRf.RxDcPreambleDetectTimeout = 0;
|
|
8008364: 4b11 ldr r3, [pc, #68] @ (80083ac <RadioRxBoosted+0x84>)
|
|
8008366: 2200 movs r2, #0
|
|
8008368: 659a str r2, [r3, #88] @ 0x58
|
|
/* Set DBG pin */
|
|
DBG_GPIO_RADIO_RX( SET );
|
|
800836a: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
800836e: 4810 ldr r0, [pc, #64] @ (80083b0 <RadioRxBoosted+0x88>)
|
|
8008370: f7ff f890 bl 8007494 <LL_GPIO_SetOutputPin>
|
|
/* RF switch configuration */
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX );
|
|
8008374: 4b0d ldr r3, [pc, #52] @ (80083ac <RadioRxBoosted+0x84>)
|
|
8008376: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
800837a: 2100 movs r1, #0
|
|
800837c: 4618 mov r0, r3
|
|
800837e: f002 f8d9 bl 800a534 <SUBGRF_SetSwitch>
|
|
|
|
if( SubgRf.RxContinuous == true )
|
|
8008382: 4b0a ldr r3, [pc, #40] @ (80083ac <RadioRxBoosted+0x84>)
|
|
8008384: 785b ldrb r3, [r3, #1]
|
|
8008386: 2b00 cmp r3, #0
|
|
8008388: d004 beq.n 8008394 <RadioRxBoosted+0x6c>
|
|
{
|
|
SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous
|
|
800838a: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
|
|
800838e: f001 fa9b bl 80098c8 <SUBGRF_SetRxBoosted>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 );
|
|
}
|
|
}
|
|
8008392: e005 b.n 80083a0 <RadioRxBoosted+0x78>
|
|
SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 );
|
|
8008394: 4b05 ldr r3, [pc, #20] @ (80083ac <RadioRxBoosted+0x84>)
|
|
8008396: 689b ldr r3, [r3, #8]
|
|
8008398: 019b lsls r3, r3, #6
|
|
800839a: 4618 mov r0, r3
|
|
800839c: f001 fa94 bl 80098c8 <SUBGRF_SetRxBoosted>
|
|
}
|
|
80083a0: bf00 nop
|
|
80083a2: 3708 adds r7, #8
|
|
80083a4: 46bd mov sp, r7
|
|
80083a6: bd80 pop {r7, pc}
|
|
80083a8: 20000304 .word 0x20000304
|
|
80083ac: 20000290 .word 0x20000290
|
|
80083b0: 48000400 .word 0x48000400
|
|
|
|
080083b4 <RadioSetRxDutyCycle>:
|
|
|
|
static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime )
|
|
{
|
|
80083b4: b580 push {r7, lr}
|
|
80083b6: b082 sub sp, #8
|
|
80083b8: af00 add r7, sp, #0
|
|
80083ba: 6078 str r0, [r7, #4]
|
|
80083bc: 6039 str r1, [r7, #0]
|
|
/*See STM32WL Errata: RadioSetRxDutyCycle*/
|
|
SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime;
|
|
80083be: 687b ldr r3, [r7, #4]
|
|
80083c0: 005a lsls r2, r3, #1
|
|
80083c2: 683b ldr r3, [r7, #0]
|
|
80083c4: 4413 add r3, r2
|
|
80083c6: 4a0c ldr r2, [pc, #48] @ (80083f8 <RadioSetRxDutyCycle+0x44>)
|
|
80083c8: 6593 str r3, [r2, #88] @ 0x58
|
|
/*Enable also the IRQ_PREAMBLE_DETECTED*/
|
|
SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE );
|
|
80083ca: 2300 movs r3, #0
|
|
80083cc: 2200 movs r2, #0
|
|
80083ce: f64f 71ff movw r1, #65535 @ 0xffff
|
|
80083d2: f64f 70ff movw r0, #65535 @ 0xffff
|
|
80083d6: f001 fbf5 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
/* RF switch configuration */
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX );
|
|
80083da: 4b07 ldr r3, [pc, #28] @ (80083f8 <RadioSetRxDutyCycle+0x44>)
|
|
80083dc: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
80083e0: 2100 movs r1, #0
|
|
80083e2: 4618 mov r0, r3
|
|
80083e4: f002 f8a6 bl 800a534 <SUBGRF_SetSwitch>
|
|
/* Start Rx DutyCycle*/
|
|
SUBGRF_SetRxDutyCycle( rxTime, sleepTime );
|
|
80083e8: 6839 ldr r1, [r7, #0]
|
|
80083ea: 6878 ldr r0, [r7, #4]
|
|
80083ec: f001 fa90 bl 8009910 <SUBGRF_SetRxDutyCycle>
|
|
}
|
|
80083f0: bf00 nop
|
|
80083f2: 3708 adds r7, #8
|
|
80083f4: 46bd mov sp, r7
|
|
80083f6: bd80 pop {r7, pc}
|
|
80083f8: 20000290 .word 0x20000290
|
|
|
|
080083fc <RadioStartCad>:
|
|
|
|
static void RadioStartCad( void )
|
|
{
|
|
80083fc: b580 push {r7, lr}
|
|
80083fe: af00 add r7, sp, #0
|
|
/* RF switch configuration */
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX );
|
|
8008400: 4b09 ldr r3, [pc, #36] @ (8008428 <RadioStartCad+0x2c>)
|
|
8008402: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
8008406: 2100 movs r1, #0
|
|
8008408: 4618 mov r0, r3
|
|
800840a: f002 f893 bl 800a534 <SUBGRF_SetSwitch>
|
|
|
|
SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED,
|
|
800840e: 2300 movs r3, #0
|
|
8008410: 2200 movs r2, #0
|
|
8008412: f44f 71c0 mov.w r1, #384 @ 0x180
|
|
8008416: f44f 70c0 mov.w r0, #384 @ 0x180
|
|
800841a: f001 fbd3 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_CAD_CLEAR | IRQ_CAD_DETECTED,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
SUBGRF_SetCad( );
|
|
800841e: f001 faa3 bl 8009968 <SUBGRF_SetCad>
|
|
}
|
|
8008422: bf00 nop
|
|
8008424: bd80 pop {r7, pc}
|
|
8008426: bf00 nop
|
|
8008428: 20000290 .word 0x20000290
|
|
|
|
0800842c <RadioSetTxContinuousWave>:
|
|
|
|
static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
|
|
{
|
|
800842c: b580 push {r7, lr}
|
|
800842e: b084 sub sp, #16
|
|
8008430: af00 add r7, sp, #0
|
|
8008432: 6078 str r0, [r7, #4]
|
|
8008434: 460b mov r3, r1
|
|
8008436: 70fb strb r3, [r7, #3]
|
|
8008438: 4613 mov r3, r2
|
|
800843a: 803b strh r3, [r7, #0]
|
|
if( SubgRf.lr_fhss.is_lr_fhss_on == true )
|
|
{
|
|
//return LORAMAC_RADIO_STATUS_ERROR;
|
|
}
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
uint32_t timeout = ( uint32_t )time * 1000;
|
|
800843c: 883b ldrh r3, [r7, #0]
|
|
800843e: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8008442: fb02 f303 mul.w r3, r2, r3
|
|
8008446: 60fb str r3, [r7, #12]
|
|
uint8_t antswitchpow;
|
|
|
|
SUBGRF_SetRfFrequency( freq );
|
|
8008448: 6878 ldr r0, [r7, #4]
|
|
800844a: f001 fc17 bl 8009c7c <SUBGRF_SetRfFrequency>
|
|
|
|
antswitchpow = SUBGRF_SetRfTxPower( power );
|
|
800844e: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8008452: 4618 mov r0, r3
|
|
8008454: f002 f896 bl 800a584 <SUBGRF_SetRfTxPower>
|
|
8008458: 4603 mov r3, r0
|
|
800845a: 72fb strb r3, [r7, #11]
|
|
|
|
/* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */
|
|
SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1);
|
|
800845c: 210e movs r1, #14
|
|
800845e: f640 101f movw r0, #2335 @ 0x91f
|
|
8008462: f001 ff59 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
/* Set RF switch */
|
|
SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX );
|
|
8008466: 7afb ldrb r3, [r7, #11]
|
|
8008468: 2101 movs r1, #1
|
|
800846a: 4618 mov r0, r3
|
|
800846c: f002 f862 bl 800a534 <SUBGRF_SetSwitch>
|
|
|
|
SUBGRF_SetTxContinuousWave( );
|
|
8008470: f001 fa88 bl 8009984 <SUBGRF_SetTxContinuousWave>
|
|
|
|
TimerSetValue( &TxTimeoutTimer, timeout );
|
|
8008474: 68f9 ldr r1, [r7, #12]
|
|
8008476: 4805 ldr r0, [pc, #20] @ (800848c <RadioSetTxContinuousWave+0x60>)
|
|
8008478: f004 fbfc bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &TxTimeoutTimer );
|
|
800847c: 4803 ldr r0, [pc, #12] @ (800848c <RadioSetTxContinuousWave+0x60>)
|
|
800847e: f004 fb1b bl 800cab8 <UTIL_TIMER_Start>
|
|
}
|
|
8008482: bf00 nop
|
|
8008484: 3710 adds r7, #16
|
|
8008486: 46bd mov sp, r7
|
|
8008488: bd80 pop {r7, pc}
|
|
800848a: bf00 nop
|
|
800848c: 200002ec .word 0x200002ec
|
|
|
|
08008490 <RadioRssi>:
|
|
|
|
static int16_t RadioRssi( RadioModems_t modem )
|
|
{
|
|
8008490: b580 push {r7, lr}
|
|
8008492: b082 sub sp, #8
|
|
8008494: af00 add r7, sp, #0
|
|
8008496: 4603 mov r3, r0
|
|
8008498: 71fb strb r3, [r7, #7]
|
|
return SUBGRF_GetRssiInst( );
|
|
800849a: f001 feaa bl 800a1f2 <SUBGRF_GetRssiInst>
|
|
800849e: 4603 mov r3, r0
|
|
}
|
|
80084a0: 4618 mov r0, r3
|
|
80084a2: 3708 adds r7, #8
|
|
80084a4: 46bd mov sp, r7
|
|
80084a6: bd80 pop {r7, pc}
|
|
|
|
080084a8 <RadioWrite>:
|
|
|
|
static void RadioWrite( uint16_t addr, uint8_t data )
|
|
{
|
|
80084a8: b580 push {r7, lr}
|
|
80084aa: b082 sub sp, #8
|
|
80084ac: af00 add r7, sp, #0
|
|
80084ae: 4603 mov r3, r0
|
|
80084b0: 460a mov r2, r1
|
|
80084b2: 80fb strh r3, [r7, #6]
|
|
80084b4: 4613 mov r3, r2
|
|
80084b6: 717b strb r3, [r7, #5]
|
|
SUBGRF_WriteRegister( addr, data );
|
|
80084b8: 797a ldrb r2, [r7, #5]
|
|
80084ba: 88fb ldrh r3, [r7, #6]
|
|
80084bc: 4611 mov r1, r2
|
|
80084be: 4618 mov r0, r3
|
|
80084c0: f001 ff2a bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
80084c4: bf00 nop
|
|
80084c6: 3708 adds r7, #8
|
|
80084c8: 46bd mov sp, r7
|
|
80084ca: bd80 pop {r7, pc}
|
|
|
|
080084cc <RadioRead>:
|
|
|
|
static uint8_t RadioRead( uint16_t addr )
|
|
{
|
|
80084cc: b580 push {r7, lr}
|
|
80084ce: b082 sub sp, #8
|
|
80084d0: af00 add r7, sp, #0
|
|
80084d2: 4603 mov r3, r0
|
|
80084d4: 80fb strh r3, [r7, #6]
|
|
return SUBGRF_ReadRegister( addr );
|
|
80084d6: 88fb ldrh r3, [r7, #6]
|
|
80084d8: 4618 mov r0, r3
|
|
80084da: f001 ff3f bl 800a35c <SUBGRF_ReadRegister>
|
|
80084de: 4603 mov r3, r0
|
|
}
|
|
80084e0: 4618 mov r0, r3
|
|
80084e2: 3708 adds r7, #8
|
|
80084e4: 46bd mov sp, r7
|
|
80084e6: bd80 pop {r7, pc}
|
|
|
|
080084e8 <RadioWriteRegisters>:
|
|
|
|
static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size )
|
|
{
|
|
80084e8: b580 push {r7, lr}
|
|
80084ea: b082 sub sp, #8
|
|
80084ec: af00 add r7, sp, #0
|
|
80084ee: 4603 mov r3, r0
|
|
80084f0: 6039 str r1, [r7, #0]
|
|
80084f2: 80fb strh r3, [r7, #6]
|
|
80084f4: 4613 mov r3, r2
|
|
80084f6: 717b strb r3, [r7, #5]
|
|
SUBGRF_WriteRegisters( addr, buffer, size );
|
|
80084f8: 797b ldrb r3, [r7, #5]
|
|
80084fa: b29a uxth r2, r3
|
|
80084fc: 88fb ldrh r3, [r7, #6]
|
|
80084fe: 6839 ldr r1, [r7, #0]
|
|
8008500: 4618 mov r0, r3
|
|
8008502: f001 ff4b bl 800a39c <SUBGRF_WriteRegisters>
|
|
}
|
|
8008506: bf00 nop
|
|
8008508: 3708 adds r7, #8
|
|
800850a: 46bd mov sp, r7
|
|
800850c: bd80 pop {r7, pc}
|
|
|
|
0800850e <RadioReadRegisters>:
|
|
|
|
static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size )
|
|
{
|
|
800850e: b580 push {r7, lr}
|
|
8008510: b082 sub sp, #8
|
|
8008512: af00 add r7, sp, #0
|
|
8008514: 4603 mov r3, r0
|
|
8008516: 6039 str r1, [r7, #0]
|
|
8008518: 80fb strh r3, [r7, #6]
|
|
800851a: 4613 mov r3, r2
|
|
800851c: 717b strb r3, [r7, #5]
|
|
SUBGRF_ReadRegisters( addr, buffer, size );
|
|
800851e: 797b ldrb r3, [r7, #5]
|
|
8008520: b29a uxth r2, r3
|
|
8008522: 88fb ldrh r3, [r7, #6]
|
|
8008524: 6839 ldr r1, [r7, #0]
|
|
8008526: 4618 mov r0, r3
|
|
8008528: f001 ff5a bl 800a3e0 <SUBGRF_ReadRegisters>
|
|
}
|
|
800852c: bf00 nop
|
|
800852e: 3708 adds r7, #8
|
|
8008530: 46bd mov sp, r7
|
|
8008532: bd80 pop {r7, pc}
|
|
|
|
08008534 <RadioSetMaxPayloadLength>:
|
|
|
|
static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max )
|
|
{
|
|
8008534: b580 push {r7, lr}
|
|
8008536: b082 sub sp, #8
|
|
8008538: af00 add r7, sp, #0
|
|
800853a: 4603 mov r3, r0
|
|
800853c: 460a mov r2, r1
|
|
800853e: 71fb strb r3, [r7, #7]
|
|
8008540: 4613 mov r3, r2
|
|
8008542: 71bb strb r3, [r7, #6]
|
|
if( modem == MODEM_LORA )
|
|
8008544: 79fb ldrb r3, [r7, #7]
|
|
8008546: 2b01 cmp r3, #1
|
|
8008548: d10a bne.n 8008560 <RadioSetMaxPayloadLength+0x2c>
|
|
{
|
|
SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max;
|
|
800854a: 4a0e ldr r2, [pc, #56] @ (8008584 <RadioSetMaxPayloadLength+0x50>)
|
|
800854c: 79bb ldrb r3, [r7, #6]
|
|
800854e: 7013 strb r3, [r2, #0]
|
|
8008550: 4b0c ldr r3, [pc, #48] @ (8008584 <RadioSetMaxPayloadLength+0x50>)
|
|
8008552: 781a ldrb r2, [r3, #0]
|
|
8008554: 4b0c ldr r3, [pc, #48] @ (8008588 <RadioSetMaxPayloadLength+0x54>)
|
|
8008556: 77da strb r2, [r3, #31]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008558: 480c ldr r0, [pc, #48] @ (800858c <RadioSetMaxPayloadLength+0x58>)
|
|
800855a: f001 fd97 bl 800a08c <SUBGRF_SetPacketParams>
|
|
{
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max;
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
}
|
|
}
|
|
}
|
|
800855e: e00d b.n 800857c <RadioSetMaxPayloadLength+0x48>
|
|
if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH )
|
|
8008560: 4b09 ldr r3, [pc, #36] @ (8008588 <RadioSetMaxPayloadLength+0x54>)
|
|
8008562: 7d5b ldrb r3, [r3, #21]
|
|
8008564: 2b01 cmp r3, #1
|
|
8008566: d109 bne.n 800857c <RadioSetMaxPayloadLength+0x48>
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max;
|
|
8008568: 4a06 ldr r2, [pc, #24] @ (8008584 <RadioSetMaxPayloadLength+0x50>)
|
|
800856a: 79bb ldrb r3, [r7, #6]
|
|
800856c: 7013 strb r3, [r2, #0]
|
|
800856e: 4b05 ldr r3, [pc, #20] @ (8008584 <RadioSetMaxPayloadLength+0x50>)
|
|
8008570: 781a ldrb r2, [r3, #0]
|
|
8008572: 4b05 ldr r3, [pc, #20] @ (8008588 <RadioSetMaxPayloadLength+0x54>)
|
|
8008574: 759a strb r2, [r3, #22]
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008576: 4805 ldr r0, [pc, #20] @ (800858c <RadioSetMaxPayloadLength+0x58>)
|
|
8008578: f001 fd88 bl 800a08c <SUBGRF_SetPacketParams>
|
|
}
|
|
800857c: bf00 nop
|
|
800857e: 3708 adds r7, #8
|
|
8008580: 46bd mov sp, r7
|
|
8008582: bd80 pop {r7, pc}
|
|
8008584: 20000008 .word 0x20000008
|
|
8008588: 20000290 .word 0x20000290
|
|
800858c: 2000029e .word 0x2000029e
|
|
|
|
08008590 <RadioSetPublicNetwork>:
|
|
|
|
static void RadioSetPublicNetwork( bool enable )
|
|
{
|
|
8008590: b580 push {r7, lr}
|
|
8008592: b082 sub sp, #8
|
|
8008594: af00 add r7, sp, #0
|
|
8008596: 4603 mov r3, r0
|
|
8008598: 71fb strb r3, [r7, #7]
|
|
SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable;
|
|
800859a: 4a13 ldr r2, [pc, #76] @ (80085e8 <RadioSetPublicNetwork+0x58>)
|
|
800859c: 79fb ldrb r3, [r7, #7]
|
|
800859e: 7313 strb r3, [r2, #12]
|
|
80085a0: 4b11 ldr r3, [pc, #68] @ (80085e8 <RadioSetPublicNetwork+0x58>)
|
|
80085a2: 7b1a ldrb r2, [r3, #12]
|
|
80085a4: 4b10 ldr r3, [pc, #64] @ (80085e8 <RadioSetPublicNetwork+0x58>)
|
|
80085a6: 735a strb r2, [r3, #13]
|
|
|
|
RadioSetModem( MODEM_LORA );
|
|
80085a8: 2001 movs r0, #1
|
|
80085aa: f7ff f801 bl 80075b0 <RadioSetModem>
|
|
if( enable == true )
|
|
80085ae: 79fb ldrb r3, [r7, #7]
|
|
80085b0: 2b00 cmp r3, #0
|
|
80085b2: d00a beq.n 80085ca <RadioSetPublicNetwork+0x3a>
|
|
{
|
|
// Change LoRa modem SyncWord
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF );
|
|
80085b4: 2134 movs r1, #52 @ 0x34
|
|
80085b6: f44f 60e8 mov.w r0, #1856 @ 0x740
|
|
80085ba: f001 fead bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF );
|
|
80085be: 2144 movs r1, #68 @ 0x44
|
|
80085c0: f240 7041 movw r0, #1857 @ 0x741
|
|
80085c4: f001 fea8 bl 800a318 <SUBGRF_WriteRegister>
|
|
{
|
|
// Change LoRa modem SyncWord
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF );
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF );
|
|
}
|
|
}
|
|
80085c8: e009 b.n 80085de <RadioSetPublicNetwork+0x4e>
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF );
|
|
80085ca: 2114 movs r1, #20
|
|
80085cc: f44f 60e8 mov.w r0, #1856 @ 0x740
|
|
80085d0: f001 fea2 bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF );
|
|
80085d4: 2124 movs r1, #36 @ 0x24
|
|
80085d6: f240 7041 movw r0, #1857 @ 0x741
|
|
80085da: f001 fe9d bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
80085de: bf00 nop
|
|
80085e0: 3708 adds r7, #8
|
|
80085e2: 46bd mov sp, r7
|
|
80085e4: bd80 pop {r7, pc}
|
|
80085e6: bf00 nop
|
|
80085e8: 20000290 .word 0x20000290
|
|
|
|
080085ec <RadioGetWakeupTime>:
|
|
|
|
static uint32_t RadioGetWakeupTime( void )
|
|
{
|
|
80085ec: b580 push {r7, lr}
|
|
80085ee: af00 add r7, sp, #0
|
|
return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME;
|
|
80085f0: f001 fffc bl 800a5ec <SUBGRF_GetRadioWakeUpTime>
|
|
80085f4: 4603 mov r3, r0
|
|
80085f6: 3303 adds r3, #3
|
|
}
|
|
80085f8: 4618 mov r0, r3
|
|
80085fa: bd80 pop {r7, pc}
|
|
|
|
080085fc <RadioOnTxTimeoutIrq>:
|
|
|
|
static void RadioOnTxTimeoutIrq( void *context )
|
|
{
|
|
80085fc: b580 push {r7, lr}
|
|
80085fe: b082 sub sp, #8
|
|
8008600: af00 add r7, sp, #0
|
|
8008602: 6078 str r0, [r7, #4]
|
|
RADIO_TX_TIMEOUT_PROCESS();
|
|
8008604: f000 f80e bl 8008624 <RadioOnTxTimeoutProcess>
|
|
}
|
|
8008608: bf00 nop
|
|
800860a: 3708 adds r7, #8
|
|
800860c: 46bd mov sp, r7
|
|
800860e: bd80 pop {r7, pc}
|
|
|
|
08008610 <RadioOnRxTimeoutIrq>:
|
|
|
|
static void RadioOnRxTimeoutIrq( void *context )
|
|
{
|
|
8008610: b580 push {r7, lr}
|
|
8008612: b082 sub sp, #8
|
|
8008614: af00 add r7, sp, #0
|
|
8008616: 6078 str r0, [r7, #4]
|
|
RADIO_RX_TIMEOUT_PROCESS();
|
|
8008618: f000 f81e bl 8008658 <RadioOnRxTimeoutProcess>
|
|
}
|
|
800861c: bf00 nop
|
|
800861e: 3708 adds r7, #8
|
|
8008620: 46bd mov sp, r7
|
|
8008622: bd80 pop {r7, pc}
|
|
|
|
08008624 <RadioOnTxTimeoutProcess>:
|
|
|
|
static void RadioOnTxTimeoutProcess( void )
|
|
{
|
|
8008624: b580 push {r7, lr}
|
|
8008626: af00 add r7, sp, #0
|
|
DBG_GPIO_RADIO_TX( RST );
|
|
8008628: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
800862c: 4808 ldr r0, [pc, #32] @ (8008650 <RadioOnTxTimeoutProcess+0x2c>)
|
|
800862e: f7fe ff3e bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) )
|
|
8008632: 4b08 ldr r3, [pc, #32] @ (8008654 <RadioOnTxTimeoutProcess+0x30>)
|
|
8008634: 681b ldr r3, [r3, #0]
|
|
8008636: 2b00 cmp r3, #0
|
|
8008638: d008 beq.n 800864c <RadioOnTxTimeoutProcess+0x28>
|
|
800863a: 4b06 ldr r3, [pc, #24] @ (8008654 <RadioOnTxTimeoutProcess+0x30>)
|
|
800863c: 681b ldr r3, [r3, #0]
|
|
800863e: 685b ldr r3, [r3, #4]
|
|
8008640: 2b00 cmp r3, #0
|
|
8008642: d003 beq.n 800864c <RadioOnTxTimeoutProcess+0x28>
|
|
{
|
|
RadioEvents->TxTimeout( );
|
|
8008644: 4b03 ldr r3, [pc, #12] @ (8008654 <RadioOnTxTimeoutProcess+0x30>)
|
|
8008646: 681b ldr r3, [r3, #0]
|
|
8008648: 685b ldr r3, [r3, #4]
|
|
800864a: 4798 blx r3
|
|
}
|
|
}
|
|
800864c: bf00 nop
|
|
800864e: bd80 pop {r7, pc}
|
|
8008650: 48000400 .word 0x48000400
|
|
8008654: 2000028c .word 0x2000028c
|
|
|
|
08008658 <RadioOnRxTimeoutProcess>:
|
|
|
|
static void RadioOnRxTimeoutProcess( void )
|
|
{
|
|
8008658: b580 push {r7, lr}
|
|
800865a: af00 add r7, sp, #0
|
|
DBG_GPIO_RADIO_RX( RST );
|
|
800865c: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8008660: 4808 ldr r0, [pc, #32] @ (8008684 <RadioOnRxTimeoutProcess+0x2c>)
|
|
8008662: f7fe ff24 bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
|
|
8008666: 4b08 ldr r3, [pc, #32] @ (8008688 <RadioOnRxTimeoutProcess+0x30>)
|
|
8008668: 681b ldr r3, [r3, #0]
|
|
800866a: 2b00 cmp r3, #0
|
|
800866c: d008 beq.n 8008680 <RadioOnRxTimeoutProcess+0x28>
|
|
800866e: 4b06 ldr r3, [pc, #24] @ (8008688 <RadioOnRxTimeoutProcess+0x30>)
|
|
8008670: 681b ldr r3, [r3, #0]
|
|
8008672: 68db ldr r3, [r3, #12]
|
|
8008674: 2b00 cmp r3, #0
|
|
8008676: d003 beq.n 8008680 <RadioOnRxTimeoutProcess+0x28>
|
|
{
|
|
RadioEvents->RxTimeout( );
|
|
8008678: 4b03 ldr r3, [pc, #12] @ (8008688 <RadioOnRxTimeoutProcess+0x30>)
|
|
800867a: 681b ldr r3, [r3, #0]
|
|
800867c: 68db ldr r3, [r3, #12]
|
|
800867e: 4798 blx r3
|
|
}
|
|
}
|
|
8008680: bf00 nop
|
|
8008682: bd80 pop {r7, pc}
|
|
8008684: 48000400 .word 0x48000400
|
|
8008688: 2000028c .word 0x2000028c
|
|
|
|
0800868c <RadioOnDioIrq>:
|
|
|
|
static void RadioOnDioIrq( RadioIrqMasks_t radioIrq )
|
|
{
|
|
800868c: b580 push {r7, lr}
|
|
800868e: b082 sub sp, #8
|
|
8008690: af00 add r7, sp, #0
|
|
8008692: 4603 mov r3, r0
|
|
8008694: 80fb strh r3, [r7, #6]
|
|
SubgRf.RadioIrq = radioIrq;
|
|
8008696: 4a05 ldr r2, [pc, #20] @ (80086ac <RadioOnDioIrq+0x20>)
|
|
8008698: 88fb ldrh r3, [r7, #6]
|
|
800869a: f8a2 3054 strh.w r3, [r2, #84] @ 0x54
|
|
|
|
RADIO_IRQ_PROCESS();
|
|
800869e: f000 f807 bl 80086b0 <RadioIrqProcess>
|
|
}
|
|
80086a2: bf00 nop
|
|
80086a4: 3708 adds r7, #8
|
|
80086a6: 46bd mov sp, r7
|
|
80086a8: bd80 pop {r7, pc}
|
|
80086aa: bf00 nop
|
|
80086ac: 20000290 .word 0x20000290
|
|
|
|
080086b0 <RadioIrqProcess>:
|
|
|
|
static void RadioIrqProcess( void )
|
|
{
|
|
80086b0: b5b0 push {r4, r5, r7, lr}
|
|
80086b2: b082 sub sp, #8
|
|
80086b4: af00 add r7, sp, #0
|
|
uint8_t size = 0;
|
|
80086b6: 2300 movs r3, #0
|
|
80086b8: 71fb strb r3, [r7, #7]
|
|
int32_t cfo = 0;
|
|
80086ba: 2300 movs r3, #0
|
|
80086bc: 603b str r3, [r7, #0]
|
|
|
|
switch( SubgRf.RadioIrq )
|
|
80086be: 4bb2 ldr r3, [pc, #712] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
80086c0: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
|
|
80086c4: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80086c8: f000 8117 beq.w 80088fa <RadioIrqProcess+0x24a>
|
|
80086cc: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80086d0: f300 81fe bgt.w 8008ad0 <RadioIrqProcess+0x420>
|
|
80086d4: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80086d8: f000 80fb beq.w 80088d2 <RadioIrqProcess+0x222>
|
|
80086dc: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80086e0: f300 81f6 bgt.w 8008ad0 <RadioIrqProcess+0x420>
|
|
80086e4: 2b80 cmp r3, #128 @ 0x80
|
|
80086e6: f000 80e0 beq.w 80088aa <RadioIrqProcess+0x1fa>
|
|
80086ea: 2b80 cmp r3, #128 @ 0x80
|
|
80086ec: f300 81f0 bgt.w 8008ad0 <RadioIrqProcess+0x420>
|
|
80086f0: 2b20 cmp r3, #32
|
|
80086f2: dc49 bgt.n 8008788 <RadioIrqProcess+0xd8>
|
|
80086f4: 2b00 cmp r3, #0
|
|
80086f6: f340 81eb ble.w 8008ad0 <RadioIrqProcess+0x420>
|
|
80086fa: 3b01 subs r3, #1
|
|
80086fc: 2b1f cmp r3, #31
|
|
80086fe: f200 81e7 bhi.w 8008ad0 <RadioIrqProcess+0x420>
|
|
8008702: a201 add r2, pc, #4 @ (adr r2, 8008708 <RadioIrqProcess+0x58>)
|
|
8008704: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008708: 08008791 .word 0x08008791
|
|
800870c: 080087d5 .word 0x080087d5
|
|
8008710: 08008ad1 .word 0x08008ad1
|
|
8008714: 080089ad .word 0x080089ad
|
|
8008718: 08008ad1 .word 0x08008ad1
|
|
800871c: 08008ad1 .word 0x08008ad1
|
|
8008720: 08008ad1 .word 0x08008ad1
|
|
8008724: 08008a29 .word 0x08008a29
|
|
8008728: 08008ad1 .word 0x08008ad1
|
|
800872c: 08008ad1 .word 0x08008ad1
|
|
8008730: 08008ad1 .word 0x08008ad1
|
|
8008734: 08008ad1 .word 0x08008ad1
|
|
8008738: 08008ad1 .word 0x08008ad1
|
|
800873c: 08008ad1 .word 0x08008ad1
|
|
8008740: 08008ad1 .word 0x08008ad1
|
|
8008744: 08008a45 .word 0x08008a45
|
|
8008748: 08008ad1 .word 0x08008ad1
|
|
800874c: 08008ad1 .word 0x08008ad1
|
|
8008750: 08008ad1 .word 0x08008ad1
|
|
8008754: 08008ad1 .word 0x08008ad1
|
|
8008758: 08008ad1 .word 0x08008ad1
|
|
800875c: 08008ad1 .word 0x08008ad1
|
|
8008760: 08008ad1 .word 0x08008ad1
|
|
8008764: 08008ad1 .word 0x08008ad1
|
|
8008768: 08008ad1 .word 0x08008ad1
|
|
800876c: 08008ad1 .word 0x08008ad1
|
|
8008770: 08008ad1 .word 0x08008ad1
|
|
8008774: 08008ad1 .word 0x08008ad1
|
|
8008778: 08008ad1 .word 0x08008ad1
|
|
800877c: 08008ad1 .word 0x08008ad1
|
|
8008780: 08008ad1 .word 0x08008ad1
|
|
8008784: 08008a53 .word 0x08008a53
|
|
8008788: 2b40 cmp r3, #64 @ 0x40
|
|
800878a: f000 8183 beq.w 8008a94 <RadioIrqProcess+0x3e4>
|
|
MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" );
|
|
break;
|
|
}
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
default:
|
|
break;
|
|
800878e: e19f b.n 8008ad0 <RadioIrqProcess+0x420>
|
|
DBG_GPIO_RADIO_TX( RST );
|
|
8008790: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8008794: 487d ldr r0, [pc, #500] @ (800898c <RadioIrqProcess+0x2dc>)
|
|
8008796: f7fe fe8a bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
TimerStop( &TxTimeoutTimer );
|
|
800879a: 487d ldr r0, [pc, #500] @ (8008990 <RadioIrqProcess+0x2e0>)
|
|
800879c: f004 f9fa bl 800cb94 <UTIL_TIMER_Stop>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
80087a0: 2000 movs r0, #0
|
|
80087a2: f001 f835 bl 8009810 <SUBGRF_SetStandby>
|
|
if( RFW_Is_LongPacketModeEnabled() == 1 )
|
|
80087a6: f002 fb3d bl 800ae24 <RFW_Is_LongPacketModeEnabled>
|
|
80087aa: 4603 mov r3, r0
|
|
80087ac: 2b01 cmp r3, #1
|
|
80087ae: d101 bne.n 80087b4 <RadioIrqProcess+0x104>
|
|
RFW_DeInit_TxLongPacket( );
|
|
80087b0: f002 fbf4 bl 800af9c <RFW_DeInit_TxLongPacket>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) )
|
|
80087b4: 4b77 ldr r3, [pc, #476] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80087b6: 681b ldr r3, [r3, #0]
|
|
80087b8: 2b00 cmp r3, #0
|
|
80087ba: f000 818b beq.w 8008ad4 <RadioIrqProcess+0x424>
|
|
80087be: 4b75 ldr r3, [pc, #468] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80087c0: 681b ldr r3, [r3, #0]
|
|
80087c2: 681b ldr r3, [r3, #0]
|
|
80087c4: 2b00 cmp r3, #0
|
|
80087c6: f000 8185 beq.w 8008ad4 <RadioIrqProcess+0x424>
|
|
RadioEvents->TxDone( );
|
|
80087ca: 4b72 ldr r3, [pc, #456] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80087cc: 681b ldr r3, [r3, #0]
|
|
80087ce: 681b ldr r3, [r3, #0]
|
|
80087d0: 4798 blx r3
|
|
break;
|
|
80087d2: e17f b.n 8008ad4 <RadioIrqProcess+0x424>
|
|
DBG_GPIO_RADIO_RX( RST );
|
|
80087d4: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
80087d8: 486c ldr r0, [pc, #432] @ (800898c <RadioIrqProcess+0x2dc>)
|
|
80087da: f7fe fe68 bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
TimerStop( &RxTimeoutTimer );
|
|
80087de: 486e ldr r0, [pc, #440] @ (8008998 <RadioIrqProcess+0x2e8>)
|
|
80087e0: f004 f9d8 bl 800cb94 <UTIL_TIMER_Stop>
|
|
if( SubgRf.RxContinuous == false )
|
|
80087e4: 4b68 ldr r3, [pc, #416] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
80087e6: 785b ldrb r3, [r3, #1]
|
|
80087e8: f083 0301 eor.w r3, r3, #1
|
|
80087ec: b2db uxtb r3, r3
|
|
80087ee: 2b00 cmp r3, #0
|
|
80087f0: d014 beq.n 800881c <RadioIrqProcess+0x16c>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
80087f2: 2000 movs r0, #0
|
|
80087f4: f001 f80c bl 8009810 <SUBGRF_SetStandby>
|
|
SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 );
|
|
80087f8: 2100 movs r1, #0
|
|
80087fa: f640 1002 movw r0, #2306 @ 0x902
|
|
80087fe: f001 fd8b bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) );
|
|
8008802: f640 1044 movw r0, #2372 @ 0x944
|
|
8008806: f001 fda9 bl 800a35c <SUBGRF_ReadRegister>
|
|
800880a: 4603 mov r3, r0
|
|
800880c: f043 0302 orr.w r3, r3, #2
|
|
8008810: b2db uxtb r3, r3
|
|
8008812: 4619 mov r1, r3
|
|
8008814: f640 1044 movw r0, #2372 @ 0x944
|
|
8008818: f001 fd7e bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_GetPayload( RadioBuffer, &size, 255 );
|
|
800881c: 1dfb adds r3, r7, #7
|
|
800881e: 22ff movs r2, #255 @ 0xff
|
|
8008820: 4619 mov r1, r3
|
|
8008822: 485e ldr r0, [pc, #376] @ (800899c <RadioIrqProcess+0x2ec>)
|
|
8008824: f000 fec2 bl 80095ac <SUBGRF_GetPayload>
|
|
SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) );
|
|
8008828: 485d ldr r0, [pc, #372] @ (80089a0 <RadioIrqProcess+0x2f0>)
|
|
800882a: f001 fd23 bl 800a274 <SUBGRF_GetPacketStatus>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) )
|
|
800882e: 4b59 ldr r3, [pc, #356] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008830: 681b ldr r3, [r3, #0]
|
|
8008832: 2b00 cmp r3, #0
|
|
8008834: f000 8150 beq.w 8008ad8 <RadioIrqProcess+0x428>
|
|
8008838: 4b56 ldr r3, [pc, #344] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
800883a: 681b ldr r3, [r3, #0]
|
|
800883c: 689b ldr r3, [r3, #8]
|
|
800883e: 2b00 cmp r3, #0
|
|
8008840: f000 814a beq.w 8008ad8 <RadioIrqProcess+0x428>
|
|
switch( SubgRf.PacketStatus.packetType )
|
|
8008844: 4b50 ldr r3, [pc, #320] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
8008846: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
800884a: 2b01 cmp r3, #1
|
|
800884c: d10e bne.n 800886c <RadioIrqProcess+0x1bc>
|
|
RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt,
|
|
800884e: 4b51 ldr r3, [pc, #324] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008850: 681b ldr r3, [r3, #0]
|
|
8008852: 689c ldr r4, [r3, #8]
|
|
8008854: 79fb ldrb r3, [r7, #7]
|
|
8008856: 4619 mov r1, r3
|
|
8008858: 4b4b ldr r3, [pc, #300] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
800885a: f993 3030 ldrsb.w r3, [r3, #48] @ 0x30
|
|
800885e: 461a mov r2, r3
|
|
8008860: 4b49 ldr r3, [pc, #292] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
8008862: f993 3031 ldrsb.w r3, [r3, #49] @ 0x31
|
|
8008866: 484d ldr r0, [pc, #308] @ (800899c <RadioIrqProcess+0x2ec>)
|
|
8008868: 47a0 blx r4
|
|
break;
|
|
800886a: e01d b.n 80088a8 <RadioIrqProcess+0x1f8>
|
|
SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo );
|
|
800886c: 4b46 ldr r3, [pc, #280] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
800886e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008870: 463a mov r2, r7
|
|
8008872: 4611 mov r1, r2
|
|
8008874: 4618 mov r0, r3
|
|
8008876: f001 ffab bl 800a7d0 <SUBGRF_GetCFO>
|
|
RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) );
|
|
800887a: 4b46 ldr r3, [pc, #280] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
800887c: 681b ldr r3, [r3, #0]
|
|
800887e: 689c ldr r4, [r3, #8]
|
|
8008880: 79fb ldrb r3, [r7, #7]
|
|
8008882: 4619 mov r1, r3
|
|
8008884: 4b40 ldr r3, [pc, #256] @ (8008988 <RadioIrqProcess+0x2d8>)
|
|
8008886: f993 3029 ldrsb.w r3, [r3, #41] @ 0x29
|
|
800888a: 4618 mov r0, r3
|
|
800888c: 683b ldr r3, [r7, #0]
|
|
800888e: f503 73fa add.w r3, r3, #500 @ 0x1f4
|
|
8008892: 4a44 ldr r2, [pc, #272] @ (80089a4 <RadioIrqProcess+0x2f4>)
|
|
8008894: fb82 5203 smull r5, r2, r2, r3
|
|
8008898: 1192 asrs r2, r2, #6
|
|
800889a: 17db asrs r3, r3, #31
|
|
800889c: 1ad3 subs r3, r2, r3
|
|
800889e: b25b sxtb r3, r3
|
|
80088a0: 4602 mov r2, r0
|
|
80088a2: 483e ldr r0, [pc, #248] @ (800899c <RadioIrqProcess+0x2ec>)
|
|
80088a4: 47a0 blx r4
|
|
break;
|
|
80088a6: bf00 nop
|
|
break;
|
|
80088a8: e116 b.n 8008ad8 <RadioIrqProcess+0x428>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
80088aa: 2000 movs r0, #0
|
|
80088ac: f000 ffb0 bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) )
|
|
80088b0: 4b38 ldr r3, [pc, #224] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088b2: 681b ldr r3, [r3, #0]
|
|
80088b4: 2b00 cmp r3, #0
|
|
80088b6: f000 8111 beq.w 8008adc <RadioIrqProcess+0x42c>
|
|
80088ba: 4b36 ldr r3, [pc, #216] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088bc: 681b ldr r3, [r3, #0]
|
|
80088be: 699b ldr r3, [r3, #24]
|
|
80088c0: 2b00 cmp r3, #0
|
|
80088c2: f000 810b beq.w 8008adc <RadioIrqProcess+0x42c>
|
|
RadioEvents->CadDone( false );
|
|
80088c6: 4b33 ldr r3, [pc, #204] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088c8: 681b ldr r3, [r3, #0]
|
|
80088ca: 699b ldr r3, [r3, #24]
|
|
80088cc: 2000 movs r0, #0
|
|
80088ce: 4798 blx r3
|
|
break;
|
|
80088d0: e104 b.n 8008adc <RadioIrqProcess+0x42c>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
80088d2: 2000 movs r0, #0
|
|
80088d4: f000 ff9c bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) )
|
|
80088d8: 4b2e ldr r3, [pc, #184] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088da: 681b ldr r3, [r3, #0]
|
|
80088dc: 2b00 cmp r3, #0
|
|
80088de: f000 80ff beq.w 8008ae0 <RadioIrqProcess+0x430>
|
|
80088e2: 4b2c ldr r3, [pc, #176] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088e4: 681b ldr r3, [r3, #0]
|
|
80088e6: 699b ldr r3, [r3, #24]
|
|
80088e8: 2b00 cmp r3, #0
|
|
80088ea: f000 80f9 beq.w 8008ae0 <RadioIrqProcess+0x430>
|
|
RadioEvents->CadDone( true );
|
|
80088ee: 4b29 ldr r3, [pc, #164] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
80088f0: 681b ldr r3, [r3, #0]
|
|
80088f2: 699b ldr r3, [r3, #24]
|
|
80088f4: 2001 movs r0, #1
|
|
80088f6: 4798 blx r3
|
|
break;
|
|
80088f8: e0f2 b.n 8008ae0 <RadioIrqProcess+0x430>
|
|
MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" );
|
|
80088fa: 4b2b ldr r3, [pc, #172] @ (80089a8 <RadioIrqProcess+0x2f8>)
|
|
80088fc: 2201 movs r2, #1
|
|
80088fe: 2100 movs r1, #0
|
|
8008900: 2002 movs r0, #2
|
|
8008902: f004 fb3f bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
if( SUBGRF_GetOperatingMode( ) == MODE_TX )
|
|
8008906: f000 fe37 bl 8009578 <SUBGRF_GetOperatingMode>
|
|
800890a: 4603 mov r3, r0
|
|
800890c: 2b04 cmp r3, #4
|
|
800890e: d11a bne.n 8008946 <RadioIrqProcess+0x296>
|
|
DBG_GPIO_RADIO_TX( RST );
|
|
8008910: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8008914: 481d ldr r0, [pc, #116] @ (800898c <RadioIrqProcess+0x2dc>)
|
|
8008916: f7fe fdca bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
TimerStop( &TxTimeoutTimer );
|
|
800891a: 481d ldr r0, [pc, #116] @ (8008990 <RadioIrqProcess+0x2e0>)
|
|
800891c: f004 f93a bl 800cb94 <UTIL_TIMER_Stop>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
8008920: 2000 movs r0, #0
|
|
8008922: f000 ff75 bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) )
|
|
8008926: 4b1b ldr r3, [pc, #108] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008928: 681b ldr r3, [r3, #0]
|
|
800892a: 2b00 cmp r3, #0
|
|
800892c: f000 80da beq.w 8008ae4 <RadioIrqProcess+0x434>
|
|
8008930: 4b18 ldr r3, [pc, #96] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008932: 681b ldr r3, [r3, #0]
|
|
8008934: 685b ldr r3, [r3, #4]
|
|
8008936: 2b00 cmp r3, #0
|
|
8008938: f000 80d4 beq.w 8008ae4 <RadioIrqProcess+0x434>
|
|
RadioEvents->TxTimeout( );
|
|
800893c: 4b15 ldr r3, [pc, #84] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
800893e: 681b ldr r3, [r3, #0]
|
|
8008940: 685b ldr r3, [r3, #4]
|
|
8008942: 4798 blx r3
|
|
break;
|
|
8008944: e0ce b.n 8008ae4 <RadioIrqProcess+0x434>
|
|
else if( SUBGRF_GetOperatingMode( ) == MODE_RX )
|
|
8008946: f000 fe17 bl 8009578 <SUBGRF_GetOperatingMode>
|
|
800894a: 4603 mov r3, r0
|
|
800894c: 2b05 cmp r3, #5
|
|
800894e: f040 80c9 bne.w 8008ae4 <RadioIrqProcess+0x434>
|
|
DBG_GPIO_RADIO_RX( RST );
|
|
8008952: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8008956: 480d ldr r0, [pc, #52] @ (800898c <RadioIrqProcess+0x2dc>)
|
|
8008958: f7fe fda9 bl 80074ae <LL_GPIO_ResetOutputPin>
|
|
TimerStop( &RxTimeoutTimer );
|
|
800895c: 480e ldr r0, [pc, #56] @ (8008998 <RadioIrqProcess+0x2e8>)
|
|
800895e: f004 f919 bl 800cb94 <UTIL_TIMER_Stop>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
8008962: 2000 movs r0, #0
|
|
8008964: f000 ff54 bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
|
|
8008968: 4b0a ldr r3, [pc, #40] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
800896a: 681b ldr r3, [r3, #0]
|
|
800896c: 2b00 cmp r3, #0
|
|
800896e: f000 80b9 beq.w 8008ae4 <RadioIrqProcess+0x434>
|
|
8008972: 4b08 ldr r3, [pc, #32] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008974: 681b ldr r3, [r3, #0]
|
|
8008976: 68db ldr r3, [r3, #12]
|
|
8008978: 2b00 cmp r3, #0
|
|
800897a: f000 80b3 beq.w 8008ae4 <RadioIrqProcess+0x434>
|
|
RadioEvents->RxTimeout( );
|
|
800897e: 4b05 ldr r3, [pc, #20] @ (8008994 <RadioIrqProcess+0x2e4>)
|
|
8008980: 681b ldr r3, [r3, #0]
|
|
8008982: 68db ldr r3, [r3, #12]
|
|
8008984: 4798 blx r3
|
|
break;
|
|
8008986: e0ad b.n 8008ae4 <RadioIrqProcess+0x434>
|
|
8008988: 20000290 .word 0x20000290
|
|
800898c: 48000400 .word 0x48000400
|
|
8008990: 200002ec .word 0x200002ec
|
|
8008994: 2000028c .word 0x2000028c
|
|
8008998: 20000304 .word 0x20000304
|
|
800899c: 2000018c .word 0x2000018c
|
|
80089a0: 200002b4 .word 0x200002b4
|
|
80089a4: 10624dd3 .word 0x10624dd3
|
|
80089a8: 0800d550 .word 0x0800d550
|
|
MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" );
|
|
80089ac: 4b54 ldr r3, [pc, #336] @ (8008b00 <RadioIrqProcess+0x450>)
|
|
80089ae: 2201 movs r2, #1
|
|
80089b0: 2100 movs r1, #0
|
|
80089b2: 2002 movs r0, #2
|
|
80089b4: f004 fae6 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
if( SubgRf.RxDcPreambleDetectTimeout != 0 )
|
|
80089b8: 4b52 ldr r3, [pc, #328] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
80089ba: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80089bc: 2b00 cmp r3, #0
|
|
80089be: f000 8093 beq.w 8008ae8 <RadioIrqProcess+0x438>
|
|
Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/
|
|
80089c2: 4a51 ldr r2, [pc, #324] @ (8008b08 <RadioIrqProcess+0x458>)
|
|
80089c4: 4b4f ldr r3, [pc, #316] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
80089c6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80089c8: 0c1b lsrs r3, r3, #16
|
|
80089ca: b2db uxtb r3, r3
|
|
80089cc: 4619 mov r1, r3
|
|
80089ce: f640 1003 movw r0, #2307 @ 0x903
|
|
80089d2: 4790 blx r2
|
|
Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/
|
|
80089d4: 4a4c ldr r2, [pc, #304] @ (8008b08 <RadioIrqProcess+0x458>)
|
|
80089d6: 4b4b ldr r3, [pc, #300] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
80089d8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80089da: 0a1b lsrs r3, r3, #8
|
|
80089dc: b2db uxtb r3, r3
|
|
80089de: 4619 mov r1, r3
|
|
80089e0: f640 1004 movw r0, #2308 @ 0x904
|
|
80089e4: 4790 blx r2
|
|
Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/
|
|
80089e6: 4a48 ldr r2, [pc, #288] @ (8008b08 <RadioIrqProcess+0x458>)
|
|
80089e8: 4b46 ldr r3, [pc, #280] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
80089ea: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80089ec: b2db uxtb r3, r3
|
|
80089ee: 4619 mov r1, r3
|
|
80089f0: f640 1005 movw r0, #2309 @ 0x905
|
|
80089f4: 4790 blx r2
|
|
Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/
|
|
80089f6: 4c44 ldr r4, [pc, #272] @ (8008b08 <RadioIrqProcess+0x458>)
|
|
80089f8: 4b44 ldr r3, [pc, #272] @ (8008b0c <RadioIrqProcess+0x45c>)
|
|
80089fa: f640 1002 movw r0, #2306 @ 0x902
|
|
80089fe: 4798 blx r3
|
|
8008a00: 4603 mov r3, r0
|
|
8008a02: f043 0301 orr.w r3, r3, #1
|
|
8008a06: b2db uxtb r3, r3
|
|
8008a08: 4619 mov r1, r3
|
|
8008a0a: f640 1002 movw r0, #2306 @ 0x902
|
|
8008a0e: 47a0 blx r4
|
|
SubgRf.RxDcPreambleDetectTimeout = 0;
|
|
8008a10: 4b3c ldr r3, [pc, #240] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
8008a12: 2200 movs r2, #0
|
|
8008a14: 659a str r2, [r3, #88] @ 0x58
|
|
SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG,
|
|
8008a16: 2300 movs r3, #0
|
|
8008a18: 2200 movs r2, #0
|
|
8008a1a: f240 2162 movw r1, #610 @ 0x262
|
|
8008a1e: f240 2062 movw r0, #610 @ 0x262
|
|
8008a22: f001 f8cf bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
break;
|
|
8008a26: e05f b.n 8008ae8 <RadioIrqProcess+0x438>
|
|
MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" );
|
|
8008a28: 4b39 ldr r3, [pc, #228] @ (8008b10 <RadioIrqProcess+0x460>)
|
|
8008a2a: 2201 movs r2, #1
|
|
8008a2c: 2100 movs r1, #0
|
|
8008a2e: 2002 movs r0, #2
|
|
8008a30: f004 faa8 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
if( 1UL == RFW_Is_Init( ) )
|
|
8008a34: f002 f9ec bl 800ae10 <RFW_Is_Init>
|
|
8008a38: 4603 mov r3, r0
|
|
8008a3a: 2b01 cmp r3, #1
|
|
8008a3c: d156 bne.n 8008aec <RadioIrqProcess+0x43c>
|
|
RFW_ReceivePayload( );
|
|
8008a3e: f002 fac9 bl 800afd4 <RFW_ReceivePayload>
|
|
break;
|
|
8008a42: e053 b.n 8008aec <RadioIrqProcess+0x43c>
|
|
MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" );
|
|
8008a44: 4b33 ldr r3, [pc, #204] @ (8008b14 <RadioIrqProcess+0x464>)
|
|
8008a46: 2201 movs r2, #1
|
|
8008a48: 2100 movs r1, #0
|
|
8008a4a: 2002 movs r0, #2
|
|
8008a4c: f004 fa9a bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
8008a50: e051 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
TimerStop( &RxTimeoutTimer );
|
|
8008a52: 4831 ldr r0, [pc, #196] @ (8008b18 <RadioIrqProcess+0x468>)
|
|
8008a54: f004 f89e bl 800cb94 <UTIL_TIMER_Stop>
|
|
if( SubgRf.RxContinuous == false )
|
|
8008a58: 4b2a ldr r3, [pc, #168] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
8008a5a: 785b ldrb r3, [r3, #1]
|
|
8008a5c: f083 0301 eor.w r3, r3, #1
|
|
8008a60: b2db uxtb r3, r3
|
|
8008a62: 2b00 cmp r3, #0
|
|
8008a64: d002 beq.n 8008a6c <RadioIrqProcess+0x3bc>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
8008a66: 2000 movs r0, #0
|
|
8008a68: f000 fed2 bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
|
|
8008a6c: 4b2b ldr r3, [pc, #172] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008a6e: 681b ldr r3, [r3, #0]
|
|
8008a70: 2b00 cmp r3, #0
|
|
8008a72: d03d beq.n 8008af0 <RadioIrqProcess+0x440>
|
|
8008a74: 4b29 ldr r3, [pc, #164] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008a76: 681b ldr r3, [r3, #0]
|
|
8008a78: 68db ldr r3, [r3, #12]
|
|
8008a7a: 2b00 cmp r3, #0
|
|
8008a7c: d038 beq.n 8008af0 <RadioIrqProcess+0x440>
|
|
RadioEvents->RxTimeout( );
|
|
8008a7e: 4b27 ldr r3, [pc, #156] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008a80: 681b ldr r3, [r3, #0]
|
|
8008a82: 68db ldr r3, [r3, #12]
|
|
8008a84: 4798 blx r3
|
|
MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" );
|
|
8008a86: 4b26 ldr r3, [pc, #152] @ (8008b20 <RadioIrqProcess+0x470>)
|
|
8008a88: 2201 movs r2, #1
|
|
8008a8a: 2100 movs r1, #0
|
|
8008a8c: 2002 movs r0, #2
|
|
8008a8e: f004 fa79 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
8008a92: e02d b.n 8008af0 <RadioIrqProcess+0x440>
|
|
MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" );
|
|
8008a94: 4b23 ldr r3, [pc, #140] @ (8008b24 <RadioIrqProcess+0x474>)
|
|
8008a96: 2201 movs r2, #1
|
|
8008a98: 2100 movs r1, #0
|
|
8008a9a: 2002 movs r0, #2
|
|
8008a9c: f004 fa72 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
if( SubgRf.RxContinuous == false )
|
|
8008aa0: 4b18 ldr r3, [pc, #96] @ (8008b04 <RadioIrqProcess+0x454>)
|
|
8008aa2: 785b ldrb r3, [r3, #1]
|
|
8008aa4: f083 0301 eor.w r3, r3, #1
|
|
8008aa8: b2db uxtb r3, r3
|
|
8008aaa: 2b00 cmp r3, #0
|
|
8008aac: d002 beq.n 8008ab4 <RadioIrqProcess+0x404>
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
8008aae: 2000 movs r0, #0
|
|
8008ab0: f000 feae bl 8009810 <SUBGRF_SetStandby>
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) )
|
|
8008ab4: 4b19 ldr r3, [pc, #100] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008ab6: 681b ldr r3, [r3, #0]
|
|
8008ab8: 2b00 cmp r3, #0
|
|
8008aba: d01b beq.n 8008af4 <RadioIrqProcess+0x444>
|
|
8008abc: 4b17 ldr r3, [pc, #92] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008abe: 681b ldr r3, [r3, #0]
|
|
8008ac0: 691b ldr r3, [r3, #16]
|
|
8008ac2: 2b00 cmp r3, #0
|
|
8008ac4: d016 beq.n 8008af4 <RadioIrqProcess+0x444>
|
|
RadioEvents->RxError( );
|
|
8008ac6: 4b15 ldr r3, [pc, #84] @ (8008b1c <RadioIrqProcess+0x46c>)
|
|
8008ac8: 681b ldr r3, [r3, #0]
|
|
8008aca: 691b ldr r3, [r3, #16]
|
|
8008acc: 4798 blx r3
|
|
break;
|
|
8008ace: e011 b.n 8008af4 <RadioIrqProcess+0x444>
|
|
break;
|
|
8008ad0: bf00 nop
|
|
8008ad2: e010 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008ad4: bf00 nop
|
|
8008ad6: e00e b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008ad8: bf00 nop
|
|
8008ada: e00c b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008adc: bf00 nop
|
|
8008ade: e00a b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008ae0: bf00 nop
|
|
8008ae2: e008 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008ae4: bf00 nop
|
|
8008ae6: e006 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008ae8: bf00 nop
|
|
8008aea: e004 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008aec: bf00 nop
|
|
8008aee: e002 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008af0: bf00 nop
|
|
8008af2: e000 b.n 8008af6 <RadioIrqProcess+0x446>
|
|
break;
|
|
8008af4: bf00 nop
|
|
}
|
|
}
|
|
8008af6: bf00 nop
|
|
8008af8: 3708 adds r7, #8
|
|
8008afa: 46bd mov sp, r7
|
|
8008afc: bdb0 pop {r4, r5, r7, pc}
|
|
8008afe: bf00 nop
|
|
8008b00: 0800d564 .word 0x0800d564
|
|
8008b04: 20000290 .word 0x20000290
|
|
8008b08: 080084a9 .word 0x080084a9
|
|
8008b0c: 080084cd .word 0x080084cd
|
|
8008b10: 0800d570 .word 0x0800d570
|
|
8008b14: 0800d57c .word 0x0800d57c
|
|
8008b18: 20000304 .word 0x20000304
|
|
8008b1c: 2000028c .word 0x2000028c
|
|
8008b20: 0800d588 .word 0x0800d588
|
|
8008b24: 0800d594 .word 0x0800d594
|
|
|
|
08008b28 <RadioTxPrbs>:
|
|
|
|
static void RadioTxPrbs( void )
|
|
{
|
|
8008b28: b580 push {r7, lr}
|
|
8008b2a: af00 add r7, sp, #0
|
|
SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX );
|
|
8008b2c: 4b09 ldr r3, [pc, #36] @ (8008b54 <RadioTxPrbs+0x2c>)
|
|
8008b2e: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
8008b32: 2101 movs r1, #1
|
|
8008b34: 4618 mov r0, r3
|
|
8008b36: f001 fcfd bl 800a534 <SUBGRF_SetSwitch>
|
|
Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble
|
|
8008b3a: 4b07 ldr r3, [pc, #28] @ (8008b58 <RadioTxPrbs+0x30>)
|
|
8008b3c: 212d movs r1, #45 @ 0x2d
|
|
8008b3e: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
8008b42: 4798 blx r3
|
|
SUBGRF_SetTxInfinitePreamble( );
|
|
8008b44: f000 ff27 bl 8009996 <SUBGRF_SetTxInfinitePreamble>
|
|
SUBGRF_SetTx( 0x0fffff );
|
|
8008b48: 4804 ldr r0, [pc, #16] @ (8008b5c <RadioTxPrbs+0x34>)
|
|
8008b4a: f000 fe7d bl 8009848 <SUBGRF_SetTx>
|
|
}
|
|
8008b4e: bf00 nop
|
|
8008b50: bd80 pop {r7, pc}
|
|
8008b52: bf00 nop
|
|
8008b54: 20000290 .word 0x20000290
|
|
8008b58: 080084a9 .word 0x080084a9
|
|
8008b5c: 000fffff .word 0x000fffff
|
|
|
|
08008b60 <RadioTxCw>:
|
|
|
|
static void RadioTxCw( int8_t power )
|
|
{
|
|
8008b60: b580 push {r7, lr}
|
|
8008b62: b084 sub sp, #16
|
|
8008b64: af00 add r7, sp, #0
|
|
8008b66: 4603 mov r3, r0
|
|
8008b68: 71fb strb r3, [r7, #7]
|
|
uint8_t paselect = SUBGRF_SetRfTxPower( power );
|
|
8008b6a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8008b6e: 4618 mov r0, r3
|
|
8008b70: f001 fd08 bl 800a584 <SUBGRF_SetRfTxPower>
|
|
8008b74: 4603 mov r3, r0
|
|
8008b76: 73fb strb r3, [r7, #15]
|
|
/* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */
|
|
SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1);
|
|
8008b78: 210e movs r1, #14
|
|
8008b7a: f640 101f movw r0, #2335 @ 0x91f
|
|
8008b7e: f001 fbcb bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_SetSwitch( paselect, RFSWITCH_TX );
|
|
8008b82: 7bfb ldrb r3, [r7, #15]
|
|
8008b84: 2101 movs r1, #1
|
|
8008b86: 4618 mov r0, r3
|
|
8008b88: f001 fcd4 bl 800a534 <SUBGRF_SetSwitch>
|
|
SUBGRF_SetTxContinuousWave( );
|
|
8008b8c: f000 fefa bl 8009984 <SUBGRF_SetTxContinuousWave>
|
|
}
|
|
8008b90: bf00 nop
|
|
8008b92: 3710 adds r7, #16
|
|
8008b94: 46bd mov sp, r7
|
|
8008b96: bd80 pop {r7, pc}
|
|
|
|
08008b98 <payload_integration>:
|
|
|
|
#if (RADIO_SIGFOX_ENABLE == 1)
|
|
static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size )
|
|
{
|
|
8008b98: b480 push {r7}
|
|
8008b9a: b089 sub sp, #36 @ 0x24
|
|
8008b9c: af00 add r7, sp, #0
|
|
8008b9e: 60f8 str r0, [r7, #12]
|
|
8008ba0: 60b9 str r1, [r7, #8]
|
|
8008ba2: 4613 mov r3, r2
|
|
8008ba4: 71fb strb r3, [r7, #7]
|
|
uint8_t prevInt = 0;
|
|
8008ba6: 2300 movs r3, #0
|
|
8008ba8: 77fb strb r3, [r7, #31]
|
|
uint8_t currBit;
|
|
uint8_t index_bit;
|
|
uint8_t index_byte;
|
|
uint8_t index_bit_out;
|
|
uint8_t index_byte_out;
|
|
int32_t i = 0;
|
|
8008baa: 2300 movs r3, #0
|
|
8008bac: 61bb str r3, [r7, #24]
|
|
|
|
for( i = 0; i < size; i++ )
|
|
8008bae: 2300 movs r3, #0
|
|
8008bb0: 61bb str r3, [r7, #24]
|
|
8008bb2: e011 b.n 8008bd8 <payload_integration+0x40>
|
|
{
|
|
/* reverse all inputs */
|
|
inBuffer[i] = ~inBuffer[i];
|
|
8008bb4: 69bb ldr r3, [r7, #24]
|
|
8008bb6: 68ba ldr r2, [r7, #8]
|
|
8008bb8: 4413 add r3, r2
|
|
8008bba: 781a ldrb r2, [r3, #0]
|
|
8008bbc: 69bb ldr r3, [r7, #24]
|
|
8008bbe: 68b9 ldr r1, [r7, #8]
|
|
8008bc0: 440b add r3, r1
|
|
8008bc2: 43d2 mvns r2, r2
|
|
8008bc4: b2d2 uxtb r2, r2
|
|
8008bc6: 701a strb r2, [r3, #0]
|
|
/* init outBuffer */
|
|
outBuffer[i] = 0;
|
|
8008bc8: 69bb ldr r3, [r7, #24]
|
|
8008bca: 68fa ldr r2, [r7, #12]
|
|
8008bcc: 4413 add r3, r2
|
|
8008bce: 2200 movs r2, #0
|
|
8008bd0: 701a strb r2, [r3, #0]
|
|
for( i = 0; i < size; i++ )
|
|
8008bd2: 69bb ldr r3, [r7, #24]
|
|
8008bd4: 3301 adds r3, #1
|
|
8008bd6: 61bb str r3, [r7, #24]
|
|
8008bd8: 79fb ldrb r3, [r7, #7]
|
|
8008bda: 69ba ldr r2, [r7, #24]
|
|
8008bdc: 429a cmp r2, r3
|
|
8008bde: dbe9 blt.n 8008bb4 <payload_integration+0x1c>
|
|
}
|
|
|
|
for( i = 0; i < ( size * 8 ); i++ )
|
|
8008be0: 2300 movs r3, #0
|
|
8008be2: 61bb str r3, [r7, #24]
|
|
8008be4: e049 b.n 8008c7a <payload_integration+0xe2>
|
|
{
|
|
/* index to take bit in inBuffer */
|
|
index_bit = 7 - ( i % 8 );
|
|
8008be6: 69bb ldr r3, [r7, #24]
|
|
8008be8: 425a negs r2, r3
|
|
8008bea: f003 0307 and.w r3, r3, #7
|
|
8008bee: f002 0207 and.w r2, r2, #7
|
|
8008bf2: bf58 it pl
|
|
8008bf4: 4253 negpl r3, r2
|
|
8008bf6: b2db uxtb r3, r3
|
|
8008bf8: f1c3 0307 rsb r3, r3, #7
|
|
8008bfc: 75fb strb r3, [r7, #23]
|
|
index_byte = i / 8;
|
|
8008bfe: 69bb ldr r3, [r7, #24]
|
|
8008c00: 2b00 cmp r3, #0
|
|
8008c02: da00 bge.n 8008c06 <payload_integration+0x6e>
|
|
8008c04: 3307 adds r3, #7
|
|
8008c06: 10db asrs r3, r3, #3
|
|
8008c08: 75bb strb r3, [r7, #22]
|
|
/* index to place bit in outBuffer is shifted 1 bit right */
|
|
index_bit_out = 7 - ( ( i + 1 ) % 8 );
|
|
8008c0a: 69bb ldr r3, [r7, #24]
|
|
8008c0c: 3301 adds r3, #1
|
|
8008c0e: 425a negs r2, r3
|
|
8008c10: f003 0307 and.w r3, r3, #7
|
|
8008c14: f002 0207 and.w r2, r2, #7
|
|
8008c18: bf58 it pl
|
|
8008c1a: 4253 negpl r3, r2
|
|
8008c1c: b2db uxtb r3, r3
|
|
8008c1e: f1c3 0307 rsb r3, r3, #7
|
|
8008c22: 757b strb r3, [r7, #21]
|
|
index_byte_out = ( i + 1 ) / 8;
|
|
8008c24: 69bb ldr r3, [r7, #24]
|
|
8008c26: 3301 adds r3, #1
|
|
8008c28: 2b00 cmp r3, #0
|
|
8008c2a: da00 bge.n 8008c2e <payload_integration+0x96>
|
|
8008c2c: 3307 adds r3, #7
|
|
8008c2e: 10db asrs r3, r3, #3
|
|
8008c30: 753b strb r3, [r7, #20]
|
|
/* extract current bit from input */
|
|
currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01;
|
|
8008c32: 7dbb ldrb r3, [r7, #22]
|
|
8008c34: 68ba ldr r2, [r7, #8]
|
|
8008c36: 4413 add r3, r2
|
|
8008c38: 781b ldrb r3, [r3, #0]
|
|
8008c3a: 461a mov r2, r3
|
|
8008c3c: 7dfb ldrb r3, [r7, #23]
|
|
8008c3e: fa42 f303 asr.w r3, r2, r3
|
|
8008c42: b2db uxtb r3, r3
|
|
8008c44: f003 0301 and.w r3, r3, #1
|
|
8008c48: 74fb strb r3, [r7, #19]
|
|
/* integration */
|
|
prevInt ^= currBit;
|
|
8008c4a: 7ffa ldrb r2, [r7, #31]
|
|
8008c4c: 7cfb ldrb r3, [r7, #19]
|
|
8008c4e: 4053 eors r3, r2
|
|
8008c50: 77fb strb r3, [r7, #31]
|
|
/* write result integration in output */
|
|
outBuffer[index_byte_out] |= ( prevInt << index_bit_out );
|
|
8008c52: 7d3b ldrb r3, [r7, #20]
|
|
8008c54: 68fa ldr r2, [r7, #12]
|
|
8008c56: 4413 add r3, r2
|
|
8008c58: 781b ldrb r3, [r3, #0]
|
|
8008c5a: b25a sxtb r2, r3
|
|
8008c5c: 7ff9 ldrb r1, [r7, #31]
|
|
8008c5e: 7d7b ldrb r3, [r7, #21]
|
|
8008c60: fa01 f303 lsl.w r3, r1, r3
|
|
8008c64: b25b sxtb r3, r3
|
|
8008c66: 4313 orrs r3, r2
|
|
8008c68: b259 sxtb r1, r3
|
|
8008c6a: 7d3b ldrb r3, [r7, #20]
|
|
8008c6c: 68fa ldr r2, [r7, #12]
|
|
8008c6e: 4413 add r3, r2
|
|
8008c70: b2ca uxtb r2, r1
|
|
8008c72: 701a strb r2, [r3, #0]
|
|
for( i = 0; i < ( size * 8 ); i++ )
|
|
8008c74: 69bb ldr r3, [r7, #24]
|
|
8008c76: 3301 adds r3, #1
|
|
8008c78: 61bb str r3, [r7, #24]
|
|
8008c7a: 79fb ldrb r3, [r7, #7]
|
|
8008c7c: 00db lsls r3, r3, #3
|
|
8008c7e: 69ba ldr r2, [r7, #24]
|
|
8008c80: 429a cmp r2, r3
|
|
8008c82: dbb0 blt.n 8008be6 <payload_integration+0x4e>
|
|
}
|
|
|
|
outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ;
|
|
8008c84: f997 301f ldrsb.w r3, [r7, #31]
|
|
8008c88: 01db lsls r3, r3, #7
|
|
8008c8a: b25a sxtb r2, r3
|
|
8008c8c: f997 301f ldrsb.w r3, [r7, #31]
|
|
8008c90: 019b lsls r3, r3, #6
|
|
8008c92: b25b sxtb r3, r3
|
|
8008c94: 4313 orrs r3, r2
|
|
8008c96: b25b sxtb r3, r3
|
|
8008c98: 7ffa ldrb r2, [r7, #31]
|
|
8008c9a: 2a00 cmp r2, #0
|
|
8008c9c: d101 bne.n 8008ca2 <payload_integration+0x10a>
|
|
8008c9e: 2220 movs r2, #32
|
|
8008ca0: e000 b.n 8008ca4 <payload_integration+0x10c>
|
|
8008ca2: 2200 movs r2, #0
|
|
8008ca4: 4313 orrs r3, r2
|
|
8008ca6: b259 sxtb r1, r3
|
|
8008ca8: 79fb ldrb r3, [r7, #7]
|
|
8008caa: 68fa ldr r2, [r7, #12]
|
|
8008cac: 4413 add r3, r2
|
|
8008cae: b2ca uxtb r2, r1
|
|
8008cb0: 701a strb r2, [r3, #0]
|
|
}
|
|
8008cb2: bf00 nop
|
|
8008cb4: 3724 adds r7, #36 @ 0x24
|
|
8008cb6: 46bd mov sp, r7
|
|
8008cb8: bc80 pop {r7}
|
|
8008cba: 4770 bx lr
|
|
|
|
08008cbc <RadioSetRxGenericConfig>:
|
|
#endif /*RADIO_SIGFOX_ENABLE == 1*/
|
|
|
|
static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous,
|
|
uint32_t symbTimeout )
|
|
{
|
|
8008cbc: b580 push {r7, lr}
|
|
8008cbe: b08c sub sp, #48 @ 0x30
|
|
8008cc0: af00 add r7, sp, #0
|
|
8008cc2: 60b9 str r1, [r7, #8]
|
|
8008cc4: 607a str r2, [r7, #4]
|
|
8008cc6: 603b str r3, [r7, #0]
|
|
8008cc8: 4603 mov r3, r0
|
|
8008cca: 73fb strb r3, [r7, #15]
|
|
#if (RADIO_GENERIC_CONFIG_ENABLE == 1)
|
|
int32_t status = 0;
|
|
8008ccc: 2300 movs r3, #0
|
|
8008cce: 62bb str r3, [r7, #40] @ 0x28
|
|
uint8_t syncword[8] = {0};
|
|
8008cd0: f107 0320 add.w r3, r7, #32
|
|
8008cd4: 2200 movs r2, #0
|
|
8008cd6: 601a str r2, [r3, #0]
|
|
8008cd8: 605a str r2, [r3, #4]
|
|
uint8_t MaxPayloadLength;
|
|
|
|
RFW_DeInit( ); /* switch Off FwPacketDecoding by default */
|
|
8008cda: f002 f88d bl 800adf8 <RFW_DeInit>
|
|
|
|
if( rxContinuous != 0 )
|
|
8008cde: 687b ldr r3, [r7, #4]
|
|
8008ce0: 2b00 cmp r3, #0
|
|
8008ce2: d001 beq.n 8008ce8 <RadioSetRxGenericConfig+0x2c>
|
|
{
|
|
symbTimeout = 0;
|
|
8008ce4: 2300 movs r3, #0
|
|
8008ce6: 603b str r3, [r7, #0]
|
|
}
|
|
SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true;
|
|
8008ce8: 687b ldr r3, [r7, #4]
|
|
8008cea: 2b00 cmp r3, #0
|
|
8008cec: bf14 ite ne
|
|
8008cee: 2301 movne r3, #1
|
|
8008cf0: 2300 moveq r3, #0
|
|
8008cf2: b2da uxtb r2, r3
|
|
8008cf4: 4ba3 ldr r3, [pc, #652] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008cf6: 705a strb r2, [r3, #1]
|
|
|
|
switch( modem )
|
|
8008cf8: 7bfb ldrb r3, [r7, #15]
|
|
8008cfa: 2b00 cmp r3, #0
|
|
8008cfc: d003 beq.n 8008d06 <RadioSetRxGenericConfig+0x4a>
|
|
8008cfe: 2b01 cmp r3, #1
|
|
8008d00: f000 80dc beq.w 8008ebc <RadioSetRxGenericConfig+0x200>
|
|
|
|
// Timeout Max, Timeout handled directly in SetRx function
|
|
SubgRf.RxTimeout = 0xFFFF;
|
|
break;
|
|
default:
|
|
break;
|
|
8008d04: e195 b.n 8009032 <RadioSetRxGenericConfig+0x376>
|
|
if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) )
|
|
8008d06: 68bb ldr r3, [r7, #8]
|
|
8008d08: 689b ldr r3, [r3, #8]
|
|
8008d0a: 2b00 cmp r3, #0
|
|
8008d0c: d003 beq.n 8008d16 <RadioSetRxGenericConfig+0x5a>
|
|
8008d0e: 68bb ldr r3, [r7, #8]
|
|
8008d10: 68db ldr r3, [r3, #12]
|
|
8008d12: 2b00 cmp r3, #0
|
|
8008d14: d102 bne.n 8008d1c <RadioSetRxGenericConfig+0x60>
|
|
return -1;
|
|
8008d16: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8008d1a: e18b b.n 8009034 <RadioSetRxGenericConfig+0x378>
|
|
if( config->fsk.SyncWordLength > 8 )
|
|
8008d1c: 68bb ldr r3, [r7, #8]
|
|
8008d1e: 7f9b ldrb r3, [r3, #30]
|
|
8008d20: 2b08 cmp r3, #8
|
|
8008d22: d902 bls.n 8008d2a <RadioSetRxGenericConfig+0x6e>
|
|
return -1;
|
|
8008d24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8008d28: e184 b.n 8009034 <RadioSetRxGenericConfig+0x378>
|
|
RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength );
|
|
8008d2a: 68bb ldr r3, [r7, #8]
|
|
8008d2c: 6919 ldr r1, [r3, #16]
|
|
8008d2e: 68bb ldr r3, [r7, #8]
|
|
8008d30: 7f9b ldrb r3, [r3, #30]
|
|
8008d32: 461a mov r2, r3
|
|
8008d34: f107 0320 add.w r3, r7, #32
|
|
8008d38: 4618 mov r0, r3
|
|
8008d3a: f003 f9d7 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true );
|
|
8008d3e: 68bb ldr r3, [r7, #8]
|
|
8008d40: 681b ldr r3, [r3, #0]
|
|
8008d42: 2b00 cmp r3, #0
|
|
8008d44: bf14 ite ne
|
|
8008d46: 2301 movne r3, #1
|
|
8008d48: 2300 moveq r3, #0
|
|
8008d4a: b2db uxtb r3, r3
|
|
8008d4c: 4618 mov r0, r3
|
|
8008d4e: f000 fe2b bl 80099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
8008d52: 4b8c ldr r3, [pc, #560] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d54: 2200 movs r2, #0
|
|
8008d56: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate;
|
|
8008d5a: 68bb ldr r3, [r7, #8]
|
|
8008d5c: 689b ldr r3, [r3, #8]
|
|
8008d5e: 4a89 ldr r2, [pc, #548] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d60: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping;
|
|
8008d62: 68bb ldr r3, [r7, #8]
|
|
8008d64: f893 2020 ldrb.w r2, [r3, #32]
|
|
8008d68: 4b86 ldr r3, [pc, #536] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d6a: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth );
|
|
8008d6e: 68bb ldr r3, [r7, #8]
|
|
8008d70: 685b ldr r3, [r3, #4]
|
|
8008d72: 4618 mov r0, r3
|
|
8008d74: f001 fd04 bl 800a780 <SUBGRF_GetFskBandwidthRegValue>
|
|
8008d78: 4603 mov r3, r0
|
|
8008d7a: 461a mov r2, r3
|
|
8008d7c: 4b81 ldr r3, [pc, #516] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d7e: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
8008d82: 4b80 ldr r3, [pc, #512] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d84: 2200 movs r2, #0
|
|
8008d86: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit
|
|
8008d88: 68bb ldr r3, [r7, #8]
|
|
8008d8a: 68db ldr r3, [r3, #12]
|
|
8008d8c: b29b uxth r3, r3
|
|
8008d8e: 00db lsls r3, r3, #3
|
|
8008d90: b29a uxth r2, r3
|
|
8008d92: 4b7c ldr r3, [pc, #496] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d94: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect;
|
|
8008d96: 68bb ldr r3, [r7, #8]
|
|
8008d98: 7fda ldrb r2, [r3, #31]
|
|
8008d9a: 4b7a ldr r3, [pc, #488] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008d9c: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit
|
|
8008d9e: 68bb ldr r3, [r7, #8]
|
|
8008da0: 7f9b ldrb r3, [r3, #30]
|
|
8008da2: 00db lsls r3, r3, #3
|
|
8008da4: b2da uxtb r2, r3
|
|
8008da6: 4b77 ldr r3, [pc, #476] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008da8: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp;
|
|
8008daa: 68bb ldr r3, [r7, #8]
|
|
8008dac: f893 2021 ldrb.w r2, [r3, #33] @ 0x21
|
|
8008db0: 4b74 ldr r3, [pc, #464] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008db2: 751a strb r2, [r3, #20]
|
|
if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH )
|
|
8008db4: 68bb ldr r3, [r7, #8]
|
|
8008db6: f893 3022 ldrb.w r3, [r3, #34] @ 0x22
|
|
8008dba: 2b00 cmp r3, #0
|
|
8008dbc: d105 bne.n 8008dca <RadioSetRxGenericConfig+0x10e>
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength;
|
|
8008dbe: 68bb ldr r3, [r7, #8]
|
|
8008dc0: 695b ldr r3, [r3, #20]
|
|
8008dc2: b2da uxtb r2, r3
|
|
8008dc4: 4b6f ldr r3, [pc, #444] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008dc6: 759a strb r2, [r3, #22]
|
|
8008dc8: e00b b.n 8008de2 <RadioSetRxGenericConfig+0x126>
|
|
else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH )
|
|
8008dca: 68bb ldr r3, [r7, #8]
|
|
8008dcc: f893 3022 ldrb.w r3, [r3, #34] @ 0x22
|
|
8008dd0: 2b02 cmp r3, #2
|
|
8008dd2: d103 bne.n 8008ddc <RadioSetRxGenericConfig+0x120>
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF;
|
|
8008dd4: 4b6b ldr r3, [pc, #428] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008dd6: 22ff movs r2, #255 @ 0xff
|
|
8008dd8: 759a strb r2, [r3, #22]
|
|
8008dda: e002 b.n 8008de2 <RadioSetRxGenericConfig+0x126>
|
|
SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF;
|
|
8008ddc: 4b69 ldr r3, [pc, #420] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008dde: 22ff movs r2, #255 @ 0xff
|
|
8008de0: 759a strb r2, [r3, #22]
|
|
if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING )
|
|
8008de2: 68bb ldr r3, [r7, #8]
|
|
8008de4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8008de8: 2b02 cmp r3, #2
|
|
8008dea: d004 beq.n 8008df6 <RadioSetRxGenericConfig+0x13a>
|
|
|| ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) )
|
|
8008dec: 68bb ldr r3, [r7, #8]
|
|
8008dee: f893 3022 ldrb.w r3, [r3, #34] @ 0x22
|
|
8008df2: 2b02 cmp r3, #2
|
|
8008df4: d12d bne.n 8008e52 <RadioSetRxGenericConfig+0x196>
|
|
if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT )
|
|
8008df6: 68bb ldr r3, [r7, #8]
|
|
8008df8: f893 3023 ldrb.w r3, [r3, #35] @ 0x23
|
|
8008dfc: 2bf1 cmp r3, #241 @ 0xf1
|
|
8008dfe: d00c beq.n 8008e1a <RadioSetRxGenericConfig+0x15e>
|
|
8008e00: 68bb ldr r3, [r7, #8]
|
|
8008e02: f893 3023 ldrb.w r3, [r3, #35] @ 0x23
|
|
8008e06: 2bf2 cmp r3, #242 @ 0xf2
|
|
8008e08: d007 beq.n 8008e1a <RadioSetRxGenericConfig+0x15e>
|
|
&& ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) )
|
|
8008e0a: 68bb ldr r3, [r7, #8]
|
|
8008e0c: f893 3023 ldrb.w r3, [r3, #35] @ 0x23
|
|
8008e10: 2b01 cmp r3, #1
|
|
8008e12: d002 beq.n 8008e1a <RadioSetRxGenericConfig+0x15e>
|
|
return -1;
|
|
8008e14: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8008e18: e10c b.n 8009034 <RadioSetRxGenericConfig+0x378>
|
|
ConfigGeneric.rtx = CONFIG_RX;
|
|
8008e1a: 2300 movs r3, #0
|
|
8008e1c: 773b strb r3, [r7, #28]
|
|
ConfigGeneric.RxConfig = config;
|
|
8008e1e: 68bb ldr r3, [r7, #8]
|
|
8008e20: 61bb str r3, [r7, #24]
|
|
if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) )
|
|
8008e22: 4b59 ldr r3, [pc, #356] @ (8008f88 <RadioSetRxGenericConfig+0x2cc>)
|
|
8008e24: 6819 ldr r1, [r3, #0]
|
|
8008e26: f107 0314 add.w r3, r7, #20
|
|
8008e2a: 4a58 ldr r2, [pc, #352] @ (8008f8c <RadioSetRxGenericConfig+0x2d0>)
|
|
8008e2c: 4618 mov r0, r3
|
|
8008e2e: f001 ff49 bl 800acc4 <RFW_Init>
|
|
8008e32: 4603 mov r3, r0
|
|
8008e34: 2b00 cmp r3, #0
|
|
8008e36: d002 beq.n 8008e3e <RadioSetRxGenericConfig+0x182>
|
|
return -1;
|
|
8008e38: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8008e3c: e0fa b.n 8009034 <RadioSetRxGenericConfig+0x378>
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF;
|
|
8008e3e: 4b51 ldr r3, [pc, #324] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e40: 2200 movs r2, #0
|
|
8008e42: 761a strb r2, [r3, #24]
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF;
|
|
8008e44: 4b4f ldr r3, [pc, #316] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e46: 2201 movs r2, #1
|
|
8008e48: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH;
|
|
8008e4a: 4b4e ldr r3, [pc, #312] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e4c: 2200 movs r2, #0
|
|
8008e4e: 755a strb r2, [r3, #21]
|
|
{
|
|
8008e50: e00e b.n 8008e70 <RadioSetRxGenericConfig+0x1b4>
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength;
|
|
8008e52: 68bb ldr r3, [r7, #8]
|
|
8008e54: f893 2023 ldrb.w r2, [r3, #35] @ 0x23
|
|
8008e58: 4b4a ldr r3, [pc, #296] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e5a: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening;
|
|
8008e5c: 68bb ldr r3, [r7, #8]
|
|
8008e5e: f893 2024 ldrb.w r2, [r3, #36] @ 0x24
|
|
8008e62: 4b48 ldr r3, [pc, #288] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e64: 761a strb r2, [r3, #24]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode;
|
|
8008e66: 68bb ldr r3, [r7, #8]
|
|
8008e68: f893 2022 ldrb.w r2, [r3, #34] @ 0x22
|
|
8008e6c: 4b45 ldr r3, [pc, #276] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008e6e: 755a strb r2, [r3, #21]
|
|
RadioStandby( );
|
|
8008e70: f7ff fa0d bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_FSK );
|
|
8008e74: 2000 movs r0, #0
|
|
8008e76: f7fe fb9b bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8008e7a: 4845 ldr r0, [pc, #276] @ (8008f90 <RadioSetRxGenericConfig+0x2d4>)
|
|
8008e7c: f001 f838 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008e80: 4844 ldr r0, [pc, #272] @ (8008f94 <RadioSetRxGenericConfig+0x2d8>)
|
|
8008e82: f001 f903 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( syncword );
|
|
8008e86: f107 0320 add.w r3, r7, #32
|
|
8008e8a: 4618 mov r0, r3
|
|
8008e8c: f000 fbc3 bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed );
|
|
8008e90: 68bb ldr r3, [r7, #8]
|
|
8008e92: 8b9b ldrh r3, [r3, #28]
|
|
8008e94: 4618 mov r0, r3
|
|
8008e96: f000 fc0d bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial );
|
|
8008e9a: 68bb ldr r3, [r7, #8]
|
|
8008e9c: 8b1b ldrh r3, [r3, #24]
|
|
8008e9e: 4618 mov r0, r3
|
|
8008ea0: f000 fbe8 bl 8009674 <SUBGRF_SetCrcPolynomial>
|
|
SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate );
|
|
8008ea4: 683b ldr r3, [r7, #0]
|
|
8008ea6: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
8008eaa: fb03 f202 mul.w r2, r3, r2
|
|
8008eae: 68bb ldr r3, [r7, #8]
|
|
8008eb0: 689b ldr r3, [r3, #8]
|
|
8008eb2: fbb2 f3f3 udiv r3, r2, r3
|
|
8008eb6: 4a33 ldr r2, [pc, #204] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008eb8: 6093 str r3, [r2, #8]
|
|
break;
|
|
8008eba: e0ba b.n 8009032 <RadioSetRxGenericConfig+0x376>
|
|
if( config->lora.PreambleLen == 0 )
|
|
8008ebc: 68bb ldr r3, [r7, #8]
|
|
8008ebe: 8e1b ldrh r3, [r3, #48] @ 0x30
|
|
8008ec0: 2b00 cmp r3, #0
|
|
8008ec2: d102 bne.n 8008eca <RadioSetRxGenericConfig+0x20e>
|
|
return -1;
|
|
8008ec4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8008ec8: e0b4 b.n 8009034 <RadioSetRxGenericConfig+0x378>
|
|
if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH )
|
|
8008eca: 68bb ldr r3, [r7, #8]
|
|
8008ecc: f893 3032 ldrb.w r3, [r3, #50] @ 0x32
|
|
8008ed0: 2b01 cmp r3, #1
|
|
8008ed2: d105 bne.n 8008ee0 <RadioSetRxGenericConfig+0x224>
|
|
MaxPayloadLength = config->lora.MaxPayloadLength;
|
|
8008ed4: 68bb ldr r3, [r7, #8]
|
|
8008ed6: f893 3033 ldrb.w r3, [r3, #51] @ 0x33
|
|
8008eda: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
8008ede: e002 b.n 8008ee6 <RadioSetRxGenericConfig+0x22a>
|
|
MaxPayloadLength = 0xFF;
|
|
8008ee0: 23ff movs r3, #255 @ 0xff
|
|
8008ee2: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true );
|
|
8008ee6: 68bb ldr r3, [r7, #8]
|
|
8008ee8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008eea: 2b00 cmp r3, #0
|
|
8008eec: bf14 ite ne
|
|
8008eee: 2301 movne r3, #1
|
|
8008ef0: 2300 moveq r3, #0
|
|
8008ef2: b2db uxtb r3, r3
|
|
8008ef4: 4618 mov r0, r3
|
|
8008ef6: f000 fd57 bl 80099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>
|
|
SUBGRF_SetLoRaSymbNumTimeout( symbTimeout );
|
|
8008efa: 683b ldr r3, [r7, #0]
|
|
8008efc: b2db uxtb r3, r3
|
|
8008efe: 4618 mov r0, r3
|
|
8008f00: f000 fd61 bl 80099c6 <SUBGRF_SetLoRaSymbNumTimeout>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA;
|
|
8008f04: 4b1f ldr r3, [pc, #124] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f06: 2201 movs r2, #1
|
|
8008f08: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor;
|
|
8008f0c: 68bb ldr r3, [r7, #8]
|
|
8008f0e: f893 202c ldrb.w r2, [r3, #44] @ 0x2c
|
|
8008f12: 4b1c ldr r3, [pc, #112] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f14: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth;
|
|
8008f18: 68bb ldr r3, [r7, #8]
|
|
8008f1a: f893 202d ldrb.w r2, [r3, #45] @ 0x2d
|
|
8008f1e: 4b19 ldr r3, [pc, #100] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f20: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate;
|
|
8008f24: 68bb ldr r3, [r7, #8]
|
|
8008f26: f893 202e ldrb.w r2, [r3, #46] @ 0x2e
|
|
8008f2a: 4b16 ldr r3, [pc, #88] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f2c: f883 2052 strb.w r2, [r3, #82] @ 0x52
|
|
switch( config->lora.LowDatarateOptimize )
|
|
8008f30: 68bb ldr r3, [r7, #8]
|
|
8008f32: f893 302f ldrb.w r3, [r3, #47] @ 0x2f
|
|
8008f36: 2b02 cmp r3, #2
|
|
8008f38: d010 beq.n 8008f5c <RadioSetRxGenericConfig+0x2a0>
|
|
8008f3a: 2b02 cmp r3, #2
|
|
8008f3c: dc2c bgt.n 8008f98 <RadioSetRxGenericConfig+0x2dc>
|
|
8008f3e: 2b00 cmp r3, #0
|
|
8008f40: d002 beq.n 8008f48 <RadioSetRxGenericConfig+0x28c>
|
|
8008f42: 2b01 cmp r3, #1
|
|
8008f44: d005 beq.n 8008f52 <RadioSetRxGenericConfig+0x296>
|
|
break;
|
|
8008f46: e027 b.n 8008f98 <RadioSetRxGenericConfig+0x2dc>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0;
|
|
8008f48: 4b0e ldr r3, [pc, #56] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f4a: 2200 movs r2, #0
|
|
8008f4c: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8008f50: e023 b.n 8008f9a <RadioSetRxGenericConfig+0x2de>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1;
|
|
8008f52: 4b0c ldr r3, [pc, #48] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f54: 2201 movs r2, #1
|
|
8008f56: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8008f5a: e01e b.n 8008f9a <RadioSetRxGenericConfig+0x2de>
|
|
if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) )
|
|
8008f5c: 68bb ldr r3, [r7, #8]
|
|
8008f5e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
8008f62: 2b0b cmp r3, #11
|
|
8008f64: d004 beq.n 8008f70 <RadioSetRxGenericConfig+0x2b4>
|
|
8008f66: 68bb ldr r3, [r7, #8]
|
|
8008f68: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
8008f6c: 2b0c cmp r3, #12
|
|
8008f6e: d104 bne.n 8008f7a <RadioSetRxGenericConfig+0x2be>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1;
|
|
8008f70: 4b04 ldr r3, [pc, #16] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f72: 2201 movs r2, #1
|
|
8008f74: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8008f78: e00f b.n 8008f9a <RadioSetRxGenericConfig+0x2de>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0;
|
|
8008f7a: 4b02 ldr r3, [pc, #8] @ (8008f84 <RadioSetRxGenericConfig+0x2c8>)
|
|
8008f7c: 2200 movs r2, #0
|
|
8008f7e: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8008f82: e00a b.n 8008f9a <RadioSetRxGenericConfig+0x2de>
|
|
8008f84: 20000290 .word 0x20000290
|
|
8008f88: 2000028c .word 0x2000028c
|
|
8008f8c: 20000304 .word 0x20000304
|
|
8008f90: 200002c8 .word 0x200002c8
|
|
8008f94: 2000029e .word 0x2000029e
|
|
break;
|
|
8008f98: bf00 nop
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA;
|
|
8008f9a: 4b28 ldr r3, [pc, #160] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008f9c: 2201 movs r2, #1
|
|
8008f9e: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen;
|
|
8008fa0: 68bb ldr r3, [r7, #8]
|
|
8008fa2: 8e1a ldrh r2, [r3, #48] @ 0x30
|
|
8008fa4: 4b25 ldr r3, [pc, #148] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fa6: 839a strh r2, [r3, #28]
|
|
SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode;
|
|
8008fa8: 68bb ldr r3, [r7, #8]
|
|
8008faa: f893 2032 ldrb.w r2, [r3, #50] @ 0x32
|
|
8008fae: 4b23 ldr r3, [pc, #140] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fb0: 779a strb r2, [r3, #30]
|
|
SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength;
|
|
8008fb2: 4a22 ldr r2, [pc, #136] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fb4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8008fb8: 77d3 strb r3, [r2, #31]
|
|
SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode;
|
|
8008fba: 68bb ldr r3, [r7, #8]
|
|
8008fbc: f893 2034 ldrb.w r2, [r3, #52] @ 0x34
|
|
8008fc0: 4b1e ldr r3, [pc, #120] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fc2: f883 2020 strb.w r2, [r3, #32]
|
|
SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted;
|
|
8008fc6: 68bb ldr r3, [r7, #8]
|
|
8008fc8: f893 2035 ldrb.w r2, [r3, #53] @ 0x35
|
|
8008fcc: 4b1b ldr r3, [pc, #108] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fce: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
RadioStandby( );
|
|
8008fd2: f7ff f95c bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_LORA );
|
|
8008fd6: 2001 movs r0, #1
|
|
8008fd8: f7fe faea bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8008fdc: 4818 ldr r0, [pc, #96] @ (8009040 <RadioSetRxGenericConfig+0x384>)
|
|
8008fde: f000 ff87 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8008fe2: 4818 ldr r0, [pc, #96] @ (8009044 <RadioSetRxGenericConfig+0x388>)
|
|
8008fe4: f001 f852 bl 800a08c <SUBGRF_SetPacketParams>
|
|
if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED )
|
|
8008fe8: 4b14 ldr r3, [pc, #80] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
8008fea: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
8008fee: 2b01 cmp r3, #1
|
|
8008ff0: d10d bne.n 800900e <RadioSetRxGenericConfig+0x352>
|
|
SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) );
|
|
8008ff2: f240 7036 movw r0, #1846 @ 0x736
|
|
8008ff6: f001 f9b1 bl 800a35c <SUBGRF_ReadRegister>
|
|
8008ffa: 4603 mov r3, r0
|
|
8008ffc: f023 0304 bic.w r3, r3, #4
|
|
8009000: b2db uxtb r3, r3
|
|
8009002: 4619 mov r1, r3
|
|
8009004: f240 7036 movw r0, #1846 @ 0x736
|
|
8009008: f001 f986 bl 800a318 <SUBGRF_WriteRegister>
|
|
800900c: e00c b.n 8009028 <RadioSetRxGenericConfig+0x36c>
|
|
SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) );
|
|
800900e: f240 7036 movw r0, #1846 @ 0x736
|
|
8009012: f001 f9a3 bl 800a35c <SUBGRF_ReadRegister>
|
|
8009016: 4603 mov r3, r0
|
|
8009018: f043 0304 orr.w r3, r3, #4
|
|
800901c: b2db uxtb r3, r3
|
|
800901e: 4619 mov r1, r3
|
|
8009020: f240 7036 movw r0, #1846 @ 0x736
|
|
8009024: f001 f978 bl 800a318 <SUBGRF_WriteRegister>
|
|
SubgRf.RxTimeout = 0xFFFF;
|
|
8009028: 4b04 ldr r3, [pc, #16] @ (800903c <RadioSetRxGenericConfig+0x380>)
|
|
800902a: f64f 72ff movw r2, #65535 @ 0xffff
|
|
800902e: 609a str r2, [r3, #8]
|
|
break;
|
|
8009030: bf00 nop
|
|
}
|
|
return status;
|
|
8009032: 6abb ldr r3, [r7, #40] @ 0x28
|
|
#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/
|
|
return -1;
|
|
#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/
|
|
}
|
|
8009034: 4618 mov r0, r3
|
|
8009036: 3730 adds r7, #48 @ 0x30
|
|
8009038: 46bd mov sp, r7
|
|
800903a: bd80 pop {r7, pc}
|
|
800903c: 20000290 .word 0x20000290
|
|
8009040: 200002c8 .word 0x200002c8
|
|
8009044: 2000029e .word 0x2000029e
|
|
|
|
08009048 <RadioSetTxGenericConfig>:
|
|
|
|
static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power,
|
|
uint32_t timeout )
|
|
{
|
|
8009048: b580 push {r7, lr}
|
|
800904a: b08e sub sp, #56 @ 0x38
|
|
800904c: af00 add r7, sp, #0
|
|
800904e: 60b9 str r1, [r7, #8]
|
|
8009050: 607b str r3, [r7, #4]
|
|
8009052: 4603 mov r3, r0
|
|
8009054: 73fb strb r3, [r7, #15]
|
|
8009056: 4613 mov r3, r2
|
|
8009058: 73bb strb r3, [r7, #14]
|
|
#if( RADIO_LR_FHSS_IS_ON == 1 )
|
|
/*disable LrFhss*/
|
|
SubgRf.lr_fhss.is_lr_fhss_on = false;
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
#if (RADIO_GENERIC_CONFIG_ENABLE == 1)
|
|
uint8_t syncword[8] = {0};
|
|
800905a: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
800905e: 2200 movs r2, #0
|
|
8009060: 601a str r2, [r3, #0]
|
|
8009062: 605a str r2, [r3, #4]
|
|
RadioModems_t radio_modem;
|
|
RFW_DeInit( ); /* switch Off FwPacketDecoding by default */
|
|
8009064: f001 fec8 bl 800adf8 <RFW_DeInit>
|
|
switch( modem )
|
|
8009068: 7bfb ldrb r3, [r7, #15]
|
|
800906a: 2b03 cmp r3, #3
|
|
800906c: f200 8205 bhi.w 800947a <RadioSetTxGenericConfig+0x432>
|
|
8009070: a201 add r2, pc, #4 @ (adr r2, 8009078 <RadioSetTxGenericConfig+0x30>)
|
|
8009072: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009076: bf00 nop
|
|
8009078: 080091fd .word 0x080091fd
|
|
800907c: 08009345 .word 0x08009345
|
|
8009080: 0800943d .word 0x0800943d
|
|
8009084: 08009089 .word 0x08009089
|
|
{
|
|
case GENERIC_MSK:
|
|
if( config->msk.SyncWordLength > 8 )
|
|
8009088: 68bb ldr r3, [r7, #8]
|
|
800908a: 7c9b ldrb r3, [r3, #18]
|
|
800908c: 2b08 cmp r3, #8
|
|
800908e: d902 bls.n 8009096 <RadioSetTxGenericConfig+0x4e>
|
|
{
|
|
return -1;
|
|
8009090: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8009094: e206 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
else
|
|
{
|
|
RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength );
|
|
8009096: 68bb ldr r3, [r7, #8]
|
|
8009098: 6899 ldr r1, [r3, #8]
|
|
800909a: 68bb ldr r3, [r7, #8]
|
|
800909c: 7c9b ldrb r3, [r3, #18]
|
|
800909e: 461a mov r2, r3
|
|
80090a0: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80090a4: 4618 mov r0, r3
|
|
80090a6: f003 f821 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
}
|
|
if( ( config->msk.BitRate == 0 ) )
|
|
80090aa: 68bb ldr r3, [r7, #8]
|
|
80090ac: 681b ldr r3, [r3, #0]
|
|
80090ae: 2b00 cmp r3, #0
|
|
80090b0: d102 bne.n 80090b8 <RadioSetTxGenericConfig+0x70>
|
|
{
|
|
return -1;
|
|
80090b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80090b6: e1f5 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
else if( config->msk.BitRate <= 10000 )
|
|
80090b8: 68bb ldr r3, [r7, #8]
|
|
80090ba: 681b ldr r3, [r3, #0]
|
|
80090bc: f242 7210 movw r2, #10000 @ 0x2710
|
|
80090c0: 4293 cmp r3, r2
|
|
80090c2: d813 bhi.n 80090ec <RadioSetTxGenericConfig+0xa4>
|
|
{
|
|
/*max msk modulator datarate is 10kbps*/
|
|
radio_modem = MODEM_MSK;
|
|
80090c4: 2302 movs r3, #2
|
|
80090c6: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK;
|
|
80090ca: 4b99 ldr r3, [pc, #612] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090cc: 2203 movs r2, #3
|
|
80090ce: 739a strb r2, [r3, #14]
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK;
|
|
80090d0: 4b97 ldr r3, [pc, #604] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090d2: 2203 movs r2, #3
|
|
80090d4: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate;
|
|
80090d8: 68bb ldr r3, [r7, #8]
|
|
80090da: 681b ldr r3, [r3, #0]
|
|
80090dc: 4a94 ldr r2, [pc, #592] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090de: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping;
|
|
80090e0: 68bb ldr r3, [r7, #8]
|
|
80090e2: 7cda ldrb r2, [r3, #19]
|
|
80090e4: 4b92 ldr r3, [pc, #584] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090e6: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
80090ea: e017 b.n 800911c <RadioSetTxGenericConfig+0xd4>
|
|
}
|
|
else
|
|
{
|
|
radio_modem = MODEM_FSK;
|
|
80090ec: 2300 movs r3, #0
|
|
80090ee: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
80090f2: 4b8f ldr r3, [pc, #572] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090f4: 2200 movs r2, #0
|
|
80090f6: 739a strb r2, [r3, #14]
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
80090f8: 4b8d ldr r3, [pc, #564] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80090fa: 2200 movs r2, #0
|
|
80090fc: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate;
|
|
8009100: 68bb ldr r3, [r7, #8]
|
|
8009102: 681b ldr r3, [r3, #0]
|
|
8009104: 4a8a ldr r2, [pc, #552] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009106: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping;
|
|
8009108: 68bb ldr r3, [r7, #8]
|
|
800910a: 7cda ldrb r2, [r3, #19]
|
|
800910c: 4b88 ldr r3, [pc, #544] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800910e: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
/*do msk with gfsk modulator*/
|
|
SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4;
|
|
8009112: 68bb ldr r3, [r7, #8]
|
|
8009114: 681b ldr r3, [r3, #0]
|
|
8009116: 089b lsrs r3, r3, #2
|
|
8009118: 4a85 ldr r2, [pc, #532] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800911a: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit
|
|
800911c: 68bb ldr r3, [r7, #8]
|
|
800911e: 685b ldr r3, [r3, #4]
|
|
8009120: b29b uxth r3, r3
|
|
8009122: 00db lsls r3, r3, #3
|
|
8009124: b29a uxth r2, r3
|
|
8009126: 4b82 ldr r3, [pc, #520] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009128: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx
|
|
800912a: 4b81 ldr r3, [pc, #516] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800912c: 2204 movs r2, #4
|
|
800912e: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit
|
|
8009130: 68bb ldr r3, [r7, #8]
|
|
8009132: 7c9b ldrb r3, [r3, #18]
|
|
8009134: 00db lsls r3, r3, #3
|
|
8009136: b2da uxtb r2, r3
|
|
8009138: 4b7d ldr r3, [pc, #500] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800913a: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx
|
|
800913c: 4b7c ldr r3, [pc, #496] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800913e: 2200 movs r2, #0
|
|
8009140: 751a strb r2, [r3, #20]
|
|
|
|
if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING )
|
|
8009142: 68bb ldr r3, [r7, #8]
|
|
8009144: 7d9b ldrb r3, [r3, #22]
|
|
8009146: 2b02 cmp r3, #2
|
|
8009148: d003 beq.n 8009152 <RadioSetTxGenericConfig+0x10a>
|
|
|| ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) )
|
|
800914a: 68bb ldr r3, [r7, #8]
|
|
800914c: 7d1b ldrb r3, [r3, #20]
|
|
800914e: 2b02 cmp r3, #2
|
|
8009150: d12b bne.n 80091aa <RadioSetTxGenericConfig+0x162>
|
|
{
|
|
/* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */
|
|
if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT )
|
|
8009152: 68bb ldr r3, [r7, #8]
|
|
8009154: 7d5b ldrb r3, [r3, #21]
|
|
8009156: 2bf1 cmp r3, #241 @ 0xf1
|
|
8009158: d00a beq.n 8009170 <RadioSetTxGenericConfig+0x128>
|
|
800915a: 68bb ldr r3, [r7, #8]
|
|
800915c: 7d5b ldrb r3, [r3, #21]
|
|
800915e: 2bf2 cmp r3, #242 @ 0xf2
|
|
8009160: d006 beq.n 8009170 <RadioSetTxGenericConfig+0x128>
|
|
&& ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) )
|
|
8009162: 68bb ldr r3, [r7, #8]
|
|
8009164: 7d5b ldrb r3, [r3, #21]
|
|
8009166: 2b01 cmp r3, #1
|
|
8009168: d002 beq.n 8009170 <RadioSetTxGenericConfig+0x128>
|
|
{
|
|
return -1;
|
|
800916a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800916e: e199 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
ConfigGeneric_t ConfigGeneric;
|
|
/*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/
|
|
ConfigGeneric.TxConfig = config;
|
|
8009170: 68bb ldr r3, [r7, #8]
|
|
8009172: 623b str r3, [r7, #32]
|
|
ConfigGeneric.rtx = CONFIG_TX;
|
|
8009174: 2301 movs r3, #1
|
|
8009176: f887 3028 strb.w r3, [r7, #40] @ 0x28
|
|
if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) )
|
|
800917a: 4b6e ldr r3, [pc, #440] @ (8009334 <RadioSetTxGenericConfig+0x2ec>)
|
|
800917c: 6819 ldr r1, [r3, #0]
|
|
800917e: f107 0320 add.w r3, r7, #32
|
|
8009182: 4a6d ldr r2, [pc, #436] @ (8009338 <RadioSetTxGenericConfig+0x2f0>)
|
|
8009184: 4618 mov r0, r3
|
|
8009186: f001 fd9d bl 800acc4 <RFW_Init>
|
|
800918a: 4603 mov r3, r0
|
|
800918c: 2b00 cmp r3, #0
|
|
800918e: d002 beq.n 8009196 <RadioSetTxGenericConfig+0x14e>
|
|
{
|
|
return -1;
|
|
8009190: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8009194: e186 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
/* whitening off, will be processed by FW, switch off built-in radio whitening */
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF;
|
|
8009196: 4b66 ldr r3, [pc, #408] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009198: 2200 movs r2, #0
|
|
800919a: 761a strb r2, [r3, #24]
|
|
/* Crc processed by FW, switch off built-in radio Crc */
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF;
|
|
800919c: 4b64 ldr r3, [pc, #400] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800919e: 2201 movs r2, #1
|
|
80091a0: 75da strb r2, [r3, #23]
|
|
/* length contained in Tx, but will be processed by FW after de-whitening */
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH;
|
|
80091a2: 4b63 ldr r3, [pc, #396] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80091a4: 2200 movs r2, #0
|
|
80091a6: 755a strb r2, [r3, #21]
|
|
{
|
|
80091a8: e00b b.n 80091c2 <RadioSetTxGenericConfig+0x17a>
|
|
}
|
|
else
|
|
{
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength;
|
|
80091aa: 68bb ldr r3, [r7, #8]
|
|
80091ac: 7d5a ldrb r2, [r3, #21]
|
|
80091ae: 4b60 ldr r3, [pc, #384] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80091b0: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening;
|
|
80091b2: 68bb ldr r3, [r7, #8]
|
|
80091b4: 7d9a ldrb r2, [r3, #22]
|
|
80091b6: 4b5e ldr r3, [pc, #376] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80091b8: 761a strb r2, [r3, #24]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType;
|
|
80091ba: 68bb ldr r3, [r7, #8]
|
|
80091bc: 7d1a ldrb r2, [r3, #20]
|
|
80091be: 4b5c ldr r3, [pc, #368] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80091c0: 755a strb r2, [r3, #21]
|
|
}
|
|
|
|
RadioStandby( );
|
|
80091c2: f7ff f864 bl 800828e <RadioStandby>
|
|
RadioSetModem( radio_modem );
|
|
80091c6: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
80091ca: 4618 mov r0, r3
|
|
80091cc: f7fe f9f0 bl 80075b0 <RadioSetModem>
|
|
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
80091d0: 485a ldr r0, [pc, #360] @ (800933c <RadioSetTxGenericConfig+0x2f4>)
|
|
80091d2: f000 fe8d bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
80091d6: 485a ldr r0, [pc, #360] @ (8009340 <RadioSetTxGenericConfig+0x2f8>)
|
|
80091d8: f000 ff58 bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( syncword );
|
|
80091dc: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80091e0: 4618 mov r0, r3
|
|
80091e2: f000 fa18 bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( config->msk.whiteSeed );
|
|
80091e6: 68bb ldr r3, [r7, #8]
|
|
80091e8: 8a1b ldrh r3, [r3, #16]
|
|
80091ea: 4618 mov r0, r3
|
|
80091ec: f000 fa62 bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial );
|
|
80091f0: 68bb ldr r3, [r7, #8]
|
|
80091f2: 899b ldrh r3, [r3, #12]
|
|
80091f4: 4618 mov r0, r3
|
|
80091f6: f000 fa3d bl 8009674 <SUBGRF_SetCrcPolynomial>
|
|
break;
|
|
80091fa: e13f b.n 800947c <RadioSetTxGenericConfig+0x434>
|
|
case GENERIC_FSK:
|
|
if( config->fsk.BitRate == 0 )
|
|
80091fc: 68bb ldr r3, [r7, #8]
|
|
80091fe: 681b ldr r3, [r3, #0]
|
|
8009200: 2b00 cmp r3, #0
|
|
8009202: d102 bne.n 800920a <RadioSetTxGenericConfig+0x1c2>
|
|
{
|
|
return -1;
|
|
8009204: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8009208: e14c b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
if( config->fsk.SyncWordLength > 8 )
|
|
800920a: 68bb ldr r3, [r7, #8]
|
|
800920c: 7c9b ldrb r3, [r3, #18]
|
|
800920e: 2b08 cmp r3, #8
|
|
8009210: d902 bls.n 8009218 <RadioSetTxGenericConfig+0x1d0>
|
|
{
|
|
return -1;
|
|
8009212: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8009216: e145 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
else
|
|
{
|
|
RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength );
|
|
8009218: 68bb ldr r3, [r7, #8]
|
|
800921a: 6899 ldr r1, [r3, #8]
|
|
800921c: 68bb ldr r3, [r7, #8]
|
|
800921e: 7c9b ldrb r3, [r3, #18]
|
|
8009220: 461a mov r2, r3
|
|
8009222: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8009226: 4618 mov r0, r3
|
|
8009228: f002 ff60 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
}
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK;
|
|
800922c: 4b40 ldr r3, [pc, #256] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800922e: 2200 movs r2, #0
|
|
8009230: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate;
|
|
8009234: 68bb ldr r3, [r7, #8]
|
|
8009236: 681b ldr r3, [r3, #0]
|
|
8009238: 4a3d ldr r2, [pc, #244] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800923a: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping;
|
|
800923c: 68bb ldr r3, [r7, #8]
|
|
800923e: 7cda ldrb r2, [r3, #19]
|
|
8009240: 4b3b ldr r3, [pc, #236] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009242: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation;
|
|
8009246: 68bb ldr r3, [r7, #8]
|
|
8009248: 699b ldr r3, [r3, #24]
|
|
800924a: 4a39 ldr r2, [pc, #228] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
800924c: 6413 str r3, [r2, #64] @ 0x40
|
|
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK;
|
|
800924e: 4b38 ldr r3, [pc, #224] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009250: 2200 movs r2, #0
|
|
8009252: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit
|
|
8009254: 68bb ldr r3, [r7, #8]
|
|
8009256: 685b ldr r3, [r3, #4]
|
|
8009258: b29b uxth r3, r3
|
|
800925a: 00db lsls r3, r3, #3
|
|
800925c: b29a uxth r2, r3
|
|
800925e: 4b34 ldr r3, [pc, #208] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009260: 821a strh r2, [r3, #16]
|
|
SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx
|
|
8009262: 4b33 ldr r3, [pc, #204] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009264: 2204 movs r2, #4
|
|
8009266: 749a strb r2, [r3, #18]
|
|
SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit
|
|
8009268: 68bb ldr r3, [r7, #8]
|
|
800926a: 7c9b ldrb r3, [r3, #18]
|
|
800926c: 00db lsls r3, r3, #3
|
|
800926e: b2da uxtb r2, r3
|
|
8009270: 4b2f ldr r3, [pc, #188] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009272: 74da strb r2, [r3, #19]
|
|
SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx
|
|
8009274: 4b2e ldr r3, [pc, #184] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
8009276: 2200 movs r2, #0
|
|
8009278: 751a strb r2, [r3, #20]
|
|
|
|
if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING )
|
|
800927a: 68bb ldr r3, [r7, #8]
|
|
800927c: 7d9b ldrb r3, [r3, #22]
|
|
800927e: 2b02 cmp r3, #2
|
|
8009280: d003 beq.n 800928a <RadioSetTxGenericConfig+0x242>
|
|
|| ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) )
|
|
8009282: 68bb ldr r3, [r7, #8]
|
|
8009284: 7d1b ldrb r3, [r3, #20]
|
|
8009286: 2b02 cmp r3, #2
|
|
8009288: d12a bne.n 80092e0 <RadioSetTxGenericConfig+0x298>
|
|
{
|
|
/* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */
|
|
if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT )
|
|
800928a: 68bb ldr r3, [r7, #8]
|
|
800928c: 7d5b ldrb r3, [r3, #21]
|
|
800928e: 2bf1 cmp r3, #241 @ 0xf1
|
|
8009290: d00a beq.n 80092a8 <RadioSetTxGenericConfig+0x260>
|
|
8009292: 68bb ldr r3, [r7, #8]
|
|
8009294: 7d5b ldrb r3, [r3, #21]
|
|
8009296: 2bf2 cmp r3, #242 @ 0xf2
|
|
8009298: d006 beq.n 80092a8 <RadioSetTxGenericConfig+0x260>
|
|
&& ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) )
|
|
800929a: 68bb ldr r3, [r7, #8]
|
|
800929c: 7d5b ldrb r3, [r3, #21]
|
|
800929e: 2b01 cmp r3, #1
|
|
80092a0: d002 beq.n 80092a8 <RadioSetTxGenericConfig+0x260>
|
|
{
|
|
return -1;
|
|
80092a2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80092a6: e0fd b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
ConfigGeneric_t ConfigGeneric;
|
|
ConfigGeneric.rtx = CONFIG_TX;
|
|
80092a8: 2301 movs r3, #1
|
|
80092aa: 773b strb r3, [r7, #28]
|
|
ConfigGeneric.TxConfig = config;
|
|
80092ac: 68bb ldr r3, [r7, #8]
|
|
80092ae: 617b str r3, [r7, #20]
|
|
if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) )
|
|
80092b0: 4b20 ldr r3, [pc, #128] @ (8009334 <RadioSetTxGenericConfig+0x2ec>)
|
|
80092b2: 6819 ldr r1, [r3, #0]
|
|
80092b4: f107 0314 add.w r3, r7, #20
|
|
80092b8: 4a1f ldr r2, [pc, #124] @ (8009338 <RadioSetTxGenericConfig+0x2f0>)
|
|
80092ba: 4618 mov r0, r3
|
|
80092bc: f001 fd02 bl 800acc4 <RFW_Init>
|
|
80092c0: 4603 mov r3, r0
|
|
80092c2: 2b00 cmp r3, #0
|
|
80092c4: d002 beq.n 80092cc <RadioSetTxGenericConfig+0x284>
|
|
{
|
|
return -1;
|
|
80092c6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80092ca: e0eb b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
/* whitening off, will be processed by FW, switch off built-in radio whitening */
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF;
|
|
80092cc: 4b18 ldr r3, [pc, #96] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092ce: 2200 movs r2, #0
|
|
80092d0: 761a strb r2, [r3, #24]
|
|
/* Crc processed by FW, switch off built-in radio Crc */
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF;
|
|
80092d2: 4b17 ldr r3, [pc, #92] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092d4: 2201 movs r2, #1
|
|
80092d6: 75da strb r2, [r3, #23]
|
|
/* length contained in Tx, but will be processed by FW after de-whitening */
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH;
|
|
80092d8: 4b15 ldr r3, [pc, #84] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092da: 2200 movs r2, #0
|
|
80092dc: 755a strb r2, [r3, #21]
|
|
{
|
|
80092de: e00b b.n 80092f8 <RadioSetTxGenericConfig+0x2b0>
|
|
}
|
|
else
|
|
{
|
|
SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength;
|
|
80092e0: 68bb ldr r3, [r7, #8]
|
|
80092e2: 7d5a ldrb r2, [r3, #21]
|
|
80092e4: 4b12 ldr r3, [pc, #72] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092e6: 75da strb r2, [r3, #23]
|
|
SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening;
|
|
80092e8: 68bb ldr r3, [r7, #8]
|
|
80092ea: 7d9a ldrb r2, [r3, #22]
|
|
80092ec: 4b10 ldr r3, [pc, #64] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092ee: 761a strb r2, [r3, #24]
|
|
SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType;
|
|
80092f0: 68bb ldr r3, [r7, #8]
|
|
80092f2: 7d1a ldrb r2, [r3, #20]
|
|
80092f4: 4b0e ldr r3, [pc, #56] @ (8009330 <RadioSetTxGenericConfig+0x2e8>)
|
|
80092f6: 755a strb r2, [r3, #21]
|
|
}
|
|
|
|
RadioStandby( );
|
|
80092f8: f7fe ffc9 bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_FSK );
|
|
80092fc: 2000 movs r0, #0
|
|
80092fe: f7fe f957 bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8009302: 480e ldr r0, [pc, #56] @ (800933c <RadioSetTxGenericConfig+0x2f4>)
|
|
8009304: f000 fdf4 bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
8009308: 480d ldr r0, [pc, #52] @ (8009340 <RadioSetTxGenericConfig+0x2f8>)
|
|
800930a: f000 febf bl 800a08c <SUBGRF_SetPacketParams>
|
|
SUBGRF_SetSyncWord( syncword );
|
|
800930e: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8009312: 4618 mov r0, r3
|
|
8009314: f000 f97f bl 8009616 <SUBGRF_SetSyncWord>
|
|
SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed );
|
|
8009318: 68bb ldr r3, [r7, #8]
|
|
800931a: 8a1b ldrh r3, [r3, #16]
|
|
800931c: 4618 mov r0, r3
|
|
800931e: f000 f9c9 bl 80096b4 <SUBGRF_SetWhiteningSeed>
|
|
SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial );
|
|
8009322: 68bb ldr r3, [r7, #8]
|
|
8009324: 899b ldrh r3, [r3, #12]
|
|
8009326: 4618 mov r0, r3
|
|
8009328: f000 f9a4 bl 8009674 <SUBGRF_SetCrcPolynomial>
|
|
break;
|
|
800932c: e0a6 b.n 800947c <RadioSetTxGenericConfig+0x434>
|
|
800932e: bf00 nop
|
|
8009330: 20000290 .word 0x20000290
|
|
8009334: 2000028c .word 0x2000028c
|
|
8009338: 200002ec .word 0x200002ec
|
|
800933c: 200002c8 .word 0x200002c8
|
|
8009340: 2000029e .word 0x2000029e
|
|
case GENERIC_LORA:
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA;
|
|
8009344: 4b59 ldr r3, [pc, #356] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009346: 2201 movs r2, #1
|
|
8009348: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor;
|
|
800934c: 68bb ldr r3, [r7, #8]
|
|
800934e: 781a ldrb r2, [r3, #0]
|
|
8009350: 4b56 ldr r3, [pc, #344] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009352: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth;
|
|
8009356: 68bb ldr r3, [r7, #8]
|
|
8009358: 785a ldrb r2, [r3, #1]
|
|
800935a: 4b54 ldr r3, [pc, #336] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800935c: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate;
|
|
8009360: 68bb ldr r3, [r7, #8]
|
|
8009362: 789a ldrb r2, [r3, #2]
|
|
8009364: 4b51 ldr r3, [pc, #324] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009366: f883 2052 strb.w r2, [r3, #82] @ 0x52
|
|
switch( config->lora.LowDatarateOptimize )
|
|
800936a: 68bb ldr r3, [r7, #8]
|
|
800936c: 78db ldrb r3, [r3, #3]
|
|
800936e: 2b02 cmp r3, #2
|
|
8009370: d010 beq.n 8009394 <RadioSetTxGenericConfig+0x34c>
|
|
8009372: 2b02 cmp r3, #2
|
|
8009374: dc20 bgt.n 80093b8 <RadioSetTxGenericConfig+0x370>
|
|
8009376: 2b00 cmp r3, #0
|
|
8009378: d002 beq.n 8009380 <RadioSetTxGenericConfig+0x338>
|
|
800937a: 2b01 cmp r3, #1
|
|
800937c: d005 beq.n 800938a <RadioSetTxGenericConfig+0x342>
|
|
{
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
800937e: e01b b.n 80093b8 <RadioSetTxGenericConfig+0x370>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0;
|
|
8009380: 4b4a ldr r3, [pc, #296] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009382: 2200 movs r2, #0
|
|
8009384: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8009388: e017 b.n 80093ba <RadioSetTxGenericConfig+0x372>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1;
|
|
800938a: 4b48 ldr r3, [pc, #288] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800938c: 2201 movs r2, #1
|
|
800938e: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
8009392: e012 b.n 80093ba <RadioSetTxGenericConfig+0x372>
|
|
if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) )
|
|
8009394: 68bb ldr r3, [r7, #8]
|
|
8009396: 781b ldrb r3, [r3, #0]
|
|
8009398: 2b0b cmp r3, #11
|
|
800939a: d003 beq.n 80093a4 <RadioSetTxGenericConfig+0x35c>
|
|
800939c: 68bb ldr r3, [r7, #8]
|
|
800939e: 781b ldrb r3, [r3, #0]
|
|
80093a0: 2b0c cmp r3, #12
|
|
80093a2: d104 bne.n 80093ae <RadioSetTxGenericConfig+0x366>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1;
|
|
80093a4: 4b41 ldr r3, [pc, #260] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093a6: 2201 movs r2, #1
|
|
80093a8: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
80093ac: e005 b.n 80093ba <RadioSetTxGenericConfig+0x372>
|
|
SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0;
|
|
80093ae: 4b3f ldr r3, [pc, #252] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093b0: 2200 movs r2, #0
|
|
80093b2: f883 2053 strb.w r2, [r3, #83] @ 0x53
|
|
break;
|
|
80093b6: e000 b.n 80093ba <RadioSetTxGenericConfig+0x372>
|
|
break;
|
|
80093b8: bf00 nop
|
|
}
|
|
|
|
SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA;
|
|
80093ba: 4b3c ldr r3, [pc, #240] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093bc: 2201 movs r2, #1
|
|
80093be: 739a strb r2, [r3, #14]
|
|
SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen;
|
|
80093c0: 68bb ldr r3, [r7, #8]
|
|
80093c2: 889a ldrh r2, [r3, #4]
|
|
80093c4: 4b39 ldr r3, [pc, #228] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093c6: 839a strh r2, [r3, #28]
|
|
SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode;
|
|
80093c8: 68bb ldr r3, [r7, #8]
|
|
80093ca: 799a ldrb r2, [r3, #6]
|
|
80093cc: 4b37 ldr r3, [pc, #220] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093ce: 779a strb r2, [r3, #30]
|
|
SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode;
|
|
80093d0: 68bb ldr r3, [r7, #8]
|
|
80093d2: 79da ldrb r2, [r3, #7]
|
|
80093d4: 4b35 ldr r3, [pc, #212] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093d6: f883 2020 strb.w r2, [r3, #32]
|
|
SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted;
|
|
80093da: 68bb ldr r3, [r7, #8]
|
|
80093dc: 7a1a ldrb r2, [r3, #8]
|
|
80093de: 4b33 ldr r3, [pc, #204] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093e0: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
RadioStandby( );
|
|
80093e4: f7fe ff53 bl 800828e <RadioStandby>
|
|
RadioSetModem( MODEM_LORA );
|
|
80093e8: 2001 movs r0, #1
|
|
80093ea: f7fe f8e1 bl 80075b0 <RadioSetModem>
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
80093ee: 4830 ldr r0, [pc, #192] @ (80094b0 <RadioSetTxGenericConfig+0x468>)
|
|
80093f0: f000 fd7e bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
SUBGRF_SetPacketParams( &SubgRf.PacketParams );
|
|
80093f4: 482f ldr r0, [pc, #188] @ (80094b4 <RadioSetTxGenericConfig+0x46c>)
|
|
80093f6: f000 fe49 bl 800a08c <SUBGRF_SetPacketParams>
|
|
|
|
/* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */
|
|
if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 )
|
|
80093fa: 4b2c ldr r3, [pc, #176] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
80093fc: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
8009400: 2b06 cmp r3, #6
|
|
8009402: d10d bne.n 8009420 <RadioSetTxGenericConfig+0x3d8>
|
|
{
|
|
// RegTxModulation = @address 0x0889
|
|
SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) );
|
|
8009404: f640 0089 movw r0, #2185 @ 0x889
|
|
8009408: f000 ffa8 bl 800a35c <SUBGRF_ReadRegister>
|
|
800940c: 4603 mov r3, r0
|
|
800940e: f023 0304 bic.w r3, r3, #4
|
|
8009412: b2db uxtb r3, r3
|
|
8009414: 4619 mov r1, r3
|
|
8009416: f640 0089 movw r0, #2185 @ 0x889
|
|
800941a: f000 ff7d bl 800a318 <SUBGRF_WriteRegister>
|
|
{
|
|
// RegTxModulation = @address 0x0889
|
|
SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) );
|
|
}
|
|
/* WORKAROUND END */
|
|
break;
|
|
800941e: e02d b.n 800947c <RadioSetTxGenericConfig+0x434>
|
|
SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) );
|
|
8009420: f640 0089 movw r0, #2185 @ 0x889
|
|
8009424: f000 ff9a bl 800a35c <SUBGRF_ReadRegister>
|
|
8009428: 4603 mov r3, r0
|
|
800942a: f043 0304 orr.w r3, r3, #4
|
|
800942e: b2db uxtb r3, r3
|
|
8009430: 4619 mov r1, r3
|
|
8009432: f640 0089 movw r0, #2185 @ 0x889
|
|
8009436: f000 ff6f bl 800a318 <SUBGRF_WriteRegister>
|
|
break;
|
|
800943a: e01f b.n 800947c <RadioSetTxGenericConfig+0x434>
|
|
case GENERIC_BPSK:
|
|
if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) )
|
|
800943c: 68bb ldr r3, [r7, #8]
|
|
800943e: 681b ldr r3, [r3, #0]
|
|
8009440: 2b00 cmp r3, #0
|
|
8009442: d004 beq.n 800944e <RadioSetTxGenericConfig+0x406>
|
|
8009444: 68bb ldr r3, [r7, #8]
|
|
8009446: 681b ldr r3, [r3, #0]
|
|
8009448: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
800944c: d902 bls.n 8009454 <RadioSetTxGenericConfig+0x40c>
|
|
{
|
|
return -1;
|
|
800944e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8009452: e027 b.n 80094a4 <RadioSetTxGenericConfig+0x45c>
|
|
}
|
|
RadioSetModem( MODEM_BPSK );
|
|
8009454: 2003 movs r0, #3
|
|
8009456: f7fe f8ab bl 80075b0 <RadioSetModem>
|
|
SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK;
|
|
800945a: 4b14 ldr r3, [pc, #80] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800945c: 2202 movs r2, #2
|
|
800945e: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate;
|
|
8009462: 68bb ldr r3, [r7, #8]
|
|
8009464: 681b ldr r3, [r3, #0]
|
|
8009466: 4a11 ldr r2, [pc, #68] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009468: 6493 str r3, [r2, #72] @ 0x48
|
|
SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK;
|
|
800946a: 4b10 ldr r3, [pc, #64] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800946c: 2216 movs r2, #22
|
|
800946e: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
SUBGRF_SetModulationParams( &SubgRf.ModulationParams );
|
|
8009472: 480f ldr r0, [pc, #60] @ (80094b0 <RadioSetTxGenericConfig+0x468>)
|
|
8009474: f000 fd3c bl 8009ef0 <SUBGRF_SetModulationParams>
|
|
break;
|
|
8009478: e000 b.n 800947c <RadioSetTxGenericConfig+0x434>
|
|
default:
|
|
break;
|
|
800947a: bf00 nop
|
|
}
|
|
|
|
SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power );
|
|
800947c: f997 300e ldrsb.w r3, [r7, #14]
|
|
8009480: 4618 mov r0, r3
|
|
8009482: f001 f87f bl 800a584 <SUBGRF_SetRfTxPower>
|
|
8009486: 4603 mov r3, r0
|
|
8009488: 461a mov r2, r3
|
|
800948a: 4b08 ldr r3, [pc, #32] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800948c: f883 2056 strb.w r2, [r3, #86] @ 0x56
|
|
RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect );
|
|
8009490: 4b06 ldr r3, [pc, #24] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
8009492: f893 3056 ldrb.w r3, [r3, #86] @ 0x56
|
|
8009496: 4618 mov r0, r3
|
|
8009498: f001 fcce bl 800ae38 <RFW_SetAntSwitch>
|
|
SubgRf.TxTimeout = timeout;
|
|
800949c: 4a03 ldr r2, [pc, #12] @ (80094ac <RadioSetTxGenericConfig+0x464>)
|
|
800949e: 687b ldr r3, [r7, #4]
|
|
80094a0: 6053 str r3, [r2, #4]
|
|
return 0;
|
|
80094a2: 2300 movs r3, #0
|
|
#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/
|
|
return -1;
|
|
#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/
|
|
}
|
|
80094a4: 4618 mov r0, r3
|
|
80094a6: 3738 adds r7, #56 @ 0x38
|
|
80094a8: 46bd mov sp, r7
|
|
80094aa: bd80 pop {r7, pc}
|
|
80094ac: 20000290 .word 0x20000290
|
|
80094b0: 200002c8 .word 0x200002c8
|
|
80094b4: 2000029e .word 0x2000029e
|
|
|
|
080094b8 <RadioLrFhssSetCfg>:
|
|
return ( prbs31_val - 1 ) % ( max );
|
|
}
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
|
|
static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params )
|
|
{
|
|
80094b8: b480 push {r7}
|
|
80094ba: b085 sub sp, #20
|
|
80094bc: af00 add r7, sp, #0
|
|
80094be: 6078 str r0, [r7, #4]
|
|
radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE;
|
|
80094c0: 2301 movs r3, #1
|
|
80094c2: 73fb strb r3, [r7, #15]
|
|
{
|
|
return status;
|
|
}
|
|
SubgRf.lr_fhss.is_lr_fhss_on = true;
|
|
#endif /* RADIO_LR_FHSS_IS_ON == 1 */
|
|
return status;
|
|
80094c4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80094c6: 4618 mov r0, r3
|
|
80094c8: 3714 adds r7, #20
|
|
80094ca: 46bd mov sp, r7
|
|
80094cc: bc80 pop {r7}
|
|
80094ce: 4770 bx lr
|
|
|
|
080094d0 <RadioLrFhssGetTimeOnAirInMs>:
|
|
|
|
static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params,
|
|
uint32_t *time_on_air_in_ms )
|
|
{
|
|
80094d0: b480 push {r7}
|
|
80094d2: b083 sub sp, #12
|
|
80094d4: af00 add r7, sp, #0
|
|
80094d6: 6078 str r0, [r7, #4]
|
|
80094d8: 6039 str r1, [r7, #0]
|
|
*time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params,
|
|
params->pld_len_in_bytes );
|
|
|
|
return RADIO_STATUS_OK;
|
|
#else
|
|
return RADIO_STATUS_UNSUPPORTED_FEATURE;
|
|
80094da: 2301 movs r3, #1
|
|
#endif /* RADIO_LR_FHSS_IS_ON */
|
|
80094dc: 4618 mov r0, r3
|
|
80094de: 370c adds r7, #12
|
|
80094e0: 46bd mov sp, r7
|
|
80094e2: bc80 pop {r7}
|
|
80094e4: 4770 bx lr
|
|
...
|
|
|
|
080094e8 <SUBGRF_Init>:
|
|
*/
|
|
static DioIrqHandler RadioOnDioIrqCb;
|
|
|
|
/* Exported functions ---------------------------------------------------------*/
|
|
void SUBGRF_Init( DioIrqHandler dioIrq )
|
|
{
|
|
80094e8: b580 push {r7, lr}
|
|
80094ea: b084 sub sp, #16
|
|
80094ec: af00 add r7, sp, #0
|
|
80094ee: 6078 str r0, [r7, #4]
|
|
if ( dioIrq != NULL)
|
|
80094f0: 687b ldr r3, [r7, #4]
|
|
80094f2: 2b00 cmp r3, #0
|
|
80094f4: d002 beq.n 80094fc <SUBGRF_Init+0x14>
|
|
{
|
|
RadioOnDioIrqCb = dioIrq;
|
|
80094f6: 4a1d ldr r2, [pc, #116] @ (800956c <SUBGRF_Init+0x84>)
|
|
80094f8: 687b ldr r3, [r7, #4]
|
|
80094fa: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
RADIO_INIT();
|
|
80094fc: f7f7 fa8e bl 8000a1c <MX_SUBGHZ_Init>
|
|
|
|
/* set default SMPS current drive to default*/
|
|
Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT);
|
|
8009500: 2002 movs r0, #2
|
|
8009502: f001 f91b bl 800a73c <Radio_SMPS_Set>
|
|
|
|
ImageCalibrated = false;
|
|
8009506: 4b1a ldr r3, [pc, #104] @ (8009570 <SUBGRF_Init+0x88>)
|
|
8009508: 2200 movs r2, #0
|
|
800950a: 701a strb r2, [r3, #0]
|
|
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800950c: 2000 movs r0, #0
|
|
800950e: f000 f97f bl 8009810 <SUBGRF_SetStandby>
|
|
|
|
// Initialize TCXO control
|
|
if (1U == RBI_IsTCXO() )
|
|
8009512: f002 fd29 bl 800bf68 <RBI_IsTCXO>
|
|
8009516: 4603 mov r3, r0
|
|
8009518: 2b01 cmp r3, #1
|
|
800951a: d10e bne.n 800953a <SUBGRF_Init+0x52>
|
|
{
|
|
SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms
|
|
800951c: 2140 movs r1, #64 @ 0x40
|
|
800951e: 2001 movs r0, #1
|
|
8009520: f000 fb8a bl 8009c38 <SUBGRF_SetTcxoMode>
|
|
SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 );
|
|
8009524: 2100 movs r1, #0
|
|
8009526: f640 1011 movw r0, #2321 @ 0x911
|
|
800952a: f000 fef5 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
/*enable calibration for cut1.1 and later*/
|
|
CalibrationParams_t calibParam;
|
|
calibParam.Value = 0x7F;
|
|
800952e: 237f movs r3, #127 @ 0x7f
|
|
8009530: 733b strb r3, [r7, #12]
|
|
SUBGRF_Calibrate( calibParam );
|
|
8009532: 7b38 ldrb r0, [r7, #12]
|
|
8009534: f000 fa8d bl 8009a52 <SUBGRF_Calibrate>
|
|
8009538: e009 b.n 800954e <SUBGRF_Init+0x66>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE );
|
|
800953a: 2120 movs r1, #32
|
|
800953c: f640 1011 movw r0, #2321 @ 0x911
|
|
8009540: f000 feea bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE );
|
|
8009544: 2120 movs r1, #32
|
|
8009546: f640 1012 movw r0, #2322 @ 0x912
|
|
800954a: f000 fee5 bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
|
|
/* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */
|
|
SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1);
|
|
800954e: 210e movs r1, #14
|
|
8009550: f640 101f movw r0, #2335 @ 0x91f
|
|
8009554: f000 fee0 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
/* Init RF Switch */
|
|
RBI_Init();
|
|
8009558: f002 fcea bl 800bf30 <RBI_Init>
|
|
|
|
OperatingMode = MODE_STDBY_RC;
|
|
800955c: 4b05 ldr r3, [pc, #20] @ (8009574 <SUBGRF_Init+0x8c>)
|
|
800955e: 2201 movs r2, #1
|
|
8009560: 701a strb r2, [r3, #0]
|
|
}
|
|
8009562: bf00 nop
|
|
8009564: 3710 adds r7, #16
|
|
8009566: 46bd mov sp, r7
|
|
8009568: bd80 pop {r7, pc}
|
|
800956a: bf00 nop
|
|
800956c: 20000328 .word 0x20000328
|
|
8009570: 20000324 .word 0x20000324
|
|
8009574: 2000031c .word 0x2000031c
|
|
|
|
08009578 <SUBGRF_GetOperatingMode>:
|
|
|
|
RadioOperatingModes_t SUBGRF_GetOperatingMode( void )
|
|
{
|
|
8009578: b480 push {r7}
|
|
800957a: af00 add r7, sp, #0
|
|
return OperatingMode;
|
|
800957c: 4b02 ldr r3, [pc, #8] @ (8009588 <SUBGRF_GetOperatingMode+0x10>)
|
|
800957e: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8009580: 4618 mov r0, r3
|
|
8009582: 46bd mov sp, r7
|
|
8009584: bc80 pop {r7}
|
|
8009586: 4770 bx lr
|
|
8009588: 2000031c .word 0x2000031c
|
|
|
|
0800958c <SUBGRF_SetPayload>:
|
|
|
|
void SUBGRF_SetPayload( uint8_t *payload, uint8_t size )
|
|
{
|
|
800958c: b580 push {r7, lr}
|
|
800958e: b082 sub sp, #8
|
|
8009590: af00 add r7, sp, #0
|
|
8009592: 6078 str r0, [r7, #4]
|
|
8009594: 460b mov r3, r1
|
|
8009596: 70fb strb r3, [r7, #3]
|
|
SUBGRF_WriteBuffer( 0x00, payload, size );
|
|
8009598: 78fb ldrb r3, [r7, #3]
|
|
800959a: 461a mov r2, r3
|
|
800959c: 6879 ldr r1, [r7, #4]
|
|
800959e: 2000 movs r0, #0
|
|
80095a0: f000 ff40 bl 800a424 <SUBGRF_WriteBuffer>
|
|
}
|
|
80095a4: bf00 nop
|
|
80095a6: 3708 adds r7, #8
|
|
80095a8: 46bd mov sp, r7
|
|
80095aa: bd80 pop {r7, pc}
|
|
|
|
080095ac <SUBGRF_GetPayload>:
|
|
|
|
uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize )
|
|
{
|
|
80095ac: b580 push {r7, lr}
|
|
80095ae: b086 sub sp, #24
|
|
80095b0: af00 add r7, sp, #0
|
|
80095b2: 60f8 str r0, [r7, #12]
|
|
80095b4: 60b9 str r1, [r7, #8]
|
|
80095b6: 4613 mov r3, r2
|
|
80095b8: 71fb strb r3, [r7, #7]
|
|
uint8_t offset = 0;
|
|
80095ba: 2300 movs r3, #0
|
|
80095bc: 75fb strb r3, [r7, #23]
|
|
|
|
SUBGRF_GetRxBufferStatus( size, &offset );
|
|
80095be: f107 0317 add.w r3, r7, #23
|
|
80095c2: 4619 mov r1, r3
|
|
80095c4: 68b8 ldr r0, [r7, #8]
|
|
80095c6: f000 fe29 bl 800a21c <SUBGRF_GetRxBufferStatus>
|
|
if( *size > maxSize )
|
|
80095ca: 68bb ldr r3, [r7, #8]
|
|
80095cc: 781b ldrb r3, [r3, #0]
|
|
80095ce: 79fa ldrb r2, [r7, #7]
|
|
80095d0: 429a cmp r2, r3
|
|
80095d2: d201 bcs.n 80095d8 <SUBGRF_GetPayload+0x2c>
|
|
{
|
|
return 1;
|
|
80095d4: 2301 movs r3, #1
|
|
80095d6: e007 b.n 80095e8 <SUBGRF_GetPayload+0x3c>
|
|
}
|
|
SUBGRF_ReadBuffer( offset, buffer, *size );
|
|
80095d8: 7df8 ldrb r0, [r7, #23]
|
|
80095da: 68bb ldr r3, [r7, #8]
|
|
80095dc: 781b ldrb r3, [r3, #0]
|
|
80095de: 461a mov r2, r3
|
|
80095e0: 68f9 ldr r1, [r7, #12]
|
|
80095e2: f000 ff41 bl 800a468 <SUBGRF_ReadBuffer>
|
|
|
|
return 0;
|
|
80095e6: 2300 movs r3, #0
|
|
}
|
|
80095e8: 4618 mov r0, r3
|
|
80095ea: 3718 adds r7, #24
|
|
80095ec: 46bd mov sp, r7
|
|
80095ee: bd80 pop {r7, pc}
|
|
|
|
080095f0 <SUBGRF_SendPayload>:
|
|
|
|
void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout)
|
|
{
|
|
80095f0: b580 push {r7, lr}
|
|
80095f2: b084 sub sp, #16
|
|
80095f4: af00 add r7, sp, #0
|
|
80095f6: 60f8 str r0, [r7, #12]
|
|
80095f8: 460b mov r3, r1
|
|
80095fa: 607a str r2, [r7, #4]
|
|
80095fc: 72fb strb r3, [r7, #11]
|
|
SUBGRF_SetPayload( payload, size );
|
|
80095fe: 7afb ldrb r3, [r7, #11]
|
|
8009600: 4619 mov r1, r3
|
|
8009602: 68f8 ldr r0, [r7, #12]
|
|
8009604: f7ff ffc2 bl 800958c <SUBGRF_SetPayload>
|
|
SUBGRF_SetTx( timeout );
|
|
8009608: 6878 ldr r0, [r7, #4]
|
|
800960a: f000 f91d bl 8009848 <SUBGRF_SetTx>
|
|
}
|
|
800960e: bf00 nop
|
|
8009610: 3710 adds r7, #16
|
|
8009612: 46bd mov sp, r7
|
|
8009614: bd80 pop {r7, pc}
|
|
|
|
08009616 <SUBGRF_SetSyncWord>:
|
|
|
|
uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord )
|
|
{
|
|
8009616: b580 push {r7, lr}
|
|
8009618: b082 sub sp, #8
|
|
800961a: af00 add r7, sp, #0
|
|
800961c: 6078 str r0, [r7, #4]
|
|
SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 );
|
|
800961e: 2208 movs r2, #8
|
|
8009620: 6879 ldr r1, [r7, #4]
|
|
8009622: f44f 60d8 mov.w r0, #1728 @ 0x6c0
|
|
8009626: f000 feb9 bl 800a39c <SUBGRF_WriteRegisters>
|
|
return 0;
|
|
800962a: 2300 movs r3, #0
|
|
}
|
|
800962c: 4618 mov r0, r3
|
|
800962e: 3708 adds r7, #8
|
|
8009630: 46bd mov sp, r7
|
|
8009632: bd80 pop {r7, pc}
|
|
|
|
08009634 <SUBGRF_SetCrcSeed>:
|
|
|
|
void SUBGRF_SetCrcSeed( uint16_t seed )
|
|
{
|
|
8009634: b580 push {r7, lr}
|
|
8009636: b084 sub sp, #16
|
|
8009638: af00 add r7, sp, #0
|
|
800963a: 4603 mov r3, r0
|
|
800963c: 80fb strh r3, [r7, #6]
|
|
uint8_t buf[2];
|
|
|
|
buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF );
|
|
800963e: 88fb ldrh r3, [r7, #6]
|
|
8009640: 0a1b lsrs r3, r3, #8
|
|
8009642: b29b uxth r3, r3
|
|
8009644: b2db uxtb r3, r3
|
|
8009646: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( seed & 0xFF );
|
|
8009648: 88fb ldrh r3, [r7, #6]
|
|
800964a: b2db uxtb r3, r3
|
|
800964c: 737b strb r3, [r7, #13]
|
|
|
|
switch( SUBGRF_GetPacketType( ) )
|
|
800964e: f000 fb77 bl 8009d40 <SUBGRF_GetPacketType>
|
|
8009652: 4603 mov r3, r0
|
|
8009654: 2b00 cmp r3, #0
|
|
8009656: d108 bne.n 800966a <SUBGRF_SetCrcSeed+0x36>
|
|
{
|
|
case PACKET_TYPE_GFSK:
|
|
SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 );
|
|
8009658: f107 030c add.w r3, r7, #12
|
|
800965c: 2202 movs r2, #2
|
|
800965e: 4619 mov r1, r3
|
|
8009660: f240 60bc movw r0, #1724 @ 0x6bc
|
|
8009664: f000 fe9a bl 800a39c <SUBGRF_WriteRegisters>
|
|
break;
|
|
8009668: e000 b.n 800966c <SUBGRF_SetCrcSeed+0x38>
|
|
|
|
default:
|
|
break;
|
|
800966a: bf00 nop
|
|
}
|
|
}
|
|
800966c: bf00 nop
|
|
800966e: 3710 adds r7, #16
|
|
8009670: 46bd mov sp, r7
|
|
8009672: bd80 pop {r7, pc}
|
|
|
|
08009674 <SUBGRF_SetCrcPolynomial>:
|
|
|
|
void SUBGRF_SetCrcPolynomial( uint16_t polynomial )
|
|
{
|
|
8009674: b580 push {r7, lr}
|
|
8009676: b084 sub sp, #16
|
|
8009678: af00 add r7, sp, #0
|
|
800967a: 4603 mov r3, r0
|
|
800967c: 80fb strh r3, [r7, #6]
|
|
uint8_t buf[2];
|
|
|
|
buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF );
|
|
800967e: 88fb ldrh r3, [r7, #6]
|
|
8009680: 0a1b lsrs r3, r3, #8
|
|
8009682: b29b uxth r3, r3
|
|
8009684: b2db uxtb r3, r3
|
|
8009686: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( polynomial & 0xFF );
|
|
8009688: 88fb ldrh r3, [r7, #6]
|
|
800968a: b2db uxtb r3, r3
|
|
800968c: 737b strb r3, [r7, #13]
|
|
|
|
switch( SUBGRF_GetPacketType( ) )
|
|
800968e: f000 fb57 bl 8009d40 <SUBGRF_GetPacketType>
|
|
8009692: 4603 mov r3, r0
|
|
8009694: 2b00 cmp r3, #0
|
|
8009696: d108 bne.n 80096aa <SUBGRF_SetCrcPolynomial+0x36>
|
|
{
|
|
case PACKET_TYPE_GFSK:
|
|
SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 );
|
|
8009698: f107 030c add.w r3, r7, #12
|
|
800969c: 2202 movs r2, #2
|
|
800969e: 4619 mov r1, r3
|
|
80096a0: f240 60be movw r0, #1726 @ 0x6be
|
|
80096a4: f000 fe7a bl 800a39c <SUBGRF_WriteRegisters>
|
|
break;
|
|
80096a8: e000 b.n 80096ac <SUBGRF_SetCrcPolynomial+0x38>
|
|
|
|
default:
|
|
break;
|
|
80096aa: bf00 nop
|
|
}
|
|
}
|
|
80096ac: bf00 nop
|
|
80096ae: 3710 adds r7, #16
|
|
80096b0: 46bd mov sp, r7
|
|
80096b2: bd80 pop {r7, pc}
|
|
|
|
080096b4 <SUBGRF_SetWhiteningSeed>:
|
|
|
|
void SUBGRF_SetWhiteningSeed( uint16_t seed )
|
|
{
|
|
80096b4: b580 push {r7, lr}
|
|
80096b6: b084 sub sp, #16
|
|
80096b8: af00 add r7, sp, #0
|
|
80096ba: 4603 mov r3, r0
|
|
80096bc: 80fb strh r3, [r7, #6]
|
|
uint8_t regValue = 0;
|
|
80096be: 2300 movs r3, #0
|
|
80096c0: 73fb strb r3, [r7, #15]
|
|
|
|
switch( SUBGRF_GetPacketType( ) )
|
|
80096c2: f000 fb3d bl 8009d40 <SUBGRF_GetPacketType>
|
|
80096c6: 4603 mov r3, r0
|
|
80096c8: 2b00 cmp r3, #0
|
|
80096ca: d121 bne.n 8009710 <SUBGRF_SetWhiteningSeed+0x5c>
|
|
{
|
|
case PACKET_TYPE_GFSK:
|
|
regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE;
|
|
80096cc: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
80096d0: f000 fe44 bl 800a35c <SUBGRF_ReadRegister>
|
|
80096d4: 4603 mov r3, r0
|
|
80096d6: f023 0301 bic.w r3, r3, #1
|
|
80096da: 73fb strb r3, [r7, #15]
|
|
regValue = ( ( seed >> 8 ) & 0x01 ) | regValue;
|
|
80096dc: 88fb ldrh r3, [r7, #6]
|
|
80096de: 0a1b lsrs r3, r3, #8
|
|
80096e0: b29b uxth r3, r3
|
|
80096e2: b25b sxtb r3, r3
|
|
80096e4: f003 0301 and.w r3, r3, #1
|
|
80096e8: b25a sxtb r2, r3
|
|
80096ea: f997 300f ldrsb.w r3, [r7, #15]
|
|
80096ee: 4313 orrs r3, r2
|
|
80096f0: b25b sxtb r3, r3
|
|
80096f2: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit.
|
|
80096f4: 7bfb ldrb r3, [r7, #15]
|
|
80096f6: 4619 mov r1, r3
|
|
80096f8: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
80096fc: f000 fe0c bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed );
|
|
8009700: 88fb ldrh r3, [r7, #6]
|
|
8009702: b2db uxtb r3, r3
|
|
8009704: 4619 mov r1, r3
|
|
8009706: f240 60b9 movw r0, #1721 @ 0x6b9
|
|
800970a: f000 fe05 bl 800a318 <SUBGRF_WriteRegister>
|
|
break;
|
|
800970e: e000 b.n 8009712 <SUBGRF_SetWhiteningSeed+0x5e>
|
|
|
|
default:
|
|
break;
|
|
8009710: bf00 nop
|
|
}
|
|
}
|
|
8009712: bf00 nop
|
|
8009714: 3710 adds r7, #16
|
|
8009716: 46bd mov sp, r7
|
|
8009718: bd80 pop {r7, pc}
|
|
|
|
0800971a <SUBGRF_GetRandom>:
|
|
|
|
uint32_t SUBGRF_GetRandom( void )
|
|
{
|
|
800971a: b580 push {r7, lr}
|
|
800971c: b082 sub sp, #8
|
|
800971e: af00 add r7, sp, #0
|
|
uint32_t number = 0;
|
|
8009720: 2300 movs r3, #0
|
|
8009722: 603b str r3, [r7, #0]
|
|
uint8_t regAnaLna = 0;
|
|
8009724: 2300 movs r3, #0
|
|
8009726: 71fb strb r3, [r7, #7]
|
|
uint8_t regAnaMixer = 0;
|
|
8009728: 2300 movs r3, #0
|
|
800972a: 71bb strb r3, [r7, #6]
|
|
|
|
regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA );
|
|
800972c: f640 00e2 movw r0, #2274 @ 0x8e2
|
|
8009730: f000 fe14 bl 800a35c <SUBGRF_ReadRegister>
|
|
8009734: 4603 mov r3, r0
|
|
8009736: 71fb strb r3, [r7, #7]
|
|
SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) );
|
|
8009738: 79fb ldrb r3, [r7, #7]
|
|
800973a: f023 0301 bic.w r3, r3, #1
|
|
800973e: b2db uxtb r3, r3
|
|
8009740: 4619 mov r1, r3
|
|
8009742: f640 00e2 movw r0, #2274 @ 0x8e2
|
|
8009746: f000 fde7 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER );
|
|
800974a: f640 00e5 movw r0, #2277 @ 0x8e5
|
|
800974e: f000 fe05 bl 800a35c <SUBGRF_ReadRegister>
|
|
8009752: 4603 mov r3, r0
|
|
8009754: 71bb strb r3, [r7, #6]
|
|
SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) );
|
|
8009756: 79bb ldrb r3, [r7, #6]
|
|
8009758: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
800975c: b2db uxtb r3, r3
|
|
800975e: 4619 mov r1, r3
|
|
8009760: f640 00e5 movw r0, #2277 @ 0x8e5
|
|
8009764: f000 fdd8 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
// Set radio in continuous reception
|
|
SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous
|
|
8009768: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
|
|
800976c: f000 f88c bl 8009888 <SUBGRF_SetRx>
|
|
|
|
SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 );
|
|
8009770: 463b mov r3, r7
|
|
8009772: 2204 movs r2, #4
|
|
8009774: 4619 mov r1, r3
|
|
8009776: f640 0019 movw r0, #2073 @ 0x819
|
|
800977a: f000 fe31 bl 800a3e0 <SUBGRF_ReadRegisters>
|
|
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800977e: 2000 movs r0, #0
|
|
8009780: f000 f846 bl 8009810 <SUBGRF_SetStandby>
|
|
|
|
SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna );
|
|
8009784: 79fb ldrb r3, [r7, #7]
|
|
8009786: 4619 mov r1, r3
|
|
8009788: f640 00e2 movw r0, #2274 @ 0x8e2
|
|
800978c: f000 fdc4 bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer );
|
|
8009790: 79bb ldrb r3, [r7, #6]
|
|
8009792: 4619 mov r1, r3
|
|
8009794: f640 00e5 movw r0, #2277 @ 0x8e5
|
|
8009798: f000 fdbe bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
return number;
|
|
800979c: 683b ldr r3, [r7, #0]
|
|
}
|
|
800979e: 4618 mov r0, r3
|
|
80097a0: 3708 adds r7, #8
|
|
80097a2: 46bd mov sp, r7
|
|
80097a4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080097a8 <SUBGRF_SetSleep>:
|
|
|
|
void SUBGRF_SetSleep( SleepParams_t sleepConfig )
|
|
{
|
|
80097a8: b580 push {r7, lr}
|
|
80097aa: b084 sub sp, #16
|
|
80097ac: af00 add r7, sp, #0
|
|
80097ae: 7138 strb r0, [r7, #4]
|
|
/* switch the antenna OFF by SW */
|
|
RBI_ConfigRFSwitch(RBI_SWITCH_OFF);
|
|
80097b0: 2000 movs r0, #0
|
|
80097b2: f002 fbc4 bl 800bf3e <RBI_ConfigRFSwitch>
|
|
|
|
Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT);
|
|
80097b6: 2002 movs r0, #2
|
|
80097b8: f000 ffc0 bl 800a73c <Radio_SMPS_Set>
|
|
|
|
uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) |
|
|
80097bc: 793b ldrb r3, [r7, #4]
|
|
80097be: f3c3 0380 ubfx r3, r3, #2, #1
|
|
80097c2: b2db uxtb r3, r3
|
|
80097c4: b25b sxtb r3, r3
|
|
80097c6: 009b lsls r3, r3, #2
|
|
80097c8: b25a sxtb r2, r3
|
|
( ( uint8_t )sleepConfig.Fields.Reset << 1 ) |
|
|
80097ca: 793b ldrb r3, [r7, #4]
|
|
80097cc: f3c3 0340 ubfx r3, r3, #1, #1
|
|
80097d0: b2db uxtb r3, r3
|
|
uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) |
|
|
80097d2: b25b sxtb r3, r3
|
|
80097d4: 005b lsls r3, r3, #1
|
|
80097d6: b25b sxtb r3, r3
|
|
80097d8: 4313 orrs r3, r2
|
|
80097da: b25a sxtb r2, r3
|
|
( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) );
|
|
80097dc: 793b ldrb r3, [r7, #4]
|
|
80097de: f3c3 0300 ubfx r3, r3, #0, #1
|
|
80097e2: b2db uxtb r3, r3
|
|
80097e4: b25b sxtb r3, r3
|
|
( ( uint8_t )sleepConfig.Fields.Reset << 1 ) |
|
|
80097e6: 4313 orrs r3, r2
|
|
80097e8: b25b sxtb r3, r3
|
|
80097ea: b2db uxtb r3, r3
|
|
uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) |
|
|
80097ec: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 );
|
|
80097ee: f107 030f add.w r3, r7, #15
|
|
80097f2: 2201 movs r2, #1
|
|
80097f4: 4619 mov r1, r3
|
|
80097f6: 2084 movs r0, #132 @ 0x84
|
|
80097f8: f000 fe58 bl 800a4ac <SUBGRF_WriteCommand>
|
|
OperatingMode = MODE_SLEEP;
|
|
80097fc: 4b03 ldr r3, [pc, #12] @ (800980c <SUBGRF_SetSleep+0x64>)
|
|
80097fe: 2200 movs r2, #0
|
|
8009800: 701a strb r2, [r3, #0]
|
|
}
|
|
8009802: bf00 nop
|
|
8009804: 3710 adds r7, #16
|
|
8009806: 46bd mov sp, r7
|
|
8009808: bd80 pop {r7, pc}
|
|
800980a: bf00 nop
|
|
800980c: 2000031c .word 0x2000031c
|
|
|
|
08009810 <SUBGRF_SetStandby>:
|
|
|
|
void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig )
|
|
{
|
|
8009810: b580 push {r7, lr}
|
|
8009812: b082 sub sp, #8
|
|
8009814: af00 add r7, sp, #0
|
|
8009816: 4603 mov r3, r0
|
|
8009818: 71fb strb r3, [r7, #7]
|
|
SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 );
|
|
800981a: 1dfb adds r3, r7, #7
|
|
800981c: 2201 movs r2, #1
|
|
800981e: 4619 mov r1, r3
|
|
8009820: 2080 movs r0, #128 @ 0x80
|
|
8009822: f000 fe43 bl 800a4ac <SUBGRF_WriteCommand>
|
|
if( standbyConfig == STDBY_RC )
|
|
8009826: 79fb ldrb r3, [r7, #7]
|
|
8009828: 2b00 cmp r3, #0
|
|
800982a: d103 bne.n 8009834 <SUBGRF_SetStandby+0x24>
|
|
{
|
|
OperatingMode = MODE_STDBY_RC;
|
|
800982c: 4b05 ldr r3, [pc, #20] @ (8009844 <SUBGRF_SetStandby+0x34>)
|
|
800982e: 2201 movs r2, #1
|
|
8009830: 701a strb r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
OperatingMode = MODE_STDBY_XOSC;
|
|
}
|
|
}
|
|
8009832: e002 b.n 800983a <SUBGRF_SetStandby+0x2a>
|
|
OperatingMode = MODE_STDBY_XOSC;
|
|
8009834: 4b03 ldr r3, [pc, #12] @ (8009844 <SUBGRF_SetStandby+0x34>)
|
|
8009836: 2202 movs r2, #2
|
|
8009838: 701a strb r2, [r3, #0]
|
|
}
|
|
800983a: bf00 nop
|
|
800983c: 3708 adds r7, #8
|
|
800983e: 46bd mov sp, r7
|
|
8009840: bd80 pop {r7, pc}
|
|
8009842: bf00 nop
|
|
8009844: 2000031c .word 0x2000031c
|
|
|
|
08009848 <SUBGRF_SetTx>:
|
|
SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 );
|
|
OperatingMode = MODE_FS;
|
|
}
|
|
|
|
void SUBGRF_SetTx( uint32_t timeout )
|
|
{
|
|
8009848: b580 push {r7, lr}
|
|
800984a: b084 sub sp, #16
|
|
800984c: af00 add r7, sp, #0
|
|
800984e: 6078 str r0, [r7, #4]
|
|
uint8_t buf[3];
|
|
|
|
OperatingMode = MODE_TX;
|
|
8009850: 4b0c ldr r3, [pc, #48] @ (8009884 <SUBGRF_SetTx+0x3c>)
|
|
8009852: 2204 movs r2, #4
|
|
8009854: 701a strb r2, [r3, #0]
|
|
|
|
buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
|
|
8009856: 687b ldr r3, [r7, #4]
|
|
8009858: 0c1b lsrs r3, r3, #16
|
|
800985a: b2db uxtb r3, r3
|
|
800985c: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
|
|
800985e: 687b ldr r3, [r7, #4]
|
|
8009860: 0a1b lsrs r3, r3, #8
|
|
8009862: b2db uxtb r3, r3
|
|
8009864: 737b strb r3, [r7, #13]
|
|
buf[2] = ( uint8_t )( timeout & 0xFF );
|
|
8009866: 687b ldr r3, [r7, #4]
|
|
8009868: b2db uxtb r3, r3
|
|
800986a: 73bb strb r3, [r7, #14]
|
|
SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 );
|
|
800986c: f107 030c add.w r3, r7, #12
|
|
8009870: 2203 movs r2, #3
|
|
8009872: 4619 mov r1, r3
|
|
8009874: 2083 movs r0, #131 @ 0x83
|
|
8009876: f000 fe19 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
800987a: bf00 nop
|
|
800987c: 3710 adds r7, #16
|
|
800987e: 46bd mov sp, r7
|
|
8009880: bd80 pop {r7, pc}
|
|
8009882: bf00 nop
|
|
8009884: 2000031c .word 0x2000031c
|
|
|
|
08009888 <SUBGRF_SetRx>:
|
|
|
|
void SUBGRF_SetRx( uint32_t timeout )
|
|
{
|
|
8009888: b580 push {r7, lr}
|
|
800988a: b084 sub sp, #16
|
|
800988c: af00 add r7, sp, #0
|
|
800988e: 6078 str r0, [r7, #4]
|
|
uint8_t buf[3];
|
|
|
|
OperatingMode = MODE_RX;
|
|
8009890: 4b0c ldr r3, [pc, #48] @ (80098c4 <SUBGRF_SetRx+0x3c>)
|
|
8009892: 2205 movs r2, #5
|
|
8009894: 701a strb r2, [r3, #0]
|
|
|
|
buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
|
|
8009896: 687b ldr r3, [r7, #4]
|
|
8009898: 0c1b lsrs r3, r3, #16
|
|
800989a: b2db uxtb r3, r3
|
|
800989c: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
|
|
800989e: 687b ldr r3, [r7, #4]
|
|
80098a0: 0a1b lsrs r3, r3, #8
|
|
80098a2: b2db uxtb r3, r3
|
|
80098a4: 737b strb r3, [r7, #13]
|
|
buf[2] = ( uint8_t )( timeout & 0xFF );
|
|
80098a6: 687b ldr r3, [r7, #4]
|
|
80098a8: b2db uxtb r3, r3
|
|
80098aa: 73bb strb r3, [r7, #14]
|
|
SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 );
|
|
80098ac: f107 030c add.w r3, r7, #12
|
|
80098b0: 2203 movs r2, #3
|
|
80098b2: 4619 mov r1, r3
|
|
80098b4: 2082 movs r0, #130 @ 0x82
|
|
80098b6: f000 fdf9 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
80098ba: bf00 nop
|
|
80098bc: 3710 adds r7, #16
|
|
80098be: 46bd mov sp, r7
|
|
80098c0: bd80 pop {r7, pc}
|
|
80098c2: bf00 nop
|
|
80098c4: 2000031c .word 0x2000031c
|
|
|
|
080098c8 <SUBGRF_SetRxBoosted>:
|
|
|
|
void SUBGRF_SetRxBoosted( uint32_t timeout )
|
|
{
|
|
80098c8: b580 push {r7, lr}
|
|
80098ca: b084 sub sp, #16
|
|
80098cc: af00 add r7, sp, #0
|
|
80098ce: 6078 str r0, [r7, #4]
|
|
uint8_t buf[3];
|
|
|
|
OperatingMode = MODE_RX;
|
|
80098d0: 4b0e ldr r3, [pc, #56] @ (800990c <SUBGRF_SetRxBoosted+0x44>)
|
|
80098d2: 2205 movs r2, #5
|
|
80098d4: 701a strb r2, [r3, #0]
|
|
|
|
SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity
|
|
80098d6: 2197 movs r1, #151 @ 0x97
|
|
80098d8: f640 00ac movw r0, #2220 @ 0x8ac
|
|
80098dc: f000 fd1c bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
|
|
80098e0: 687b ldr r3, [r7, #4]
|
|
80098e2: 0c1b lsrs r3, r3, #16
|
|
80098e4: b2db uxtb r3, r3
|
|
80098e6: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
|
|
80098e8: 687b ldr r3, [r7, #4]
|
|
80098ea: 0a1b lsrs r3, r3, #8
|
|
80098ec: b2db uxtb r3, r3
|
|
80098ee: 737b strb r3, [r7, #13]
|
|
buf[2] = ( uint8_t )( timeout & 0xFF );
|
|
80098f0: 687b ldr r3, [r7, #4]
|
|
80098f2: b2db uxtb r3, r3
|
|
80098f4: 73bb strb r3, [r7, #14]
|
|
SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 );
|
|
80098f6: f107 030c add.w r3, r7, #12
|
|
80098fa: 2203 movs r2, #3
|
|
80098fc: 4619 mov r1, r3
|
|
80098fe: 2082 movs r0, #130 @ 0x82
|
|
8009900: f000 fdd4 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009904: bf00 nop
|
|
8009906: 3710 adds r7, #16
|
|
8009908: 46bd mov sp, r7
|
|
800990a: bd80 pop {r7, pc}
|
|
800990c: 2000031c .word 0x2000031c
|
|
|
|
08009910 <SUBGRF_SetRxDutyCycle>:
|
|
|
|
void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime )
|
|
{
|
|
8009910: b580 push {r7, lr}
|
|
8009912: b084 sub sp, #16
|
|
8009914: af00 add r7, sp, #0
|
|
8009916: 6078 str r0, [r7, #4]
|
|
8009918: 6039 str r1, [r7, #0]
|
|
uint8_t buf[6];
|
|
|
|
buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF );
|
|
800991a: 687b ldr r3, [r7, #4]
|
|
800991c: 0c1b lsrs r3, r3, #16
|
|
800991e: b2db uxtb r3, r3
|
|
8009920: 723b strb r3, [r7, #8]
|
|
buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF );
|
|
8009922: 687b ldr r3, [r7, #4]
|
|
8009924: 0a1b lsrs r3, r3, #8
|
|
8009926: b2db uxtb r3, r3
|
|
8009928: 727b strb r3, [r7, #9]
|
|
buf[2] = ( uint8_t )( rxTime & 0xFF );
|
|
800992a: 687b ldr r3, [r7, #4]
|
|
800992c: b2db uxtb r3, r3
|
|
800992e: 72bb strb r3, [r7, #10]
|
|
buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF );
|
|
8009930: 683b ldr r3, [r7, #0]
|
|
8009932: 0c1b lsrs r3, r3, #16
|
|
8009934: b2db uxtb r3, r3
|
|
8009936: 72fb strb r3, [r7, #11]
|
|
buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF );
|
|
8009938: 683b ldr r3, [r7, #0]
|
|
800993a: 0a1b lsrs r3, r3, #8
|
|
800993c: b2db uxtb r3, r3
|
|
800993e: 733b strb r3, [r7, #12]
|
|
buf[5] = ( uint8_t )( sleepTime & 0xFF );
|
|
8009940: 683b ldr r3, [r7, #0]
|
|
8009942: b2db uxtb r3, r3
|
|
8009944: 737b strb r3, [r7, #13]
|
|
SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 );
|
|
8009946: f107 0308 add.w r3, r7, #8
|
|
800994a: 2206 movs r2, #6
|
|
800994c: 4619 mov r1, r3
|
|
800994e: 2094 movs r0, #148 @ 0x94
|
|
8009950: f000 fdac bl 800a4ac <SUBGRF_WriteCommand>
|
|
OperatingMode = MODE_RX_DC;
|
|
8009954: 4b03 ldr r3, [pc, #12] @ (8009964 <SUBGRF_SetRxDutyCycle+0x54>)
|
|
8009956: 2206 movs r2, #6
|
|
8009958: 701a strb r2, [r3, #0]
|
|
}
|
|
800995a: bf00 nop
|
|
800995c: 3710 adds r7, #16
|
|
800995e: 46bd mov sp, r7
|
|
8009960: bd80 pop {r7, pc}
|
|
8009962: bf00 nop
|
|
8009964: 2000031c .word 0x2000031c
|
|
|
|
08009968 <SUBGRF_SetCad>:
|
|
|
|
void SUBGRF_SetCad( void )
|
|
{
|
|
8009968: b580 push {r7, lr}
|
|
800996a: af00 add r7, sp, #0
|
|
SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 );
|
|
800996c: 2200 movs r2, #0
|
|
800996e: 2100 movs r1, #0
|
|
8009970: 20c5 movs r0, #197 @ 0xc5
|
|
8009972: f000 fd9b bl 800a4ac <SUBGRF_WriteCommand>
|
|
OperatingMode = MODE_CAD;
|
|
8009976: 4b02 ldr r3, [pc, #8] @ (8009980 <SUBGRF_SetCad+0x18>)
|
|
8009978: 2207 movs r2, #7
|
|
800997a: 701a strb r2, [r3, #0]
|
|
}
|
|
800997c: bf00 nop
|
|
800997e: bd80 pop {r7, pc}
|
|
8009980: 2000031c .word 0x2000031c
|
|
|
|
08009984 <SUBGRF_SetTxContinuousWave>:
|
|
|
|
void SUBGRF_SetTxContinuousWave( void )
|
|
{
|
|
8009984: b580 push {r7, lr}
|
|
8009986: af00 add r7, sp, #0
|
|
SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 );
|
|
8009988: 2200 movs r2, #0
|
|
800998a: 2100 movs r1, #0
|
|
800998c: 20d1 movs r0, #209 @ 0xd1
|
|
800998e: f000 fd8d bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009992: bf00 nop
|
|
8009994: bd80 pop {r7, pc}
|
|
|
|
08009996 <SUBGRF_SetTxInfinitePreamble>:
|
|
|
|
void SUBGRF_SetTxInfinitePreamble( void )
|
|
{
|
|
8009996: b580 push {r7, lr}
|
|
8009998: af00 add r7, sp, #0
|
|
SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 );
|
|
800999a: 2200 movs r2, #0
|
|
800999c: 2100 movs r1, #0
|
|
800999e: 20d2 movs r0, #210 @ 0xd2
|
|
80099a0: f000 fd84 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
80099a4: bf00 nop
|
|
80099a6: bd80 pop {r7, pc}
|
|
|
|
080099a8 <SUBGRF_SetStopRxTimerOnPreambleDetect>:
|
|
|
|
void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable )
|
|
{
|
|
80099a8: b580 push {r7, lr}
|
|
80099aa: b082 sub sp, #8
|
|
80099ac: af00 add r7, sp, #0
|
|
80099ae: 4603 mov r3, r0
|
|
80099b0: 71fb strb r3, [r7, #7]
|
|
SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 );
|
|
80099b2: 1dfb adds r3, r7, #7
|
|
80099b4: 2201 movs r2, #1
|
|
80099b6: 4619 mov r1, r3
|
|
80099b8: 209f movs r0, #159 @ 0x9f
|
|
80099ba: f000 fd77 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
80099be: bf00 nop
|
|
80099c0: 3708 adds r7, #8
|
|
80099c2: 46bd mov sp, r7
|
|
80099c4: bd80 pop {r7, pc}
|
|
|
|
080099c6 <SUBGRF_SetLoRaSymbNumTimeout>:
|
|
|
|
void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum )
|
|
{
|
|
80099c6: b580 push {r7, lr}
|
|
80099c8: b084 sub sp, #16
|
|
80099ca: af00 add r7, sp, #0
|
|
80099cc: 4603 mov r3, r0
|
|
80099ce: 71fb strb r3, [r7, #7]
|
|
SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 );
|
|
80099d0: 1dfb adds r3, r7, #7
|
|
80099d2: 2201 movs r2, #1
|
|
80099d4: 4619 mov r1, r3
|
|
80099d6: 20a0 movs r0, #160 @ 0xa0
|
|
80099d8: f000 fd68 bl 800a4ac <SUBGRF_WriteCommand>
|
|
|
|
if( symbNum >= 64 )
|
|
80099dc: 79fb ldrb r3, [r7, #7]
|
|
80099de: 2b3f cmp r3, #63 @ 0x3f
|
|
80099e0: d91c bls.n 8009a1c <SUBGRF_SetLoRaSymbNumTimeout+0x56>
|
|
{
|
|
uint8_t mant = symbNum >> 1;
|
|
80099e2: 79fb ldrb r3, [r7, #7]
|
|
80099e4: 085b lsrs r3, r3, #1
|
|
80099e6: 73fb strb r3, [r7, #15]
|
|
uint8_t exp = 0;
|
|
80099e8: 2300 movs r3, #0
|
|
80099ea: 73bb strb r3, [r7, #14]
|
|
uint8_t reg = 0;
|
|
80099ec: 2300 movs r3, #0
|
|
80099ee: 737b strb r3, [r7, #13]
|
|
|
|
while( mant > 31 )
|
|
80099f0: e005 b.n 80099fe <SUBGRF_SetLoRaSymbNumTimeout+0x38>
|
|
{
|
|
mant >>= 2;
|
|
80099f2: 7bfb ldrb r3, [r7, #15]
|
|
80099f4: 089b lsrs r3, r3, #2
|
|
80099f6: 73fb strb r3, [r7, #15]
|
|
exp++;
|
|
80099f8: 7bbb ldrb r3, [r7, #14]
|
|
80099fa: 3301 adds r3, #1
|
|
80099fc: 73bb strb r3, [r7, #14]
|
|
while( mant > 31 )
|
|
80099fe: 7bfb ldrb r3, [r7, #15]
|
|
8009a00: 2b1f cmp r3, #31
|
|
8009a02: d8f6 bhi.n 80099f2 <SUBGRF_SetLoRaSymbNumTimeout+0x2c>
|
|
}
|
|
|
|
reg = exp + ( mant << 3 );
|
|
8009a04: 7bfb ldrb r3, [r7, #15]
|
|
8009a06: 00db lsls r3, r3, #3
|
|
8009a08: b2da uxtb r2, r3
|
|
8009a0a: 7bbb ldrb r3, [r7, #14]
|
|
8009a0c: 4413 add r3, r2
|
|
8009a0e: 737b strb r3, [r7, #13]
|
|
SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg );
|
|
8009a10: 7b7b ldrb r3, [r7, #13]
|
|
8009a12: 4619 mov r1, r3
|
|
8009a14: f240 7006 movw r0, #1798 @ 0x706
|
|
8009a18: f000 fc7e bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
}
|
|
8009a1c: bf00 nop
|
|
8009a1e: 3710 adds r7, #16
|
|
8009a20: 46bd mov sp, r7
|
|
8009a22: bd80 pop {r7, pc}
|
|
|
|
08009a24 <SUBGRF_SetRegulatorMode>:
|
|
|
|
void SUBGRF_SetRegulatorMode( void )
|
|
{
|
|
8009a24: b580 push {r7, lr}
|
|
8009a26: b082 sub sp, #8
|
|
8009a28: af00 add r7, sp, #0
|
|
RadioRegulatorMode_t mode;
|
|
|
|
if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) )
|
|
8009a2a: f002 faa4 bl 800bf76 <RBI_IsDCDC>
|
|
8009a2e: 4603 mov r3, r0
|
|
8009a30: 2b01 cmp r3, #1
|
|
8009a32: d102 bne.n 8009a3a <SUBGRF_SetRegulatorMode+0x16>
|
|
{
|
|
mode = USE_DCDC ;
|
|
8009a34: 2301 movs r3, #1
|
|
8009a36: 71fb strb r3, [r7, #7]
|
|
8009a38: e001 b.n 8009a3e <SUBGRF_SetRegulatorMode+0x1a>
|
|
}
|
|
else
|
|
{
|
|
mode = USE_LDO ;
|
|
8009a3a: 2300 movs r3, #0
|
|
8009a3c: 71fb strb r3, [r7, #7]
|
|
}
|
|
SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 );
|
|
8009a3e: 1dfb adds r3, r7, #7
|
|
8009a40: 2201 movs r2, #1
|
|
8009a42: 4619 mov r1, r3
|
|
8009a44: 2096 movs r0, #150 @ 0x96
|
|
8009a46: f000 fd31 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009a4a: bf00 nop
|
|
8009a4c: 3708 adds r7, #8
|
|
8009a4e: 46bd mov sp, r7
|
|
8009a50: bd80 pop {r7, pc}
|
|
|
|
08009a52 <SUBGRF_Calibrate>:
|
|
|
|
void SUBGRF_Calibrate( CalibrationParams_t calibParam )
|
|
{
|
|
8009a52: b580 push {r7, lr}
|
|
8009a54: b084 sub sp, #16
|
|
8009a56: af00 add r7, sp, #0
|
|
8009a58: 7138 strb r0, [r7, #4]
|
|
uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) |
|
|
8009a5a: 793b ldrb r3, [r7, #4]
|
|
8009a5c: f3c3 1380 ubfx r3, r3, #6, #1
|
|
8009a60: b2db uxtb r3, r3
|
|
8009a62: b25b sxtb r3, r3
|
|
8009a64: 019b lsls r3, r3, #6
|
|
8009a66: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) |
|
|
8009a68: 793b ldrb r3, [r7, #4]
|
|
8009a6a: f3c3 1340 ubfx r3, r3, #5, #1
|
|
8009a6e: b2db uxtb r3, r3
|
|
uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) |
|
|
8009a70: b25b sxtb r3, r3
|
|
8009a72: 015b lsls r3, r3, #5
|
|
8009a74: b25b sxtb r3, r3
|
|
8009a76: 4313 orrs r3, r2
|
|
8009a78: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) |
|
|
8009a7a: 793b ldrb r3, [r7, #4]
|
|
8009a7c: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8009a80: b2db uxtb r3, r3
|
|
( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) |
|
|
8009a82: b25b sxtb r3, r3
|
|
8009a84: 011b lsls r3, r3, #4
|
|
8009a86: b25b sxtb r3, r3
|
|
8009a88: 4313 orrs r3, r2
|
|
8009a8a: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) |
|
|
8009a8c: 793b ldrb r3, [r7, #4]
|
|
8009a8e: f3c3 03c0 ubfx r3, r3, #3, #1
|
|
8009a92: b2db uxtb r3, r3
|
|
( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) |
|
|
8009a94: b25b sxtb r3, r3
|
|
8009a96: 00db lsls r3, r3, #3
|
|
8009a98: b25b sxtb r3, r3
|
|
8009a9a: 4313 orrs r3, r2
|
|
8009a9c: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) |
|
|
8009a9e: 793b ldrb r3, [r7, #4]
|
|
8009aa0: f3c3 0380 ubfx r3, r3, #2, #1
|
|
8009aa4: b2db uxtb r3, r3
|
|
( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) |
|
|
8009aa6: b25b sxtb r3, r3
|
|
8009aa8: 009b lsls r3, r3, #2
|
|
8009aaa: b25b sxtb r3, r3
|
|
8009aac: 4313 orrs r3, r2
|
|
8009aae: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) |
|
|
8009ab0: 793b ldrb r3, [r7, #4]
|
|
8009ab2: f3c3 0340 ubfx r3, r3, #1, #1
|
|
8009ab6: b2db uxtb r3, r3
|
|
( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) |
|
|
8009ab8: b25b sxtb r3, r3
|
|
8009aba: 005b lsls r3, r3, #1
|
|
8009abc: b25b sxtb r3, r3
|
|
8009abe: 4313 orrs r3, r2
|
|
8009ac0: b25a sxtb r2, r3
|
|
( ( uint8_t )calibParam.Fields.RC64KEnable ) );
|
|
8009ac2: 793b ldrb r3, [r7, #4]
|
|
8009ac4: f3c3 0300 ubfx r3, r3, #0, #1
|
|
8009ac8: b2db uxtb r3, r3
|
|
8009aca: b25b sxtb r3, r3
|
|
( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) |
|
|
8009acc: 4313 orrs r3, r2
|
|
8009ace: b25b sxtb r3, r3
|
|
8009ad0: b2db uxtb r3, r3
|
|
uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) |
|
|
8009ad2: 73fb strb r3, [r7, #15]
|
|
|
|
SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 );
|
|
8009ad4: f107 030f add.w r3, r7, #15
|
|
8009ad8: 2201 movs r2, #1
|
|
8009ada: 4619 mov r1, r3
|
|
8009adc: 2089 movs r0, #137 @ 0x89
|
|
8009ade: f000 fce5 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009ae2: bf00 nop
|
|
8009ae4: 3710 adds r7, #16
|
|
8009ae6: 46bd mov sp, r7
|
|
8009ae8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009aec <SUBGRF_CalibrateImage>:
|
|
|
|
void SUBGRF_CalibrateImage( uint32_t freq )
|
|
{
|
|
8009aec: b580 push {r7, lr}
|
|
8009aee: b084 sub sp, #16
|
|
8009af0: af00 add r7, sp, #0
|
|
8009af2: 6078 str r0, [r7, #4]
|
|
uint8_t calFreq[2];
|
|
|
|
if( freq > 900000000 )
|
|
8009af4: 687b ldr r3, [r7, #4]
|
|
8009af6: 4a1d ldr r2, [pc, #116] @ (8009b6c <SUBGRF_CalibrateImage+0x80>)
|
|
8009af8: 4293 cmp r3, r2
|
|
8009afa: d904 bls.n 8009b06 <SUBGRF_CalibrateImage+0x1a>
|
|
{
|
|
calFreq[0] = 0xE1;
|
|
8009afc: 23e1 movs r3, #225 @ 0xe1
|
|
8009afe: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0xE9;
|
|
8009b00: 23e9 movs r3, #233 @ 0xe9
|
|
8009b02: 737b strb r3, [r7, #13]
|
|
8009b04: e027 b.n 8009b56 <SUBGRF_CalibrateImage+0x6a>
|
|
}
|
|
else if( freq > 850000000 )
|
|
8009b06: 687b ldr r3, [r7, #4]
|
|
8009b08: 4a19 ldr r2, [pc, #100] @ (8009b70 <SUBGRF_CalibrateImage+0x84>)
|
|
8009b0a: 4293 cmp r3, r2
|
|
8009b0c: d904 bls.n 8009b18 <SUBGRF_CalibrateImage+0x2c>
|
|
{
|
|
calFreq[0] = 0xD7;
|
|
8009b0e: 23d7 movs r3, #215 @ 0xd7
|
|
8009b10: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0xDB;
|
|
8009b12: 23db movs r3, #219 @ 0xdb
|
|
8009b14: 737b strb r3, [r7, #13]
|
|
8009b16: e01e b.n 8009b56 <SUBGRF_CalibrateImage+0x6a>
|
|
}
|
|
else if( freq > 770000000 )
|
|
8009b18: 687b ldr r3, [r7, #4]
|
|
8009b1a: 4a16 ldr r2, [pc, #88] @ (8009b74 <SUBGRF_CalibrateImage+0x88>)
|
|
8009b1c: 4293 cmp r3, r2
|
|
8009b1e: d904 bls.n 8009b2a <SUBGRF_CalibrateImage+0x3e>
|
|
{
|
|
calFreq[0] = 0xC1;
|
|
8009b20: 23c1 movs r3, #193 @ 0xc1
|
|
8009b22: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0xC5;
|
|
8009b24: 23c5 movs r3, #197 @ 0xc5
|
|
8009b26: 737b strb r3, [r7, #13]
|
|
8009b28: e015 b.n 8009b56 <SUBGRF_CalibrateImage+0x6a>
|
|
}
|
|
else if( freq > 460000000 )
|
|
8009b2a: 687b ldr r3, [r7, #4]
|
|
8009b2c: 4a12 ldr r2, [pc, #72] @ (8009b78 <SUBGRF_CalibrateImage+0x8c>)
|
|
8009b2e: 4293 cmp r3, r2
|
|
8009b30: d904 bls.n 8009b3c <SUBGRF_CalibrateImage+0x50>
|
|
{
|
|
calFreq[0] = 0x75;
|
|
8009b32: 2375 movs r3, #117 @ 0x75
|
|
8009b34: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0x81;
|
|
8009b36: 2381 movs r3, #129 @ 0x81
|
|
8009b38: 737b strb r3, [r7, #13]
|
|
8009b3a: e00c b.n 8009b56 <SUBGRF_CalibrateImage+0x6a>
|
|
}
|
|
else if( freq > 425000000 )
|
|
8009b3c: 687b ldr r3, [r7, #4]
|
|
8009b3e: 4a0f ldr r2, [pc, #60] @ (8009b7c <SUBGRF_CalibrateImage+0x90>)
|
|
8009b40: 4293 cmp r3, r2
|
|
8009b42: d904 bls.n 8009b4e <SUBGRF_CalibrateImage+0x62>
|
|
{
|
|
calFreq[0] = 0x6B;
|
|
8009b44: 236b movs r3, #107 @ 0x6b
|
|
8009b46: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0x6F;
|
|
8009b48: 236f movs r3, #111 @ 0x6f
|
|
8009b4a: 737b strb r3, [r7, #13]
|
|
8009b4c: e003 b.n 8009b56 <SUBGRF_CalibrateImage+0x6a>
|
|
}
|
|
else /* freq <= 425000000*/
|
|
{
|
|
/* [ 156MHz - 171MHz ] */
|
|
calFreq[0] = 0x29;
|
|
8009b4e: 2329 movs r3, #41 @ 0x29
|
|
8009b50: 733b strb r3, [r7, #12]
|
|
calFreq[1] = 0x2B ;
|
|
8009b52: 232b movs r3, #43 @ 0x2b
|
|
8009b54: 737b strb r3, [r7, #13]
|
|
}
|
|
SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 );
|
|
8009b56: f107 030c add.w r3, r7, #12
|
|
8009b5a: 2202 movs r2, #2
|
|
8009b5c: 4619 mov r1, r3
|
|
8009b5e: 2098 movs r0, #152 @ 0x98
|
|
8009b60: f000 fca4 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009b64: bf00 nop
|
|
8009b66: 3710 adds r7, #16
|
|
8009b68: 46bd mov sp, r7
|
|
8009b6a: bd80 pop {r7, pc}
|
|
8009b6c: 35a4e900 .word 0x35a4e900
|
|
8009b70: 32a9f880 .word 0x32a9f880
|
|
8009b74: 2de54480 .word 0x2de54480
|
|
8009b78: 1b6b0b00 .word 0x1b6b0b00
|
|
8009b7c: 1954fc40 .word 0x1954fc40
|
|
|
|
08009b80 <SUBGRF_SetPaConfig>:
|
|
|
|
void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut )
|
|
{
|
|
8009b80: b590 push {r4, r7, lr}
|
|
8009b82: b085 sub sp, #20
|
|
8009b84: af00 add r7, sp, #0
|
|
8009b86: 4604 mov r4, r0
|
|
8009b88: 4608 mov r0, r1
|
|
8009b8a: 4611 mov r1, r2
|
|
8009b8c: 461a mov r2, r3
|
|
8009b8e: 4623 mov r3, r4
|
|
8009b90: 71fb strb r3, [r7, #7]
|
|
8009b92: 4603 mov r3, r0
|
|
8009b94: 71bb strb r3, [r7, #6]
|
|
8009b96: 460b mov r3, r1
|
|
8009b98: 717b strb r3, [r7, #5]
|
|
8009b9a: 4613 mov r3, r2
|
|
8009b9c: 713b strb r3, [r7, #4]
|
|
uint8_t buf[4];
|
|
|
|
buf[0] = paDutyCycle;
|
|
8009b9e: 79fb ldrb r3, [r7, #7]
|
|
8009ba0: 733b strb r3, [r7, #12]
|
|
buf[1] = hpMax;
|
|
8009ba2: 79bb ldrb r3, [r7, #6]
|
|
8009ba4: 737b strb r3, [r7, #13]
|
|
buf[2] = deviceSel;
|
|
8009ba6: 797b ldrb r3, [r7, #5]
|
|
8009ba8: 73bb strb r3, [r7, #14]
|
|
buf[3] = paLut;
|
|
8009baa: 793b ldrb r3, [r7, #4]
|
|
8009bac: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 );
|
|
8009bae: f107 030c add.w r3, r7, #12
|
|
8009bb2: 2204 movs r2, #4
|
|
8009bb4: 4619 mov r1, r3
|
|
8009bb6: 2095 movs r0, #149 @ 0x95
|
|
8009bb8: f000 fc78 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009bbc: bf00 nop
|
|
8009bbe: 3714 adds r7, #20
|
|
8009bc0: 46bd mov sp, r7
|
|
8009bc2: bd90 pop {r4, r7, pc}
|
|
|
|
08009bc4 <SUBGRF_SetDioIrqParams>:
|
|
{
|
|
SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 );
|
|
}
|
|
|
|
void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask )
|
|
{
|
|
8009bc4: b590 push {r4, r7, lr}
|
|
8009bc6: b085 sub sp, #20
|
|
8009bc8: af00 add r7, sp, #0
|
|
8009bca: 4604 mov r4, r0
|
|
8009bcc: 4608 mov r0, r1
|
|
8009bce: 4611 mov r1, r2
|
|
8009bd0: 461a mov r2, r3
|
|
8009bd2: 4623 mov r3, r4
|
|
8009bd4: 80fb strh r3, [r7, #6]
|
|
8009bd6: 4603 mov r3, r0
|
|
8009bd8: 80bb strh r3, [r7, #4]
|
|
8009bda: 460b mov r3, r1
|
|
8009bdc: 807b strh r3, [r7, #2]
|
|
8009bde: 4613 mov r3, r2
|
|
8009be0: 803b strh r3, [r7, #0]
|
|
uint8_t buf[8];
|
|
|
|
buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF );
|
|
8009be2: 88fb ldrh r3, [r7, #6]
|
|
8009be4: 0a1b lsrs r3, r3, #8
|
|
8009be6: b29b uxth r3, r3
|
|
8009be8: b2db uxtb r3, r3
|
|
8009bea: 723b strb r3, [r7, #8]
|
|
buf[1] = ( uint8_t )( irqMask & 0x00FF );
|
|
8009bec: 88fb ldrh r3, [r7, #6]
|
|
8009bee: b2db uxtb r3, r3
|
|
8009bf0: 727b strb r3, [r7, #9]
|
|
buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF );
|
|
8009bf2: 88bb ldrh r3, [r7, #4]
|
|
8009bf4: 0a1b lsrs r3, r3, #8
|
|
8009bf6: b29b uxth r3, r3
|
|
8009bf8: b2db uxtb r3, r3
|
|
8009bfa: 72bb strb r3, [r7, #10]
|
|
buf[3] = ( uint8_t )( dio1Mask & 0x00FF );
|
|
8009bfc: 88bb ldrh r3, [r7, #4]
|
|
8009bfe: b2db uxtb r3, r3
|
|
8009c00: 72fb strb r3, [r7, #11]
|
|
buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF );
|
|
8009c02: 887b ldrh r3, [r7, #2]
|
|
8009c04: 0a1b lsrs r3, r3, #8
|
|
8009c06: b29b uxth r3, r3
|
|
8009c08: b2db uxtb r3, r3
|
|
8009c0a: 733b strb r3, [r7, #12]
|
|
buf[5] = ( uint8_t )( dio2Mask & 0x00FF );
|
|
8009c0c: 887b ldrh r3, [r7, #2]
|
|
8009c0e: b2db uxtb r3, r3
|
|
8009c10: 737b strb r3, [r7, #13]
|
|
buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF );
|
|
8009c12: 883b ldrh r3, [r7, #0]
|
|
8009c14: 0a1b lsrs r3, r3, #8
|
|
8009c16: b29b uxth r3, r3
|
|
8009c18: b2db uxtb r3, r3
|
|
8009c1a: 73bb strb r3, [r7, #14]
|
|
buf[7] = ( uint8_t )( dio3Mask & 0x00FF );
|
|
8009c1c: 883b ldrh r3, [r7, #0]
|
|
8009c1e: b2db uxtb r3, r3
|
|
8009c20: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 );
|
|
8009c22: f107 0308 add.w r3, r7, #8
|
|
8009c26: 2208 movs r2, #8
|
|
8009c28: 4619 mov r1, r3
|
|
8009c2a: 2008 movs r0, #8
|
|
8009c2c: f000 fc3e bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009c30: bf00 nop
|
|
8009c32: 3714 adds r7, #20
|
|
8009c34: 46bd mov sp, r7
|
|
8009c36: bd90 pop {r4, r7, pc}
|
|
|
|
08009c38 <SUBGRF_SetTcxoMode>:
|
|
SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 );
|
|
return ( irqStatus[0] << 8 ) | irqStatus[1];
|
|
}
|
|
|
|
void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout )
|
|
{
|
|
8009c38: b580 push {r7, lr}
|
|
8009c3a: b084 sub sp, #16
|
|
8009c3c: af00 add r7, sp, #0
|
|
8009c3e: 4603 mov r3, r0
|
|
8009c40: 6039 str r1, [r7, #0]
|
|
8009c42: 71fb strb r3, [r7, #7]
|
|
uint8_t buf[4];
|
|
|
|
buf[0] = tcxoVoltage & 0x07;
|
|
8009c44: 79fb ldrb r3, [r7, #7]
|
|
8009c46: f003 0307 and.w r3, r3, #7
|
|
8009c4a: b2db uxtb r3, r3
|
|
8009c4c: 733b strb r3, [r7, #12]
|
|
buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
|
|
8009c4e: 683b ldr r3, [r7, #0]
|
|
8009c50: 0c1b lsrs r3, r3, #16
|
|
8009c52: b2db uxtb r3, r3
|
|
8009c54: 737b strb r3, [r7, #13]
|
|
buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
|
|
8009c56: 683b ldr r3, [r7, #0]
|
|
8009c58: 0a1b lsrs r3, r3, #8
|
|
8009c5a: b2db uxtb r3, r3
|
|
8009c5c: 73bb strb r3, [r7, #14]
|
|
buf[3] = ( uint8_t )( timeout & 0xFF );
|
|
8009c5e: 683b ldr r3, [r7, #0]
|
|
8009c60: b2db uxtb r3, r3
|
|
8009c62: 73fb strb r3, [r7, #15]
|
|
|
|
SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 );
|
|
8009c64: f107 030c add.w r3, r7, #12
|
|
8009c68: 2204 movs r2, #4
|
|
8009c6a: 4619 mov r1, r3
|
|
8009c6c: 2097 movs r0, #151 @ 0x97
|
|
8009c6e: f000 fc1d bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009c72: bf00 nop
|
|
8009c74: 3710 adds r7, #16
|
|
8009c76: 46bd mov sp, r7
|
|
8009c78: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009c7c <SUBGRF_SetRfFrequency>:
|
|
|
|
void SUBGRF_SetRfFrequency( uint32_t frequency )
|
|
{
|
|
8009c7c: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
|
|
8009c80: b084 sub sp, #16
|
|
8009c82: af00 add r7, sp, #0
|
|
8009c84: 6078 str r0, [r7, #4]
|
|
uint8_t buf[4];
|
|
uint32_t chan = 0;
|
|
8009c86: 2300 movs r3, #0
|
|
8009c88: 60fb str r3, [r7, #12]
|
|
|
|
if( ImageCalibrated == false )
|
|
8009c8a: 4b1d ldr r3, [pc, #116] @ (8009d00 <SUBGRF_SetRfFrequency+0x84>)
|
|
8009c8c: 781b ldrb r3, [r3, #0]
|
|
8009c8e: f083 0301 eor.w r3, r3, #1
|
|
8009c92: b2db uxtb r3, r3
|
|
8009c94: 2b00 cmp r3, #0
|
|
8009c96: d005 beq.n 8009ca4 <SUBGRF_SetRfFrequency+0x28>
|
|
{
|
|
SUBGRF_CalibrateImage( frequency );
|
|
8009c98: 6878 ldr r0, [r7, #4]
|
|
8009c9a: f7ff ff27 bl 8009aec <SUBGRF_CalibrateImage>
|
|
ImageCalibrated = true;
|
|
8009c9e: 4b18 ldr r3, [pc, #96] @ (8009d00 <SUBGRF_SetRfFrequency+0x84>)
|
|
8009ca0: 2201 movs r2, #1
|
|
8009ca2: 701a strb r2, [r3, #0]
|
|
}
|
|
SX_FREQ_TO_CHANNEL(chan, frequency);
|
|
8009ca4: 687b ldr r3, [r7, #4]
|
|
8009ca6: 2200 movs r2, #0
|
|
8009ca8: 461c mov r4, r3
|
|
8009caa: 4615 mov r5, r2
|
|
8009cac: ea4f 19d4 mov.w r9, r4, lsr #7
|
|
8009cb0: ea4f 6844 mov.w r8, r4, lsl #25
|
|
8009cb4: 4a13 ldr r2, [pc, #76] @ (8009d04 <SUBGRF_SetRfFrequency+0x88>)
|
|
8009cb6: f04f 0300 mov.w r3, #0
|
|
8009cba: 4640 mov r0, r8
|
|
8009cbc: 4649 mov r1, r9
|
|
8009cbe: f7f6 fa63 bl 8000188 <__aeabi_uldivmod>
|
|
8009cc2: 4602 mov r2, r0
|
|
8009cc4: 460b mov r3, r1
|
|
8009cc6: 4613 mov r3, r2
|
|
8009cc8: 60fb str r3, [r7, #12]
|
|
buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF );
|
|
8009cca: 68fb ldr r3, [r7, #12]
|
|
8009ccc: 0e1b lsrs r3, r3, #24
|
|
8009cce: b2db uxtb r3, r3
|
|
8009cd0: 723b strb r3, [r7, #8]
|
|
buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF );
|
|
8009cd2: 68fb ldr r3, [r7, #12]
|
|
8009cd4: 0c1b lsrs r3, r3, #16
|
|
8009cd6: b2db uxtb r3, r3
|
|
8009cd8: 727b strb r3, [r7, #9]
|
|
buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF );
|
|
8009cda: 68fb ldr r3, [r7, #12]
|
|
8009cdc: 0a1b lsrs r3, r3, #8
|
|
8009cde: b2db uxtb r3, r3
|
|
8009ce0: 72bb strb r3, [r7, #10]
|
|
buf[3] = ( uint8_t )( chan & 0xFF );
|
|
8009ce2: 68fb ldr r3, [r7, #12]
|
|
8009ce4: b2db uxtb r3, r3
|
|
8009ce6: 72fb strb r3, [r7, #11]
|
|
SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 );
|
|
8009ce8: f107 0308 add.w r3, r7, #8
|
|
8009cec: 2204 movs r2, #4
|
|
8009cee: 4619 mov r1, r3
|
|
8009cf0: 2086 movs r0, #134 @ 0x86
|
|
8009cf2: f000 fbdb bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009cf6: bf00 nop
|
|
8009cf8: 3710 adds r7, #16
|
|
8009cfa: 46bd mov sp, r7
|
|
8009cfc: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
|
|
8009d00: 20000324 .word 0x20000324
|
|
8009d04: 01e84800 .word 0x01e84800
|
|
|
|
08009d08 <SUBGRF_SetPacketType>:
|
|
|
|
void SUBGRF_SetPacketType( RadioPacketTypes_t packetType )
|
|
{
|
|
8009d08: b580 push {r7, lr}
|
|
8009d0a: b082 sub sp, #8
|
|
8009d0c: af00 add r7, sp, #0
|
|
8009d0e: 4603 mov r3, r0
|
|
8009d10: 71fb strb r3, [r7, #7]
|
|
// Save packet type internally to avoid questioning the radio
|
|
PacketType = packetType;
|
|
8009d12: 79fa ldrb r2, [r7, #7]
|
|
8009d14: 4b09 ldr r3, [pc, #36] @ (8009d3c <SUBGRF_SetPacketType+0x34>)
|
|
8009d16: 701a strb r2, [r3, #0]
|
|
|
|
if( packetType == PACKET_TYPE_GFSK )
|
|
8009d18: 79fb ldrb r3, [r7, #7]
|
|
8009d1a: 2b00 cmp r3, #0
|
|
8009d1c: d104 bne.n 8009d28 <SUBGRF_SetPacketType+0x20>
|
|
{
|
|
SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 );
|
|
8009d1e: 2100 movs r1, #0
|
|
8009d20: f240 60ac movw r0, #1708 @ 0x6ac
|
|
8009d24: f000 faf8 bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 );
|
|
8009d28: 1dfb adds r3, r7, #7
|
|
8009d2a: 2201 movs r2, #1
|
|
8009d2c: 4619 mov r1, r3
|
|
8009d2e: 208a movs r0, #138 @ 0x8a
|
|
8009d30: f000 fbbc bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009d34: bf00 nop
|
|
8009d36: 3708 adds r7, #8
|
|
8009d38: 46bd mov sp, r7
|
|
8009d3a: bd80 pop {r7, pc}
|
|
8009d3c: 2000031d .word 0x2000031d
|
|
|
|
08009d40 <SUBGRF_GetPacketType>:
|
|
|
|
RadioPacketTypes_t SUBGRF_GetPacketType( void )
|
|
{
|
|
8009d40: b480 push {r7}
|
|
8009d42: af00 add r7, sp, #0
|
|
return PacketType;
|
|
8009d44: 4b02 ldr r3, [pc, #8] @ (8009d50 <SUBGRF_GetPacketType+0x10>)
|
|
8009d46: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8009d48: 4618 mov r0, r3
|
|
8009d4a: 46bd mov sp, r7
|
|
8009d4c: bc80 pop {r7}
|
|
8009d4e: 4770 bx lr
|
|
8009d50: 2000031d .word 0x2000031d
|
|
|
|
08009d54 <SUBGRF_SetTxParams>:
|
|
|
|
void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime )
|
|
{
|
|
8009d54: b580 push {r7, lr}
|
|
8009d56: b084 sub sp, #16
|
|
8009d58: af00 add r7, sp, #0
|
|
8009d5a: 4603 mov r3, r0
|
|
8009d5c: 71fb strb r3, [r7, #7]
|
|
8009d5e: 460b mov r3, r1
|
|
8009d60: 71bb strb r3, [r7, #6]
|
|
8009d62: 4613 mov r3, r2
|
|
8009d64: 717b strb r3, [r7, #5]
|
|
uint8_t buf[2];
|
|
int32_t max_power;
|
|
|
|
if (paSelect == RFO_LP)
|
|
8009d66: 79fb ldrb r3, [r7, #7]
|
|
8009d68: 2b01 cmp r3, #1
|
|
8009d6a: d149 bne.n 8009e00 <SUBGRF_SetTxParams+0xac>
|
|
{
|
|
max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER);
|
|
8009d6c: 2000 movs r0, #0
|
|
8009d6e: f002 f909 bl 800bf84 <RBI_GetRFOMaxPowerConfig>
|
|
8009d72: 60f8 str r0, [r7, #12]
|
|
if (power > max_power)
|
|
8009d74: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8009d78: 68fa ldr r2, [r7, #12]
|
|
8009d7a: 429a cmp r2, r3
|
|
8009d7c: da01 bge.n 8009d82 <SUBGRF_SetTxParams+0x2e>
|
|
{
|
|
power = max_power;
|
|
8009d7e: 68fb ldr r3, [r7, #12]
|
|
8009d80: 71bb strb r3, [r7, #6]
|
|
}
|
|
if (max_power == 14)
|
|
8009d82: 68fb ldr r3, [r7, #12]
|
|
8009d84: 2b0e cmp r3, #14
|
|
8009d86: d10e bne.n 8009da6 <SUBGRF_SetTxParams+0x52>
|
|
{
|
|
SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01);
|
|
8009d88: 2301 movs r3, #1
|
|
8009d8a: 2201 movs r2, #1
|
|
8009d8c: 2100 movs r1, #0
|
|
8009d8e: 2004 movs r0, #4
|
|
8009d90: f7ff fef6 bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x0E - (max_power - power);
|
|
8009d94: 79ba ldrb r2, [r7, #6]
|
|
8009d96: 68fb ldr r3, [r7, #12]
|
|
8009d98: b2db uxtb r3, r3
|
|
8009d9a: 1ad3 subs r3, r2, r3
|
|
8009d9c: b2db uxtb r3, r3
|
|
8009d9e: 330e adds r3, #14
|
|
8009da0: b2db uxtb r3, r3
|
|
8009da2: 71bb strb r3, [r7, #6]
|
|
8009da4: e01f b.n 8009de6 <SUBGRF_SetTxParams+0x92>
|
|
}
|
|
else if (max_power == 10)
|
|
8009da6: 68fb ldr r3, [r7, #12]
|
|
8009da8: 2b0a cmp r3, #10
|
|
8009daa: d10e bne.n 8009dca <SUBGRF_SetTxParams+0x76>
|
|
{
|
|
SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01);
|
|
8009dac: 2301 movs r3, #1
|
|
8009dae: 2201 movs r2, #1
|
|
8009db0: 2100 movs r1, #0
|
|
8009db2: 2001 movs r0, #1
|
|
8009db4: f7ff fee4 bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x0D - (max_power - power);
|
|
8009db8: 79ba ldrb r2, [r7, #6]
|
|
8009dba: 68fb ldr r3, [r7, #12]
|
|
8009dbc: b2db uxtb r3, r3
|
|
8009dbe: 1ad3 subs r3, r2, r3
|
|
8009dc0: b2db uxtb r3, r3
|
|
8009dc2: 330d adds r3, #13
|
|
8009dc4: b2db uxtb r3, r3
|
|
8009dc6: 71bb strb r3, [r7, #6]
|
|
8009dc8: e00d b.n 8009de6 <SUBGRF_SetTxParams+0x92>
|
|
}
|
|
else /*default 15dBm*/
|
|
{
|
|
SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01);
|
|
8009dca: 2301 movs r3, #1
|
|
8009dcc: 2201 movs r2, #1
|
|
8009dce: 2100 movs r1, #0
|
|
8009dd0: 2007 movs r0, #7
|
|
8009dd2: f7ff fed5 bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x0E - (max_power - power);
|
|
8009dd6: 79ba ldrb r2, [r7, #6]
|
|
8009dd8: 68fb ldr r3, [r7, #12]
|
|
8009dda: b2db uxtb r3, r3
|
|
8009ddc: 1ad3 subs r3, r2, r3
|
|
8009dde: b2db uxtb r3, r3
|
|
8009de0: 330e adds r3, #14
|
|
8009de2: b2db uxtb r3, r3
|
|
8009de4: 71bb strb r3, [r7, #6]
|
|
}
|
|
if (power < -17)
|
|
8009de6: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8009dea: f113 0f11 cmn.w r3, #17
|
|
8009dee: da01 bge.n 8009df4 <SUBGRF_SetTxParams+0xa0>
|
|
{
|
|
power = -17;
|
|
8009df0: 23ef movs r3, #239 @ 0xef
|
|
8009df2: 71bb strb r3, [r7, #6]
|
|
}
|
|
SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/
|
|
8009df4: 2118 movs r1, #24
|
|
8009df6: f640 00e7 movw r0, #2279 @ 0x8e7
|
|
8009dfa: f000 fa8d bl 800a318 <SUBGRF_WriteRegister>
|
|
8009dfe: e067 b.n 8009ed0 <SUBGRF_SetTxParams+0x17c>
|
|
}
|
|
else /* rfo_hp*/
|
|
{
|
|
/* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/
|
|
SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1));
|
|
8009e00: f640 00d8 movw r0, #2264 @ 0x8d8
|
|
8009e04: f000 faaa bl 800a35c <SUBGRF_ReadRegister>
|
|
8009e08: 4603 mov r3, r0
|
|
8009e0a: f043 031e orr.w r3, r3, #30
|
|
8009e0e: b2db uxtb r3, r3
|
|
8009e10: 4619 mov r1, r3
|
|
8009e12: f640 00d8 movw r0, #2264 @ 0x8d8
|
|
8009e16: f000 fa7f bl 800a318 <SUBGRF_WriteRegister>
|
|
/* WORKAROUND END*/
|
|
max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER);
|
|
8009e1a: 2001 movs r0, #1
|
|
8009e1c: f002 f8b2 bl 800bf84 <RBI_GetRFOMaxPowerConfig>
|
|
8009e20: 60f8 str r0, [r7, #12]
|
|
if (power > max_power)
|
|
8009e22: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8009e26: 68fa ldr r2, [r7, #12]
|
|
8009e28: 429a cmp r2, r3
|
|
8009e2a: da01 bge.n 8009e30 <SUBGRF_SetTxParams+0xdc>
|
|
{
|
|
power = max_power;
|
|
8009e2c: 68fb ldr r3, [r7, #12]
|
|
8009e2e: 71bb strb r3, [r7, #6]
|
|
}
|
|
if (max_power == 20)
|
|
8009e30: 68fb ldr r3, [r7, #12]
|
|
8009e32: 2b14 cmp r3, #20
|
|
8009e34: d10e bne.n 8009e54 <SUBGRF_SetTxParams+0x100>
|
|
{
|
|
SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01);
|
|
8009e36: 2301 movs r3, #1
|
|
8009e38: 2200 movs r2, #0
|
|
8009e3a: 2105 movs r1, #5
|
|
8009e3c: 2003 movs r0, #3
|
|
8009e3e: f7ff fe9f bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x16 - (max_power - power);
|
|
8009e42: 79ba ldrb r2, [r7, #6]
|
|
8009e44: 68fb ldr r3, [r7, #12]
|
|
8009e46: b2db uxtb r3, r3
|
|
8009e48: 1ad3 subs r3, r2, r3
|
|
8009e4a: b2db uxtb r3, r3
|
|
8009e4c: 3316 adds r3, #22
|
|
8009e4e: b2db uxtb r3, r3
|
|
8009e50: 71bb strb r3, [r7, #6]
|
|
8009e52: e031 b.n 8009eb8 <SUBGRF_SetTxParams+0x164>
|
|
}
|
|
else if (max_power == 17)
|
|
8009e54: 68fb ldr r3, [r7, #12]
|
|
8009e56: 2b11 cmp r3, #17
|
|
8009e58: d10e bne.n 8009e78 <SUBGRF_SetTxParams+0x124>
|
|
{
|
|
SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01);
|
|
8009e5a: 2301 movs r3, #1
|
|
8009e5c: 2200 movs r2, #0
|
|
8009e5e: 2103 movs r1, #3
|
|
8009e60: 2002 movs r0, #2
|
|
8009e62: f7ff fe8d bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x16 - (max_power - power);
|
|
8009e66: 79ba ldrb r2, [r7, #6]
|
|
8009e68: 68fb ldr r3, [r7, #12]
|
|
8009e6a: b2db uxtb r3, r3
|
|
8009e6c: 1ad3 subs r3, r2, r3
|
|
8009e6e: b2db uxtb r3, r3
|
|
8009e70: 3316 adds r3, #22
|
|
8009e72: b2db uxtb r3, r3
|
|
8009e74: 71bb strb r3, [r7, #6]
|
|
8009e76: e01f b.n 8009eb8 <SUBGRF_SetTxParams+0x164>
|
|
}
|
|
else if (max_power == 14)
|
|
8009e78: 68fb ldr r3, [r7, #12]
|
|
8009e7a: 2b0e cmp r3, #14
|
|
8009e7c: d10e bne.n 8009e9c <SUBGRF_SetTxParams+0x148>
|
|
{
|
|
SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01);
|
|
8009e7e: 2301 movs r3, #1
|
|
8009e80: 2200 movs r2, #0
|
|
8009e82: 2102 movs r1, #2
|
|
8009e84: 2002 movs r0, #2
|
|
8009e86: f7ff fe7b bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x0E - (max_power - power);
|
|
8009e8a: 79ba ldrb r2, [r7, #6]
|
|
8009e8c: 68fb ldr r3, [r7, #12]
|
|
8009e8e: b2db uxtb r3, r3
|
|
8009e90: 1ad3 subs r3, r2, r3
|
|
8009e92: b2db uxtb r3, r3
|
|
8009e94: 330e adds r3, #14
|
|
8009e96: b2db uxtb r3, r3
|
|
8009e98: 71bb strb r3, [r7, #6]
|
|
8009e9a: e00d b.n 8009eb8 <SUBGRF_SetTxParams+0x164>
|
|
}
|
|
else /*22dBm*/
|
|
{
|
|
SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01);
|
|
8009e9c: 2301 movs r3, #1
|
|
8009e9e: 2200 movs r2, #0
|
|
8009ea0: 2107 movs r1, #7
|
|
8009ea2: 2004 movs r0, #4
|
|
8009ea4: f7ff fe6c bl 8009b80 <SUBGRF_SetPaConfig>
|
|
power = 0x16 - (max_power - power);
|
|
8009ea8: 79ba ldrb r2, [r7, #6]
|
|
8009eaa: 68fb ldr r3, [r7, #12]
|
|
8009eac: b2db uxtb r3, r3
|
|
8009eae: 1ad3 subs r3, r2, r3
|
|
8009eb0: b2db uxtb r3, r3
|
|
8009eb2: 3316 adds r3, #22
|
|
8009eb4: b2db uxtb r3, r3
|
|
8009eb6: 71bb strb r3, [r7, #6]
|
|
}
|
|
if (power < -9)
|
|
8009eb8: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8009ebc: f113 0f09 cmn.w r3, #9
|
|
8009ec0: da01 bge.n 8009ec6 <SUBGRF_SetTxParams+0x172>
|
|
{
|
|
power = -9;
|
|
8009ec2: 23f7 movs r3, #247 @ 0xf7
|
|
8009ec4: 71bb strb r3, [r7, #6]
|
|
}
|
|
SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/
|
|
8009ec6: 2138 movs r1, #56 @ 0x38
|
|
8009ec8: f640 00e7 movw r0, #2279 @ 0x8e7
|
|
8009ecc: f000 fa24 bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
buf[0] = power;
|
|
8009ed0: 79bb ldrb r3, [r7, #6]
|
|
8009ed2: 723b strb r3, [r7, #8]
|
|
buf[1] = (uint8_t)rampTime;
|
|
8009ed4: 797b ldrb r3, [r7, #5]
|
|
8009ed6: 727b strb r3, [r7, #9]
|
|
SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2);
|
|
8009ed8: f107 0308 add.w r3, r7, #8
|
|
8009edc: 2202 movs r2, #2
|
|
8009ede: 4619 mov r1, r3
|
|
8009ee0: 208e movs r0, #142 @ 0x8e
|
|
8009ee2: f000 fae3 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
8009ee6: bf00 nop
|
|
8009ee8: 3710 adds r7, #16
|
|
8009eea: 46bd mov sp, r7
|
|
8009eec: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009ef0 <SUBGRF_SetModulationParams>:
|
|
|
|
void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams )
|
|
{
|
|
8009ef0: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
|
|
8009ef4: b086 sub sp, #24
|
|
8009ef6: af00 add r7, sp, #0
|
|
8009ef8: 6078 str r0, [r7, #4]
|
|
uint8_t n;
|
|
uint32_t tempVal = 0;
|
|
8009efa: 2300 movs r3, #0
|
|
8009efc: 617b str r3, [r7, #20]
|
|
uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
|
8009efe: f107 0308 add.w r3, r7, #8
|
|
8009f02: 2200 movs r2, #0
|
|
8009f04: 601a str r2, [r3, #0]
|
|
8009f06: 605a str r2, [r3, #4]
|
|
|
|
// Check if required configuration corresponds to the stored packet type
|
|
// If not, silently update radio packet type
|
|
if( PacketType != modulationParams->PacketType )
|
|
8009f08: 687b ldr r3, [r7, #4]
|
|
8009f0a: 781a ldrb r2, [r3, #0]
|
|
8009f0c: 4b5c ldr r3, [pc, #368] @ (800a080 <SUBGRF_SetModulationParams+0x190>)
|
|
8009f0e: 781b ldrb r3, [r3, #0]
|
|
8009f10: 429a cmp r2, r3
|
|
8009f12: d004 beq.n 8009f1e <SUBGRF_SetModulationParams+0x2e>
|
|
{
|
|
SUBGRF_SetPacketType( modulationParams->PacketType );
|
|
8009f14: 687b ldr r3, [r7, #4]
|
|
8009f16: 781b ldrb r3, [r3, #0]
|
|
8009f18: 4618 mov r0, r3
|
|
8009f1a: f7ff fef5 bl 8009d08 <SUBGRF_SetPacketType>
|
|
}
|
|
|
|
switch( modulationParams->PacketType )
|
|
8009f1e: 687b ldr r3, [r7, #4]
|
|
8009f20: 781b ldrb r3, [r3, #0]
|
|
8009f22: 2b03 cmp r3, #3
|
|
8009f24: f200 80a5 bhi.w 800a072 <SUBGRF_SetModulationParams+0x182>
|
|
8009f28: a201 add r2, pc, #4 @ (adr r2, 8009f30 <SUBGRF_SetModulationParams+0x40>)
|
|
8009f2a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009f2e: bf00 nop
|
|
8009f30: 08009f41 .word 0x08009f41
|
|
8009f34: 0800a001 .word 0x0800a001
|
|
8009f38: 08009fc3 .word 0x08009fc3
|
|
8009f3c: 0800a02f .word 0x0800a02f
|
|
{
|
|
case PACKET_TYPE_GFSK:
|
|
n = 8;
|
|
8009f40: 2308 movs r3, #8
|
|
8009f42: 74fb strb r3, [r7, #19]
|
|
tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate );
|
|
8009f44: 687b ldr r3, [r7, #4]
|
|
8009f46: 685b ldr r3, [r3, #4]
|
|
8009f48: 4a4e ldr r2, [pc, #312] @ (800a084 <SUBGRF_SetModulationParams+0x194>)
|
|
8009f4a: fbb2 f3f3 udiv r3, r2, r3
|
|
8009f4e: 617b str r3, [r7, #20]
|
|
buf[0] = ( tempVal >> 16 ) & 0xFF;
|
|
8009f50: 697b ldr r3, [r7, #20]
|
|
8009f52: 0c1b lsrs r3, r3, #16
|
|
8009f54: b2db uxtb r3, r3
|
|
8009f56: 723b strb r3, [r7, #8]
|
|
buf[1] = ( tempVal >> 8 ) & 0xFF;
|
|
8009f58: 697b ldr r3, [r7, #20]
|
|
8009f5a: 0a1b lsrs r3, r3, #8
|
|
8009f5c: b2db uxtb r3, r3
|
|
8009f5e: 727b strb r3, [r7, #9]
|
|
buf[2] = tempVal & 0xFF;
|
|
8009f60: 697b ldr r3, [r7, #20]
|
|
8009f62: b2db uxtb r3, r3
|
|
8009f64: 72bb strb r3, [r7, #10]
|
|
buf[3] = modulationParams->Params.Gfsk.ModulationShaping;
|
|
8009f66: 687b ldr r3, [r7, #4]
|
|
8009f68: 7b1b ldrb r3, [r3, #12]
|
|
8009f6a: 72fb strb r3, [r7, #11]
|
|
buf[4] = modulationParams->Params.Gfsk.Bandwidth;
|
|
8009f6c: 687b ldr r3, [r7, #4]
|
|
8009f6e: 7b5b ldrb r3, [r3, #13]
|
|
8009f70: 733b strb r3, [r7, #12]
|
|
SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev);
|
|
8009f72: 687b ldr r3, [r7, #4]
|
|
8009f74: 689b ldr r3, [r3, #8]
|
|
8009f76: 2200 movs r2, #0
|
|
8009f78: 461c mov r4, r3
|
|
8009f7a: 4615 mov r5, r2
|
|
8009f7c: ea4f 19d4 mov.w r9, r4, lsr #7
|
|
8009f80: ea4f 6844 mov.w r8, r4, lsl #25
|
|
8009f84: 4a40 ldr r2, [pc, #256] @ (800a088 <SUBGRF_SetModulationParams+0x198>)
|
|
8009f86: f04f 0300 mov.w r3, #0
|
|
8009f8a: 4640 mov r0, r8
|
|
8009f8c: 4649 mov r1, r9
|
|
8009f8e: f7f6 f8fb bl 8000188 <__aeabi_uldivmod>
|
|
8009f92: 4602 mov r2, r0
|
|
8009f94: 460b mov r3, r1
|
|
8009f96: 4613 mov r3, r2
|
|
8009f98: 617b str r3, [r7, #20]
|
|
buf[5] = ( tempVal >> 16 ) & 0xFF;
|
|
8009f9a: 697b ldr r3, [r7, #20]
|
|
8009f9c: 0c1b lsrs r3, r3, #16
|
|
8009f9e: b2db uxtb r3, r3
|
|
8009fa0: 737b strb r3, [r7, #13]
|
|
buf[6] = ( tempVal >> 8 ) & 0xFF;
|
|
8009fa2: 697b ldr r3, [r7, #20]
|
|
8009fa4: 0a1b lsrs r3, r3, #8
|
|
8009fa6: b2db uxtb r3, r3
|
|
8009fa8: 73bb strb r3, [r7, #14]
|
|
buf[7] = ( tempVal& 0xFF );
|
|
8009faa: 697b ldr r3, [r7, #20]
|
|
8009fac: b2db uxtb r3, r3
|
|
8009fae: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
|
|
8009fb0: 7cfb ldrb r3, [r7, #19]
|
|
8009fb2: b29a uxth r2, r3
|
|
8009fb4: f107 0308 add.w r3, r7, #8
|
|
8009fb8: 4619 mov r1, r3
|
|
8009fba: 208b movs r0, #139 @ 0x8b
|
|
8009fbc: f000 fa76 bl 800a4ac <SUBGRF_WriteCommand>
|
|
break;
|
|
8009fc0: e058 b.n 800a074 <SUBGRF_SetModulationParams+0x184>
|
|
case PACKET_TYPE_BPSK:
|
|
n = 4;
|
|
8009fc2: 2304 movs r3, #4
|
|
8009fc4: 74fb strb r3, [r7, #19]
|
|
tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate );
|
|
8009fc6: 687b ldr r3, [r7, #4]
|
|
8009fc8: 691b ldr r3, [r3, #16]
|
|
8009fca: 4a2e ldr r2, [pc, #184] @ (800a084 <SUBGRF_SetModulationParams+0x194>)
|
|
8009fcc: fbb2 f3f3 udiv r3, r2, r3
|
|
8009fd0: 617b str r3, [r7, #20]
|
|
buf[0] = ( tempVal >> 16 ) & 0xFF;
|
|
8009fd2: 697b ldr r3, [r7, #20]
|
|
8009fd4: 0c1b lsrs r3, r3, #16
|
|
8009fd6: b2db uxtb r3, r3
|
|
8009fd8: 723b strb r3, [r7, #8]
|
|
buf[1] = ( tempVal >> 8 ) & 0xFF;
|
|
8009fda: 697b ldr r3, [r7, #20]
|
|
8009fdc: 0a1b lsrs r3, r3, #8
|
|
8009fde: b2db uxtb r3, r3
|
|
8009fe0: 727b strb r3, [r7, #9]
|
|
buf[2] = tempVal & 0xFF;
|
|
8009fe2: 697b ldr r3, [r7, #20]
|
|
8009fe4: b2db uxtb r3, r3
|
|
8009fe6: 72bb strb r3, [r7, #10]
|
|
buf[3] = modulationParams->Params.Bpsk.ModulationShaping;
|
|
8009fe8: 687b ldr r3, [r7, #4]
|
|
8009fea: 7d1b ldrb r3, [r3, #20]
|
|
8009fec: 72fb strb r3, [r7, #11]
|
|
SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
|
|
8009fee: 7cfb ldrb r3, [r7, #19]
|
|
8009ff0: b29a uxth r2, r3
|
|
8009ff2: f107 0308 add.w r3, r7, #8
|
|
8009ff6: 4619 mov r1, r3
|
|
8009ff8: 208b movs r0, #139 @ 0x8b
|
|
8009ffa: f000 fa57 bl 800a4ac <SUBGRF_WriteCommand>
|
|
break;
|
|
8009ffe: e039 b.n 800a074 <SUBGRF_SetModulationParams+0x184>
|
|
case PACKET_TYPE_LORA:
|
|
n = 4;
|
|
800a000: 2304 movs r3, #4
|
|
800a002: 74fb strb r3, [r7, #19]
|
|
buf[0] = modulationParams->Params.LoRa.SpreadingFactor;
|
|
800a004: 687b ldr r3, [r7, #4]
|
|
800a006: 7e1b ldrb r3, [r3, #24]
|
|
800a008: 723b strb r3, [r7, #8]
|
|
buf[1] = modulationParams->Params.LoRa.Bandwidth;
|
|
800a00a: 687b ldr r3, [r7, #4]
|
|
800a00c: 7e5b ldrb r3, [r3, #25]
|
|
800a00e: 727b strb r3, [r7, #9]
|
|
buf[2] = modulationParams->Params.LoRa.CodingRate;
|
|
800a010: 687b ldr r3, [r7, #4]
|
|
800a012: 7e9b ldrb r3, [r3, #26]
|
|
800a014: 72bb strb r3, [r7, #10]
|
|
buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize;
|
|
800a016: 687b ldr r3, [r7, #4]
|
|
800a018: 7edb ldrb r3, [r3, #27]
|
|
800a01a: 72fb strb r3, [r7, #11]
|
|
|
|
SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
|
|
800a01c: 7cfb ldrb r3, [r7, #19]
|
|
800a01e: b29a uxth r2, r3
|
|
800a020: f107 0308 add.w r3, r7, #8
|
|
800a024: 4619 mov r1, r3
|
|
800a026: 208b movs r0, #139 @ 0x8b
|
|
800a028: f000 fa40 bl 800a4ac <SUBGRF_WriteCommand>
|
|
|
|
break;
|
|
800a02c: e022 b.n 800a074 <SUBGRF_SetModulationParams+0x184>
|
|
case PACKET_TYPE_GMSK:
|
|
n = 5;
|
|
800a02e: 2305 movs r3, #5
|
|
800a030: 74fb strb r3, [r7, #19]
|
|
tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate );
|
|
800a032: 687b ldr r3, [r7, #4]
|
|
800a034: 685b ldr r3, [r3, #4]
|
|
800a036: 4a13 ldr r2, [pc, #76] @ (800a084 <SUBGRF_SetModulationParams+0x194>)
|
|
800a038: fbb2 f3f3 udiv r3, r2, r3
|
|
800a03c: 617b str r3, [r7, #20]
|
|
buf[0] = ( tempVal >> 16 ) & 0xFF;
|
|
800a03e: 697b ldr r3, [r7, #20]
|
|
800a040: 0c1b lsrs r3, r3, #16
|
|
800a042: b2db uxtb r3, r3
|
|
800a044: 723b strb r3, [r7, #8]
|
|
buf[1] = ( tempVal >> 8 ) & 0xFF;
|
|
800a046: 697b ldr r3, [r7, #20]
|
|
800a048: 0a1b lsrs r3, r3, #8
|
|
800a04a: b2db uxtb r3, r3
|
|
800a04c: 727b strb r3, [r7, #9]
|
|
buf[2] = tempVal & 0xFF;
|
|
800a04e: 697b ldr r3, [r7, #20]
|
|
800a050: b2db uxtb r3, r3
|
|
800a052: 72bb strb r3, [r7, #10]
|
|
buf[3] = modulationParams->Params.Gfsk.ModulationShaping;
|
|
800a054: 687b ldr r3, [r7, #4]
|
|
800a056: 7b1b ldrb r3, [r3, #12]
|
|
800a058: 72fb strb r3, [r7, #11]
|
|
buf[4] = modulationParams->Params.Gfsk.Bandwidth;
|
|
800a05a: 687b ldr r3, [r7, #4]
|
|
800a05c: 7b5b ldrb r3, [r3, #13]
|
|
800a05e: 733b strb r3, [r7, #12]
|
|
SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
|
|
800a060: 7cfb ldrb r3, [r7, #19]
|
|
800a062: b29a uxth r2, r3
|
|
800a064: f107 0308 add.w r3, r7, #8
|
|
800a068: 4619 mov r1, r3
|
|
800a06a: 208b movs r0, #139 @ 0x8b
|
|
800a06c: f000 fa1e bl 800a4ac <SUBGRF_WriteCommand>
|
|
break;
|
|
800a070: e000 b.n 800a074 <SUBGRF_SetModulationParams+0x184>
|
|
default:
|
|
case PACKET_TYPE_NONE:
|
|
break;
|
|
800a072: bf00 nop
|
|
}
|
|
}
|
|
800a074: bf00 nop
|
|
800a076: 3718 adds r7, #24
|
|
800a078: 46bd mov sp, r7
|
|
800a07a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
|
|
800a07e: bf00 nop
|
|
800a080: 2000031d .word 0x2000031d
|
|
800a084: 3d090000 .word 0x3d090000
|
|
800a088: 01e84800 .word 0x01e84800
|
|
|
|
0800a08c <SUBGRF_SetPacketParams>:
|
|
|
|
void SUBGRF_SetPacketParams( PacketParams_t *packetParams )
|
|
{
|
|
800a08c: b580 push {r7, lr}
|
|
800a08e: b086 sub sp, #24
|
|
800a090: af00 add r7, sp, #0
|
|
800a092: 6078 str r0, [r7, #4]
|
|
uint8_t n;
|
|
uint8_t crcVal = 0;
|
|
800a094: 2300 movs r3, #0
|
|
800a096: 75bb strb r3, [r7, #22]
|
|
uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
|
800a098: f107 030c add.w r3, r7, #12
|
|
800a09c: 2200 movs r2, #0
|
|
800a09e: 601a str r2, [r3, #0]
|
|
800a0a0: 605a str r2, [r3, #4]
|
|
800a0a2: 721a strb r2, [r3, #8]
|
|
|
|
// Check if required configuration corresponds to the stored packet type
|
|
// If not, silently update radio packet type
|
|
if( PacketType != packetParams->PacketType )
|
|
800a0a4: 687b ldr r3, [r7, #4]
|
|
800a0a6: 781a ldrb r2, [r3, #0]
|
|
800a0a8: 4b44 ldr r3, [pc, #272] @ (800a1bc <SUBGRF_SetPacketParams+0x130>)
|
|
800a0aa: 781b ldrb r3, [r3, #0]
|
|
800a0ac: 429a cmp r2, r3
|
|
800a0ae: d004 beq.n 800a0ba <SUBGRF_SetPacketParams+0x2e>
|
|
{
|
|
SUBGRF_SetPacketType( packetParams->PacketType );
|
|
800a0b0: 687b ldr r3, [r7, #4]
|
|
800a0b2: 781b ldrb r3, [r3, #0]
|
|
800a0b4: 4618 mov r0, r3
|
|
800a0b6: f7ff fe27 bl 8009d08 <SUBGRF_SetPacketType>
|
|
}
|
|
|
|
switch( packetParams->PacketType )
|
|
800a0ba: 687b ldr r3, [r7, #4]
|
|
800a0bc: 781b ldrb r3, [r3, #0]
|
|
800a0be: 2b03 cmp r3, #3
|
|
800a0c0: d878 bhi.n 800a1b4 <SUBGRF_SetPacketParams+0x128>
|
|
800a0c2: a201 add r2, pc, #4 @ (adr r2, 800a0c8 <SUBGRF_SetPacketParams+0x3c>)
|
|
800a0c4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a0c8: 0800a0d9 .word 0x0800a0d9
|
|
800a0cc: 0800a169 .word 0x0800a169
|
|
800a0d0: 0800a15d .word 0x0800a15d
|
|
800a0d4: 0800a0d9 .word 0x0800a0d9
|
|
{
|
|
case PACKET_TYPE_GMSK:
|
|
case PACKET_TYPE_GFSK:
|
|
if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM )
|
|
800a0d8: 687b ldr r3, [r7, #4]
|
|
800a0da: 7a5b ldrb r3, [r3, #9]
|
|
800a0dc: 2bf1 cmp r3, #241 @ 0xf1
|
|
800a0de: d10a bne.n 800a0f6 <SUBGRF_SetPacketParams+0x6a>
|
|
{
|
|
SUBGRF_SetCrcSeed( CRC_IBM_SEED );
|
|
800a0e0: f64f 70ff movw r0, #65535 @ 0xffff
|
|
800a0e4: f7ff faa6 bl 8009634 <SUBGRF_SetCrcSeed>
|
|
SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM );
|
|
800a0e8: f248 0005 movw r0, #32773 @ 0x8005
|
|
800a0ec: f7ff fac2 bl 8009674 <SUBGRF_SetCrcPolynomial>
|
|
crcVal = RADIO_CRC_2_BYTES;
|
|
800a0f0: 2302 movs r3, #2
|
|
800a0f2: 75bb strb r3, [r7, #22]
|
|
800a0f4: e011 b.n 800a11a <SUBGRF_SetPacketParams+0x8e>
|
|
}
|
|
else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT )
|
|
800a0f6: 687b ldr r3, [r7, #4]
|
|
800a0f8: 7a5b ldrb r3, [r3, #9]
|
|
800a0fa: 2bf2 cmp r3, #242 @ 0xf2
|
|
800a0fc: d10a bne.n 800a114 <SUBGRF_SetPacketParams+0x88>
|
|
{
|
|
SUBGRF_SetCrcSeed( CRC_CCITT_SEED );
|
|
800a0fe: f641 500f movw r0, #7439 @ 0x1d0f
|
|
800a102: f7ff fa97 bl 8009634 <SUBGRF_SetCrcSeed>
|
|
SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT );
|
|
800a106: f241 0021 movw r0, #4129 @ 0x1021
|
|
800a10a: f7ff fab3 bl 8009674 <SUBGRF_SetCrcPolynomial>
|
|
crcVal = RADIO_CRC_2_BYTES_INV;
|
|
800a10e: 2306 movs r3, #6
|
|
800a110: 75bb strb r3, [r7, #22]
|
|
800a112: e002 b.n 800a11a <SUBGRF_SetPacketParams+0x8e>
|
|
}
|
|
else
|
|
{
|
|
crcVal = packetParams->Params.Gfsk.CrcLength;
|
|
800a114: 687b ldr r3, [r7, #4]
|
|
800a116: 7a5b ldrb r3, [r3, #9]
|
|
800a118: 75bb strb r3, [r7, #22]
|
|
}
|
|
n = 9;
|
|
800a11a: 2309 movs r3, #9
|
|
800a11c: 75fb strb r3, [r7, #23]
|
|
buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF;
|
|
800a11e: 687b ldr r3, [r7, #4]
|
|
800a120: 885b ldrh r3, [r3, #2]
|
|
800a122: 0a1b lsrs r3, r3, #8
|
|
800a124: b29b uxth r3, r3
|
|
800a126: b2db uxtb r3, r3
|
|
800a128: 733b strb r3, [r7, #12]
|
|
buf[1] = packetParams->Params.Gfsk.PreambleLength;
|
|
800a12a: 687b ldr r3, [r7, #4]
|
|
800a12c: 885b ldrh r3, [r3, #2]
|
|
800a12e: b2db uxtb r3, r3
|
|
800a130: 737b strb r3, [r7, #13]
|
|
buf[2] = packetParams->Params.Gfsk.PreambleMinDetect;
|
|
800a132: 687b ldr r3, [r7, #4]
|
|
800a134: 791b ldrb r3, [r3, #4]
|
|
800a136: 73bb strb r3, [r7, #14]
|
|
buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit
|
|
800a138: 687b ldr r3, [r7, #4]
|
|
800a13a: 795b ldrb r3, [r3, #5]
|
|
800a13c: 73fb strb r3, [r7, #15]
|
|
buf[4] = packetParams->Params.Gfsk.AddrComp;
|
|
800a13e: 687b ldr r3, [r7, #4]
|
|
800a140: 799b ldrb r3, [r3, #6]
|
|
800a142: 743b strb r3, [r7, #16]
|
|
buf[5] = packetParams->Params.Gfsk.HeaderType;
|
|
800a144: 687b ldr r3, [r7, #4]
|
|
800a146: 79db ldrb r3, [r3, #7]
|
|
800a148: 747b strb r3, [r7, #17]
|
|
buf[6] = packetParams->Params.Gfsk.PayloadLength;
|
|
800a14a: 687b ldr r3, [r7, #4]
|
|
800a14c: 7a1b ldrb r3, [r3, #8]
|
|
800a14e: 74bb strb r3, [r7, #18]
|
|
buf[7] = crcVal;
|
|
800a150: 7dbb ldrb r3, [r7, #22]
|
|
800a152: 74fb strb r3, [r7, #19]
|
|
buf[8] = packetParams->Params.Gfsk.DcFree;
|
|
800a154: 687b ldr r3, [r7, #4]
|
|
800a156: 7a9b ldrb r3, [r3, #10]
|
|
800a158: 753b strb r3, [r7, #20]
|
|
break;
|
|
800a15a: e022 b.n 800a1a2 <SUBGRF_SetPacketParams+0x116>
|
|
case PACKET_TYPE_BPSK:
|
|
n = 1;
|
|
800a15c: 2301 movs r3, #1
|
|
800a15e: 75fb strb r3, [r7, #23]
|
|
buf[0] = packetParams->Params.Bpsk.PayloadLength;
|
|
800a160: 687b ldr r3, [r7, #4]
|
|
800a162: 7b1b ldrb r3, [r3, #12]
|
|
800a164: 733b strb r3, [r7, #12]
|
|
break;
|
|
800a166: e01c b.n 800a1a2 <SUBGRF_SetPacketParams+0x116>
|
|
case PACKET_TYPE_LORA:
|
|
n = 6;
|
|
800a168: 2306 movs r3, #6
|
|
800a16a: 75fb strb r3, [r7, #23]
|
|
buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF;
|
|
800a16c: 687b ldr r3, [r7, #4]
|
|
800a16e: 89db ldrh r3, [r3, #14]
|
|
800a170: 0a1b lsrs r3, r3, #8
|
|
800a172: b29b uxth r3, r3
|
|
800a174: b2db uxtb r3, r3
|
|
800a176: 733b strb r3, [r7, #12]
|
|
buf[1] = packetParams->Params.LoRa.PreambleLength;
|
|
800a178: 687b ldr r3, [r7, #4]
|
|
800a17a: 89db ldrh r3, [r3, #14]
|
|
800a17c: b2db uxtb r3, r3
|
|
800a17e: 737b strb r3, [r7, #13]
|
|
buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType;
|
|
800a180: 687b ldr r3, [r7, #4]
|
|
800a182: 7c1a ldrb r2, [r3, #16]
|
|
800a184: 4b0e ldr r3, [pc, #56] @ (800a1c0 <SUBGRF_SetPacketParams+0x134>)
|
|
800a186: 4611 mov r1, r2
|
|
800a188: 7019 strb r1, [r3, #0]
|
|
800a18a: 4613 mov r3, r2
|
|
800a18c: 73bb strb r3, [r7, #14]
|
|
buf[3] = packetParams->Params.LoRa.PayloadLength;
|
|
800a18e: 687b ldr r3, [r7, #4]
|
|
800a190: 7c5b ldrb r3, [r3, #17]
|
|
800a192: 73fb strb r3, [r7, #15]
|
|
buf[4] = packetParams->Params.LoRa.CrcMode;
|
|
800a194: 687b ldr r3, [r7, #4]
|
|
800a196: 7c9b ldrb r3, [r3, #18]
|
|
800a198: 743b strb r3, [r7, #16]
|
|
buf[5] = packetParams->Params.LoRa.InvertIQ;
|
|
800a19a: 687b ldr r3, [r7, #4]
|
|
800a19c: 7cdb ldrb r3, [r3, #19]
|
|
800a19e: 747b strb r3, [r7, #17]
|
|
break;
|
|
800a1a0: bf00 nop
|
|
default:
|
|
case PACKET_TYPE_NONE:
|
|
return;
|
|
}
|
|
SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n );
|
|
800a1a2: 7dfb ldrb r3, [r7, #23]
|
|
800a1a4: b29a uxth r2, r3
|
|
800a1a6: f107 030c add.w r3, r7, #12
|
|
800a1aa: 4619 mov r1, r3
|
|
800a1ac: 208c movs r0, #140 @ 0x8c
|
|
800a1ae: f000 f97d bl 800a4ac <SUBGRF_WriteCommand>
|
|
800a1b2: e000 b.n 800a1b6 <SUBGRF_SetPacketParams+0x12a>
|
|
return;
|
|
800a1b4: bf00 nop
|
|
}
|
|
800a1b6: 3718 adds r7, #24
|
|
800a1b8: 46bd mov sp, r7
|
|
800a1ba: bd80 pop {r7, pc}
|
|
800a1bc: 2000031d .word 0x2000031d
|
|
800a1c0: 2000031e .word 0x2000031e
|
|
|
|
0800a1c4 <SUBGRF_SetBufferBaseAddress>:
|
|
SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 );
|
|
OperatingMode = MODE_CAD;
|
|
}
|
|
|
|
void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress )
|
|
{
|
|
800a1c4: b580 push {r7, lr}
|
|
800a1c6: b084 sub sp, #16
|
|
800a1c8: af00 add r7, sp, #0
|
|
800a1ca: 4603 mov r3, r0
|
|
800a1cc: 460a mov r2, r1
|
|
800a1ce: 71fb strb r3, [r7, #7]
|
|
800a1d0: 4613 mov r3, r2
|
|
800a1d2: 71bb strb r3, [r7, #6]
|
|
uint8_t buf[2];
|
|
|
|
buf[0] = txBaseAddress;
|
|
800a1d4: 79fb ldrb r3, [r7, #7]
|
|
800a1d6: 733b strb r3, [r7, #12]
|
|
buf[1] = rxBaseAddress;
|
|
800a1d8: 79bb ldrb r3, [r7, #6]
|
|
800a1da: 737b strb r3, [r7, #13]
|
|
SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 );
|
|
800a1dc: f107 030c add.w r3, r7, #12
|
|
800a1e0: 2202 movs r2, #2
|
|
800a1e2: 4619 mov r1, r3
|
|
800a1e4: 208f movs r0, #143 @ 0x8f
|
|
800a1e6: f000 f961 bl 800a4ac <SUBGRF_WriteCommand>
|
|
}
|
|
800a1ea: bf00 nop
|
|
800a1ec: 3710 adds r7, #16
|
|
800a1ee: 46bd mov sp, r7
|
|
800a1f0: bd80 pop {r7, pc}
|
|
|
|
0800a1f2 <SUBGRF_GetRssiInst>:
|
|
status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4;
|
|
return status;
|
|
}
|
|
|
|
int8_t SUBGRF_GetRssiInst( void )
|
|
{
|
|
800a1f2: b580 push {r7, lr}
|
|
800a1f4: b082 sub sp, #8
|
|
800a1f6: af00 add r7, sp, #0
|
|
uint8_t buf[1];
|
|
int8_t rssi = 0;
|
|
800a1f8: 2300 movs r3, #0
|
|
800a1fa: 71fb strb r3, [r7, #7]
|
|
|
|
SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 );
|
|
800a1fc: 1d3b adds r3, r7, #4
|
|
800a1fe: 2201 movs r2, #1
|
|
800a200: 4619 mov r1, r3
|
|
800a202: 2015 movs r0, #21
|
|
800a204: f000 f974 bl 800a4f0 <SUBGRF_ReadCommand>
|
|
rssi = -buf[0] >> 1;
|
|
800a208: 793b ldrb r3, [r7, #4]
|
|
800a20a: 425b negs r3, r3
|
|
800a20c: 105b asrs r3, r3, #1
|
|
800a20e: 71fb strb r3, [r7, #7]
|
|
return rssi;
|
|
800a210: f997 3007 ldrsb.w r3, [r7, #7]
|
|
}
|
|
800a214: 4618 mov r0, r3
|
|
800a216: 3708 adds r7, #8
|
|
800a218: 46bd mov sp, r7
|
|
800a21a: bd80 pop {r7, pc}
|
|
|
|
0800a21c <SUBGRF_GetRxBufferStatus>:
|
|
|
|
void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer )
|
|
{
|
|
800a21c: b580 push {r7, lr}
|
|
800a21e: b084 sub sp, #16
|
|
800a220: af00 add r7, sp, #0
|
|
800a222: 6078 str r0, [r7, #4]
|
|
800a224: 6039 str r1, [r7, #0]
|
|
uint8_t status[2];
|
|
|
|
SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 );
|
|
800a226: f107 030c add.w r3, r7, #12
|
|
800a22a: 2202 movs r2, #2
|
|
800a22c: 4619 mov r1, r3
|
|
800a22e: 2013 movs r0, #19
|
|
800a230: f000 f95e bl 800a4f0 <SUBGRF_ReadCommand>
|
|
|
|
// In case of LORA fixed header, the payloadLength is obtained by reading
|
|
// the register REG_LR_PAYLOADLENGTH
|
|
if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) )
|
|
800a234: f7ff fd84 bl 8009d40 <SUBGRF_GetPacketType>
|
|
800a238: 4603 mov r3, r0
|
|
800a23a: 2b01 cmp r3, #1
|
|
800a23c: d10d bne.n 800a25a <SUBGRF_GetRxBufferStatus+0x3e>
|
|
800a23e: 4b0c ldr r3, [pc, #48] @ (800a270 <SUBGRF_GetRxBufferStatus+0x54>)
|
|
800a240: 781b ldrb r3, [r3, #0]
|
|
800a242: b2db uxtb r3, r3
|
|
800a244: 2b01 cmp r3, #1
|
|
800a246: d108 bne.n 800a25a <SUBGRF_GetRxBufferStatus+0x3e>
|
|
{
|
|
*payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH );
|
|
800a248: f240 7002 movw r0, #1794 @ 0x702
|
|
800a24c: f000 f886 bl 800a35c <SUBGRF_ReadRegister>
|
|
800a250: 4603 mov r3, r0
|
|
800a252: 461a mov r2, r3
|
|
800a254: 687b ldr r3, [r7, #4]
|
|
800a256: 701a strb r2, [r3, #0]
|
|
800a258: e002 b.n 800a260 <SUBGRF_GetRxBufferStatus+0x44>
|
|
}
|
|
else
|
|
{
|
|
*payloadLength = status[0];
|
|
800a25a: 7b3a ldrb r2, [r7, #12]
|
|
800a25c: 687b ldr r3, [r7, #4]
|
|
800a25e: 701a strb r2, [r3, #0]
|
|
}
|
|
*rxStartBufferPointer = status[1];
|
|
800a260: 7b7a ldrb r2, [r7, #13]
|
|
800a262: 683b ldr r3, [r7, #0]
|
|
800a264: 701a strb r2, [r3, #0]
|
|
}
|
|
800a266: bf00 nop
|
|
800a268: 3710 adds r7, #16
|
|
800a26a: 46bd mov sp, r7
|
|
800a26c: bd80 pop {r7, pc}
|
|
800a26e: bf00 nop
|
|
800a270: 2000031e .word 0x2000031e
|
|
|
|
0800a274 <SUBGRF_GetPacketStatus>:
|
|
|
|
void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus )
|
|
{
|
|
800a274: b580 push {r7, lr}
|
|
800a276: b084 sub sp, #16
|
|
800a278: af00 add r7, sp, #0
|
|
800a27a: 6078 str r0, [r7, #4]
|
|
uint8_t status[3];
|
|
|
|
SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 );
|
|
800a27c: f107 030c add.w r3, r7, #12
|
|
800a280: 2203 movs r2, #3
|
|
800a282: 4619 mov r1, r3
|
|
800a284: 2014 movs r0, #20
|
|
800a286: f000 f933 bl 800a4f0 <SUBGRF_ReadCommand>
|
|
|
|
pktStatus->packetType = SUBGRF_GetPacketType( );
|
|
800a28a: f7ff fd59 bl 8009d40 <SUBGRF_GetPacketType>
|
|
800a28e: 4603 mov r3, r0
|
|
800a290: 461a mov r2, r3
|
|
800a292: 687b ldr r3, [r7, #4]
|
|
800a294: 701a strb r2, [r3, #0]
|
|
switch( pktStatus->packetType )
|
|
800a296: 687b ldr r3, [r7, #4]
|
|
800a298: 781b ldrb r3, [r3, #0]
|
|
800a29a: 2b00 cmp r3, #0
|
|
800a29c: d002 beq.n 800a2a4 <SUBGRF_GetPacketStatus+0x30>
|
|
800a29e: 2b01 cmp r3, #1
|
|
800a2a0: d013 beq.n 800a2ca <SUBGRF_GetPacketStatus+0x56>
|
|
800a2a2: e02a b.n 800a2fa <SUBGRF_GetPacketStatus+0x86>
|
|
{
|
|
case PACKET_TYPE_GFSK:
|
|
pktStatus->Params.Gfsk.RxStatus = status[0];
|
|
800a2a4: 7b3a ldrb r2, [r7, #12]
|
|
800a2a6: 687b ldr r3, [r7, #4]
|
|
800a2a8: 711a strb r2, [r3, #4]
|
|
pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1;
|
|
800a2aa: 7b7b ldrb r3, [r7, #13]
|
|
800a2ac: 425b negs r3, r3
|
|
800a2ae: 105b asrs r3, r3, #1
|
|
800a2b0: b25a sxtb r2, r3
|
|
800a2b2: 687b ldr r3, [r7, #4]
|
|
800a2b4: 719a strb r2, [r3, #6]
|
|
pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1;
|
|
800a2b6: 7bbb ldrb r3, [r7, #14]
|
|
800a2b8: 425b negs r3, r3
|
|
800a2ba: 105b asrs r3, r3, #1
|
|
800a2bc: b25a sxtb r2, r3
|
|
800a2be: 687b ldr r3, [r7, #4]
|
|
800a2c0: 715a strb r2, [r3, #5]
|
|
pktStatus->Params.Gfsk.FreqError = 0;
|
|
800a2c2: 687b ldr r3, [r7, #4]
|
|
800a2c4: 2200 movs r2, #0
|
|
800a2c6: 609a str r2, [r3, #8]
|
|
break;
|
|
800a2c8: e020 b.n 800a30c <SUBGRF_GetPacketStatus+0x98>
|
|
|
|
case PACKET_TYPE_LORA:
|
|
pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1;
|
|
800a2ca: 7b3b ldrb r3, [r7, #12]
|
|
800a2cc: 425b negs r3, r3
|
|
800a2ce: 105b asrs r3, r3, #1
|
|
800a2d0: b25a sxtb r2, r3
|
|
800a2d2: 687b ldr r3, [r7, #4]
|
|
800a2d4: 731a strb r2, [r3, #12]
|
|
// Returns SNR value [dB] rounded to the nearest integer value
|
|
pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2;
|
|
800a2d6: 7b7b ldrb r3, [r7, #13]
|
|
800a2d8: b25b sxtb r3, r3
|
|
800a2da: 3302 adds r3, #2
|
|
800a2dc: 109b asrs r3, r3, #2
|
|
800a2de: b25a sxtb r2, r3
|
|
800a2e0: 687b ldr r3, [r7, #4]
|
|
800a2e2: 735a strb r2, [r3, #13]
|
|
pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1;
|
|
800a2e4: 7bbb ldrb r3, [r7, #14]
|
|
800a2e6: 425b negs r3, r3
|
|
800a2e8: 105b asrs r3, r3, #1
|
|
800a2ea: b25a sxtb r2, r3
|
|
800a2ec: 687b ldr r3, [r7, #4]
|
|
800a2ee: 739a strb r2, [r3, #14]
|
|
pktStatus->Params.LoRa.FreqError = FrequencyError;
|
|
800a2f0: 4b08 ldr r3, [pc, #32] @ (800a314 <SUBGRF_GetPacketStatus+0xa0>)
|
|
800a2f2: 681a ldr r2, [r3, #0]
|
|
800a2f4: 687b ldr r3, [r7, #4]
|
|
800a2f6: 611a str r2, [r3, #16]
|
|
break;
|
|
800a2f8: e008 b.n 800a30c <SUBGRF_GetPacketStatus+0x98>
|
|
|
|
default:
|
|
case PACKET_TYPE_NONE:
|
|
// In that specific case, we set everything in the pktStatus to zeros
|
|
// and reset the packet type accordingly
|
|
RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) );
|
|
800a2fa: 2214 movs r2, #20
|
|
800a2fc: 2100 movs r1, #0
|
|
800a2fe: 6878 ldr r0, [r7, #4]
|
|
800a300: f001 ff13 bl 800c12a <UTIL_MEM_set_8>
|
|
pktStatus->packetType = PACKET_TYPE_NONE;
|
|
800a304: 687b ldr r3, [r7, #4]
|
|
800a306: 220f movs r2, #15
|
|
800a308: 701a strb r2, [r3, #0]
|
|
break;
|
|
800a30a: bf00 nop
|
|
}
|
|
}
|
|
800a30c: bf00 nop
|
|
800a30e: 3710 adds r7, #16
|
|
800a310: 46bd mov sp, r7
|
|
800a312: bd80 pop {r7, pc}
|
|
800a314: 20000320 .word 0x20000320
|
|
|
|
0800a318 <SUBGRF_WriteRegister>:
|
|
buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF );
|
|
SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 );
|
|
}
|
|
|
|
void SUBGRF_WriteRegister( uint16_t addr, uint8_t data )
|
|
{
|
|
800a318: b580 push {r7, lr}
|
|
800a31a: b086 sub sp, #24
|
|
800a31c: af00 add r7, sp, #0
|
|
800a31e: 4603 mov r3, r0
|
|
800a320: 460a mov r2, r1
|
|
800a322: 80fb strh r3, [r7, #6]
|
|
800a324: 4613 mov r3, r2
|
|
800a326: 717b strb r3, [r7, #5]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a328: f3ef 8310 mrs r3, PRIMASK
|
|
800a32c: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a32e: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a330: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a332: b672 cpsid i
|
|
}
|
|
800a334: bf00 nop
|
|
HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 );
|
|
800a336: 1d7a adds r2, r7, #5
|
|
800a338: 88f9 ldrh r1, [r7, #6]
|
|
800a33a: 2301 movs r3, #1
|
|
800a33c: 4806 ldr r0, [pc, #24] @ (800a358 <SUBGRF_WriteRegister+0x40>)
|
|
800a33e: f7fa fa95 bl 800486c <HAL_SUBGHZ_WriteRegisters>
|
|
800a342: 697b ldr r3, [r7, #20]
|
|
800a344: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a346: 693b ldr r3, [r7, #16]
|
|
800a348: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a34c: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a34e: bf00 nop
|
|
800a350: 3718 adds r7, #24
|
|
800a352: 46bd mov sp, r7
|
|
800a354: bd80 pop {r7, pc}
|
|
800a356: bf00 nop
|
|
800a358: 20000078 .word 0x20000078
|
|
|
|
0800a35c <SUBGRF_ReadRegister>:
|
|
|
|
uint8_t SUBGRF_ReadRegister( uint16_t addr )
|
|
{
|
|
800a35c: b580 push {r7, lr}
|
|
800a35e: b086 sub sp, #24
|
|
800a360: af00 add r7, sp, #0
|
|
800a362: 4603 mov r3, r0
|
|
800a364: 80fb strh r3, [r7, #6]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a366: f3ef 8310 mrs r3, PRIMASK
|
|
800a36a: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a36c: 68fb ldr r3, [r7, #12]
|
|
uint8_t data;
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a36e: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a370: b672 cpsid i
|
|
}
|
|
800a372: bf00 nop
|
|
HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 );
|
|
800a374: f107 020b add.w r2, r7, #11
|
|
800a378: 88f9 ldrh r1, [r7, #6]
|
|
800a37a: 2301 movs r3, #1
|
|
800a37c: 4806 ldr r0, [pc, #24] @ (800a398 <SUBGRF_ReadRegister+0x3c>)
|
|
800a37e: f7fa fad4 bl 800492a <HAL_SUBGHZ_ReadRegisters>
|
|
800a382: 697b ldr r3, [r7, #20]
|
|
800a384: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a386: 693b ldr r3, [r7, #16]
|
|
800a388: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a38c: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
return data;
|
|
800a38e: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
800a390: 4618 mov r0, r3
|
|
800a392: 3718 adds r7, #24
|
|
800a394: 46bd mov sp, r7
|
|
800a396: bd80 pop {r7, pc}
|
|
800a398: 20000078 .word 0x20000078
|
|
|
|
0800a39c <SUBGRF_WriteRegisters>:
|
|
|
|
void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size )
|
|
{
|
|
800a39c: b580 push {r7, lr}
|
|
800a39e: b086 sub sp, #24
|
|
800a3a0: af00 add r7, sp, #0
|
|
800a3a2: 4603 mov r3, r0
|
|
800a3a4: 6039 str r1, [r7, #0]
|
|
800a3a6: 80fb strh r3, [r7, #6]
|
|
800a3a8: 4613 mov r3, r2
|
|
800a3aa: 80bb strh r3, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a3ac: f3ef 8310 mrs r3, PRIMASK
|
|
800a3b0: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a3b2: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a3b4: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a3b6: b672 cpsid i
|
|
}
|
|
800a3b8: bf00 nop
|
|
HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size );
|
|
800a3ba: 88bb ldrh r3, [r7, #4]
|
|
800a3bc: 88f9 ldrh r1, [r7, #6]
|
|
800a3be: 683a ldr r2, [r7, #0]
|
|
800a3c0: 4806 ldr r0, [pc, #24] @ (800a3dc <SUBGRF_WriteRegisters+0x40>)
|
|
800a3c2: f7fa fa53 bl 800486c <HAL_SUBGHZ_WriteRegisters>
|
|
800a3c6: 697b ldr r3, [r7, #20]
|
|
800a3c8: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a3ca: 693b ldr r3, [r7, #16]
|
|
800a3cc: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a3d0: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a3d2: bf00 nop
|
|
800a3d4: 3718 adds r7, #24
|
|
800a3d6: 46bd mov sp, r7
|
|
800a3d8: bd80 pop {r7, pc}
|
|
800a3da: bf00 nop
|
|
800a3dc: 20000078 .word 0x20000078
|
|
|
|
0800a3e0 <SUBGRF_ReadRegisters>:
|
|
|
|
void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size )
|
|
{
|
|
800a3e0: b580 push {r7, lr}
|
|
800a3e2: b086 sub sp, #24
|
|
800a3e4: af00 add r7, sp, #0
|
|
800a3e6: 4603 mov r3, r0
|
|
800a3e8: 6039 str r1, [r7, #0]
|
|
800a3ea: 80fb strh r3, [r7, #6]
|
|
800a3ec: 4613 mov r3, r2
|
|
800a3ee: 80bb strh r3, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a3f0: f3ef 8310 mrs r3, PRIMASK
|
|
800a3f4: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a3f6: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a3f8: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a3fa: b672 cpsid i
|
|
}
|
|
800a3fc: bf00 nop
|
|
HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size );
|
|
800a3fe: 88bb ldrh r3, [r7, #4]
|
|
800a400: 88f9 ldrh r1, [r7, #6]
|
|
800a402: 683a ldr r2, [r7, #0]
|
|
800a404: 4806 ldr r0, [pc, #24] @ (800a420 <SUBGRF_ReadRegisters+0x40>)
|
|
800a406: f7fa fa90 bl 800492a <HAL_SUBGHZ_ReadRegisters>
|
|
800a40a: 697b ldr r3, [r7, #20]
|
|
800a40c: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a40e: 693b ldr r3, [r7, #16]
|
|
800a410: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a414: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a416: bf00 nop
|
|
800a418: 3718 adds r7, #24
|
|
800a41a: 46bd mov sp, r7
|
|
800a41c: bd80 pop {r7, pc}
|
|
800a41e: bf00 nop
|
|
800a420: 20000078 .word 0x20000078
|
|
|
|
0800a424 <SUBGRF_WriteBuffer>:
|
|
|
|
void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
|
|
{
|
|
800a424: b580 push {r7, lr}
|
|
800a426: b086 sub sp, #24
|
|
800a428: af00 add r7, sp, #0
|
|
800a42a: 4603 mov r3, r0
|
|
800a42c: 6039 str r1, [r7, #0]
|
|
800a42e: 71fb strb r3, [r7, #7]
|
|
800a430: 4613 mov r3, r2
|
|
800a432: 71bb strb r3, [r7, #6]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a434: f3ef 8310 mrs r3, PRIMASK
|
|
800a438: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a43a: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a43c: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a43e: b672 cpsid i
|
|
}
|
|
800a440: bf00 nop
|
|
HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size );
|
|
800a442: 79bb ldrb r3, [r7, #6]
|
|
800a444: b29b uxth r3, r3
|
|
800a446: 79f9 ldrb r1, [r7, #7]
|
|
800a448: 683a ldr r2, [r7, #0]
|
|
800a44a: 4806 ldr r0, [pc, #24] @ (800a464 <SUBGRF_WriteBuffer+0x40>)
|
|
800a44c: f7fa fb81 bl 8004b52 <HAL_SUBGHZ_WriteBuffer>
|
|
800a450: 697b ldr r3, [r7, #20]
|
|
800a452: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a454: 693b ldr r3, [r7, #16]
|
|
800a456: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a45a: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a45c: bf00 nop
|
|
800a45e: 3718 adds r7, #24
|
|
800a460: 46bd mov sp, r7
|
|
800a462: bd80 pop {r7, pc}
|
|
800a464: 20000078 .word 0x20000078
|
|
|
|
0800a468 <SUBGRF_ReadBuffer>:
|
|
|
|
void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
|
|
{
|
|
800a468: b580 push {r7, lr}
|
|
800a46a: b086 sub sp, #24
|
|
800a46c: af00 add r7, sp, #0
|
|
800a46e: 4603 mov r3, r0
|
|
800a470: 6039 str r1, [r7, #0]
|
|
800a472: 71fb strb r3, [r7, #7]
|
|
800a474: 4613 mov r3, r2
|
|
800a476: 71bb strb r3, [r7, #6]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a478: f3ef 8310 mrs r3, PRIMASK
|
|
800a47c: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a47e: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a480: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a482: b672 cpsid i
|
|
}
|
|
800a484: bf00 nop
|
|
HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size );
|
|
800a486: 79bb ldrb r3, [r7, #6]
|
|
800a488: b29b uxth r3, r3
|
|
800a48a: 79f9 ldrb r1, [r7, #7]
|
|
800a48c: 683a ldr r2, [r7, #0]
|
|
800a48e: 4806 ldr r0, [pc, #24] @ (800a4a8 <SUBGRF_ReadBuffer+0x40>)
|
|
800a490: f7fa fbb2 bl 8004bf8 <HAL_SUBGHZ_ReadBuffer>
|
|
800a494: 697b ldr r3, [r7, #20]
|
|
800a496: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a498: 693b ldr r3, [r7, #16]
|
|
800a49a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a49e: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a4a0: bf00 nop
|
|
800a4a2: 3718 adds r7, #24
|
|
800a4a4: 46bd mov sp, r7
|
|
800a4a6: bd80 pop {r7, pc}
|
|
800a4a8: 20000078 .word 0x20000078
|
|
|
|
0800a4ac <SUBGRF_WriteCommand>:
|
|
|
|
void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer,
|
|
uint16_t Size )
|
|
{
|
|
800a4ac: b580 push {r7, lr}
|
|
800a4ae: b086 sub sp, #24
|
|
800a4b0: af00 add r7, sp, #0
|
|
800a4b2: 4603 mov r3, r0
|
|
800a4b4: 6039 str r1, [r7, #0]
|
|
800a4b6: 71fb strb r3, [r7, #7]
|
|
800a4b8: 4613 mov r3, r2
|
|
800a4ba: 80bb strh r3, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a4bc: f3ef 8310 mrs r3, PRIMASK
|
|
800a4c0: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a4c2: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a4c4: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a4c6: b672 cpsid i
|
|
}
|
|
800a4c8: bf00 nop
|
|
HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size );
|
|
800a4ca: 88bb ldrh r3, [r7, #4]
|
|
800a4cc: 79f9 ldrb r1, [r7, #7]
|
|
800a4ce: 683a ldr r2, [r7, #0]
|
|
800a4d0: 4806 ldr r0, [pc, #24] @ (800a4ec <SUBGRF_WriteCommand+0x40>)
|
|
800a4d2: f7fa fa8b bl 80049ec <HAL_SUBGHZ_ExecSetCmd>
|
|
800a4d6: 697b ldr r3, [r7, #20]
|
|
800a4d8: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a4da: 693b ldr r3, [r7, #16]
|
|
800a4dc: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a4e0: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a4e2: bf00 nop
|
|
800a4e4: 3718 adds r7, #24
|
|
800a4e6: 46bd mov sp, r7
|
|
800a4e8: bd80 pop {r7, pc}
|
|
800a4ea: bf00 nop
|
|
800a4ec: 20000078 .word 0x20000078
|
|
|
|
0800a4f0 <SUBGRF_ReadCommand>:
|
|
|
|
void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer,
|
|
uint16_t Size )
|
|
{
|
|
800a4f0: b580 push {r7, lr}
|
|
800a4f2: b086 sub sp, #24
|
|
800a4f4: af00 add r7, sp, #0
|
|
800a4f6: 4603 mov r3, r0
|
|
800a4f8: 6039 str r1, [r7, #0]
|
|
800a4fa: 71fb strb r3, [r7, #7]
|
|
800a4fc: 4613 mov r3, r2
|
|
800a4fe: 80bb strh r3, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800a500: f3ef 8310 mrs r3, PRIMASK
|
|
800a504: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800a506: 68fb ldr r3, [r7, #12]
|
|
CRITICAL_SECTION_BEGIN();
|
|
800a508: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800a50a: b672 cpsid i
|
|
}
|
|
800a50c: bf00 nop
|
|
HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size );
|
|
800a50e: 88bb ldrh r3, [r7, #4]
|
|
800a510: 79f9 ldrb r1, [r7, #7]
|
|
800a512: 683a ldr r2, [r7, #0]
|
|
800a514: 4806 ldr r0, [pc, #24] @ (800a530 <SUBGRF_ReadCommand+0x40>)
|
|
800a516: f7fa fac8 bl 8004aaa <HAL_SUBGHZ_ExecGetCmd>
|
|
800a51a: 697b ldr r3, [r7, #20]
|
|
800a51c: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800a51e: 693b ldr r3, [r7, #16]
|
|
800a520: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800a524: bf00 nop
|
|
CRITICAL_SECTION_END();
|
|
}
|
|
800a526: bf00 nop
|
|
800a528: 3718 adds r7, #24
|
|
800a52a: 46bd mov sp, r7
|
|
800a52c: bd80 pop {r7, pc}
|
|
800a52e: bf00 nop
|
|
800a530: 20000078 .word 0x20000078
|
|
|
|
0800a534 <SUBGRF_SetSwitch>:
|
|
|
|
void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx )
|
|
{
|
|
800a534: b580 push {r7, lr}
|
|
800a536: b084 sub sp, #16
|
|
800a538: af00 add r7, sp, #0
|
|
800a53a: 4603 mov r3, r0
|
|
800a53c: 460a mov r2, r1
|
|
800a53e: 71fb strb r3, [r7, #7]
|
|
800a540: 4613 mov r3, r2
|
|
800a542: 71bb strb r3, [r7, #6]
|
|
RBI_Switch_TypeDef state = RBI_SWITCH_RX;
|
|
800a544: 2301 movs r3, #1
|
|
800a546: 73fb strb r3, [r7, #15]
|
|
|
|
if (rxtx == RFSWITCH_TX)
|
|
800a548: 79bb ldrb r3, [r7, #6]
|
|
800a54a: 2b01 cmp r3, #1
|
|
800a54c: d10d bne.n 800a56a <SUBGRF_SetSwitch+0x36>
|
|
{
|
|
if (paSelect == RFO_LP)
|
|
800a54e: 79fb ldrb r3, [r7, #7]
|
|
800a550: 2b01 cmp r3, #1
|
|
800a552: d104 bne.n 800a55e <SUBGRF_SetSwitch+0x2a>
|
|
{
|
|
state = RBI_SWITCH_RFO_LP;
|
|
800a554: 2302 movs r3, #2
|
|
800a556: 73fb strb r3, [r7, #15]
|
|
Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX);
|
|
800a558: 2004 movs r0, #4
|
|
800a55a: f000 f8ef bl 800a73c <Radio_SMPS_Set>
|
|
}
|
|
if (paSelect == RFO_HP)
|
|
800a55e: 79fb ldrb r3, [r7, #7]
|
|
800a560: 2b02 cmp r3, #2
|
|
800a562: d107 bne.n 800a574 <SUBGRF_SetSwitch+0x40>
|
|
{
|
|
state = RBI_SWITCH_RFO_HP;
|
|
800a564: 2303 movs r3, #3
|
|
800a566: 73fb strb r3, [r7, #15]
|
|
800a568: e004 b.n 800a574 <SUBGRF_SetSwitch+0x40>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (rxtx == RFSWITCH_RX)
|
|
800a56a: 79bb ldrb r3, [r7, #6]
|
|
800a56c: 2b00 cmp r3, #0
|
|
800a56e: d101 bne.n 800a574 <SUBGRF_SetSwitch+0x40>
|
|
{
|
|
state = RBI_SWITCH_RX;
|
|
800a570: 2301 movs r3, #1
|
|
800a572: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
RBI_ConfigRFSwitch(state);
|
|
800a574: 7bfb ldrb r3, [r7, #15]
|
|
800a576: 4618 mov r0, r3
|
|
800a578: f001 fce1 bl 800bf3e <RBI_ConfigRFSwitch>
|
|
}
|
|
800a57c: bf00 nop
|
|
800a57e: 3710 adds r7, #16
|
|
800a580: 46bd mov sp, r7
|
|
800a582: bd80 pop {r7, pc}
|
|
|
|
0800a584 <SUBGRF_SetRfTxPower>:
|
|
|
|
uint8_t SUBGRF_SetRfTxPower( int8_t power )
|
|
{
|
|
800a584: b580 push {r7, lr}
|
|
800a586: b084 sub sp, #16
|
|
800a588: af00 add r7, sp, #0
|
|
800a58a: 4603 mov r3, r0
|
|
800a58c: 71fb strb r3, [r7, #7]
|
|
uint8_t paSelect= RFO_LP;
|
|
800a58e: 2301 movs r3, #1
|
|
800a590: 73fb strb r3, [r7, #15]
|
|
|
|
int32_t TxConfig = RBI_GetTxConfig();
|
|
800a592: f001 fce2 bl 800bf5a <RBI_GetTxConfig>
|
|
800a596: 60b8 str r0, [r7, #8]
|
|
|
|
switch (TxConfig)
|
|
800a598: 68bb ldr r3, [r7, #8]
|
|
800a59a: 2b02 cmp r3, #2
|
|
800a59c: d016 beq.n 800a5cc <SUBGRF_SetRfTxPower+0x48>
|
|
800a59e: 68bb ldr r3, [r7, #8]
|
|
800a5a0: 2b02 cmp r3, #2
|
|
800a5a2: dc16 bgt.n 800a5d2 <SUBGRF_SetRfTxPower+0x4e>
|
|
800a5a4: 68bb ldr r3, [r7, #8]
|
|
800a5a6: 2b00 cmp r3, #0
|
|
800a5a8: d003 beq.n 800a5b2 <SUBGRF_SetRfTxPower+0x2e>
|
|
800a5aa: 68bb ldr r3, [r7, #8]
|
|
800a5ac: 2b01 cmp r3, #1
|
|
800a5ae: d00a beq.n 800a5c6 <SUBGRF_SetRfTxPower+0x42>
|
|
{
|
|
paSelect = RFO_HP;
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
800a5b0: e00f b.n 800a5d2 <SUBGRF_SetRfTxPower+0x4e>
|
|
if (power > 15)
|
|
800a5b2: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800a5b6: 2b0f cmp r3, #15
|
|
800a5b8: dd02 ble.n 800a5c0 <SUBGRF_SetRfTxPower+0x3c>
|
|
paSelect = RFO_HP;
|
|
800a5ba: 2302 movs r3, #2
|
|
800a5bc: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a5be: e009 b.n 800a5d4 <SUBGRF_SetRfTxPower+0x50>
|
|
paSelect = RFO_LP;
|
|
800a5c0: 2301 movs r3, #1
|
|
800a5c2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a5c4: e006 b.n 800a5d4 <SUBGRF_SetRfTxPower+0x50>
|
|
paSelect = RFO_LP;
|
|
800a5c6: 2301 movs r3, #1
|
|
800a5c8: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a5ca: e003 b.n 800a5d4 <SUBGRF_SetRfTxPower+0x50>
|
|
paSelect = RFO_HP;
|
|
800a5cc: 2302 movs r3, #2
|
|
800a5ce: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a5d0: e000 b.n 800a5d4 <SUBGRF_SetRfTxPower+0x50>
|
|
break;
|
|
800a5d2: bf00 nop
|
|
}
|
|
|
|
SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US );
|
|
800a5d4: f997 1007 ldrsb.w r1, [r7, #7]
|
|
800a5d8: 7bfb ldrb r3, [r7, #15]
|
|
800a5da: 2202 movs r2, #2
|
|
800a5dc: 4618 mov r0, r3
|
|
800a5de: f7ff fbb9 bl 8009d54 <SUBGRF_SetTxParams>
|
|
|
|
return paSelect;
|
|
800a5e2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800a5e4: 4618 mov r0, r3
|
|
800a5e6: 3710 adds r7, #16
|
|
800a5e8: 46bd mov sp, r7
|
|
800a5ea: bd80 pop {r7, pc}
|
|
|
|
0800a5ec <SUBGRF_GetRadioWakeUpTime>:
|
|
|
|
uint32_t SUBGRF_GetRadioWakeUpTime( void )
|
|
{
|
|
800a5ec: b480 push {r7}
|
|
800a5ee: af00 add r7, sp, #0
|
|
return RF_WAKEUP_TIME;
|
|
800a5f0: 2301 movs r3, #1
|
|
}
|
|
800a5f2: 4618 mov r0, r3
|
|
800a5f4: 46bd mov sp, r7
|
|
800a5f6: bc80 pop {r7}
|
|
800a5f8: 4770 bx lr
|
|
...
|
|
|
|
0800a5fc <HAL_SUBGHZ_TxCpltCallback>:
|
|
|
|
/* HAL_SUBGHz Callbacks definitions */
|
|
void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a5fc: b580 push {r7, lr}
|
|
800a5fe: b082 sub sp, #8
|
|
800a600: af00 add r7, sp, #0
|
|
800a602: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_TX_DONE );
|
|
800a604: 4b03 ldr r3, [pc, #12] @ (800a614 <HAL_SUBGHZ_TxCpltCallback+0x18>)
|
|
800a606: 681b ldr r3, [r3, #0]
|
|
800a608: 2001 movs r0, #1
|
|
800a60a: 4798 blx r3
|
|
}
|
|
800a60c: bf00 nop
|
|
800a60e: 3708 adds r7, #8
|
|
800a610: 46bd mov sp, r7
|
|
800a612: bd80 pop {r7, pc}
|
|
800a614: 20000328 .word 0x20000328
|
|
|
|
0800a618 <HAL_SUBGHZ_RxCpltCallback>:
|
|
|
|
void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a618: b580 push {r7, lr}
|
|
800a61a: b082 sub sp, #8
|
|
800a61c: af00 add r7, sp, #0
|
|
800a61e: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_RX_DONE );
|
|
800a620: 4b03 ldr r3, [pc, #12] @ (800a630 <HAL_SUBGHZ_RxCpltCallback+0x18>)
|
|
800a622: 681b ldr r3, [r3, #0]
|
|
800a624: 2002 movs r0, #2
|
|
800a626: 4798 blx r3
|
|
}
|
|
800a628: bf00 nop
|
|
800a62a: 3708 adds r7, #8
|
|
800a62c: 46bd mov sp, r7
|
|
800a62e: bd80 pop {r7, pc}
|
|
800a630: 20000328 .word 0x20000328
|
|
|
|
0800a634 <HAL_SUBGHZ_CRCErrorCallback>:
|
|
|
|
void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a634: b580 push {r7, lr}
|
|
800a636: b082 sub sp, #8
|
|
800a638: af00 add r7, sp, #0
|
|
800a63a: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_CRC_ERROR);
|
|
800a63c: 4b03 ldr r3, [pc, #12] @ (800a64c <HAL_SUBGHZ_CRCErrorCallback+0x18>)
|
|
800a63e: 681b ldr r3, [r3, #0]
|
|
800a640: 2040 movs r0, #64 @ 0x40
|
|
800a642: 4798 blx r3
|
|
}
|
|
800a644: bf00 nop
|
|
800a646: 3708 adds r7, #8
|
|
800a648: 46bd mov sp, r7
|
|
800a64a: bd80 pop {r7, pc}
|
|
800a64c: 20000328 .word 0x20000328
|
|
|
|
0800a650 <HAL_SUBGHZ_CADStatusCallback>:
|
|
|
|
void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus)
|
|
{
|
|
800a650: b580 push {r7, lr}
|
|
800a652: b082 sub sp, #8
|
|
800a654: af00 add r7, sp, #0
|
|
800a656: 6078 str r0, [r7, #4]
|
|
800a658: 460b mov r3, r1
|
|
800a65a: 70fb strb r3, [r7, #3]
|
|
switch (cadstatus)
|
|
800a65c: 78fb ldrb r3, [r7, #3]
|
|
800a65e: 2b00 cmp r3, #0
|
|
800a660: d002 beq.n 800a668 <HAL_SUBGHZ_CADStatusCallback+0x18>
|
|
800a662: 2b01 cmp r3, #1
|
|
800a664: d005 beq.n 800a672 <HAL_SUBGHZ_CADStatusCallback+0x22>
|
|
break;
|
|
case HAL_SUBGHZ_CAD_DETECTED:
|
|
RadioOnDioIrqCb( IRQ_CAD_DETECTED);
|
|
break;
|
|
default:
|
|
break;
|
|
800a666: e00a b.n 800a67e <HAL_SUBGHZ_CADStatusCallback+0x2e>
|
|
RadioOnDioIrqCb( IRQ_CAD_CLEAR);
|
|
800a668: 4b07 ldr r3, [pc, #28] @ (800a688 <HAL_SUBGHZ_CADStatusCallback+0x38>)
|
|
800a66a: 681b ldr r3, [r3, #0]
|
|
800a66c: 2080 movs r0, #128 @ 0x80
|
|
800a66e: 4798 blx r3
|
|
break;
|
|
800a670: e005 b.n 800a67e <HAL_SUBGHZ_CADStatusCallback+0x2e>
|
|
RadioOnDioIrqCb( IRQ_CAD_DETECTED);
|
|
800a672: 4b05 ldr r3, [pc, #20] @ (800a688 <HAL_SUBGHZ_CADStatusCallback+0x38>)
|
|
800a674: 681b ldr r3, [r3, #0]
|
|
800a676: f44f 7080 mov.w r0, #256 @ 0x100
|
|
800a67a: 4798 blx r3
|
|
break;
|
|
800a67c: bf00 nop
|
|
}
|
|
}
|
|
800a67e: bf00 nop
|
|
800a680: 3708 adds r7, #8
|
|
800a682: 46bd mov sp, r7
|
|
800a684: bd80 pop {r7, pc}
|
|
800a686: bf00 nop
|
|
800a688: 20000328 .word 0x20000328
|
|
|
|
0800a68c <HAL_SUBGHZ_RxTxTimeoutCallback>:
|
|
|
|
void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a68c: b580 push {r7, lr}
|
|
800a68e: b082 sub sp, #8
|
|
800a690: af00 add r7, sp, #0
|
|
800a692: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT );
|
|
800a694: 4b04 ldr r3, [pc, #16] @ (800a6a8 <HAL_SUBGHZ_RxTxTimeoutCallback+0x1c>)
|
|
800a696: 681b ldr r3, [r3, #0]
|
|
800a698: f44f 7000 mov.w r0, #512 @ 0x200
|
|
800a69c: 4798 blx r3
|
|
}
|
|
800a69e: bf00 nop
|
|
800a6a0: 3708 adds r7, #8
|
|
800a6a2: 46bd mov sp, r7
|
|
800a6a4: bd80 pop {r7, pc}
|
|
800a6a6: bf00 nop
|
|
800a6a8: 20000328 .word 0x20000328
|
|
|
|
0800a6ac <HAL_SUBGHZ_HeaderErrorCallback>:
|
|
|
|
void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a6ac: b580 push {r7, lr}
|
|
800a6ae: b082 sub sp, #8
|
|
800a6b0: af00 add r7, sp, #0
|
|
800a6b2: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_HEADER_ERROR );
|
|
800a6b4: 4b03 ldr r3, [pc, #12] @ (800a6c4 <HAL_SUBGHZ_HeaderErrorCallback+0x18>)
|
|
800a6b6: 681b ldr r3, [r3, #0]
|
|
800a6b8: 2020 movs r0, #32
|
|
800a6ba: 4798 blx r3
|
|
}
|
|
800a6bc: bf00 nop
|
|
800a6be: 3708 adds r7, #8
|
|
800a6c0: 46bd mov sp, r7
|
|
800a6c2: bd80 pop {r7, pc}
|
|
800a6c4: 20000328 .word 0x20000328
|
|
|
|
0800a6c8 <HAL_SUBGHZ_PreambleDetectedCallback>:
|
|
|
|
void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a6c8: b580 push {r7, lr}
|
|
800a6ca: b082 sub sp, #8
|
|
800a6cc: af00 add r7, sp, #0
|
|
800a6ce: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED );
|
|
800a6d0: 4b03 ldr r3, [pc, #12] @ (800a6e0 <HAL_SUBGHZ_PreambleDetectedCallback+0x18>)
|
|
800a6d2: 681b ldr r3, [r3, #0]
|
|
800a6d4: 2004 movs r0, #4
|
|
800a6d6: 4798 blx r3
|
|
}
|
|
800a6d8: bf00 nop
|
|
800a6da: 3708 adds r7, #8
|
|
800a6dc: 46bd mov sp, r7
|
|
800a6de: bd80 pop {r7, pc}
|
|
800a6e0: 20000328 .word 0x20000328
|
|
|
|
0800a6e4 <HAL_SUBGHZ_SyncWordValidCallback>:
|
|
|
|
void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a6e4: b580 push {r7, lr}
|
|
800a6e6: b082 sub sp, #8
|
|
800a6e8: af00 add r7, sp, #0
|
|
800a6ea: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_SYNCWORD_VALID );
|
|
800a6ec: 4b03 ldr r3, [pc, #12] @ (800a6fc <HAL_SUBGHZ_SyncWordValidCallback+0x18>)
|
|
800a6ee: 681b ldr r3, [r3, #0]
|
|
800a6f0: 2008 movs r0, #8
|
|
800a6f2: 4798 blx r3
|
|
}
|
|
800a6f4: bf00 nop
|
|
800a6f6: 3708 adds r7, #8
|
|
800a6f8: 46bd mov sp, r7
|
|
800a6fa: bd80 pop {r7, pc}
|
|
800a6fc: 20000328 .word 0x20000328
|
|
|
|
0800a700 <HAL_SUBGHZ_HeaderValidCallback>:
|
|
|
|
void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a700: b580 push {r7, lr}
|
|
800a702: b082 sub sp, #8
|
|
800a704: af00 add r7, sp, #0
|
|
800a706: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_HEADER_VALID );
|
|
800a708: 4b03 ldr r3, [pc, #12] @ (800a718 <HAL_SUBGHZ_HeaderValidCallback+0x18>)
|
|
800a70a: 681b ldr r3, [r3, #0]
|
|
800a70c: 2010 movs r0, #16
|
|
800a70e: 4798 blx r3
|
|
}
|
|
800a710: bf00 nop
|
|
800a712: 3708 adds r7, #8
|
|
800a714: 46bd mov sp, r7
|
|
800a716: bd80 pop {r7, pc}
|
|
800a718: 20000328 .word 0x20000328
|
|
|
|
0800a71c <HAL_SUBGHZ_LrFhssHopCallback>:
|
|
|
|
void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz)
|
|
{
|
|
800a71c: b580 push {r7, lr}
|
|
800a71e: b082 sub sp, #8
|
|
800a720: af00 add r7, sp, #0
|
|
800a722: 6078 str r0, [r7, #4]
|
|
RadioOnDioIrqCb( IRQ_LR_FHSS_HOP );
|
|
800a724: 4b04 ldr r3, [pc, #16] @ (800a738 <HAL_SUBGHZ_LrFhssHopCallback+0x1c>)
|
|
800a726: 681b ldr r3, [r3, #0]
|
|
800a728: f44f 4080 mov.w r0, #16384 @ 0x4000
|
|
800a72c: 4798 blx r3
|
|
}
|
|
800a72e: bf00 nop
|
|
800a730: 3708 adds r7, #8
|
|
800a732: 46bd mov sp, r7
|
|
800a734: bd80 pop {r7, pc}
|
|
800a736: bf00 nop
|
|
800a738: 20000328 .word 0x20000328
|
|
|
|
0800a73c <Radio_SMPS_Set>:
|
|
|
|
static void Radio_SMPS_Set(uint8_t level)
|
|
{
|
|
800a73c: b580 push {r7, lr}
|
|
800a73e: b084 sub sp, #16
|
|
800a740: af00 add r7, sp, #0
|
|
800a742: 4603 mov r3, r0
|
|
800a744: 71fb strb r3, [r7, #7]
|
|
if ( 1U == RBI_IsDCDC() )
|
|
800a746: f001 fc16 bl 800bf76 <RBI_IsDCDC>
|
|
800a74a: 4603 mov r3, r0
|
|
800a74c: 2b01 cmp r3, #1
|
|
800a74e: d112 bne.n 800a776 <Radio_SMPS_Set+0x3a>
|
|
{
|
|
uint8_t modReg;
|
|
modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R);
|
|
800a750: f640 1023 movw r0, #2339 @ 0x923
|
|
800a754: f7ff fe02 bl 800a35c <SUBGRF_ReadRegister>
|
|
800a758: 4603 mov r3, r0
|
|
800a75a: 73fb strb r3, [r7, #15]
|
|
modReg&= (~SMPS_DRV_MASK);
|
|
800a75c: 7bfb ldrb r3, [r7, #15]
|
|
800a75e: f023 0306 bic.w r3, r3, #6
|
|
800a762: 73fb strb r3, [r7, #15]
|
|
SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level);
|
|
800a764: 7bfa ldrb r2, [r7, #15]
|
|
800a766: 79fb ldrb r3, [r7, #7]
|
|
800a768: 4313 orrs r3, r2
|
|
800a76a: b2db uxtb r3, r3
|
|
800a76c: 4619 mov r1, r3
|
|
800a76e: f640 1023 movw r0, #2339 @ 0x923
|
|
800a772: f7ff fdd1 bl 800a318 <SUBGRF_WriteRegister>
|
|
}
|
|
}
|
|
800a776: bf00 nop
|
|
800a778: 3710 adds r7, #16
|
|
800a77a: 46bd mov sp, r7
|
|
800a77c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a780 <SUBGRF_GetFskBandwidthRegValue>:
|
|
|
|
uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth )
|
|
{
|
|
800a780: b480 push {r7}
|
|
800a782: b085 sub sp, #20
|
|
800a784: af00 add r7, sp, #0
|
|
800a786: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
|
|
if( bandwidth == 0 )
|
|
800a788: 687b ldr r3, [r7, #4]
|
|
800a78a: 2b00 cmp r3, #0
|
|
800a78c: d101 bne.n 800a792 <SUBGRF_GetFskBandwidthRegValue+0x12>
|
|
{
|
|
return( 0x1F );
|
|
800a78e: 231f movs r3, #31
|
|
800a790: e017 b.n 800a7c2 <SUBGRF_GetFskBandwidthRegValue+0x42>
|
|
}
|
|
|
|
for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ )
|
|
800a792: 2300 movs r3, #0
|
|
800a794: 73fb strb r3, [r7, #15]
|
|
800a796: e00f b.n 800a7b8 <SUBGRF_GetFskBandwidthRegValue+0x38>
|
|
{
|
|
if ( bandwidth < FskBandwidths[i].bandwidth )
|
|
800a798: 7bfb ldrb r3, [r7, #15]
|
|
800a79a: 4a0c ldr r2, [pc, #48] @ (800a7cc <SUBGRF_GetFskBandwidthRegValue+0x4c>)
|
|
800a79c: f852 3033 ldr.w r3, [r2, r3, lsl #3]
|
|
800a7a0: 687a ldr r2, [r7, #4]
|
|
800a7a2: 429a cmp r2, r3
|
|
800a7a4: d205 bcs.n 800a7b2 <SUBGRF_GetFskBandwidthRegValue+0x32>
|
|
{
|
|
return FskBandwidths[i].RegValue;
|
|
800a7a6: 7bfb ldrb r3, [r7, #15]
|
|
800a7a8: 4a08 ldr r2, [pc, #32] @ (800a7cc <SUBGRF_GetFskBandwidthRegValue+0x4c>)
|
|
800a7aa: 00db lsls r3, r3, #3
|
|
800a7ac: 4413 add r3, r2
|
|
800a7ae: 791b ldrb r3, [r3, #4]
|
|
800a7b0: e007 b.n 800a7c2 <SUBGRF_GetFskBandwidthRegValue+0x42>
|
|
for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ )
|
|
800a7b2: 7bfb ldrb r3, [r7, #15]
|
|
800a7b4: 3301 adds r3, #1
|
|
800a7b6: 73fb strb r3, [r7, #15]
|
|
800a7b8: 7bfb ldrb r3, [r7, #15]
|
|
800a7ba: 2b15 cmp r3, #21
|
|
800a7bc: d9ec bls.n 800a798 <SUBGRF_GetFskBandwidthRegValue+0x18>
|
|
}
|
|
}
|
|
// ERROR: Value not found
|
|
while( 1 );
|
|
800a7be: bf00 nop
|
|
800a7c0: e7fd b.n 800a7be <SUBGRF_GetFskBandwidthRegValue+0x3e>
|
|
}
|
|
800a7c2: 4618 mov r0, r3
|
|
800a7c4: 3714 adds r7, #20
|
|
800a7c6: 46bd mov sp, r7
|
|
800a7c8: bc80 pop {r7}
|
|
800a7ca: 4770 bx lr
|
|
800a7cc: 0800da70 .word 0x0800da70
|
|
|
|
0800a7d0 <SUBGRF_GetCFO>:
|
|
void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo)
|
|
{
|
|
800a7d0: b580 push {r7, lr}
|
|
800a7d2: b08a sub sp, #40 @ 0x28
|
|
800a7d4: af00 add r7, sp, #0
|
|
800a7d6: 6078 str r0, [r7, #4]
|
|
800a7d8: 6039 str r1, [r7, #0]
|
|
uint8_t BwMant[] = {4, 8, 10, 12};
|
|
800a7da: 4b35 ldr r3, [pc, #212] @ (800a8b0 <SUBGRF_GetCFO+0xe0>)
|
|
800a7dc: 60fb str r3, [r7, #12]
|
|
/* read demod bandwidth: mant bit4:3, exp bits 2:0 */
|
|
uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR ));
|
|
800a7de: f640 0007 movw r0, #2055 @ 0x807
|
|
800a7e2: f7ff fdbb bl 800a35c <SUBGRF_ReadRegister>
|
|
800a7e6: 4603 mov r3, r0
|
|
800a7e8: 77fb strb r3, [r7, #31]
|
|
uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3];
|
|
800a7ea: 7ffb ldrb r3, [r7, #31]
|
|
800a7ec: 08db lsrs r3, r3, #3
|
|
800a7ee: b2db uxtb r3, r3
|
|
800a7f0: f003 0303 and.w r3, r3, #3
|
|
800a7f4: 3328 adds r3, #40 @ 0x28
|
|
800a7f6: 443b add r3, r7
|
|
800a7f8: f813 3c1c ldrb.w r3, [r3, #-28]
|
|
800a7fc: 77bb strb r3, [r7, #30]
|
|
uint8_t bandwidth_exp = reg & 0x7;
|
|
800a7fe: 7ffb ldrb r3, [r7, #31]
|
|
800a800: f003 0307 and.w r3, r3, #7
|
|
800a804: 777b strb r3, [r7, #29]
|
|
uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 )));
|
|
800a806: 7fba ldrb r2, [r7, #30]
|
|
800a808: 7f7b ldrb r3, [r7, #29]
|
|
800a80a: 3301 adds r3, #1
|
|
800a80c: fa02 f303 lsl.w r3, r2, r3
|
|
800a810: 461a mov r2, r3
|
|
800a812: 4b28 ldr r3, [pc, #160] @ (800a8b4 <SUBGRF_GetCFO+0xe4>)
|
|
800a814: fbb3 f3f2 udiv r3, r3, r2
|
|
800a818: 61bb str r3, [r7, #24]
|
|
uint32_t cf_osr = cf_fs / bitRate;
|
|
800a81a: 69ba ldr r2, [r7, #24]
|
|
800a81c: 687b ldr r3, [r7, #4]
|
|
800a81e: fbb2 f3f3 udiv r3, r2, r3
|
|
800a822: 617b str r3, [r7, #20]
|
|
uint8_t interp = 1;
|
|
800a824: 2301 movs r3, #1
|
|
800a826: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
/* calculate demod interpolation factor */
|
|
if (cf_osr * interp < 8)
|
|
800a82a: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800a82e: 697a ldr r2, [r7, #20]
|
|
800a830: fb02 f303 mul.w r3, r2, r3
|
|
800a834: 2b07 cmp r3, #7
|
|
800a836: d802 bhi.n 800a83e <SUBGRF_GetCFO+0x6e>
|
|
{
|
|
interp = 2;
|
|
800a838: 2302 movs r3, #2
|
|
800a83a: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
if (cf_osr * interp < 4)
|
|
800a83e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800a842: 697a ldr r2, [r7, #20]
|
|
800a844: fb02 f303 mul.w r3, r2, r3
|
|
800a848: 2b03 cmp r3, #3
|
|
800a84a: d802 bhi.n 800a852 <SUBGRF_GetCFO+0x82>
|
|
{
|
|
interp = 4;
|
|
800a84c: 2304 movs r3, #4
|
|
800a84e: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
/* calculate demod sampling frequency */
|
|
uint32_t fs = cf_fs* interp;
|
|
800a852: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
|
|
800a856: 69bb ldr r3, [r7, #24]
|
|
800a858: fb02 f303 mul.w r3, r2, r3
|
|
800a85c: 613b str r3, [r7, #16]
|
|
/* get the cfo registers */
|
|
int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8;
|
|
800a85e: f44f 60d6 mov.w r0, #1712 @ 0x6b0
|
|
800a862: f7ff fd7b bl 800a35c <SUBGRF_ReadRegister>
|
|
800a866: 4603 mov r3, r0
|
|
800a868: 021b lsls r3, r3, #8
|
|
800a86a: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
800a86e: 623b str r3, [r7, #32]
|
|
cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL );
|
|
800a870: f240 60b1 movw r0, #1713 @ 0x6b1
|
|
800a874: f7ff fd72 bl 800a35c <SUBGRF_ReadRegister>
|
|
800a878: 4603 mov r3, r0
|
|
800a87a: 461a mov r2, r3
|
|
800a87c: 6a3b ldr r3, [r7, #32]
|
|
800a87e: 4313 orrs r3, r2
|
|
800a880: 623b str r3, [r7, #32]
|
|
/* negate if 12 bits sign bit is 1 */
|
|
if (( cfo_bin & 0x800 ) == 0x800 )
|
|
800a882: 6a3b ldr r3, [r7, #32]
|
|
800a884: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800a888: 2b00 cmp r3, #0
|
|
800a88a: d005 beq.n 800a898 <SUBGRF_GetCFO+0xc8>
|
|
{
|
|
cfo_bin |= 0xFFFFF000;
|
|
800a88c: 6a3b ldr r3, [r7, #32]
|
|
800a88e: ea6f 5303 mvn.w r3, r3, lsl #20
|
|
800a892: ea6f 5313 mvn.w r3, r3, lsr #20
|
|
800a896: 623b str r3, [r7, #32]
|
|
}
|
|
/* calculate cfo in Hz */
|
|
/* shift by 5 first to not saturate, cfo_bin on 12bits */
|
|
*cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 );
|
|
800a898: 693b ldr r3, [r7, #16]
|
|
800a89a: 095b lsrs r3, r3, #5
|
|
800a89c: 6a3a ldr r2, [r7, #32]
|
|
800a89e: fb02 f303 mul.w r3, r2, r3
|
|
800a8a2: 11da asrs r2, r3, #7
|
|
800a8a4: 683b ldr r3, [r7, #0]
|
|
800a8a6: 601a str r2, [r3, #0]
|
|
}
|
|
800a8a8: bf00 nop
|
|
800a8aa: 3728 adds r7, #40 @ 0x28
|
|
800a8ac: 46bd mov sp, r7
|
|
800a8ae: bd80 pop {r7, pc}
|
|
800a8b0: 0c0a0804 .word 0x0c0a0804
|
|
800a8b4: 01e84800 .word 0x01e84800
|
|
|
|
0800a8b8 <LL_DBGMCU_GetRevisionID>:
|
|
{
|
|
800a8b8: b480 push {r7}
|
|
800a8ba: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
|
|
800a8bc: 4b03 ldr r3, [pc, #12] @ (800a8cc <LL_DBGMCU_GetRevisionID+0x14>)
|
|
800a8be: 681b ldr r3, [r3, #0]
|
|
800a8c0: 0c1b lsrs r3, r3, #16
|
|
800a8c2: b29b uxth r3, r3
|
|
}
|
|
800a8c4: 4618 mov r0, r3
|
|
800a8c6: 46bd mov sp, r7
|
|
800a8c8: bc80 pop {r7}
|
|
800a8ca: 4770 bx lr
|
|
800a8cc: e0042000 .word 0xe0042000
|
|
|
|
0800a8d0 <LL_GPIO_SetOutputPin>:
|
|
{
|
|
800a8d0: b480 push {r7}
|
|
800a8d2: b083 sub sp, #12
|
|
800a8d4: af00 add r7, sp, #0
|
|
800a8d6: 6078 str r0, [r7, #4]
|
|
800a8d8: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BSRR, PinMask);
|
|
800a8da: 687b ldr r3, [r7, #4]
|
|
800a8dc: 683a ldr r2, [r7, #0]
|
|
800a8de: 619a str r2, [r3, #24]
|
|
}
|
|
800a8e0: bf00 nop
|
|
800a8e2: 370c adds r7, #12
|
|
800a8e4: 46bd mov sp, r7
|
|
800a8e6: bc80 pop {r7}
|
|
800a8e8: 4770 bx lr
|
|
|
|
0800a8ea <LL_GPIO_ResetOutputPin>:
|
|
{
|
|
800a8ea: b480 push {r7}
|
|
800a8ec: b083 sub sp, #12
|
|
800a8ee: af00 add r7, sp, #0
|
|
800a8f0: 6078 str r0, [r7, #4]
|
|
800a8f2: 6039 str r1, [r7, #0]
|
|
WRITE_REG(GPIOx->BRR, PinMask);
|
|
800a8f4: 687b ldr r3, [r7, #4]
|
|
800a8f6: 683a ldr r2, [r7, #0]
|
|
800a8f8: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
800a8fa: bf00 nop
|
|
800a8fc: 370c adds r7, #12
|
|
800a8fe: 46bd mov sp, r7
|
|
800a900: bc80 pop {r7}
|
|
800a902: 4770 bx lr
|
|
|
|
0800a904 <RFW_TransmitLongPacket>:
|
|
#endif /* RFW_ENABLE == 1 */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout,
|
|
void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) )
|
|
{
|
|
800a904: b580 push {r7, lr}
|
|
800a906: b08e sub sp, #56 @ 0x38
|
|
800a908: af02 add r7, sp, #8
|
|
800a90a: 4603 mov r3, r0
|
|
800a90c: 60b9 str r1, [r7, #8]
|
|
800a90e: 607a str r2, [r7, #4]
|
|
800a910: 81fb strh r3, [r7, #14]
|
|
int32_t status = 0;
|
|
800a912: 2300 movs r3, #0
|
|
800a914: 62fb str r3, [r7, #44] @ 0x2c
|
|
#if (RFW_LONGPACKET_ENABLE == 1 )
|
|
uint32_t total_size = payload_size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize;
|
|
800a916: 89fb ldrh r3, [r7, #14]
|
|
800a918: 4ab0 ldr r2, [pc, #704] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a91a: 7852 ldrb r2, [r2, #1]
|
|
800a91c: 4413 add r3, r2
|
|
800a91e: 4aaf ldr r2, [pc, #700] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a920: 78d2 ldrb r2, [r2, #3]
|
|
800a922: 4413 add r3, r2
|
|
800a924: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "RevID=%04X\r\n", LL_DBGMCU_GetRevisionID() );
|
|
800a926: f7ff ffc7 bl 800a8b8 <LL_DBGMCU_GetRevisionID>
|
|
800a92a: 4603 mov r3, r0
|
|
800a92c: 9300 str r3, [sp, #0]
|
|
800a92e: 4bac ldr r3, [pc, #688] @ (800abe0 <RFW_TransmitLongPacket+0x2dc>)
|
|
800a930: 2201 movs r2, #1
|
|
800a932: 2100 movs r1, #0
|
|
800a934: 2002 movs r0, #2
|
|
800a936: f002 fb25 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
|
|
if( ( TxLongPacketGetNextChunkCb == NULL ) ||
|
|
800a93a: 687b ldr r3, [r7, #4]
|
|
800a93c: 2b00 cmp r3, #0
|
|
800a93e: d012 beq.n 800a966 <RFW_TransmitLongPacket+0x62>
|
|
( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/
|
|
800a940: 4ba6 ldr r3, [pc, #664] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a942: 785b ldrb r3, [r3, #1]
|
|
800a944: 00db lsls r3, r3, #3
|
|
800a946: 2201 movs r2, #1
|
|
800a948: 409a lsls r2, r3
|
|
800a94a: 89fb ldrh r3, [r7, #14]
|
|
if( ( TxLongPacketGetNextChunkCb == NULL ) ||
|
|
800a94c: 429a cmp r2, r3
|
|
800a94e: dd0a ble.n 800a966 <RFW_TransmitLongPacket+0x62>
|
|
( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/
|
|
800a950: 4ba2 ldr r3, [pc, #648] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a952: 781b ldrb r3, [r3, #0]
|
|
( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/
|
|
800a954: 2b00 cmp r3, #0
|
|
800a956: d006 beq.n 800a966 <RFW_TransmitLongPacket+0x62>
|
|
( LL_DBGMCU_GetRevisionID() < 0x1003 ) ) /* Only available from stm32wl revision Y*/
|
|
800a958: f7ff ffae bl 800a8b8 <LL_DBGMCU_GetRevisionID>
|
|
800a95c: 4603 mov r3, r0
|
|
( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/
|
|
800a95e: f241 0202 movw r2, #4098 @ 0x1002
|
|
800a962: 4293 cmp r3, r2
|
|
800a964: d803 bhi.n 800a96e <RFW_TransmitLongPacket+0x6a>
|
|
{
|
|
status = -1;
|
|
800a966: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800a96a: 62fb str r3, [r7, #44] @ 0x2c
|
|
800a96c: e130 b.n 800abd0 <RFW_TransmitLongPacket+0x2cc>
|
|
}
|
|
else
|
|
{
|
|
/*chunk buffer pointer fed by the application*/
|
|
uint8_t *app_chunk_buffer_ptr = NULL;
|
|
800a96e: 2300 movs r3, #0
|
|
800a970: 61bb str r3, [r7, #24]
|
|
uint8_t chunk_size;
|
|
uint8_t crc_size;
|
|
/*timeout for next chunk*/
|
|
uint32_t chunk_timeout;
|
|
/*Records call back*/
|
|
RFWPacket.TxLongPacketGetNextChunkCb = TxLongPacketGetNextChunkCb;
|
|
800a972: 4a9a ldr r2, [pc, #616] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a974: 687b ldr r3, [r7, #4]
|
|
800a976: 6413 str r3, [r2, #64] @ 0x40
|
|
|
|
/* Radio IRQ is set to DIO1 by default */
|
|
SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT,
|
|
800a978: 2300 movs r3, #0
|
|
800a97a: 2200 movs r2, #0
|
|
800a97c: f240 2101 movw r1, #513 @ 0x201
|
|
800a980: f240 2001 movw r0, #513 @ 0x201
|
|
800a984: f7ff f91e bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
|
|
/* Set DBG pin */
|
|
DBG_GPIO_RADIO_TX( SET );
|
|
800a988: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
800a98c: 4895 ldr r0, [pc, #596] @ (800abe4 <RFW_TransmitLongPacket+0x2e0>)
|
|
800a98e: f7ff ff9f bl 800a8d0 <LL_GPIO_SetOutputPin>
|
|
/* Set RF switch */
|
|
SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_TX );
|
|
800a992: 4b92 ldr r3, [pc, #584] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a994: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800a998: 2101 movs r1, #1
|
|
800a99a: 4618 mov r0, r3
|
|
800a99c: f7ff fdca bl 800a534 <SUBGRF_SetSwitch>
|
|
|
|
switch( RFWPacket.Init.Modem )
|
|
800a9a0: 4b8e ldr r3, [pc, #568] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9a2: 7b9b ldrb r3, [r3, #14]
|
|
800a9a4: 2b04 cmp r3, #4
|
|
800a9a6: f200 8110 bhi.w 800abca <RFW_TransmitLongPacket+0x2c6>
|
|
800a9aa: a201 add r2, pc, #4 @ (adr r2, 800a9b0 <RFW_TransmitLongPacket+0xac>)
|
|
800a9ac: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a9b0: 0800a9c5 .word 0x0800a9c5
|
|
800a9b4: 0800abb3 .word 0x0800abb3
|
|
800a9b8: 0800a9c5 .word 0x0800a9c5
|
|
800a9bc: 0800abbb .word 0x0800abbb
|
|
800a9c0: 0800abc3 .word 0x0800abc3
|
|
{
|
|
case MODEM_FSK:
|
|
case MODEM_MSK:
|
|
{
|
|
if( RFWPacket.Init.Enable == 1 )
|
|
800a9c4: 4b85 ldr r3, [pc, #532] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9c6: 781b ldrb r3, [r3, #0]
|
|
800a9c8: 2b01 cmp r3, #1
|
|
800a9ca: f040 80ee bne.w 800abaa <RFW_TransmitLongPacket+0x2a6>
|
|
{
|
|
/*crc will be calculated on the fly along with packet chunk transmission*/
|
|
uint8_t crc_result[2];
|
|
/*init radio buffer offset*/
|
|
RFWPacket.RadioBufferOffset = 0;
|
|
800a9ce: 4b83 ldr r3, [pc, #524] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9d0: 2200 movs r2, #0
|
|
800a9d2: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
/*long packet mode enable*/
|
|
RFWPacket.LongPacketModeEnable = 1;
|
|
800a9d6: 4b81 ldr r3, [pc, #516] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9d8: 2201 movs r2, #1
|
|
800a9da: 769a strb r2, [r3, #26]
|
|
/*Remaining bytes to transmit*/
|
|
RFWPacket.LongPacketRemainingBytes = total_size;
|
|
800a9dc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a9de: b29a uxth r2, r3
|
|
800a9e0: 4b7e ldr r3, [pc, #504] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9e2: 869a strh r2, [r3, #52] @ 0x34
|
|
/*Records total payload bytes to transmit*/
|
|
RFWPacket.PayloadLength = total_size;
|
|
800a9e4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a9e6: b29a uxth r2, r3
|
|
800a9e8: 4b7c ldr r3, [pc, #496] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9ea: 831a strh r2, [r3, #24]
|
|
if( total_size > RADIO_BUF_SIZE )
|
|
800a9ec: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a9ee: 2bff cmp r3, #255 @ 0xff
|
|
800a9f0: d919 bls.n 800aa26 <RFW_TransmitLongPacket+0x122>
|
|
{
|
|
/*cut in chunk*/
|
|
if( total_size < RADIO_BUF_SIZE + RFWPacket.Init.CrcFieldSize )
|
|
800a9f2: 4b7a ldr r3, [pc, #488] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800a9f4: 78db ldrb r3, [r3, #3]
|
|
800a9f6: 33ff adds r3, #255 @ 0xff
|
|
800a9f8: 461a mov r2, r3
|
|
800a9fa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a9fc: 4293 cmp r3, r2
|
|
800a9fe: d209 bcs.n 800aa14 <RFW_TransmitLongPacket+0x110>
|
|
{
|
|
/*reduce chunk so that crc is treated in the next chunk*/
|
|
chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize - RFWPacket.Init.CrcFieldSize;
|
|
800aa00: 4b76 ldr r3, [pc, #472] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa02: 785b ldrb r3, [r3, #1]
|
|
800aa04: 43db mvns r3, r3
|
|
800aa06: b2da uxtb r2, r3
|
|
800aa08: 4b74 ldr r3, [pc, #464] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa0a: 78db ldrb r3, [r3, #3]
|
|
800aa0c: 1ad3 subs r3, r2, r3
|
|
800aa0e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800aa12: e004 b.n 800aa1e <RFW_TransmitLongPacket+0x11a>
|
|
}
|
|
else
|
|
{
|
|
chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize;
|
|
800aa14: 4b71 ldr r3, [pc, #452] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa16: 785b ldrb r3, [r3, #1]
|
|
800aa18: 43db mvns r3, r3
|
|
800aa1a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
}
|
|
/*Set crc size for the crc calculation: no crc here because it is not the end of the packet*/
|
|
crc_size = 0;
|
|
800aa1e: 2300 movs r3, #0
|
|
800aa20: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
800aa24: e006 b.n 800aa34 <RFW_TransmitLongPacket+0x130>
|
|
}
|
|
else
|
|
{
|
|
chunk_size = payload_size;
|
|
800aa26: 89fb ldrh r3, [r7, #14]
|
|
800aa28: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
/*Set crc size for the crc calculation*/
|
|
crc_size = RFWPacket.Init.CrcFieldSize;
|
|
800aa2c: 4b6b ldr r3, [pc, #428] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa2e: 78db ldrb r3, [r3, #3]
|
|
800aa30: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
/* Prepend payload size before Payload*/
|
|
if( RFWPacket.Init.PayloadLengthFieldSize == 1 )
|
|
800aa34: 4b69 ldr r3, [pc, #420] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa36: 785b ldrb r3, [r3, #1]
|
|
800aa38: 2b01 cmp r3, #1
|
|
800aa3a: d104 bne.n 800aa46 <RFW_TransmitLongPacket+0x142>
|
|
{
|
|
ChunkBuffer[0] = payload_size;
|
|
800aa3c: 89fb ldrh r3, [r7, #14]
|
|
800aa3e: b2da uxtb r2, r3
|
|
800aa40: 4b69 ldr r3, [pc, #420] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aa42: 701a strb r2, [r3, #0]
|
|
800aa44: e009 b.n 800aa5a <RFW_TransmitLongPacket+0x156>
|
|
}
|
|
else
|
|
{
|
|
ChunkBuffer[0] = ( uint8_t )( ( payload_size ) >> 8 );
|
|
800aa46: 89fb ldrh r3, [r7, #14]
|
|
800aa48: 0a1b lsrs r3, r3, #8
|
|
800aa4a: b29b uxth r3, r3
|
|
800aa4c: b2da uxtb r2, r3
|
|
800aa4e: 4b66 ldr r3, [pc, #408] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aa50: 701a strb r2, [r3, #0]
|
|
ChunkBuffer[1] = ( uint8_t )( ( payload_size ) & 0xFF );
|
|
800aa52: 89fb ldrh r3, [r7, #14]
|
|
800aa54: b2da uxtb r2, r3
|
|
800aa56: 4b64 ldr r3, [pc, #400] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aa58: 705a strb r2, [r3, #1]
|
|
}
|
|
/* Get Tx chunk from app*/
|
|
TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size );
|
|
800aa5a: f897 102b ldrb.w r1, [r7, #43] @ 0x2b
|
|
800aa5e: f107 0218 add.w r2, r7, #24
|
|
800aa62: 687b ldr r3, [r7, #4]
|
|
800aa64: 4610 mov r0, r2
|
|
800aa66: 4798 blx r3
|
|
|
|
/* Copy first chunk in ChunkBuffer Buffer*/
|
|
RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], app_chunk_buffer_ptr, chunk_size );
|
|
800aa68: 4b5c ldr r3, [pc, #368] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa6a: 785b ldrb r3, [r3, #1]
|
|
800aa6c: 461a mov r2, r3
|
|
800aa6e: 4b5e ldr r3, [pc, #376] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aa70: 4413 add r3, r2
|
|
800aa72: 69b9 ldr r1, [r7, #24]
|
|
800aa74: f897 202b ldrb.w r2, [r7, #43] @ 0x2b
|
|
800aa78: b292 uxth r2, r2
|
|
800aa7a: 4618 mov r0, r3
|
|
800aa7c: f001 fb36 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800aa80: 4b56 ldr r3, [pc, #344] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa82: 789b ldrb r3, [r3, #2]
|
|
800aa84: 2b01 cmp r3, #1
|
|
800aa86: d11f bne.n 800aac8 <RFW_TransmitLongPacket+0x1c4>
|
|
{
|
|
/* Set the state of the Crc to crc_seed*/
|
|
RFW_CrcSetState( &RFWPacket );
|
|
800aa88: 4854 ldr r0, [pc, #336] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa8a: f000 fc57 bl 800b33c <RFW_CrcSetState>
|
|
/* Run the crc calculation on payload length and payload*/
|
|
RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size, crc_result );
|
|
800aa8e: 4b53 ldr r3, [pc, #332] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aa90: 785b ldrb r3, [r3, #1]
|
|
800aa92: 461a mov r2, r3
|
|
800aa94: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
800aa98: 4413 add r3, r2
|
|
800aa9a: 461a mov r2, r3
|
|
800aa9c: f107 0314 add.w r3, r7, #20
|
|
800aaa0: 4951 ldr r1, [pc, #324] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aaa2: 484e ldr r0, [pc, #312] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aaa4: f000 fc9f bl 800b3e6 <RFW_CrcRun>
|
|
/* Append the crc result after the payload if total_size<= RADIO_BUF_SIZE*/
|
|
RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize + chunk_size], crc_result, crc_size );
|
|
800aaa8: 4b4c ldr r3, [pc, #304] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aaaa: 785b ldrb r3, [r3, #1]
|
|
800aaac: 461a mov r2, r3
|
|
800aaae: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
800aab2: 4413 add r3, r2
|
|
800aab4: 4a4c ldr r2, [pc, #304] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aab6: 4413 add r3, r2
|
|
800aab8: f897 202a ldrb.w r2, [r7, #42] @ 0x2a
|
|
800aabc: b292 uxth r2, r2
|
|
800aabe: f107 0114 add.w r1, r7, #20
|
|
800aac2: 4618 mov r0, r3
|
|
800aac4: f001 fb12 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
}
|
|
/* Init whitening at beginning of the packet*/
|
|
RFW_WhiteSetState( &RFWPacket );
|
|
800aac8: 4844 ldr r0, [pc, #272] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aaca: f000 fc0f bl 800b2ec <RFW_WhiteSetState>
|
|
/* Run the whitening calculation on payload length, payload and crc if crc fits inside 1st chunk*/
|
|
RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size );
|
|
800aace: 4b43 ldr r3, [pc, #268] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aad0: 785b ldrb r3, [r3, #1]
|
|
800aad2: 461a mov r2, r3
|
|
800aad4: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
800aad8: 441a add r2, r3
|
|
800aada: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
800aade: 4413 add r3, r2
|
|
800aae0: 461a mov r2, r3
|
|
800aae2: 4941 ldr r1, [pc, #260] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800aae4: 483d ldr r0, [pc, #244] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aae6: f000 fc36 bl 800b356 <RFW_WhiteRun>
|
|
/* Configure the Transmitter to send all*/
|
|
/* Init radio buffer */
|
|
SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size );
|
|
800aaea: 4b3c ldr r3, [pc, #240] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aaec: 785a ldrb r2, [r3, #1]
|
|
800aaee: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
800aaf2: 4413 add r3, r2
|
|
800aaf4: b2da uxtb r2, r3
|
|
800aaf6: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
800aafa: 4413 add r3, r2
|
|
800aafc: b2db uxtb r3, r3
|
|
800aafe: 4619 mov r1, r3
|
|
800ab00: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800ab04: f7ff fc08 bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( SUBGHZ_TXADRPTR, 0 );
|
|
800ab08: 2100 movs r1, #0
|
|
800ab0a: f640 0002 movw r0, #2050 @ 0x802
|
|
800ab0e: f7ff fc03 bl 800a318 <SUBGRF_WriteRegister>
|
|
/* Send*/
|
|
SUBGRF_SendPayload( ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size, 0 );
|
|
800ab12: 4b32 ldr r3, [pc, #200] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800ab14: 785a ldrb r2, [r3, #1]
|
|
800ab16: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
800ab1a: 4413 add r3, r2
|
|
800ab1c: b2da uxtb r2, r3
|
|
800ab1e: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
800ab22: 4413 add r3, r2
|
|
800ab24: b2db uxtb r3, r3
|
|
800ab26: 2200 movs r2, #0
|
|
800ab28: 4619 mov r1, r3
|
|
800ab2a: 482f ldr r0, [pc, #188] @ (800abe8 <RFW_TransmitLongPacket+0x2e4>)
|
|
800ab2c: f7fe fd60 bl 80095f0 <SUBGRF_SendPayload>
|
|
if( total_size > RADIO_BUF_SIZE )
|
|
800ab30: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ab32: 2bff cmp r3, #255 @ 0xff
|
|
800ab34: d94b bls.n 800abce <RFW_TransmitLongPacket+0x2ca>
|
|
{
|
|
/*in case total size is greater than RADIO_BUF_SIZE, need to program a timer to get next chunk*/
|
|
/*RFWPacket.LongPacketRemainingBytes-= RFWPacket.Init.PayloadLengthFieldSize+ chunk_size+ crc_size;*/
|
|
/*Initialize Timer to get new chunk and update radio ptr*/
|
|
chunk_timeout = ( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000 ) / RFWPacket.BitRate;
|
|
800ab36: 4b29 ldr r3, [pc, #164] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800ab38: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800ab3a: f44f 227a mov.w r2, #1024000 @ 0xfa000
|
|
800ab3e: fbb2 f3f3 udiv r3, r2, r3
|
|
800ab42: 623b str r3, [r7, #32]
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "Timeout=%d,\r\n", chunk_timeout );
|
|
800ab44: 6a3b ldr r3, [r7, #32]
|
|
800ab46: 9300 str r3, [sp, #0]
|
|
800ab48: 4b28 ldr r3, [pc, #160] @ (800abec <RFW_TransmitLongPacket+0x2e8>)
|
|
800ab4a: 2201 movs r2, #1
|
|
800ab4c: 2100 movs r1, #0
|
|
800ab4e: 2002 movs r0, #2
|
|
800ab50: f002 fa18 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
TimerInit( &RFWPacket.Timer, RFW_TransmitLongPacket_NewTxChunkTimerEvent );
|
|
800ab54: 2300 movs r3, #0
|
|
800ab56: 9300 str r3, [sp, #0]
|
|
800ab58: 4b25 ldr r3, [pc, #148] @ (800abf0 <RFW_TransmitLongPacket+0x2ec>)
|
|
800ab5a: 2200 movs r2, #0
|
|
800ab5c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
800ab60: 4824 ldr r0, [pc, #144] @ (800abf4 <RFW_TransmitLongPacket+0x2f0>)
|
|
800ab62: f001 ff73 bl 800ca4c <UTIL_TIMER_Create>
|
|
TimerSetValue( &RFWPacket.Timer, chunk_timeout );
|
|
800ab66: 6a39 ldr r1, [r7, #32]
|
|
800ab68: 4822 ldr r0, [pc, #136] @ (800abf4 <RFW_TransmitLongPacket+0x2f0>)
|
|
800ab6a: f002 f883 bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RFWPacket.Timer );
|
|
800ab6e: 4821 ldr r0, [pc, #132] @ (800abf4 <RFW_TransmitLongPacket+0x2f0>)
|
|
800ab70: f001 ffa2 bl 800cab8 <UTIL_TIMER_Start>
|
|
/*Write bit infinite_sequence = 1, required for long packet*/
|
|
uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR );
|
|
800ab74: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
800ab78: f7ff fbf0 bl 800a35c <SUBGRF_ReadRegister>
|
|
800ab7c: 4603 mov r3, r0
|
|
800ab7e: 77fb strb r3, [r7, #31]
|
|
SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg | 0x02 );
|
|
800ab80: 7ffb ldrb r3, [r7, #31]
|
|
800ab82: f043 0302 orr.w r3, r3, #2
|
|
800ab86: b2db uxtb r3, r3
|
|
800ab88: 4619 mov r1, r3
|
|
800ab8a: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
800ab8e: f7ff fbc3 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
TimerSetValue( RFWPacket.RxTimeoutTimer, timeout );
|
|
800ab92: 4b12 ldr r3, [pc, #72] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800ab94: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800ab96: 68b9 ldr r1, [r7, #8]
|
|
800ab98: 4618 mov r0, r3
|
|
800ab9a: f002 f86b bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( RFWPacket.RxTimeoutTimer );
|
|
800ab9e: 4b0f ldr r3, [pc, #60] @ (800abdc <RFW_TransmitLongPacket+0x2d8>)
|
|
800aba0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800aba2: 4618 mov r0, r3
|
|
800aba4: f001 ff88 bl 800cab8 <UTIL_TIMER_Start>
|
|
else
|
|
{
|
|
/* error*/
|
|
status = -1;
|
|
}
|
|
break;
|
|
800aba8: e011 b.n 800abce <RFW_TransmitLongPacket+0x2ca>
|
|
status = -1;
|
|
800abaa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800abae: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
800abb0: e00d b.n 800abce <RFW_TransmitLongPacket+0x2ca>
|
|
}
|
|
case MODEM_LORA:
|
|
{
|
|
/* not supported by the radio Ip*/
|
|
status = -2;
|
|
800abb2: f06f 0301 mvn.w r3, #1
|
|
800abb6: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
800abb8: e00a b.n 800abd0 <RFW_TransmitLongPacket+0x2cc>
|
|
}
|
|
case MODEM_BPSK:
|
|
{
|
|
/* not supported by the FW*/
|
|
status = -2;
|
|
800abba: f06f 0301 mvn.w r3, #1
|
|
800abbe: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
800abc0: e006 b.n 800abd0 <RFW_TransmitLongPacket+0x2cc>
|
|
}
|
|
case MODEM_SIGFOX_TX:
|
|
{
|
|
/* not supported by the FW*/
|
|
status = -2;
|
|
800abc2: f06f 0301 mvn.w r3, #1
|
|
800abc6: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
800abc8: e002 b.n 800abd0 <RFW_TransmitLongPacket+0x2cc>
|
|
}
|
|
default:
|
|
break;
|
|
800abca: bf00 nop
|
|
800abcc: e000 b.n 800abd0 <RFW_TransmitLongPacket+0x2cc>
|
|
break;
|
|
800abce: bf00 nop
|
|
}
|
|
}
|
|
#else
|
|
status = -1;
|
|
#endif /* RFW_LONGPACKET_ENABLE == 1 */
|
|
return status;
|
|
800abd0: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
800abd2: 4618 mov r0, r3
|
|
800abd4: 3730 adds r7, #48 @ 0x30
|
|
800abd6: 46bd mov sp, r7
|
|
800abd8: bd80 pop {r7, pc}
|
|
800abda: bf00 nop
|
|
800abdc: 2000032c .word 0x2000032c
|
|
800abe0: 0800d5a4 .word 0x0800d5a4
|
|
800abe4: 48000400 .word 0x48000400
|
|
800abe8: 20000380 .word 0x20000380
|
|
800abec: 0800d5b4 .word 0x0800d5b4
|
|
800abf0: 0800b0ed .word 0x0800b0ed
|
|
800abf4: 20000348 .word 0x20000348
|
|
|
|
0800abf8 <RFW_ReceiveLongPacket>:
|
|
|
|
int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout,
|
|
void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) )
|
|
{
|
|
800abf8: b580 push {r7, lr}
|
|
800abfa: b086 sub sp, #24
|
|
800abfc: af00 add r7, sp, #0
|
|
800abfe: 4603 mov r3, r0
|
|
800ac00: 60b9 str r1, [r7, #8]
|
|
800ac02: 607a str r2, [r7, #4]
|
|
800ac04: 73fb strb r3, [r7, #15]
|
|
int32_t status = 0;
|
|
800ac06: 2300 movs r3, #0
|
|
800ac08: 617b str r3, [r7, #20]
|
|
#if (RFW_LONGPACKET_ENABLE == 1 )
|
|
if( ( RxLongPacketStoreChunkCb == NULL ) ||
|
|
800ac0a: 687b ldr r3, [r7, #4]
|
|
800ac0c: 2b00 cmp r3, #0
|
|
800ac0e: d003 beq.n 800ac18 <RFW_ReceiveLongPacket+0x20>
|
|
( RFWPacket.Init.Enable == 0 ) ) /* Can only be used when after RadioSetRxGenericConfig*/
|
|
800ac10: 4b2a ldr r3, [pc, #168] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac12: 781b ldrb r3, [r3, #0]
|
|
if( ( RxLongPacketStoreChunkCb == NULL ) ||
|
|
800ac14: 2b00 cmp r3, #0
|
|
800ac16: d103 bne.n 800ac20 <RFW_ReceiveLongPacket+0x28>
|
|
{
|
|
status = -1;
|
|
800ac18: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800ac1c: 617b str r3, [r7, #20]
|
|
800ac1e: e047 b.n 800acb0 <RFW_ReceiveLongPacket+0xb8>
|
|
}
|
|
else
|
|
{
|
|
/*Records call back*/
|
|
RFWPacket.RxLongPacketStoreChunkCb = RxLongPacketStoreChunkCb;
|
|
800ac20: 4a26 ldr r2, [pc, #152] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac22: 687b ldr r3, [r7, #4]
|
|
800ac24: 63d3 str r3, [r2, #60] @ 0x3c
|
|
SUBGRF_SetDioIrqParams( IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT,
|
|
800ac26: 2300 movs r3, #0
|
|
800ac28: 2200 movs r2, #0
|
|
800ac2a: f44f 7102 mov.w r1, #520 @ 0x208
|
|
800ac2e: f44f 7002 mov.w r0, #520 @ 0x208
|
|
800ac32: f7fe ffc7 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT,
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_RX );
|
|
800ac36: 4b21 ldr r3, [pc, #132] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac38: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800ac3c: 2100 movs r1, #0
|
|
800ac3e: 4618 mov r0, r3
|
|
800ac40: f7ff fc78 bl 800a534 <SUBGRF_SetSwitch>
|
|
/*init radio buffer offset*/
|
|
RFWPacket.RadioBufferOffset = 0;
|
|
800ac44: 4b1d ldr r3, [pc, #116] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac46: 2200 movs r2, #0
|
|
800ac48: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
/* Init whitening at beginning of the packet*/
|
|
RFW_WhiteSetState( &RFWPacket );
|
|
800ac4c: 481b ldr r0, [pc, #108] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac4e: f000 fb4d bl 800b2ec <RFW_WhiteSetState>
|
|
/* Set the state of the Crc to crc_seed*/
|
|
RFW_CrcSetState( &RFWPacket );
|
|
800ac52: 481a ldr r0, [pc, #104] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac54: f000 fb72 bl 800b33c <RFW_CrcSetState>
|
|
/* Init radio buffer */
|
|
SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 255 );
|
|
800ac58: 21ff movs r1, #255 @ 0xff
|
|
800ac5a: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800ac5e: f7ff fb5b bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( SUBGHZ_RXADRPTR, 0 );
|
|
800ac62: 2100 movs r1, #0
|
|
800ac64: f640 0003 movw r0, #2051 @ 0x803
|
|
800ac68: f7ff fb56 bl 800a318 <SUBGRF_WriteRegister>
|
|
/*enable long packet*/
|
|
RFWPacket.LongPacketModeEnable = 1;
|
|
800ac6c: 4b13 ldr r3, [pc, #76] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac6e: 2201 movs r2, #1
|
|
800ac70: 769a strb r2, [r3, #26]
|
|
|
|
if( timeout != 0 )
|
|
800ac72: 68bb ldr r3, [r7, #8]
|
|
800ac74: 2b00 cmp r3, #0
|
|
800ac76: d00a beq.n 800ac8e <RFW_ReceiveLongPacket+0x96>
|
|
{
|
|
TimerSetValue( RFWPacket.RxTimeoutTimer, timeout );
|
|
800ac78: 4b10 ldr r3, [pc, #64] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac7a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800ac7c: 68b9 ldr r1, [r7, #8]
|
|
800ac7e: 4618 mov r0, r3
|
|
800ac80: f001 fff8 bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( RFWPacket.RxTimeoutTimer );
|
|
800ac84: 4b0d ldr r3, [pc, #52] @ (800acbc <RFW_ReceiveLongPacket+0xc4>)
|
|
800ac86: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800ac88: 4618 mov r0, r3
|
|
800ac8a: f001 ff15 bl 800cab8 <UTIL_TIMER_Start>
|
|
}
|
|
DBG_GPIO_RADIO_RX( SET );
|
|
800ac8e: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
800ac92: 480b ldr r0, [pc, #44] @ (800acc0 <RFW_ReceiveLongPacket+0xc8>)
|
|
800ac94: f7ff fe1c bl 800a8d0 <LL_GPIO_SetOutputPin>
|
|
if( boosted_mode == 1 )
|
|
800ac98: 7bfb ldrb r3, [r7, #15]
|
|
800ac9a: 2b01 cmp r3, #1
|
|
800ac9c: d104 bne.n 800aca8 <RFW_ReceiveLongPacket+0xb0>
|
|
{
|
|
SUBGRF_SetRxBoosted( 0xFFFFFF ); /* Rx Continuous */
|
|
800ac9e: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
|
|
800aca2: f7fe fe11 bl 80098c8 <SUBGRF_SetRxBoosted>
|
|
800aca6: e003 b.n 800acb0 <RFW_ReceiveLongPacket+0xb8>
|
|
}
|
|
else
|
|
{
|
|
SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */
|
|
800aca8: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
|
|
800acac: f7fe fdec bl 8009888 <SUBGRF_SetRx>
|
|
}
|
|
}
|
|
#else
|
|
status = -1;
|
|
#endif /* RFW_LONGPACKET_ENABLE == 1 */
|
|
return status;
|
|
800acb0: 697b ldr r3, [r7, #20]
|
|
}
|
|
800acb2: 4618 mov r0, r3
|
|
800acb4: 3718 adds r7, #24
|
|
800acb6: 46bd mov sp, r7
|
|
800acb8: bd80 pop {r7, pc}
|
|
800acba: bf00 nop
|
|
800acbc: 2000032c .word 0x2000032c
|
|
800acc0: 48000400 .word 0x48000400
|
|
|
|
0800acc4 <RFW_Init>:
|
|
|
|
int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent )
|
|
{
|
|
800acc4: b580 push {r7, lr}
|
|
800acc6: b08a sub sp, #40 @ 0x28
|
|
800acc8: af02 add r7, sp, #8
|
|
800acca: 60f8 str r0, [r7, #12]
|
|
800accc: 60b9 str r1, [r7, #8]
|
|
800acce: 607a str r2, [r7, #4]
|
|
#if (RFW_ENABLE == 1 )
|
|
RADIO_FSK_PacketLengthModes_t HeaderType;
|
|
uint32_t RxMaxPayloadLength = 0;
|
|
800acd0: 2300 movs r3, #0
|
|
800acd2: 61bb str r3, [r7, #24]
|
|
RADIO_FSK_CrcTypes_t CrcLength;
|
|
uint16_t whiteSeed;
|
|
uint16_t CrcPolynomial;
|
|
uint16_t CrcSeed;
|
|
if( config->rtx == CONFIG_TX )
|
|
800acd4: 68fb ldr r3, [r7, #12]
|
|
800acd6: 7a1b ldrb r3, [r3, #8]
|
|
800acd8: 2b01 cmp r3, #1
|
|
800acda: d11c bne.n 800ad16 <RFW_Init+0x52>
|
|
{
|
|
HeaderType = config->TxConfig->fsk.HeaderType;
|
|
800acdc: 68fb ldr r3, [r7, #12]
|
|
800acde: 681b ldr r3, [r3, #0]
|
|
800ace0: 7d1b ldrb r3, [r3, #20]
|
|
800ace2: 77fb strb r3, [r7, #31]
|
|
CrcLength = config->TxConfig->fsk.CrcLength;
|
|
800ace4: 68fb ldr r3, [r7, #12]
|
|
800ace6: 681b ldr r3, [r3, #0]
|
|
800ace8: 7d5b ldrb r3, [r3, #21]
|
|
800acea: 75fb strb r3, [r7, #23]
|
|
whiteSeed = config->TxConfig->fsk.whiteSeed;
|
|
800acec: 68fb ldr r3, [r7, #12]
|
|
800acee: 681b ldr r3, [r3, #0]
|
|
800acf0: 8a1b ldrh r3, [r3, #16]
|
|
800acf2: 82bb strh r3, [r7, #20]
|
|
CrcPolynomial = config->TxConfig->fsk.CrcPolynomial;
|
|
800acf4: 68fb ldr r3, [r7, #12]
|
|
800acf6: 681b ldr r3, [r3, #0]
|
|
800acf8: 899b ldrh r3, [r3, #12]
|
|
800acfa: 827b strh r3, [r7, #18]
|
|
CrcSeed = config->TxConfig->fsk.CrcSeed;
|
|
800acfc: 68fb ldr r3, [r7, #12]
|
|
800acfe: 681b ldr r3, [r3, #0]
|
|
800ad00: 89db ldrh r3, [r3, #14]
|
|
800ad02: 823b strh r3, [r7, #16]
|
|
RFWPacket.BitRate = config->TxConfig->fsk.BitRate;
|
|
800ad04: 68fb ldr r3, [r7, #12]
|
|
800ad06: 681b ldr r3, [r3, #0]
|
|
800ad08: 681b ldr r3, [r3, #0]
|
|
800ad0a: 4a38 ldr r2, [pc, #224] @ (800adec <RFW_Init+0x128>)
|
|
800ad0c: 6493 str r3, [r2, #72] @ 0x48
|
|
RFWPacket.TxTimeoutTimer = TimeoutTimerEvent;
|
|
800ad0e: 4a37 ldr r2, [pc, #220] @ (800adec <RFW_Init+0x128>)
|
|
800ad10: 687b ldr r3, [r7, #4]
|
|
800ad12: 6513 str r3, [r2, #80] @ 0x50
|
|
800ad14: e021 b.n 800ad5a <RFW_Init+0x96>
|
|
}
|
|
else
|
|
{
|
|
HeaderType = config->RxConfig->fsk.LengthMode;
|
|
800ad16: 68fb ldr r3, [r7, #12]
|
|
800ad18: 685b ldr r3, [r3, #4]
|
|
800ad1a: f893 3022 ldrb.w r3, [r3, #34] @ 0x22
|
|
800ad1e: 77fb strb r3, [r7, #31]
|
|
CrcLength = config->RxConfig->fsk.CrcLength;
|
|
800ad20: 68fb ldr r3, [r7, #12]
|
|
800ad22: 685b ldr r3, [r3, #4]
|
|
800ad24: f893 3023 ldrb.w r3, [r3, #35] @ 0x23
|
|
800ad28: 75fb strb r3, [r7, #23]
|
|
RxMaxPayloadLength = config->RxConfig->fsk.MaxPayloadLength;
|
|
800ad2a: 68fb ldr r3, [r7, #12]
|
|
800ad2c: 685b ldr r3, [r3, #4]
|
|
800ad2e: 695b ldr r3, [r3, #20]
|
|
800ad30: 61bb str r3, [r7, #24]
|
|
whiteSeed = config->RxConfig->fsk.whiteSeed;
|
|
800ad32: 68fb ldr r3, [r7, #12]
|
|
800ad34: 685b ldr r3, [r3, #4]
|
|
800ad36: 8b9b ldrh r3, [r3, #28]
|
|
800ad38: 82bb strh r3, [r7, #20]
|
|
CrcPolynomial = config->RxConfig->fsk.CrcPolynomial;
|
|
800ad3a: 68fb ldr r3, [r7, #12]
|
|
800ad3c: 685b ldr r3, [r3, #4]
|
|
800ad3e: 8b1b ldrh r3, [r3, #24]
|
|
800ad40: 827b strh r3, [r7, #18]
|
|
CrcSeed = config->RxConfig->fsk.CrcSeed;
|
|
800ad42: 68fb ldr r3, [r7, #12]
|
|
800ad44: 685b ldr r3, [r3, #4]
|
|
800ad46: 8b5b ldrh r3, [r3, #26]
|
|
800ad48: 823b strh r3, [r7, #16]
|
|
RFWPacket.BitRate = config->RxConfig->fsk.BitRate;
|
|
800ad4a: 68fb ldr r3, [r7, #12]
|
|
800ad4c: 685b ldr r3, [r3, #4]
|
|
800ad4e: 689b ldr r3, [r3, #8]
|
|
800ad50: 4a26 ldr r2, [pc, #152] @ (800adec <RFW_Init+0x128>)
|
|
800ad52: 6493 str r3, [r2, #72] @ 0x48
|
|
RFWPacket.RxTimeoutTimer = TimeoutTimerEvent;
|
|
800ad54: 4a25 ldr r2, [pc, #148] @ (800adec <RFW_Init+0x128>)
|
|
800ad56: 687b ldr r3, [r7, #4]
|
|
800ad58: 64d3 str r3, [r2, #76] @ 0x4c
|
|
}
|
|
if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) )
|
|
800ad5a: 68bb ldr r3, [r7, #8]
|
|
800ad5c: 2b00 cmp r3, #0
|
|
800ad5e: d00a beq.n 800ad76 <RFW_Init+0xb2>
|
|
800ad60: 68bb ldr r3, [r7, #8]
|
|
800ad62: 691b ldr r3, [r3, #16]
|
|
800ad64: 2b00 cmp r3, #0
|
|
800ad66: d006 beq.n 800ad76 <RFW_Init+0xb2>
|
|
{
|
|
RFWPacket.Init.RadioEvents = RadioEvents;
|
|
800ad68: 4a20 ldr r2, [pc, #128] @ (800adec <RFW_Init+0x128>)
|
|
800ad6a: 68bb ldr r3, [r7, #8]
|
|
800ad6c: 6113 str r3, [r2, #16]
|
|
}
|
|
else
|
|
{
|
|
return -1;
|
|
}
|
|
if( HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH )
|
|
800ad6e: 7ffb ldrb r3, [r7, #31]
|
|
800ad70: 2b02 cmp r3, #2
|
|
800ad72: d003 beq.n 800ad7c <RFW_Init+0xb8>
|
|
800ad74: e006 b.n 800ad84 <RFW_Init+0xc0>
|
|
return -1;
|
|
800ad76: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800ad7a: e032 b.n 800ade2 <RFW_Init+0x11e>
|
|
{
|
|
#if (RFW_LONGPACKET_ENABLE == 1 )
|
|
RFWPacket.Init.PayloadLengthFieldSize = 2;
|
|
800ad7c: 4b1b ldr r3, [pc, #108] @ (800adec <RFW_Init+0x128>)
|
|
800ad7e: 2202 movs r2, #2
|
|
800ad80: 705a strb r2, [r3, #1]
|
|
800ad82: e002 b.n 800ad8a <RFW_Init+0xc6>
|
|
return -1;
|
|
#endif /* RFW_LONGPACKET_ENABLE == 1 */
|
|
}
|
|
else
|
|
{
|
|
RFWPacket.Init.PayloadLengthFieldSize = 1;
|
|
800ad84: 4b19 ldr r3, [pc, #100] @ (800adec <RFW_Init+0x128>)
|
|
800ad86: 2201 movs r2, #1
|
|
800ad88: 705a strb r2, [r3, #1]
|
|
}
|
|
/*record, used to reject packet in length decoded at sync time out greater than LongPacketMaxRxLength*/
|
|
RFWPacket.Init.LongPacketMaxRxLength = RxMaxPayloadLength;
|
|
800ad8a: 69bb ldr r3, [r7, #24]
|
|
800ad8c: b29a uxth r2, r3
|
|
800ad8e: 4b17 ldr r3, [pc, #92] @ (800adec <RFW_Init+0x128>)
|
|
800ad90: 819a strh r2, [r3, #12]
|
|
if( CrcLength == RADIO_FSK_CRC_OFF )
|
|
800ad92: 7dfb ldrb r3, [r7, #23]
|
|
800ad94: 2b01 cmp r3, #1
|
|
800ad96: d106 bne.n 800ada6 <RFW_Init+0xe2>
|
|
{
|
|
RFWPacket.Init.CrcEnable = 0;
|
|
800ad98: 4b14 ldr r3, [pc, #80] @ (800adec <RFW_Init+0x128>)
|
|
800ad9a: 2200 movs r2, #0
|
|
800ad9c: 709a strb r2, [r3, #2]
|
|
RFWPacket.Init.CrcFieldSize = 0;
|
|
800ad9e: 4b13 ldr r3, [pc, #76] @ (800adec <RFW_Init+0x128>)
|
|
800ada0: 2200 movs r2, #0
|
|
800ada2: 70da strb r2, [r3, #3]
|
|
800ada4: e005 b.n 800adb2 <RFW_Init+0xee>
|
|
}
|
|
else
|
|
{
|
|
RFWPacket.Init.CrcEnable = 1;
|
|
800ada6: 4b11 ldr r3, [pc, #68] @ (800adec <RFW_Init+0x128>)
|
|
800ada8: 2201 movs r2, #1
|
|
800adaa: 709a strb r2, [r3, #2]
|
|
RFWPacket.Init.CrcFieldSize = 2;
|
|
800adac: 4b0f ldr r3, [pc, #60] @ (800adec <RFW_Init+0x128>)
|
|
800adae: 2202 movs r2, #2
|
|
800adb0: 70da strb r2, [r3, #3]
|
|
}
|
|
/*Macro can be used to init interrupt behaviour*/
|
|
RFW_IT_INIT();
|
|
/*Initialise whitening Seed*/
|
|
RFW_WhiteInitState( &RFWPacket.Init, whiteSeed );
|
|
800adb2: 8abb ldrh r3, [r7, #20]
|
|
800adb4: 4619 mov r1, r3
|
|
800adb6: 480d ldr r0, [pc, #52] @ (800adec <RFW_Init+0x128>)
|
|
800adb8: f000 fa8a bl 800b2d0 <RFW_WhiteInitState>
|
|
/*Initialise Crc Seed*/
|
|
RFW_CrcInitState( &RFWPacket.Init, CrcPolynomial, CrcSeed, CrcLength );
|
|
800adbc: 7dfb ldrb r3, [r7, #23]
|
|
800adbe: 8a3a ldrh r2, [r7, #16]
|
|
800adc0: 8a79 ldrh r1, [r7, #18]
|
|
800adc2: 480a ldr r0, [pc, #40] @ (800adec <RFW_Init+0x128>)
|
|
800adc4: f000 fa9f bl 800b306 <RFW_CrcInitState>
|
|
/*Enable the RFWPacket decoding*/
|
|
RFWPacket.Init.Enable = 1;
|
|
800adc8: 4b08 ldr r3, [pc, #32] @ (800adec <RFW_Init+0x128>)
|
|
800adca: 2201 movs r2, #1
|
|
800adcc: 701a strb r2, [r3, #0]
|
|
/* Initialize Timer for end of fixed packet, started at sync*/
|
|
TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent );
|
|
800adce: 2300 movs r3, #0
|
|
800add0: 9300 str r3, [sp, #0]
|
|
800add2: 4b07 ldr r3, [pc, #28] @ (800adf0 <RFW_Init+0x12c>)
|
|
800add4: 2200 movs r2, #0
|
|
800add6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
800adda: 4806 ldr r0, [pc, #24] @ (800adf4 <RFW_Init+0x130>)
|
|
800addc: f001 fe36 bl 800ca4c <UTIL_TIMER_Create>
|
|
return 0;
|
|
800ade0: 2300 movs r3, #0
|
|
#else
|
|
return -1;
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800ade2: 4618 mov r0, r3
|
|
800ade4: 3720 adds r7, #32
|
|
800ade6: 46bd mov sp, r7
|
|
800ade8: bd80 pop {r7, pc}
|
|
800adea: bf00 nop
|
|
800adec: 2000032c .word 0x2000032c
|
|
800adf0: 0800b601 .word 0x0800b601
|
|
800adf4: 20000348 .word 0x20000348
|
|
|
|
0800adf8 <RFW_DeInit>:
|
|
|
|
void RFW_DeInit( void )
|
|
{
|
|
800adf8: b480 push {r7}
|
|
800adfa: af00 add r7, sp, #0
|
|
#if (RFW_ENABLE == 1 )
|
|
RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/
|
|
800adfc: 4b03 ldr r3, [pc, #12] @ (800ae0c <RFW_DeInit+0x14>)
|
|
800adfe: 2200 movs r2, #0
|
|
800ae00: 701a strb r2, [r3, #0]
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800ae02: bf00 nop
|
|
800ae04: 46bd mov sp, r7
|
|
800ae06: bc80 pop {r7}
|
|
800ae08: 4770 bx lr
|
|
800ae0a: bf00 nop
|
|
800ae0c: 2000032c .word 0x2000032c
|
|
|
|
0800ae10 <RFW_Is_Init>:
|
|
|
|
uint8_t RFW_Is_Init( void )
|
|
{
|
|
800ae10: b480 push {r7}
|
|
800ae12: af00 add r7, sp, #0
|
|
#if (RFW_ENABLE == 1 )
|
|
return RFWPacket.Init.Enable;
|
|
800ae14: 4b02 ldr r3, [pc, #8] @ (800ae20 <RFW_Is_Init+0x10>)
|
|
800ae16: 781b ldrb r3, [r3, #0]
|
|
#else
|
|
return 0;
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800ae18: 4618 mov r0, r3
|
|
800ae1a: 46bd mov sp, r7
|
|
800ae1c: bc80 pop {r7}
|
|
800ae1e: 4770 bx lr
|
|
800ae20: 2000032c .word 0x2000032c
|
|
|
|
0800ae24 <RFW_Is_LongPacketModeEnabled>:
|
|
|
|
uint8_t RFW_Is_LongPacketModeEnabled( void )
|
|
{
|
|
800ae24: b480 push {r7}
|
|
800ae26: af00 add r7, sp, #0
|
|
#if (RFW_ENABLE == 1 )
|
|
return RFWPacket.LongPacketModeEnable;
|
|
800ae28: 4b02 ldr r3, [pc, #8] @ (800ae34 <RFW_Is_LongPacketModeEnabled+0x10>)
|
|
800ae2a: 7e9b ldrb r3, [r3, #26]
|
|
#else
|
|
return 0;
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800ae2c: 4618 mov r0, r3
|
|
800ae2e: 46bd mov sp, r7
|
|
800ae30: bc80 pop {r7}
|
|
800ae32: 4770 bx lr
|
|
800ae34: 2000032c .word 0x2000032c
|
|
|
|
0800ae38 <RFW_SetAntSwitch>:
|
|
|
|
void RFW_SetAntSwitch( uint8_t AntSwitch )
|
|
{
|
|
800ae38: b480 push {r7}
|
|
800ae3a: b083 sub sp, #12
|
|
800ae3c: af00 add r7, sp, #0
|
|
800ae3e: 4603 mov r3, r0
|
|
800ae40: 71fb strb r3, [r7, #7]
|
|
#if (RFW_ENABLE == 1 )
|
|
RFWPacket.AntSwitchPaSelect = AntSwitch;
|
|
800ae42: 4a04 ldr r2, [pc, #16] @ (800ae54 <RFW_SetAntSwitch+0x1c>)
|
|
800ae44: 79fb ldrb r3, [r7, #7]
|
|
800ae46: f882 3044 strb.w r3, [r2, #68] @ 0x44
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800ae4a: bf00 nop
|
|
800ae4c: 370c adds r7, #12
|
|
800ae4e: 46bd mov sp, r7
|
|
800ae50: bc80 pop {r7}
|
|
800ae52: 4770 bx lr
|
|
800ae54: 2000032c .word 0x2000032c
|
|
|
|
0800ae58 <RFW_TransmitInit>:
|
|
|
|
int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize )
|
|
{
|
|
800ae58: b580 push {r7, lr}
|
|
800ae5a: b086 sub sp, #24
|
|
800ae5c: af00 add r7, sp, #0
|
|
800ae5e: 60f8 str r0, [r7, #12]
|
|
800ae60: 460b mov r3, r1
|
|
800ae62: 607a str r2, [r7, #4]
|
|
800ae64: 72fb strb r3, [r7, #11]
|
|
int32_t status = -1;
|
|
800ae66: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800ae6a: 617b str r3, [r7, #20]
|
|
#if (RFW_ENABLE == 1 )
|
|
uint8_t crc_result[2];
|
|
if( size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize > RADIO_BUF_SIZE )
|
|
800ae6c: 7afb ldrb r3, [r7, #11]
|
|
800ae6e: 4a3a ldr r2, [pc, #232] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800ae70: 7852 ldrb r2, [r2, #1]
|
|
800ae72: 4413 add r3, r2
|
|
800ae74: 4a38 ldr r2, [pc, #224] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800ae76: 78d2 ldrb r2, [r2, #3]
|
|
800ae78: 4413 add r3, r2
|
|
800ae7a: 2bff cmp r3, #255 @ 0xff
|
|
800ae7c: dd09 ble.n 800ae92 <RFW_TransmitInit+0x3a>
|
|
{
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" );
|
|
800ae7e: 4b37 ldr r3, [pc, #220] @ (800af5c <RFW_TransmitInit+0x104>)
|
|
800ae80: 2201 movs r2, #1
|
|
800ae82: 2100 movs r1, #0
|
|
800ae84: 2002 movs r0, #2
|
|
800ae86: f002 f87d bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
status = -1;
|
|
800ae8a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800ae8e: 617b str r3, [r7, #20]
|
|
800ae90: e05d b.n 800af4e <RFW_TransmitInit+0xf6>
|
|
}
|
|
else
|
|
{
|
|
/* Copy tx buffer in payload*/
|
|
RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], inOutBuffer, size );
|
|
800ae92: 4b31 ldr r3, [pc, #196] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800ae94: 785b ldrb r3, [r3, #1]
|
|
800ae96: 461a mov r2, r3
|
|
800ae98: 4b31 ldr r3, [pc, #196] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800ae9a: 4413 add r3, r2
|
|
800ae9c: 7afa ldrb r2, [r7, #11]
|
|
800ae9e: b292 uxth r2, r2
|
|
800aea0: 68f9 ldr r1, [r7, #12]
|
|
800aea2: 4618 mov r0, r3
|
|
800aea4: f001 f922 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
/* Calculate the crc on */
|
|
/* Payload Size without the packet length field nor the CRC */
|
|
/* Prepend payload size before Payload*/
|
|
if( RFWPacket.Init.PayloadLengthFieldSize == 1 )
|
|
800aea8: 4b2b ldr r3, [pc, #172] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aeaa: 785b ldrb r3, [r3, #1]
|
|
800aeac: 2b01 cmp r3, #1
|
|
800aeae: d103 bne.n 800aeb8 <RFW_TransmitInit+0x60>
|
|
{
|
|
ChunkBuffer[0] = size;
|
|
800aeb0: 4a2b ldr r2, [pc, #172] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800aeb2: 7afb ldrb r3, [r7, #11]
|
|
800aeb4: 7013 strb r3, [r2, #0]
|
|
800aeb6: e005 b.n 800aec4 <RFW_TransmitInit+0x6c>
|
|
}
|
|
else
|
|
{
|
|
ChunkBuffer[0] = 0;
|
|
800aeb8: 4b29 ldr r3, [pc, #164] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800aeba: 2200 movs r2, #0
|
|
800aebc: 701a strb r2, [r3, #0]
|
|
ChunkBuffer[1] = size;
|
|
800aebe: 4a28 ldr r2, [pc, #160] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800aec0: 7afb ldrb r3, [r7, #11]
|
|
800aec2: 7053 strb r3, [r2, #1]
|
|
}
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800aec4: 4b24 ldr r3, [pc, #144] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aec6: 789b ldrb r3, [r3, #2]
|
|
800aec8: 2b01 cmp r3, #1
|
|
800aeca: d11a bne.n 800af02 <RFW_TransmitInit+0xaa>
|
|
{
|
|
/* Set the state of the Crc to crc_seed*/
|
|
RFW_CrcSetState( &RFWPacket );
|
|
800aecc: 4822 ldr r0, [pc, #136] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aece: f000 fa35 bl 800b33c <RFW_CrcSetState>
|
|
/*Run the crc calculation on payload length and payload*/
|
|
RFW_CrcRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize, crc_result );
|
|
800aed2: 7afb ldrb r3, [r7, #11]
|
|
800aed4: 4a20 ldr r2, [pc, #128] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aed6: 7852 ldrb r2, [r2, #1]
|
|
800aed8: 4413 add r3, r2
|
|
800aeda: 461a mov r2, r3
|
|
800aedc: f107 0310 add.w r3, r7, #16
|
|
800aee0: 491f ldr r1, [pc, #124] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800aee2: 481d ldr r0, [pc, #116] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aee4: f000 fa7f bl 800b3e6 <RFW_CrcRun>
|
|
/*append the crc result after the payload*/
|
|
RADIO_MEMCPY8( &ChunkBuffer[size + RFWPacket.Init.PayloadLengthFieldSize], crc_result, RFWPacket.Init.CrcFieldSize );
|
|
800aee8: 7afb ldrb r3, [r7, #11]
|
|
800aeea: 4a1b ldr r2, [pc, #108] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aeec: 7852 ldrb r2, [r2, #1]
|
|
800aeee: 4413 add r3, r2
|
|
800aef0: 4a1b ldr r2, [pc, #108] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800aef2: 4413 add r3, r2
|
|
800aef4: 4a18 ldr r2, [pc, #96] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800aef6: 78d2 ldrb r2, [r2, #3]
|
|
800aef8: f107 0110 add.w r1, r7, #16
|
|
800aefc: 4618 mov r0, r3
|
|
800aefe: f001 f8f5 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
}
|
|
/*init whitening at beginning of the packet*/
|
|
RFW_WhiteSetState( &RFWPacket );
|
|
800af02: 4815 ldr r0, [pc, #84] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af04: f000 f9f2 bl 800b2ec <RFW_WhiteSetState>
|
|
/*Run the whitening calculation on payload length, payload and crc*/
|
|
RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize );
|
|
800af08: 7afb ldrb r3, [r7, #11]
|
|
800af0a: 4a13 ldr r2, [pc, #76] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af0c: 7852 ldrb r2, [r2, #1]
|
|
800af0e: 4413 add r3, r2
|
|
800af10: 4a11 ldr r2, [pc, #68] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af12: 78d2 ldrb r2, [r2, #3]
|
|
800af14: 4413 add r3, r2
|
|
800af16: 461a mov r2, r3
|
|
800af18: 4911 ldr r1, [pc, #68] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800af1a: 480f ldr r0, [pc, #60] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af1c: f000 fa1b bl 800b356 <RFW_WhiteRun>
|
|
/*Configure the Transmitter to send all*/
|
|
*outSize = ( uint8_t ) size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize;
|
|
800af20: 4b0d ldr r3, [pc, #52] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af22: 785a ldrb r2, [r3, #1]
|
|
800af24: 7afb ldrb r3, [r7, #11]
|
|
800af26: 4413 add r3, r2
|
|
800af28: b2da uxtb r2, r3
|
|
800af2a: 4b0b ldr r3, [pc, #44] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af2c: 78db ldrb r3, [r3, #3]
|
|
800af2e: 4413 add r3, r2
|
|
800af30: b2da uxtb r2, r3
|
|
800af32: 687b ldr r3, [r7, #4]
|
|
800af34: 701a strb r2, [r3, #0]
|
|
/*copy result*/
|
|
RADIO_MEMCPY8( inOutBuffer, ChunkBuffer, *outSize );
|
|
800af36: 687b ldr r3, [r7, #4]
|
|
800af38: 781b ldrb r3, [r3, #0]
|
|
800af3a: 461a mov r2, r3
|
|
800af3c: 4908 ldr r1, [pc, #32] @ (800af60 <RFW_TransmitInit+0x108>)
|
|
800af3e: 68f8 ldr r0, [r7, #12]
|
|
800af40: f001 f8d4 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
|
|
RFWPacket.LongPacketModeEnable = 0;
|
|
800af44: 4b04 ldr r3, [pc, #16] @ (800af58 <RFW_TransmitInit+0x100>)
|
|
800af46: 2200 movs r2, #0
|
|
800af48: 769a strb r2, [r3, #26]
|
|
|
|
status = 0;
|
|
800af4a: 2300 movs r3, #0
|
|
800af4c: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* RFW_ENABLE == 1 */
|
|
return status;
|
|
800af4e: 697b ldr r3, [r7, #20]
|
|
}
|
|
800af50: 4618 mov r0, r3
|
|
800af52: 3718 adds r7, #24
|
|
800af54: 46bd mov sp, r7
|
|
800af56: bd80 pop {r7, pc}
|
|
800af58: 2000032c .word 0x2000032c
|
|
800af5c: 0800d5c4 .word 0x0800d5c4
|
|
800af60: 20000380 .word 0x20000380
|
|
|
|
0800af64 <RFW_ReceiveInit>:
|
|
|
|
int32_t RFW_ReceiveInit( void )
|
|
{
|
|
800af64: b580 push {r7, lr}
|
|
800af66: af00 add r7, sp, #0
|
|
#if (RFW_ENABLE == 1 )
|
|
/* Radio IRQ is set to DIO1 by default */
|
|
SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */
|
|
800af68: 2300 movs r3, #0
|
|
800af6a: 2200 movs r2, #0
|
|
800af6c: f64f 71fd movw r1, #65533 @ 0xfffd
|
|
800af70: f64f 70fd movw r0, #65533 @ 0xfffd
|
|
800af74: f7fe fe26 bl 8009bc4 <SUBGRF_SetDioIrqParams>
|
|
IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */
|
|
IRQ_RADIO_NONE,
|
|
IRQ_RADIO_NONE );
|
|
|
|
/*init whitening at beginning of the packet*/
|
|
RFW_WhiteSetState( &RFWPacket );
|
|
800af78: 4807 ldr r0, [pc, #28] @ (800af98 <RFW_ReceiveInit+0x34>)
|
|
800af7a: f000 f9b7 bl 800b2ec <RFW_WhiteSetState>
|
|
/* Set the state of the Crc to crc_seed*/
|
|
RFW_CrcSetState( &RFWPacket );
|
|
800af7e: 4806 ldr r0, [pc, #24] @ (800af98 <RFW_ReceiveInit+0x34>)
|
|
800af80: f000 f9dc bl 800b33c <RFW_CrcSetState>
|
|
|
|
RFWPacket.RxPayloadOffset = 0;
|
|
800af84: 4b04 ldr r3, [pc, #16] @ (800af98 <RFW_ReceiveInit+0x34>)
|
|
800af86: 2200 movs r2, #0
|
|
800af88: 871a strh r2, [r3, #56] @ 0x38
|
|
|
|
RFWPacket.LongPacketModeEnable = 0;
|
|
800af8a: 4b03 ldr r3, [pc, #12] @ (800af98 <RFW_ReceiveInit+0x34>)
|
|
800af8c: 2200 movs r2, #0
|
|
800af8e: 769a strb r2, [r3, #26]
|
|
return 0;
|
|
800af90: 2300 movs r3, #0
|
|
#else
|
|
return -1;
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800af92: 4618 mov r0, r3
|
|
800af94: bd80 pop {r7, pc}
|
|
800af96: bf00 nop
|
|
800af98: 2000032c .word 0x2000032c
|
|
|
|
0800af9c <RFW_DeInit_TxLongPacket>:
|
|
|
|
void RFW_DeInit_TxLongPacket( void )
|
|
{
|
|
800af9c: b580 push {r7, lr}
|
|
800af9e: b082 sub sp, #8
|
|
800afa0: af00 add r7, sp, #0
|
|
#if (RFW_LONGPACKET_ENABLE == 1 )
|
|
/*long packet WA*/
|
|
uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR );
|
|
800afa2: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
800afa6: f7ff f9d9 bl 800a35c <SUBGRF_ReadRegister>
|
|
800afaa: 4603 mov r3, r0
|
|
800afac: 71fb strb r3, [r7, #7]
|
|
SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */
|
|
800afae: 79fb ldrb r3, [r7, #7]
|
|
800afb0: f023 0302 bic.w r3, r3, #2
|
|
800afb4: b2db uxtb r3, r3
|
|
800afb6: 4619 mov r1, r3
|
|
800afb8: f44f 60d7 mov.w r0, #1720 @ 0x6b8
|
|
800afbc: f7ff f9ac bl 800a318 <SUBGRF_WriteRegister>
|
|
SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */
|
|
800afc0: 21ff movs r1, #255 @ 0xff
|
|
800afc2: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800afc6: f7ff f9a7 bl 800a318 <SUBGRF_WriteRegister>
|
|
#endif /* RFW_LONGPACKET_ENABLE == 1 */
|
|
}
|
|
800afca: bf00 nop
|
|
800afcc: 3708 adds r7, #8
|
|
800afce: 46bd mov sp, r7
|
|
800afd0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800afd4 <RFW_ReceivePayload>:
|
|
|
|
void RFW_ReceivePayload( void )
|
|
{
|
|
800afd4: b580 push {r7, lr}
|
|
800afd6: b086 sub sp, #24
|
|
800afd8: af02 add r7, sp, #8
|
|
#if (RFW_ENABLE == 1 )
|
|
uint16_t PayloadLength = 0;
|
|
800afda: 2300 movs r3, #0
|
|
800afdc: 80fb strh r3, [r7, #6]
|
|
if( RFW_GetPacketLength( &PayloadLength ) == 0 )
|
|
800afde: 1dbb adds r3, r7, #6
|
|
800afe0: 4618 mov r0, r3
|
|
800afe2: f000 fab7 bl 800b554 <RFW_GetPacketLength>
|
|
800afe6: 4603 mov r3, r0
|
|
800afe8: 2b00 cmp r3, #0
|
|
800afea: d15e bne.n 800b0aa <RFW_ReceivePayload+0xd6>
|
|
{
|
|
uint32_t timeout;
|
|
uint32_t packet_length = PayloadLength + RFWPacket.Init.CrcFieldSize;
|
|
800afec: 88fb ldrh r3, [r7, #6]
|
|
800afee: 461a mov r2, r3
|
|
800aff0: 4b33 ldr r3, [pc, #204] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800aff2: 78db ldrb r3, [r3, #3]
|
|
800aff4: 4413 add r3, r2
|
|
800aff6: 60bb str r3, [r7, #8]
|
|
/*record payload length*/
|
|
RFWPacket.PayloadLength = PayloadLength;
|
|
800aff8: 88fa ldrh r2, [r7, #6]
|
|
800affa: 4b31 ldr r3, [pc, #196] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800affc: 831a strh r2, [r3, #24]
|
|
/*record remaining payload length*/
|
|
RFWPacket.LongPacketRemainingBytes = ( uint16_t ) packet_length;
|
|
800affe: 68bb ldr r3, [r7, #8]
|
|
800b000: b29a uxth r2, r3
|
|
800b002: 4b2f ldr r3, [pc, #188] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b004: 869a strh r2, [r3, #52] @ 0x34
|
|
/*record rx buffer offset*/
|
|
RFWPacket.RadioBufferOffset = RFWPacket.Init.PayloadLengthFieldSize;
|
|
800b006: 4b2e ldr r3, [pc, #184] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b008: 785a ldrb r2, [r3, #1]
|
|
800b00a: 4b2d ldr r3, [pc, #180] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b00c: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
/*if decoded PayloadLength is longer than LongPacketMaxRxLength, reject packet*/
|
|
if( PayloadLength > RFWPacket.Init.LongPacketMaxRxLength )
|
|
800b010: 4b2b ldr r3, [pc, #172] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b012: 899a ldrh r2, [r3, #12]
|
|
800b014: 88fb ldrh r3, [r7, #6]
|
|
800b016: 429a cmp r2, r3
|
|
800b018: d207 bcs.n 800b02a <RFW_ReceivePayload+0x56>
|
|
{
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800b01a: 2000 movs r0, #0
|
|
800b01c: f7fe fbf8 bl 8009810 <SUBGRF_SetStandby>
|
|
RFWPacket.Init.RadioEvents->RxError( );
|
|
800b020: 4b27 ldr r3, [pc, #156] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b022: 691b ldr r3, [r3, #16]
|
|
800b024: 691b ldr r3, [r3, #16]
|
|
800b026: 4798 blx r3
|
|
800b028: e046 b.n 800b0b8 <RFW_ReceivePayload+0xe4>
|
|
return;
|
|
}
|
|
if( packet_length < LONGPACKET_CHUNK_LENGTH_BYTES )
|
|
800b02a: 68bb ldr r3, [r7, #8]
|
|
800b02c: 2b7f cmp r3, #127 @ 0x7f
|
|
800b02e: d817 bhi.n 800b060 <RFW_ReceivePayload+0x8c>
|
|
{
|
|
/* all in one chunks*/
|
|
/* calculate time to end of packet*/
|
|
timeout = DIVC( ( packet_length ) * 8 * 1000, RFWPacket.BitRate ) + 2;
|
|
800b030: 68bb ldr r3, [r7, #8]
|
|
800b032: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
800b036: fb03 f202 mul.w r2, r3, r2
|
|
800b03a: 4b21 ldr r3, [pc, #132] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b03c: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b03e: 4413 add r3, r2
|
|
800b040: 1e5a subs r2, r3, #1
|
|
800b042: 4b1f ldr r3, [pc, #124] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b044: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b046: fbb2 f3f3 udiv r3, r2, r3
|
|
800b04a: 3302 adds r3, #2
|
|
800b04c: 60fb str r3, [r7, #12]
|
|
/**/
|
|
/* start timer at the end of the packet*/
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "end packet in %dms\r\n", timeout );
|
|
800b04e: 68fb ldr r3, [r7, #12]
|
|
800b050: 9300 str r3, [sp, #0]
|
|
800b052: 4b1c ldr r3, [pc, #112] @ (800b0c4 <RFW_ReceivePayload+0xf0>)
|
|
800b054: 2201 movs r2, #1
|
|
800b056: 2100 movs r1, #0
|
|
800b058: 2002 movs r0, #2
|
|
800b05a: f001 ff93 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
800b05e: e01c b.n 800b09a <RFW_ReceivePayload+0xc6>
|
|
|
|
}
|
|
else if( packet_length < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES / 2 ) )
|
|
800b060: 68bb ldr r3, [r7, #8]
|
|
800b062: 2bbf cmp r3, #191 @ 0xbf
|
|
800b064: d80f bhi.n 800b086 <RFW_ReceivePayload+0xb2>
|
|
{
|
|
/* packet contained in 2 chunks*/
|
|
/* make sure that crc not cut in chunk*/
|
|
timeout = DIVR( ( packet_length * 8 * 1000 ) / 2, RFWPacket.BitRate );
|
|
800b066: 68bb ldr r3, [r7, #8]
|
|
800b068: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
800b06c: fb02 f303 mul.w r3, r2, r3
|
|
800b070: 085a lsrs r2, r3, #1
|
|
800b072: 4b13 ldr r3, [pc, #76] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b074: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b076: 085b lsrs r3, r3, #1
|
|
800b078: 441a add r2, r3
|
|
800b07a: 4b11 ldr r3, [pc, #68] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b07c: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b07e: fbb2 f3f3 udiv r3, r2, r3
|
|
800b082: 60fb str r3, [r7, #12]
|
|
800b084: e009 b.n 800b09a <RFW_ReceivePayload+0xc6>
|
|
}
|
|
else
|
|
{
|
|
/* packet contained in multiple chunk*/
|
|
/* program radio timer for first chunk*/
|
|
timeout = DIVR( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000, RFWPacket.BitRate );
|
|
800b086: 4b0e ldr r3, [pc, #56] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b088: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b08a: 085b lsrs r3, r3, #1
|
|
800b08c: f503 227a add.w r2, r3, #1024000 @ 0xfa000
|
|
800b090: 4b0b ldr r3, [pc, #44] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b092: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b094: fbb2 f3f3 udiv r3, r2, r3
|
|
800b098: 60fb str r3, [r7, #12]
|
|
}
|
|
TimerSetValue( &RFWPacket.Timer, timeout );
|
|
800b09a: 68f9 ldr r1, [r7, #12]
|
|
800b09c: 480a ldr r0, [pc, #40] @ (800b0c8 <RFW_ReceivePayload+0xf4>)
|
|
800b09e: f001 fde9 bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RFWPacket.Timer );
|
|
800b0a2: 4809 ldr r0, [pc, #36] @ (800b0c8 <RFW_ReceivePayload+0xf4>)
|
|
800b0a4: f001 fd08 bl 800cab8 <UTIL_TIMER_Start>
|
|
800b0a8: e006 b.n 800b0b8 <RFW_ReceivePayload+0xe4>
|
|
}
|
|
else
|
|
{
|
|
/*timeout*/
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800b0aa: 2000 movs r0, #0
|
|
800b0ac: f7fe fbb0 bl 8009810 <SUBGRF_SetStandby>
|
|
RFWPacket.Init.RadioEvents->RxTimeout( );
|
|
800b0b0: 4b03 ldr r3, [pc, #12] @ (800b0c0 <RFW_ReceivePayload+0xec>)
|
|
800b0b2: 691b ldr r3, [r3, #16]
|
|
800b0b4: 68db ldr r3, [r3, #12]
|
|
800b0b6: 4798 blx r3
|
|
}
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800b0b8: 3710 adds r7, #16
|
|
800b0ba: 46bd mov sp, r7
|
|
800b0bc: bd80 pop {r7, pc}
|
|
800b0be: bf00 nop
|
|
800b0c0: 2000032c .word 0x2000032c
|
|
800b0c4: 0800d5dc .word 0x0800d5dc
|
|
800b0c8: 20000348 .word 0x20000348
|
|
|
|
0800b0cc <RFW_SetRadioModem>:
|
|
|
|
void RFW_SetRadioModem( RadioModems_t Modem )
|
|
{
|
|
800b0cc: b480 push {r7}
|
|
800b0ce: b083 sub sp, #12
|
|
800b0d0: af00 add r7, sp, #0
|
|
800b0d2: 4603 mov r3, r0
|
|
800b0d4: 71fb strb r3, [r7, #7]
|
|
#if (RFW_ENABLE == 1 )
|
|
RFWPacket.Init.Modem = Modem;
|
|
800b0d6: 4a04 ldr r2, [pc, #16] @ (800b0e8 <RFW_SetRadioModem+0x1c>)
|
|
800b0d8: 79fb ldrb r3, [r7, #7]
|
|
800b0da: 7393 strb r3, [r2, #14]
|
|
#endif /* RFW_ENABLE == 1 */
|
|
}
|
|
800b0dc: bf00 nop
|
|
800b0de: 370c adds r7, #12
|
|
800b0e0: 46bd mov sp, r7
|
|
800b0e2: bc80 pop {r7}
|
|
800b0e4: 4770 bx lr
|
|
800b0e6: bf00 nop
|
|
800b0e8: 2000032c .word 0x2000032c
|
|
|
|
0800b0ec <RFW_TransmitLongPacket_NewTxChunkTimerEvent>:
|
|
|
|
/* Private Functions Definition -----------------------------------------------*/
|
|
#if (RFW_LONGPACKET_ENABLE == 1 )
|
|
static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param )
|
|
{
|
|
800b0ec: b580 push {r7, lr}
|
|
800b0ee: b082 sub sp, #8
|
|
800b0f0: af00 add r7, sp, #0
|
|
800b0f2: 6078 str r0, [r7, #4]
|
|
RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS();
|
|
800b0f4: f000 f804 bl 800b100 <RFW_TransmitLongPacket_TxChunkProcess>
|
|
}
|
|
800b0f8: bf00 nop
|
|
800b0fa: 3708 adds r7, #8
|
|
800b0fc: 46bd mov sp, r7
|
|
800b0fe: bd80 pop {r7, pc}
|
|
|
|
0800b100 <RFW_TransmitLongPacket_TxChunkProcess>:
|
|
|
|
static void RFW_TransmitLongPacket_TxChunkProcess( void )
|
|
{
|
|
800b100: b590 push {r4, r7, lr}
|
|
800b102: b08d sub sp, #52 @ 0x34
|
|
800b104: af06 add r7, sp, #24
|
|
uint8_t *app_chunk_buffer_ptr = NULL;
|
|
800b106: 2300 movs r3, #0
|
|
800b108: 60bb str r3, [r7, #8]
|
|
uint8_t chunk_size = 0;
|
|
800b10a: 2300 movs r3, #0
|
|
800b10c: 75fb strb r3, [r7, #23]
|
|
uint8_t crc_result[2] = {0};
|
|
800b10e: 2300 movs r3, #0
|
|
800b110: 80bb strh r3, [r7, #4]
|
|
uint8_t crc_size;
|
|
uint32_t timeout;/*timeout for next chunk*/
|
|
/*records how much has been sent*/
|
|
uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_TXADRPTR ); /*radio has transmitted up to read_ptr*/
|
|
800b112: f640 0002 movw r0, #2050 @ 0x802
|
|
800b116: f7ff f921 bl 800a35c <SUBGRF_ReadRegister>
|
|
800b11a: 4603 mov r3, r0
|
|
800b11c: 757b strb r3, [r7, #21]
|
|
uint8_t write_ptr = SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ); /*from read_ptr to write_ptr still to be transmitted*/
|
|
800b11e: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800b122: f7ff f91b bl 800a35c <SUBGRF_ReadRegister>
|
|
800b126: 4603 mov r3, r0
|
|
800b128: 753b strb r3, [r7, #20]
|
|
/*calculates how much bytes were sent since previous radio loading*/
|
|
uint8_t bytes_sent = read_ptr - RFWPacket.RadioBufferOffset;
|
|
800b12a: 4b64 ldr r3, [pc, #400] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b12c: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b130: 7d7a ldrb r2, [r7, #21]
|
|
800b132: 1ad3 subs r3, r2, r3
|
|
800b134: 74fb strb r3, [r7, #19]
|
|
/*bytes already loaded in the radio to send*/
|
|
uint8_t bytes_loaded = write_ptr - read_ptr;
|
|
800b136: 7d3a ldrb r2, [r7, #20]
|
|
800b138: 7d7b ldrb r3, [r7, #21]
|
|
800b13a: 1ad3 subs r3, r2, r3
|
|
800b13c: 74bb strb r3, [r7, #18]
|
|
|
|
/* Update offset tx, intentional wrap around*/
|
|
RFWPacket.RadioBufferOffset += bytes_sent;
|
|
800b13e: 4b5f ldr r3, [pc, #380] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b140: f893 2036 ldrb.w r2, [r3, #54] @ 0x36
|
|
800b144: 7cfb ldrb r3, [r7, #19]
|
|
800b146: 4413 add r3, r2
|
|
800b148: b2da uxtb r2, r3
|
|
800b14a: 4b5c ldr r3, [pc, #368] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b14c: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
/*record payload remaining bytes to send*/
|
|
RFWPacket.LongPacketRemainingBytes -= bytes_sent;
|
|
800b150: 4b5a ldr r3, [pc, #360] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b152: 8e9a ldrh r2, [r3, #52] @ 0x34
|
|
800b154: 7cfb ldrb r3, [r7, #19]
|
|
800b156: b29b uxth r3, r3
|
|
800b158: 1ad3 subs r3, r2, r3
|
|
800b15a: b29a uxth r2, r3
|
|
800b15c: 4b57 ldr r3, [pc, #348] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b15e: 869a strh r2, [r3, #52] @ 0x34
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "read_ptr=%d, write_ptr=%d, bytes_sent=%d, bytes_loaded=%d,remaining to send=%d\r\n",
|
|
800b160: 7d7b ldrb r3, [r7, #21]
|
|
800b162: 7d3a ldrb r2, [r7, #20]
|
|
800b164: 7cf9 ldrb r1, [r7, #19]
|
|
800b166: 7cb8 ldrb r0, [r7, #18]
|
|
800b168: 4c54 ldr r4, [pc, #336] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b16a: 8ea4 ldrh r4, [r4, #52] @ 0x34
|
|
800b16c: 9404 str r4, [sp, #16]
|
|
800b16e: 9003 str r0, [sp, #12]
|
|
800b170: 9102 str r1, [sp, #8]
|
|
800b172: 9201 str r2, [sp, #4]
|
|
800b174: 9300 str r3, [sp, #0]
|
|
800b176: 4b52 ldr r3, [pc, #328] @ (800b2c0 <RFW_TransmitLongPacket_TxChunkProcess+0x1c0>)
|
|
800b178: 2201 movs r2, #1
|
|
800b17a: 2100 movs r1, #0
|
|
800b17c: 2002 movs r0, #2
|
|
800b17e: f001 ff01 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
read_ptr, write_ptr, bytes_sent, bytes_loaded, RFWPacket.LongPacketRemainingBytes );
|
|
if( RFWPacket.LongPacketRemainingBytes > 256 )
|
|
800b182: 4b4e ldr r3, [pc, #312] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b184: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b186: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
800b18a: d929 bls.n 800b1e0 <RFW_TransmitLongPacket_TxChunkProcess+0xe0>
|
|
{
|
|
/*get next chunk */
|
|
/*make sure that at least full CrcFieldSize will be loaded for the last chunk*/
|
|
if( RFWPacket.LongPacketRemainingBytes > 256 + RFWPacket.Init.CrcFieldSize )
|
|
800b18c: 4b4b ldr r3, [pc, #300] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b18e: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b190: 461a mov r2, r3
|
|
800b192: 4b4a ldr r3, [pc, #296] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b194: 78db ldrb r3, [r3, #3]
|
|
800b196: f503 7380 add.w r3, r3, #256 @ 0x100
|
|
800b19a: 429a cmp r2, r3
|
|
800b19c: dd02 ble.n 800b1a4 <RFW_TransmitLongPacket_TxChunkProcess+0xa4>
|
|
{
|
|
chunk_size = bytes_sent;
|
|
800b19e: 7cfb ldrb r3, [r7, #19]
|
|
800b1a0: 75fb strb r3, [r7, #23]
|
|
800b1a2: e004 b.n 800b1ae <RFW_TransmitLongPacket_TxChunkProcess+0xae>
|
|
}
|
|
else
|
|
{
|
|
chunk_size = bytes_sent - RFWPacket.Init.CrcFieldSize;
|
|
800b1a4: 4b45 ldr r3, [pc, #276] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1a6: 78db ldrb r3, [r3, #3]
|
|
800b1a8: 7cfa ldrb r2, [r7, #19]
|
|
800b1aa: 1ad3 subs r3, r2, r3
|
|
800b1ac: 75fb strb r3, [r7, #23]
|
|
}
|
|
/*no crc since it is not the last chunk*/
|
|
crc_size = 0;
|
|
800b1ae: 2300 movs r3, #0
|
|
800b1b0: 75bb strb r3, [r7, #22]
|
|
/*calculate timeout for next chunk*/
|
|
timeout = DIVR( chunk_size * 8 * 1000, RFWPacket.BitRate );
|
|
800b1b2: 7dfb ldrb r3, [r7, #23]
|
|
800b1b4: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
800b1b8: fb02 f303 mul.w r3, r2, r3
|
|
800b1bc: 461a mov r2, r3
|
|
800b1be: 4b3f ldr r3, [pc, #252] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1c0: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b1c2: 085b lsrs r3, r3, #1
|
|
800b1c4: 441a add r2, r3
|
|
800b1c6: 4b3d ldr r3, [pc, #244] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1c8: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b1ca: fbb2 f3f3 udiv r3, r2, r3
|
|
800b1ce: 60fb str r3, [r7, #12]
|
|
|
|
TimerSetValue( &RFWPacket.Timer, timeout );
|
|
800b1d0: 68f9 ldr r1, [r7, #12]
|
|
800b1d2: 483c ldr r0, [pc, #240] @ (800b2c4 <RFW_TransmitLongPacket_TxChunkProcess+0x1c4>)
|
|
800b1d4: f001 fd4e bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RFWPacket.Timer );
|
|
800b1d8: 483a ldr r0, [pc, #232] @ (800b2c4 <RFW_TransmitLongPacket_TxChunkProcess+0x1c4>)
|
|
800b1da: f001 fc6d bl 800cab8 <UTIL_TIMER_Start>
|
|
800b1de: e015 b.n 800b20c <RFW_TransmitLongPacket_TxChunkProcess+0x10c>
|
|
}
|
|
else
|
|
{
|
|
/*last chunk to send*/
|
|
|
|
if( RFWPacket.LongPacketRemainingBytes > bytes_loaded )
|
|
800b1e0: 4b36 ldr r3, [pc, #216] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1e2: 8e9a ldrh r2, [r3, #52] @ 0x34
|
|
800b1e4: 7cbb ldrb r3, [r7, #18]
|
|
800b1e6: b29b uxth r3, r3
|
|
800b1e8: 429a cmp r2, r3
|
|
800b1ea: d906 bls.n 800b1fa <RFW_TransmitLongPacket_TxChunkProcess+0xfa>
|
|
{
|
|
chunk_size = RFWPacket.LongPacketRemainingBytes - bytes_loaded;
|
|
800b1ec: 4b33 ldr r3, [pc, #204] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1ee: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b1f0: b2da uxtb r2, r3
|
|
800b1f2: 7cbb ldrb r3, [r7, #18]
|
|
800b1f4: 1ad3 subs r3, r2, r3
|
|
800b1f6: 75fb strb r3, [r7, #23]
|
|
800b1f8: e002 b.n 800b200 <RFW_TransmitLongPacket_TxChunkProcess+0x100>
|
|
}
|
|
else/* nothing to load anymore*/
|
|
{
|
|
chunk_size = RFWPacket.Init.CrcFieldSize;
|
|
800b1fa: 4b30 ldr r3, [pc, #192] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b1fc: 78db ldrb r3, [r3, #3]
|
|
800b1fe: 75fb strb r3, [r7, #23]
|
|
}
|
|
/* crc, since it is the last chunk*/
|
|
crc_size = RFWPacket.Init.CrcFieldSize;
|
|
800b200: 4b2e ldr r3, [pc, #184] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b202: 78db ldrb r3, [r3, #3]
|
|
800b204: 75bb strb r3, [r7, #22]
|
|
/*no more bytes to send*/
|
|
RFWPacket.LongPacketRemainingBytes = 0;
|
|
800b206: 4b2d ldr r3, [pc, #180] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b208: 2200 movs r2, #0
|
|
800b20a: 869a strh r2, [r3, #52] @ 0x34
|
|
/*no need to program another timer, Tx done will complete the Tx process*/
|
|
}
|
|
/*get new chunk from the app*/
|
|
RFWPacket.TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size - crc_size );
|
|
800b20c: 4b2b ldr r3, [pc, #172] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b20e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800b210: 7df9 ldrb r1, [r7, #23]
|
|
800b212: 7dba ldrb r2, [r7, #22]
|
|
800b214: 1a8a subs r2, r1, r2
|
|
800b216: b2d1 uxtb r1, r2
|
|
800b218: f107 0208 add.w r2, r7, #8
|
|
800b21c: 4610 mov r0, r2
|
|
800b21e: 4798 blx r3
|
|
/* Copy app_chunk_buffer_ptr in ChunkBuffer Buffer*/
|
|
RADIO_MEMCPY8( ChunkBuffer, app_chunk_buffer_ptr, chunk_size - crc_size );
|
|
800b220: 68b9 ldr r1, [r7, #8]
|
|
800b222: 7dfb ldrb r3, [r7, #23]
|
|
800b224: b29a uxth r2, r3
|
|
800b226: 7dbb ldrb r3, [r7, #22]
|
|
800b228: b29b uxth r3, r3
|
|
800b22a: 1ad3 subs r3, r2, r3
|
|
800b22c: b29b uxth r3, r3
|
|
800b22e: 461a mov r2, r3
|
|
800b230: 4825 ldr r0, [pc, #148] @ (800b2c8 <RFW_TransmitLongPacket_TxChunkProcess+0x1c8>)
|
|
800b232: f000 ff5b bl 800c0ec <UTIL_MEM_cpy_8>
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800b236: 4b21 ldr r3, [pc, #132] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b238: 789b ldrb r3, [r3, #2]
|
|
800b23a: 2b01 cmp r3, #1
|
|
800b23c: d113 bne.n 800b266 <RFW_TransmitLongPacket_TxChunkProcess+0x166>
|
|
{
|
|
/* Run the crc calculation on payload length and payload*/
|
|
RFW_CrcRun( &RFWPacket, ChunkBuffer, chunk_size - crc_size, crc_result );
|
|
800b23e: 7dfa ldrb r2, [r7, #23]
|
|
800b240: 7dbb ldrb r3, [r7, #22]
|
|
800b242: 1ad3 subs r3, r2, r3
|
|
800b244: 461a mov r2, r3
|
|
800b246: 1d3b adds r3, r7, #4
|
|
800b248: 491f ldr r1, [pc, #124] @ (800b2c8 <RFW_TransmitLongPacket_TxChunkProcess+0x1c8>)
|
|
800b24a: 481c ldr r0, [pc, #112] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b24c: f000 f8cb bl 800b3e6 <RFW_CrcRun>
|
|
/* Append the crc result after the payload (if last chunk)*/
|
|
RADIO_MEMCPY8( &ChunkBuffer[chunk_size - crc_size], crc_result, crc_size );
|
|
800b250: 7dfa ldrb r2, [r7, #23]
|
|
800b252: 7dbb ldrb r3, [r7, #22]
|
|
800b254: 1ad3 subs r3, r2, r3
|
|
800b256: 4a1c ldr r2, [pc, #112] @ (800b2c8 <RFW_TransmitLongPacket_TxChunkProcess+0x1c8>)
|
|
800b258: 4413 add r3, r2
|
|
800b25a: 7dba ldrb r2, [r7, #22]
|
|
800b25c: b292 uxth r2, r2
|
|
800b25e: 1d39 adds r1, r7, #4
|
|
800b260: 4618 mov r0, r3
|
|
800b262: f000 ff43 bl 800c0ec <UTIL_MEM_cpy_8>
|
|
}
|
|
/* Run the whitening calculation on payload length, payload and crc*/
|
|
RFW_WhiteRun( &RFWPacket, ChunkBuffer, chunk_size );
|
|
800b266: 7dfb ldrb r3, [r7, #23]
|
|
800b268: 461a mov r2, r3
|
|
800b26a: 4917 ldr r1, [pc, #92] @ (800b2c8 <RFW_TransmitLongPacket_TxChunkProcess+0x1c8>)
|
|
800b26c: 4813 ldr r0, [pc, #76] @ (800b2bc <RFW_TransmitLongPacket_TxChunkProcess+0x1bc>)
|
|
800b26e: f000 f872 bl 800b356 <RFW_WhiteRun>
|
|
/*write next chunk*/
|
|
SUBGRF_WriteBuffer( write_ptr, ChunkBuffer, chunk_size );
|
|
800b272: 7dfa ldrb r2, [r7, #23]
|
|
800b274: 7d3b ldrb r3, [r7, #20]
|
|
800b276: 4914 ldr r1, [pc, #80] @ (800b2c8 <RFW_TransmitLongPacket_TxChunkProcess+0x1c8>)
|
|
800b278: 4618 mov r0, r3
|
|
800b27a: f7ff f8d3 bl 800a424 <SUBGRF_WriteBuffer>
|
|
|
|
/*update end ptr*/
|
|
SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, ( uint8_t )( chunk_size + write_ptr ) );
|
|
800b27e: 7dfa ldrb r2, [r7, #23]
|
|
800b280: 7d3b ldrb r3, [r7, #20]
|
|
800b282: 4413 add r3, r2
|
|
800b284: b2db uxtb r3, r3
|
|
800b286: 4619 mov r1, r3
|
|
800b288: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800b28c: f7ff f844 bl 800a318 <SUBGRF_WriteRegister>
|
|
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "next chunk size=%d, new write ptr=%d\n\r", chunk_size + crc_size,
|
|
800b290: 7dfa ldrb r2, [r7, #23]
|
|
800b292: 7dbb ldrb r3, [r7, #22]
|
|
800b294: 4413 add r3, r2
|
|
800b296: 7df9 ldrb r1, [r7, #23]
|
|
800b298: 7dba ldrb r2, [r7, #22]
|
|
800b29a: 440a add r2, r1
|
|
800b29c: b2d1 uxtb r1, r2
|
|
800b29e: 7d3a ldrb r2, [r7, #20]
|
|
800b2a0: 440a add r2, r1
|
|
800b2a2: b2d2 uxtb r2, r2
|
|
800b2a4: 9201 str r2, [sp, #4]
|
|
800b2a6: 9300 str r3, [sp, #0]
|
|
800b2a8: 4b08 ldr r3, [pc, #32] @ (800b2cc <RFW_TransmitLongPacket_TxChunkProcess+0x1cc>)
|
|
800b2aa: 2201 movs r2, #1
|
|
800b2ac: 2100 movs r1, #0
|
|
800b2ae: 2002 movs r0, #2
|
|
800b2b0: f001 fe68 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
( uint8_t )( chunk_size + crc_size + write_ptr ) );
|
|
}
|
|
800b2b4: bf00 nop
|
|
800b2b6: 371c adds r7, #28
|
|
800b2b8: 46bd mov sp, r7
|
|
800b2ba: bd90 pop {r4, r7, pc}
|
|
800b2bc: 2000032c .word 0x2000032c
|
|
800b2c0: 0800d5f4 .word 0x0800d5f4
|
|
800b2c4: 20000348 .word 0x20000348
|
|
800b2c8: 20000380 .word 0x20000380
|
|
800b2cc: 0800d648 .word 0x0800d648
|
|
|
|
0800b2d0 <RFW_WhiteInitState>:
|
|
#endif /* RFW_LONGPACKET_ENABLE == 1 */
|
|
|
|
#if (RFW_ENABLE == 1 )
|
|
static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed )
|
|
{
|
|
800b2d0: b480 push {r7}
|
|
800b2d2: b083 sub sp, #12
|
|
800b2d4: af00 add r7, sp, #0
|
|
800b2d6: 6078 str r0, [r7, #4]
|
|
800b2d8: 460b mov r3, r1
|
|
800b2da: 807b strh r3, [r7, #2]
|
|
Init->WhiteSeed = WhiteSeed;
|
|
800b2dc: 687b ldr r3, [r7, #4]
|
|
800b2de: 887a ldrh r2, [r7, #2]
|
|
800b2e0: 815a strh r2, [r3, #10]
|
|
}
|
|
800b2e2: bf00 nop
|
|
800b2e4: 370c adds r7, #12
|
|
800b2e6: 46bd mov sp, r7
|
|
800b2e8: bc80 pop {r7}
|
|
800b2ea: 4770 bx lr
|
|
|
|
0800b2ec <RFW_WhiteSetState>:
|
|
|
|
static void RFW_WhiteSetState( RadioFw_t *RFWPacket )
|
|
{
|
|
800b2ec: b480 push {r7}
|
|
800b2ee: b083 sub sp, #12
|
|
800b2f0: af00 add r7, sp, #0
|
|
800b2f2: 6078 str r0, [r7, #4]
|
|
RFWPacket->WhiteLfsrState = RFWPacket->Init.WhiteSeed;
|
|
800b2f4: 687b ldr r3, [r7, #4]
|
|
800b2f6: 895a ldrh r2, [r3, #10]
|
|
800b2f8: 687b ldr r3, [r7, #4]
|
|
800b2fa: 82da strh r2, [r3, #22]
|
|
}
|
|
800b2fc: bf00 nop
|
|
800b2fe: 370c adds r7, #12
|
|
800b300: 46bd mov sp, r7
|
|
800b302: bc80 pop {r7}
|
|
800b304: 4770 bx lr
|
|
|
|
0800b306 <RFW_CrcInitState>:
|
|
|
|
static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed,
|
|
const RADIO_FSK_CrcTypes_t CrcType )
|
|
{
|
|
800b306: b480 push {r7}
|
|
800b308: b085 sub sp, #20
|
|
800b30a: af00 add r7, sp, #0
|
|
800b30c: 60f8 str r0, [r7, #12]
|
|
800b30e: 4608 mov r0, r1
|
|
800b310: 4611 mov r1, r2
|
|
800b312: 461a mov r2, r3
|
|
800b314: 4603 mov r3, r0
|
|
800b316: 817b strh r3, [r7, #10]
|
|
800b318: 460b mov r3, r1
|
|
800b31a: 813b strh r3, [r7, #8]
|
|
800b31c: 4613 mov r3, r2
|
|
800b31e: 71fb strb r3, [r7, #7]
|
|
Init->CrcPolynomial = CrcPolynomial;
|
|
800b320: 68fb ldr r3, [r7, #12]
|
|
800b322: 897a ldrh r2, [r7, #10]
|
|
800b324: 809a strh r2, [r3, #4]
|
|
Init->CrcSeed = CrcSeed;
|
|
800b326: 68fb ldr r3, [r7, #12]
|
|
800b328: 893a ldrh r2, [r7, #8]
|
|
800b32a: 80da strh r2, [r3, #6]
|
|
Init->CrcType = CrcType;
|
|
800b32c: 68fb ldr r3, [r7, #12]
|
|
800b32e: 79fa ldrb r2, [r7, #7]
|
|
800b330: 721a strb r2, [r3, #8]
|
|
}
|
|
800b332: bf00 nop
|
|
800b334: 3714 adds r7, #20
|
|
800b336: 46bd mov sp, r7
|
|
800b338: bc80 pop {r7}
|
|
800b33a: 4770 bx lr
|
|
|
|
0800b33c <RFW_CrcSetState>:
|
|
|
|
static void RFW_CrcSetState( RadioFw_t *RFWPacket )
|
|
{
|
|
800b33c: b480 push {r7}
|
|
800b33e: b083 sub sp, #12
|
|
800b340: af00 add r7, sp, #0
|
|
800b342: 6078 str r0, [r7, #4]
|
|
RFWPacket->CrcLfsrState = RFWPacket->Init.CrcSeed;
|
|
800b344: 687b ldr r3, [r7, #4]
|
|
800b346: 88da ldrh r2, [r3, #6]
|
|
800b348: 687b ldr r3, [r7, #4]
|
|
800b34a: 829a strh r2, [r3, #20]
|
|
}
|
|
800b34c: bf00 nop
|
|
800b34e: 370c adds r7, #12
|
|
800b350: 46bd mov sp, r7
|
|
800b352: bc80 pop {r7}
|
|
800b354: 4770 bx lr
|
|
|
|
0800b356 <RFW_WhiteRun>:
|
|
|
|
static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size )
|
|
{
|
|
800b356: b480 push {r7}
|
|
800b358: b089 sub sp, #36 @ 0x24
|
|
800b35a: af00 add r7, sp, #0
|
|
800b35c: 60f8 str r0, [r7, #12]
|
|
800b35e: 60b9 str r1, [r7, #8]
|
|
800b360: 607a str r2, [r7, #4]
|
|
/*run the whitening algo on Size bytes*/
|
|
uint16_t ibmwhite_state = RFWPacket->WhiteLfsrState;
|
|
800b362: 68fb ldr r3, [r7, #12]
|
|
800b364: 8adb ldrh r3, [r3, #22]
|
|
800b366: 83fb strh r3, [r7, #30]
|
|
for( int32_t i = 0; i < Size; i++ )
|
|
800b368: 2300 movs r3, #0
|
|
800b36a: 61bb str r3, [r7, #24]
|
|
800b36c: e02f b.n 800b3ce <RFW_WhiteRun+0x78>
|
|
{
|
|
Payload[i] ^= ibmwhite_state & 0xFF;
|
|
800b36e: 69bb ldr r3, [r7, #24]
|
|
800b370: 68ba ldr r2, [r7, #8]
|
|
800b372: 4413 add r3, r2
|
|
800b374: 781b ldrb r3, [r3, #0]
|
|
800b376: b25a sxtb r2, r3
|
|
800b378: 8bfb ldrh r3, [r7, #30]
|
|
800b37a: b25b sxtb r3, r3
|
|
800b37c: 4053 eors r3, r2
|
|
800b37e: b259 sxtb r1, r3
|
|
800b380: 69bb ldr r3, [r7, #24]
|
|
800b382: 68ba ldr r2, [r7, #8]
|
|
800b384: 4413 add r3, r2
|
|
800b386: b2ca uxtb r2, r1
|
|
800b388: 701a strb r2, [r3, #0]
|
|
for( int32_t j = 0; j < 8; j++ )
|
|
800b38a: 2300 movs r3, #0
|
|
800b38c: 617b str r3, [r7, #20]
|
|
800b38e: e018 b.n 800b3c2 <RFW_WhiteRun+0x6c>
|
|
{
|
|
uint8_t msb = ( ( ibmwhite_state >> 5 ) & 0x1 ) ^ ( ( ibmwhite_state >> 0 ) & 0x1 );
|
|
800b390: 8bfb ldrh r3, [r7, #30]
|
|
800b392: 095b lsrs r3, r3, #5
|
|
800b394: b29b uxth r3, r3
|
|
800b396: b2da uxtb r2, r3
|
|
800b398: 8bfb ldrh r3, [r7, #30]
|
|
800b39a: b2db uxtb r3, r3
|
|
800b39c: 4053 eors r3, r2
|
|
800b39e: b2db uxtb r3, r3
|
|
800b3a0: f003 0301 and.w r3, r3, #1
|
|
800b3a4: 74fb strb r3, [r7, #19]
|
|
ibmwhite_state = ( ( msb << 8 ) | ( ibmwhite_state >> 1 ) );
|
|
800b3a6: 7cfb ldrb r3, [r7, #19]
|
|
800b3a8: b21b sxth r3, r3
|
|
800b3aa: 021b lsls r3, r3, #8
|
|
800b3ac: b21a sxth r2, r3
|
|
800b3ae: 8bfb ldrh r3, [r7, #30]
|
|
800b3b0: 085b lsrs r3, r3, #1
|
|
800b3b2: b29b uxth r3, r3
|
|
800b3b4: b21b sxth r3, r3
|
|
800b3b6: 4313 orrs r3, r2
|
|
800b3b8: b21b sxth r3, r3
|
|
800b3ba: 83fb strh r3, [r7, #30]
|
|
for( int32_t j = 0; j < 8; j++ )
|
|
800b3bc: 697b ldr r3, [r7, #20]
|
|
800b3be: 3301 adds r3, #1
|
|
800b3c0: 617b str r3, [r7, #20]
|
|
800b3c2: 697b ldr r3, [r7, #20]
|
|
800b3c4: 2b07 cmp r3, #7
|
|
800b3c6: dde3 ble.n 800b390 <RFW_WhiteRun+0x3a>
|
|
for( int32_t i = 0; i < Size; i++ )
|
|
800b3c8: 69bb ldr r3, [r7, #24]
|
|
800b3ca: 3301 adds r3, #1
|
|
800b3cc: 61bb str r3, [r7, #24]
|
|
800b3ce: 69bb ldr r3, [r7, #24]
|
|
800b3d0: 687a ldr r2, [r7, #4]
|
|
800b3d2: 429a cmp r2, r3
|
|
800b3d4: d8cb bhi.n 800b36e <RFW_WhiteRun+0x18>
|
|
}
|
|
}
|
|
RFWPacket->WhiteLfsrState = ibmwhite_state;
|
|
800b3d6: 68fb ldr r3, [r7, #12]
|
|
800b3d8: 8bfa ldrh r2, [r7, #30]
|
|
800b3da: 82da strh r2, [r3, #22]
|
|
}
|
|
800b3dc: bf00 nop
|
|
800b3de: 3724 adds r7, #36 @ 0x24
|
|
800b3e0: 46bd mov sp, r7
|
|
800b3e2: bc80 pop {r7}
|
|
800b3e4: 4770 bx lr
|
|
|
|
0800b3e6 <RFW_CrcRun>:
|
|
|
|
static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size,
|
|
uint8_t CrcResult[2] )
|
|
{
|
|
800b3e6: b580 push {r7, lr}
|
|
800b3e8: b088 sub sp, #32
|
|
800b3ea: af00 add r7, sp, #0
|
|
800b3ec: 60f8 str r0, [r7, #12]
|
|
800b3ee: 60b9 str r1, [r7, #8]
|
|
800b3f0: 607a str r2, [r7, #4]
|
|
800b3f2: 603b str r3, [r7, #0]
|
|
int32_t status = 0;
|
|
800b3f4: 2300 movs r3, #0
|
|
800b3f6: 617b str r3, [r7, #20]
|
|
int32_t i = 0;
|
|
800b3f8: 2300 movs r3, #0
|
|
800b3fa: 61fb str r3, [r7, #28]
|
|
uint16_t polynomial = RFWPacket->Init.CrcPolynomial;
|
|
800b3fc: 68fb ldr r3, [r7, #12]
|
|
800b3fe: 889b ldrh r3, [r3, #4]
|
|
800b400: 827b strh r3, [r7, #18]
|
|
/* Restore state from previous chunk*/
|
|
uint16_t crc = RFWPacket->CrcLfsrState;
|
|
800b402: 68fb ldr r3, [r7, #12]
|
|
800b404: 8a9b ldrh r3, [r3, #20]
|
|
800b406: 837b strh r3, [r7, #26]
|
|
for( i = 0; i < Size; i++ )
|
|
800b408: 2300 movs r3, #0
|
|
800b40a: 61fb str r3, [r7, #28]
|
|
800b40c: e00d b.n 800b42a <RFW_CrcRun+0x44>
|
|
{
|
|
crc = RFW_CrcRun1Byte( crc, Payload[i], polynomial );
|
|
800b40e: 69fb ldr r3, [r7, #28]
|
|
800b410: 68ba ldr r2, [r7, #8]
|
|
800b412: 4413 add r3, r2
|
|
800b414: 7819 ldrb r1, [r3, #0]
|
|
800b416: 8a7a ldrh r2, [r7, #18]
|
|
800b418: 8b7b ldrh r3, [r7, #26]
|
|
800b41a: 4618 mov r0, r3
|
|
800b41c: f000 f82f bl 800b47e <RFW_CrcRun1Byte>
|
|
800b420: 4603 mov r3, r0
|
|
800b422: 837b strh r3, [r7, #26]
|
|
for( i = 0; i < Size; i++ )
|
|
800b424: 69fb ldr r3, [r7, #28]
|
|
800b426: 3301 adds r3, #1
|
|
800b428: 61fb str r3, [r7, #28]
|
|
800b42a: 69fb ldr r3, [r7, #28]
|
|
800b42c: 687a ldr r2, [r7, #4]
|
|
800b42e: 429a cmp r2, r3
|
|
800b430: d8ed bhi.n 800b40e <RFW_CrcRun+0x28>
|
|
}
|
|
/*Save state for next chunk*/
|
|
RFWPacket->CrcLfsrState = crc;
|
|
800b432: 68fb ldr r3, [r7, #12]
|
|
800b434: 8b7a ldrh r2, [r7, #26]
|
|
800b436: 829a strh r2, [r3, #20]
|
|
|
|
if( RFWPacket->Init.CrcType == RADIO_FSK_CRC_2_BYTES_IBM )
|
|
800b438: 68fb ldr r3, [r7, #12]
|
|
800b43a: 7a1b ldrb r3, [r3, #8]
|
|
800b43c: 2bf1 cmp r3, #241 @ 0xf1
|
|
800b43e: d10b bne.n 800b458 <RFW_CrcRun+0x72>
|
|
{
|
|
CrcResult[1] = crc & 0xFF;
|
|
800b440: 683b ldr r3, [r7, #0]
|
|
800b442: 3301 adds r3, #1
|
|
800b444: 8b7a ldrh r2, [r7, #26]
|
|
800b446: b2d2 uxtb r2, r2
|
|
800b448: 701a strb r2, [r3, #0]
|
|
CrcResult[0] = crc >> 8;
|
|
800b44a: 8b7b ldrh r3, [r7, #26]
|
|
800b44c: 0a1b lsrs r3, r3, #8
|
|
800b44e: b29b uxth r3, r3
|
|
800b450: b2da uxtb r2, r3
|
|
800b452: 683b ldr r3, [r7, #0]
|
|
800b454: 701a strb r2, [r3, #0]
|
|
800b456: e00d b.n 800b474 <RFW_CrcRun+0x8e>
|
|
}
|
|
else
|
|
{
|
|
crc = ~crc ;
|
|
800b458: 8b7b ldrh r3, [r7, #26]
|
|
800b45a: 43db mvns r3, r3
|
|
800b45c: 837b strh r3, [r7, #26]
|
|
CrcResult[1] = crc & 0xFF;
|
|
800b45e: 683b ldr r3, [r7, #0]
|
|
800b460: 3301 adds r3, #1
|
|
800b462: 8b7a ldrh r2, [r7, #26]
|
|
800b464: b2d2 uxtb r2, r2
|
|
800b466: 701a strb r2, [r3, #0]
|
|
CrcResult[0] = crc >> 8;
|
|
800b468: 8b7b ldrh r3, [r7, #26]
|
|
800b46a: 0a1b lsrs r3, r3, #8
|
|
800b46c: b29b uxth r3, r3
|
|
800b46e: b2da uxtb r2, r3
|
|
800b470: 683b ldr r3, [r7, #0]
|
|
800b472: 701a strb r2, [r3, #0]
|
|
}
|
|
return status;
|
|
800b474: 697b ldr r3, [r7, #20]
|
|
}
|
|
800b476: 4618 mov r0, r3
|
|
800b478: 3720 adds r7, #32
|
|
800b47a: 46bd mov sp, r7
|
|
800b47c: bd80 pop {r7, pc}
|
|
|
|
0800b47e <RFW_CrcRun1Byte>:
|
|
|
|
uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial )
|
|
{
|
|
800b47e: b480 push {r7}
|
|
800b480: b085 sub sp, #20
|
|
800b482: af00 add r7, sp, #0
|
|
800b484: 4603 mov r3, r0
|
|
800b486: 80fb strh r3, [r7, #6]
|
|
800b488: 460b mov r3, r1
|
|
800b48a: 717b strb r3, [r7, #5]
|
|
800b48c: 4613 mov r3, r2
|
|
800b48e: 807b strh r3, [r7, #2]
|
|
uint8_t i;
|
|
for( i = 0; i < 8; i++ )
|
|
800b490: 2300 movs r3, #0
|
|
800b492: 73fb strb r3, [r7, #15]
|
|
800b494: e018 b.n 800b4c8 <RFW_CrcRun1Byte+0x4a>
|
|
{
|
|
if( ( ( ( Crc & 0x8000 ) >> 8 ) ^ ( DataByte & 0x80 ) ) != 0 )
|
|
800b496: 88fb ldrh r3, [r7, #6]
|
|
800b498: 121a asrs r2, r3, #8
|
|
800b49a: 797b ldrb r3, [r7, #5]
|
|
800b49c: 4053 eors r3, r2
|
|
800b49e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800b4a2: 2b00 cmp r3, #0
|
|
800b4a4: d007 beq.n 800b4b6 <RFW_CrcRun1Byte+0x38>
|
|
{
|
|
Crc <<= 1;
|
|
800b4a6: 88fb ldrh r3, [r7, #6]
|
|
800b4a8: 005b lsls r3, r3, #1
|
|
800b4aa: 80fb strh r3, [r7, #6]
|
|
Crc ^= Polynomial;
|
|
800b4ac: 88fa ldrh r2, [r7, #6]
|
|
800b4ae: 887b ldrh r3, [r7, #2]
|
|
800b4b0: 4053 eors r3, r2
|
|
800b4b2: 80fb strh r3, [r7, #6]
|
|
800b4b4: e002 b.n 800b4bc <RFW_CrcRun1Byte+0x3e>
|
|
}
|
|
else
|
|
{
|
|
Crc <<= 1;
|
|
800b4b6: 88fb ldrh r3, [r7, #6]
|
|
800b4b8: 005b lsls r3, r3, #1
|
|
800b4ba: 80fb strh r3, [r7, #6]
|
|
}
|
|
DataByte <<= 1;
|
|
800b4bc: 797b ldrb r3, [r7, #5]
|
|
800b4be: 005b lsls r3, r3, #1
|
|
800b4c0: 717b strb r3, [r7, #5]
|
|
for( i = 0; i < 8; i++ )
|
|
800b4c2: 7bfb ldrb r3, [r7, #15]
|
|
800b4c4: 3301 adds r3, #1
|
|
800b4c6: 73fb strb r3, [r7, #15]
|
|
800b4c8: 7bfb ldrb r3, [r7, #15]
|
|
800b4ca: 2b07 cmp r3, #7
|
|
800b4cc: d9e3 bls.n 800b496 <RFW_CrcRun1Byte+0x18>
|
|
}
|
|
return Crc;
|
|
800b4ce: 88fb ldrh r3, [r7, #6]
|
|
}
|
|
800b4d0: 4618 mov r0, r3
|
|
800b4d2: 3714 adds r7, #20
|
|
800b4d4: 46bd mov sp, r7
|
|
800b4d6: bc80 pop {r7}
|
|
800b4d8: 4770 bx lr
|
|
...
|
|
|
|
0800b4dc <RFW_PollRxBytes>:
|
|
|
|
static int32_t RFW_PollRxBytes( uint32_t bytes )
|
|
{
|
|
800b4dc: b580 push {r7, lr}
|
|
800b4de: b086 sub sp, #24
|
|
800b4e0: af00 add r7, sp, #0
|
|
800b4e2: 6078 str r0, [r7, #4]
|
|
uint32_t now = TimerGetCurrentTime( );
|
|
800b4e4: f001 fc70 bl 800cdc8 <UTIL_TIMER_GetCurrentTime>
|
|
800b4e8: 6138 str r0, [r7, #16]
|
|
uint8_t reg_buff_ptr_ref = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR );
|
|
800b4ea: f640 0003 movw r0, #2051 @ 0x803
|
|
800b4ee: f7fe ff35 bl 800a35c <SUBGRF_ReadRegister>
|
|
800b4f2: 4603 mov r3, r0
|
|
800b4f4: 73fb strb r3, [r7, #15]
|
|
uint8_t reg_buff_ptr = reg_buff_ptr_ref;
|
|
800b4f6: 7bfb ldrb r3, [r7, #15]
|
|
800b4f8: 75fb strb r3, [r7, #23]
|
|
uint32_t timeout = DIVC( bytes * 8 * 1000, RFWPacket.BitRate );
|
|
800b4fa: 687b ldr r3, [r7, #4]
|
|
800b4fc: f44f 52fa mov.w r2, #8000 @ 0x1f40
|
|
800b500: fb03 f202 mul.w r2, r3, r2
|
|
800b504: 4b12 ldr r3, [pc, #72] @ (800b550 <RFW_PollRxBytes+0x74>)
|
|
800b506: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b508: 4413 add r3, r2
|
|
800b50a: 1e5a subs r2, r3, #1
|
|
800b50c: 4b10 ldr r3, [pc, #64] @ (800b550 <RFW_PollRxBytes+0x74>)
|
|
800b50e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b510: fbb2 f3f3 udiv r3, r2, r3
|
|
800b514: 60bb str r3, [r7, #8]
|
|
/* Wait that packet length is received */
|
|
while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes )
|
|
800b516: e00f b.n 800b538 <RFW_PollRxBytes+0x5c>
|
|
{
|
|
/*reading rx address pointer*/
|
|
reg_buff_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR );
|
|
800b518: f640 0003 movw r0, #2051 @ 0x803
|
|
800b51c: f7fe ff1e bl 800a35c <SUBGRF_ReadRegister>
|
|
800b520: 4603 mov r3, r0
|
|
800b522: 75fb strb r3, [r7, #23]
|
|
if( TimerGetElapsedTime( now ) > timeout )
|
|
800b524: 6938 ldr r0, [r7, #16]
|
|
800b526: f001 fc61 bl 800cdec <UTIL_TIMER_GetElapsedTime>
|
|
800b52a: 4602 mov r2, r0
|
|
800b52c: 68bb ldr r3, [r7, #8]
|
|
800b52e: 4293 cmp r3, r2
|
|
800b530: d202 bcs.n 800b538 <RFW_PollRxBytes+0x5c>
|
|
{
|
|
/*timeout*/
|
|
return -1;
|
|
800b532: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800b536: e007 b.n 800b548 <RFW_PollRxBytes+0x6c>
|
|
while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes )
|
|
800b538: 7dfa ldrb r2, [r7, #23]
|
|
800b53a: 7bfb ldrb r3, [r7, #15]
|
|
800b53c: 1ad3 subs r3, r2, r3
|
|
800b53e: 461a mov r2, r3
|
|
800b540: 687b ldr r3, [r7, #4]
|
|
800b542: 4293 cmp r3, r2
|
|
800b544: d8e8 bhi.n 800b518 <RFW_PollRxBytes+0x3c>
|
|
}
|
|
}
|
|
return 0;
|
|
800b546: 2300 movs r3, #0
|
|
}
|
|
800b548: 4618 mov r0, r3
|
|
800b54a: 3718 adds r7, #24
|
|
800b54c: 46bd mov sp, r7
|
|
800b54e: bd80 pop {r7, pc}
|
|
800b550: 2000032c .word 0x2000032c
|
|
|
|
0800b554 <RFW_GetPacketLength>:
|
|
|
|
static int32_t RFW_GetPacketLength( uint16_t *PayloadLength )
|
|
{
|
|
800b554: b580 push {r7, lr}
|
|
800b556: b086 sub sp, #24
|
|
800b558: af02 add r7, sp, #8
|
|
800b55a: 6078 str r0, [r7, #4]
|
|
if( 0UL != RFW_PollRxBytes( RFWPacket.Init.PayloadLengthFieldSize ) )
|
|
800b55c: 4b25 ldr r3, [pc, #148] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b55e: 785b ldrb r3, [r3, #1]
|
|
800b560: 4618 mov r0, r3
|
|
800b562: f7ff ffbb bl 800b4dc <RFW_PollRxBytes>
|
|
800b566: 4603 mov r3, r0
|
|
800b568: 2b00 cmp r3, #0
|
|
800b56a: d002 beq.n 800b572 <RFW_GetPacketLength+0x1e>
|
|
{
|
|
return -1;
|
|
800b56c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800b570: e03b b.n 800b5ea <RFW_GetPacketLength+0x96>
|
|
}
|
|
/* Get buffer from Radio*/
|
|
SUBGRF_ReadBuffer( 0, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize );
|
|
800b572: 4b20 ldr r3, [pc, #128] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b574: 785b ldrb r3, [r3, #1]
|
|
800b576: 461a mov r2, r3
|
|
800b578: 491f ldr r1, [pc, #124] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b57a: 2000 movs r0, #0
|
|
800b57c: f7fe ff74 bl 800a468 <SUBGRF_ReadBuffer>
|
|
/* De-whiten packet length*/
|
|
RFW_WhiteRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize );
|
|
800b580: 4b1c ldr r3, [pc, #112] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b582: 785b ldrb r3, [r3, #1]
|
|
800b584: 461a mov r2, r3
|
|
800b586: 491c ldr r1, [pc, #112] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b588: 481a ldr r0, [pc, #104] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b58a: f7ff fee4 bl 800b356 <RFW_WhiteRun>
|
|
/*do crc 1st calculation packetLengthField and store intermediate result */
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800b58e: 4b19 ldr r3, [pc, #100] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b590: 789b ldrb r3, [r3, #2]
|
|
800b592: 2b01 cmp r3, #1
|
|
800b594: d108 bne.n 800b5a8 <RFW_GetPacketLength+0x54>
|
|
{
|
|
/*run Crc algo on payloadLengthField*/
|
|
uint8_t crc_dummy[2];
|
|
RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize, crc_dummy );
|
|
800b596: 4b17 ldr r3, [pc, #92] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b598: 785b ldrb r3, [r3, #1]
|
|
800b59a: 461a mov r2, r3
|
|
800b59c: f107 030c add.w r3, r7, #12
|
|
800b5a0: 4915 ldr r1, [pc, #84] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b5a2: 4814 ldr r0, [pc, #80] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b5a4: f7ff ff1f bl 800b3e6 <RFW_CrcRun>
|
|
}
|
|
if( RFWPacket.Init.PayloadLengthFieldSize == 1 )
|
|
800b5a8: 4b12 ldr r3, [pc, #72] @ (800b5f4 <RFW_GetPacketLength+0xa0>)
|
|
800b5aa: 785b ldrb r3, [r3, #1]
|
|
800b5ac: 2b01 cmp r3, #1
|
|
800b5ae: d105 bne.n 800b5bc <RFW_GetPacketLength+0x68>
|
|
{
|
|
*PayloadLength = ( uint16_t ) ChunkBuffer[0];
|
|
800b5b0: 4b11 ldr r3, [pc, #68] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b5b2: 781b ldrb r3, [r3, #0]
|
|
800b5b4: 461a mov r2, r3
|
|
800b5b6: 687b ldr r3, [r7, #4]
|
|
800b5b8: 801a strh r2, [r3, #0]
|
|
800b5ba: e00c b.n 800b5d6 <RFW_GetPacketLength+0x82>
|
|
}
|
|
else
|
|
{
|
|
/*packet length is 2 bytes*/
|
|
*PayloadLength = ( ( ( uint16_t ) ChunkBuffer[0] ) << 8 ) | ChunkBuffer[1];
|
|
800b5bc: 4b0e ldr r3, [pc, #56] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b5be: 781b ldrb r3, [r3, #0]
|
|
800b5c0: b21b sxth r3, r3
|
|
800b5c2: 021b lsls r3, r3, #8
|
|
800b5c4: b21a sxth r2, r3
|
|
800b5c6: 4b0c ldr r3, [pc, #48] @ (800b5f8 <RFW_GetPacketLength+0xa4>)
|
|
800b5c8: 785b ldrb r3, [r3, #1]
|
|
800b5ca: b21b sxth r3, r3
|
|
800b5cc: 4313 orrs r3, r2
|
|
800b5ce: b21b sxth r3, r3
|
|
800b5d0: b29a uxth r2, r3
|
|
800b5d2: 687b ldr r3, [r7, #4]
|
|
800b5d4: 801a strh r2, [r3, #0]
|
|
}
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "PayloadLength=%d,\r\n", *PayloadLength );
|
|
800b5d6: 687b ldr r3, [r7, #4]
|
|
800b5d8: 881b ldrh r3, [r3, #0]
|
|
800b5da: 9300 str r3, [sp, #0]
|
|
800b5dc: 4b07 ldr r3, [pc, #28] @ (800b5fc <RFW_GetPacketLength+0xa8>)
|
|
800b5de: 2201 movs r2, #1
|
|
800b5e0: 2100 movs r1, #0
|
|
800b5e2: 2002 movs r0, #2
|
|
800b5e4: f001 fcce bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
return 0;
|
|
800b5e8: 2300 movs r3, #0
|
|
}
|
|
800b5ea: 4618 mov r0, r3
|
|
800b5ec: 3710 adds r7, #16
|
|
800b5ee: 46bd mov sp, r7
|
|
800b5f0: bd80 pop {r7, pc}
|
|
800b5f2: bf00 nop
|
|
800b5f4: 2000032c .word 0x2000032c
|
|
800b5f8: 20000380 .word 0x20000380
|
|
800b5fc: 0800d670 .word 0x0800d670
|
|
|
|
0800b600 <RFW_GetPayloadTimerEvent>:
|
|
|
|
static void RFW_GetPayloadTimerEvent( void *context )
|
|
{
|
|
800b600: b580 push {r7, lr}
|
|
800b602: b082 sub sp, #8
|
|
800b604: af00 add r7, sp, #0
|
|
800b606: 6078 str r0, [r7, #4]
|
|
RFW_GET_PAYLOAD_PROCESS();
|
|
800b608: f000 f804 bl 800b614 <RFW_GetPayloadProcess>
|
|
}
|
|
800b60c: bf00 nop
|
|
800b60e: 3708 adds r7, #8
|
|
800b610: 46bd mov sp, r7
|
|
800b612: bd80 pop {r7, pc}
|
|
|
|
0800b614 <RFW_GetPayloadProcess>:
|
|
|
|
static void RFW_GetPayloadProcess( void )
|
|
{
|
|
800b614: b580 push {r7, lr}
|
|
800b616: b086 sub sp, #24
|
|
800b618: af04 add r7, sp, #16
|
|
/*long packet mode*/
|
|
uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR );
|
|
800b61a: f640 0003 movw r0, #2051 @ 0x803
|
|
800b61e: f7fe fe9d bl 800a35c <SUBGRF_ReadRegister>
|
|
800b622: 4603 mov r3, r0
|
|
800b624: 70fb strb r3, [r7, #3]
|
|
uint8_t size = read_ptr - RFWPacket.RadioBufferOffset;
|
|
800b626: 4b83 ldr r3, [pc, #524] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b628: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b62c: 78fa ldrb r2, [r7, #3]
|
|
800b62e: 1ad3 subs r3, r2, r3
|
|
800b630: 70bb strb r3, [r7, #2]
|
|
uint32_t Timeout;
|
|
/*check remaining size*/
|
|
if( RFWPacket.LongPacketRemainingBytes > size )
|
|
800b632: 4b80 ldr r3, [pc, #512] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b634: 8e9a ldrh r2, [r3, #52] @ 0x34
|
|
800b636: 78bb ldrb r3, [r7, #2]
|
|
800b638: b29b uxth r3, r3
|
|
800b63a: 429a cmp r2, r3
|
|
800b63c: f240 80cd bls.w 800b7da <RFW_GetPayloadProcess+0x1c6>
|
|
{
|
|
/* update LongPacketRemainingBytes*/
|
|
RFWPacket.LongPacketRemainingBytes -= size;
|
|
800b640: 4b7c ldr r3, [pc, #496] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b642: 8e9a ldrh r2, [r3, #52] @ 0x34
|
|
800b644: 78bb ldrb r3, [r7, #2]
|
|
800b646: b29b uxth r3, r3
|
|
800b648: 1ad3 subs r3, r2, r3
|
|
800b64a: b29a uxth r2, r3
|
|
800b64c: 4b79 ldr r3, [pc, #484] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b64e: 869a strh r2, [r3, #52] @ 0x34
|
|
/*intermediate chunk*/
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "RxTxPldLen=0x%02X,\r\n", SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ) );
|
|
800b650: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800b654: f7fe fe82 bl 800a35c <SUBGRF_ReadRegister>
|
|
800b658: 4603 mov r3, r0
|
|
800b65a: 9300 str r3, [sp, #0]
|
|
800b65c: 4b76 ldr r3, [pc, #472] @ (800b838 <RFW_GetPayloadProcess+0x224>)
|
|
800b65e: 2201 movs r2, #1
|
|
800b660: 2100 movs r1, #0
|
|
800b662: 2002 movs r0, #2
|
|
800b664: f001 fc8e bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "RxAddrPtr=0x%02X,\r\n", read_ptr );
|
|
800b668: 78fb ldrb r3, [r7, #3]
|
|
800b66a: 9300 str r3, [sp, #0]
|
|
800b66c: 4b73 ldr r3, [pc, #460] @ (800b83c <RFW_GetPayloadProcess+0x228>)
|
|
800b66e: 2201 movs r2, #1
|
|
800b670: 2100 movs r1, #0
|
|
800b672: 2002 movs r0, #2
|
|
800b674: f001 fc86 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size,
|
|
800b678: 4b6e ldr r3, [pc, #440] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b67a: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b67e: 4619 mov r1, r3
|
|
800b680: 78bb ldrb r3, [r7, #2]
|
|
800b682: 4a6c ldr r2, [pc, #432] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b684: 8e92 ldrh r2, [r2, #52] @ 0x34
|
|
800b686: 9202 str r2, [sp, #8]
|
|
800b688: 9301 str r3, [sp, #4]
|
|
800b68a: 9100 str r1, [sp, #0]
|
|
800b68c: 4b6c ldr r3, [pc, #432] @ (800b840 <RFW_GetPayloadProcess+0x22c>)
|
|
800b68e: 2201 movs r2, #1
|
|
800b690: 2100 movs r1, #0
|
|
800b692: 2002 movs r0, #2
|
|
800b694: f001 fc76 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
RFWPacket.LongPacketRemainingBytes );
|
|
/*update pld length so that not reached*/
|
|
SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, read_ptr - 1 );
|
|
800b698: 78fb ldrb r3, [r7, #3]
|
|
800b69a: 3b01 subs r3, #1
|
|
800b69c: b2db uxtb r3, r3
|
|
800b69e: 4619 mov r1, r3
|
|
800b6a0: f240 60bb movw r0, #1723 @ 0x6bb
|
|
800b6a4: f7fe fe38 bl 800a318 <SUBGRF_WriteRegister>
|
|
/* read data from radio*/
|
|
SUBGRF_ReadBuffer( RFWPacket.RadioBufferOffset, ChunkBuffer, size );
|
|
800b6a8: 4b62 ldr r3, [pc, #392] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6aa: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b6ae: 78ba ldrb r2, [r7, #2]
|
|
800b6b0: 4964 ldr r1, [pc, #400] @ (800b844 <RFW_GetPayloadProcess+0x230>)
|
|
800b6b2: 4618 mov r0, r3
|
|
800b6b4: f7fe fed8 bl 800a468 <SUBGRF_ReadBuffer>
|
|
/* update buffer Offset, with intentional wrap around*/
|
|
RFWPacket.RadioBufferOffset += size;
|
|
800b6b8: 4b5e ldr r3, [pc, #376] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6ba: f893 2036 ldrb.w r2, [r3, #54] @ 0x36
|
|
800b6be: 78bb ldrb r3, [r7, #2]
|
|
800b6c0: 4413 add r3, r2
|
|
800b6c2: b2da uxtb r2, r3
|
|
800b6c4: 4b5b ldr r3, [pc, #364] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6c6: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
/*Run the de-whitening on current chunk*/
|
|
RFW_WhiteRun( &RFWPacket, ChunkBuffer, size );
|
|
800b6ca: 78bb ldrb r3, [r7, #2]
|
|
800b6cc: 461a mov r2, r3
|
|
800b6ce: 495d ldr r1, [pc, #372] @ (800b844 <RFW_GetPayloadProcess+0x230>)
|
|
800b6d0: 4858 ldr r0, [pc, #352] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6d2: f7ff fe40 bl 800b356 <RFW_WhiteRun>
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800b6d6: 4b57 ldr r3, [pc, #348] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6d8: 789b ldrb r3, [r3, #2]
|
|
800b6da: 2b01 cmp r3, #1
|
|
800b6dc: d105 bne.n 800b6ea <RFW_GetPayloadProcess+0xd6>
|
|
{
|
|
/*run Crc algo on partial chunk*/
|
|
uint8_t crc_dummy[2];
|
|
RFW_CrcRun( &RFWPacket, ChunkBuffer, size, crc_dummy );
|
|
800b6de: 78ba ldrb r2, [r7, #2]
|
|
800b6e0: 463b mov r3, r7
|
|
800b6e2: 4958 ldr r1, [pc, #352] @ (800b844 <RFW_GetPayloadProcess+0x230>)
|
|
800b6e4: 4853 ldr r0, [pc, #332] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6e6: f7ff fe7e bl 800b3e6 <RFW_CrcRun>
|
|
}
|
|
|
|
if( RFWPacket.LongPacketModeEnable == 1 )
|
|
800b6ea: 4b52 ldr r3, [pc, #328] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6ec: 7e9b ldrb r3, [r3, #26]
|
|
800b6ee: 2b01 cmp r3, #1
|
|
800b6f0: d106 bne.n 800b700 <RFW_GetPayloadProcess+0xec>
|
|
{
|
|
/*report rx data chunk to application*/
|
|
RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, size );
|
|
800b6f2: 4b50 ldr r3, [pc, #320] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b6f4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800b6f6: 78ba ldrb r2, [r7, #2]
|
|
800b6f8: 4611 mov r1, r2
|
|
800b6fa: 4852 ldr r0, [pc, #328] @ (800b844 <RFW_GetPayloadProcess+0x230>)
|
|
800b6fc: 4798 blx r3
|
|
800b6fe: e02b b.n 800b758 <RFW_GetPayloadProcess+0x144>
|
|
}
|
|
else
|
|
{
|
|
if( RFWPacket.RxPayloadOffset += size < RADIO_BUF_SIZE )
|
|
800b700: 4b4c ldr r3, [pc, #304] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b702: 8f1b ldrh r3, [r3, #56] @ 0x38
|
|
800b704: 78ba ldrb r2, [r7, #2]
|
|
800b706: 2aff cmp r2, #255 @ 0xff
|
|
800b708: bf14 ite ne
|
|
800b70a: 2201 movne r2, #1
|
|
800b70c: 2200 moveq r2, #0
|
|
800b70e: b2d2 uxtb r2, r2
|
|
800b710: 4413 add r3, r2
|
|
800b712: b29a uxth r2, r3
|
|
800b714: 4b47 ldr r3, [pc, #284] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b716: 871a strh r2, [r3, #56] @ 0x38
|
|
800b718: 4b46 ldr r3, [pc, #280] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b71a: 8f1b ldrh r3, [r3, #56] @ 0x38
|
|
800b71c: 2b00 cmp r3, #0
|
|
800b71e: d013 beq.n 800b748 <RFW_GetPayloadProcess+0x134>
|
|
{
|
|
RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, size );
|
|
800b720: 4b44 ldr r3, [pc, #272] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b722: 8f1b ldrh r3, [r3, #56] @ 0x38
|
|
800b724: 461a mov r2, r3
|
|
800b726: 4b48 ldr r3, [pc, #288] @ (800b848 <RFW_GetPayloadProcess+0x234>)
|
|
800b728: 4413 add r3, r2
|
|
800b72a: 78ba ldrb r2, [r7, #2]
|
|
800b72c: b292 uxth r2, r2
|
|
800b72e: 4945 ldr r1, [pc, #276] @ (800b844 <RFW_GetPayloadProcess+0x230>)
|
|
800b730: 4618 mov r0, r3
|
|
800b732: f000 fcdb bl 800c0ec <UTIL_MEM_cpy_8>
|
|
RFWPacket.RxPayloadOffset += size;
|
|
800b736: 4b3f ldr r3, [pc, #252] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b738: 8f1a ldrh r2, [r3, #56] @ 0x38
|
|
800b73a: 78bb ldrb r3, [r7, #2]
|
|
800b73c: b29b uxth r3, r3
|
|
800b73e: 4413 add r3, r2
|
|
800b740: b29a uxth r2, r3
|
|
800b742: 4b3c ldr r3, [pc, #240] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b744: 871a strh r2, [r3, #56] @ 0x38
|
|
800b746: e007 b.n 800b758 <RFW_GetPayloadProcess+0x144>
|
|
}
|
|
else
|
|
{
|
|
/*stop the radio*/
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800b748: 2000 movs r0, #0
|
|
800b74a: f7fe f861 bl 8009810 <SUBGRF_SetStandby>
|
|
/*report CRC error*/
|
|
RFWPacket.Init.RadioEvents->RxError( );
|
|
800b74e: 4b39 ldr r3, [pc, #228] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b750: 691b ldr r3, [r3, #16]
|
|
800b752: 691b ldr r3, [r3, #16]
|
|
800b754: 4798 blx r3
|
|
return;
|
|
800b756: e069 b.n 800b82c <RFW_GetPayloadProcess+0x218>
|
|
}
|
|
}
|
|
/*calculate next timer timeout*/
|
|
if( RFWPacket.LongPacketRemainingBytes < LONGPACKET_CHUNK_LENGTH_BYTES )
|
|
800b758: 4b36 ldr r3, [pc, #216] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b75a: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b75c: 2b7f cmp r3, #127 @ 0x7f
|
|
800b75e: d812 bhi.n 800b786 <RFW_GetPayloadProcess+0x172>
|
|
{
|
|
/*for the next and last chunk DIVC +1 to make sure crc is received.*/
|
|
Timeout = DIVC( ( RFWPacket.LongPacketRemainingBytes ) * 8 * 1000, RFWPacket.BitRate ) + 2;
|
|
800b760: 4b34 ldr r3, [pc, #208] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b762: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b764: 461a mov r2, r3
|
|
800b766: f44f 53fa mov.w r3, #8000 @ 0x1f40
|
|
800b76a: fb02 f303 mul.w r3, r2, r3
|
|
800b76e: 461a mov r2, r3
|
|
800b770: 4b30 ldr r3, [pc, #192] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b772: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b774: 4413 add r3, r2
|
|
800b776: 1e5a subs r2, r3, #1
|
|
800b778: 4b2e ldr r3, [pc, #184] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b77a: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b77c: fbb2 f3f3 udiv r3, r2, r3
|
|
800b780: 3302 adds r3, #2
|
|
800b782: 607b str r3, [r7, #4]
|
|
800b784: e021 b.n 800b7ca <RFW_GetPayloadProcess+0x1b6>
|
|
}
|
|
else if( RFWPacket.LongPacketRemainingBytes < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES ) / 2 )
|
|
800b786: 4b2b ldr r3, [pc, #172] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b788: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b78a: 2bbf cmp r3, #191 @ 0xbf
|
|
800b78c: d813 bhi.n 800b7b6 <RFW_GetPayloadProcess+0x1a2>
|
|
{
|
|
/*this is to make sure that last chunk will always be greater than LONGPACKET_CHUNK_LENGTH_BYTES/2 */
|
|
Timeout = DIVR( ( RFWPacket.LongPacketRemainingBytes / 2 ) * 8 * 1000, RFWPacket.BitRate );
|
|
800b78e: 4b29 ldr r3, [pc, #164] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b790: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b792: 085b lsrs r3, r3, #1
|
|
800b794: b29b uxth r3, r3
|
|
800b796: 461a mov r2, r3
|
|
800b798: f44f 53fa mov.w r3, #8000 @ 0x1f40
|
|
800b79c: fb02 f303 mul.w r3, r2, r3
|
|
800b7a0: 461a mov r2, r3
|
|
800b7a2: 4b24 ldr r3, [pc, #144] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7a4: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b7a6: 085b lsrs r3, r3, #1
|
|
800b7a8: 441a add r2, r3
|
|
800b7aa: 4b22 ldr r3, [pc, #136] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7ac: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b7ae: fbb2 f3f3 udiv r3, r2, r3
|
|
800b7b2: 607b str r3, [r7, #4]
|
|
800b7b4: e009 b.n 800b7ca <RFW_GetPayloadProcess+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
/*size value is close to LONGPACKET_CHUNK_LENGTH_BYTES with +/- errors compensated in closed loop here*/
|
|
Timeout = DIVR( ( LONGPACKET_CHUNK_LENGTH_BYTES ) * 8 * 1000, RFWPacket.BitRate );
|
|
800b7b6: 4b1f ldr r3, [pc, #124] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7b8: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b7ba: 085b lsrs r3, r3, #1
|
|
800b7bc: f503 227a add.w r2, r3, #1024000 @ 0xfa000
|
|
800b7c0: 4b1c ldr r3, [pc, #112] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7c2: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b7c4: fbb2 f3f3 udiv r3, r2, r3
|
|
800b7c8: 607b str r3, [r7, #4]
|
|
}
|
|
TimerSetValue( &RFWPacket.Timer, Timeout );
|
|
800b7ca: 6879 ldr r1, [r7, #4]
|
|
800b7cc: 481f ldr r0, [pc, #124] @ (800b84c <RFW_GetPayloadProcess+0x238>)
|
|
800b7ce: f001 fa51 bl 800cc74 <UTIL_TIMER_SetPeriod>
|
|
TimerStart( &RFWPacket.Timer );
|
|
800b7d2: 481e ldr r0, [pc, #120] @ (800b84c <RFW_GetPayloadProcess+0x238>)
|
|
800b7d4: f001 f970 bl 800cab8 <UTIL_TIMER_Start>
|
|
800b7d8: e028 b.n 800b82c <RFW_GetPayloadProcess+0x218>
|
|
}
|
|
else
|
|
{
|
|
if( RFWPacket.LongPacketRemainingBytes < RFWPacket.Init.CrcFieldSize )
|
|
800b7da: 4b16 ldr r3, [pc, #88] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7dc: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b7de: 4a15 ldr r2, [pc, #84] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7e0: 78d2 ldrb r2, [r2, #3]
|
|
800b7e2: 4293 cmp r3, r2
|
|
800b7e4: d204 bcs.n 800b7f0 <RFW_GetPayloadProcess+0x1dc>
|
|
{
|
|
/* force LongPacketRemainingBytes to CrcFieldSize: this should never happen*/
|
|
RFWPacket.LongPacketRemainingBytes = RFWPacket.Init.CrcFieldSize;
|
|
800b7e6: 4b13 ldr r3, [pc, #76] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7e8: 78db ldrb r3, [r3, #3]
|
|
800b7ea: 461a mov r2, r3
|
|
800b7ec: 4b11 ldr r3, [pc, #68] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7ee: 869a strh r2, [r3, #52] @ 0x34
|
|
}
|
|
/*last chunk*/
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "LastChunk. offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size,
|
|
800b7f0: 4b10 ldr r3, [pc, #64] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7f2: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b7f6: 4619 mov r1, r3
|
|
800b7f8: 78bb ldrb r3, [r7, #2]
|
|
800b7fa: 4a0e ldr r2, [pc, #56] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b7fc: 8e92 ldrh r2, [r2, #52] @ 0x34
|
|
800b7fe: 9202 str r2, [sp, #8]
|
|
800b800: 9301 str r3, [sp, #4]
|
|
800b802: 9100 str r1, [sp, #0]
|
|
800b804: 4b12 ldr r3, [pc, #72] @ (800b850 <RFW_GetPayloadProcess+0x23c>)
|
|
800b806: 2201 movs r2, #1
|
|
800b808: 2100 movs r1, #0
|
|
800b80a: 2002 movs r0, #2
|
|
800b80c: f001 fbba bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
RFWPacket.LongPacketRemainingBytes );
|
|
size = RFWPacket.LongPacketRemainingBytes;
|
|
800b810: 4b08 ldr r3, [pc, #32] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b812: 8e9b ldrh r3, [r3, #52] @ 0x34
|
|
800b814: 70bb strb r3, [r7, #2]
|
|
/* update LongPacketRemainingBytes*/
|
|
RFWPacket.LongPacketRemainingBytes = 0;
|
|
800b816: 4b07 ldr r3, [pc, #28] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b818: 2200 movs r2, #0
|
|
800b81a: 869a strh r2, [r3, #52] @ 0x34
|
|
/*Process last chunk*/
|
|
RFW_GetPayload( RFWPacket.RadioBufferOffset, size );
|
|
800b81c: 4b05 ldr r3, [pc, #20] @ (800b834 <RFW_GetPayloadProcess+0x220>)
|
|
800b81e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800b822: 78ba ldrb r2, [r7, #2]
|
|
800b824: 4611 mov r1, r2
|
|
800b826: 4618 mov r0, r3
|
|
800b828: f000 f814 bl 800b854 <RFW_GetPayload>
|
|
}
|
|
}
|
|
800b82c: 3708 adds r7, #8
|
|
800b82e: 46bd mov sp, r7
|
|
800b830: bd80 pop {r7, pc}
|
|
800b832: bf00 nop
|
|
800b834: 2000032c .word 0x2000032c
|
|
800b838: 0800d684 .word 0x0800d684
|
|
800b83c: 0800d69c .word 0x0800d69c
|
|
800b840: 0800d6b0 .word 0x0800d6b0
|
|
800b844: 20000380 .word 0x20000380
|
|
800b848: 20000480 .word 0x20000480
|
|
800b84c: 20000348 .word 0x20000348
|
|
800b850: 0800d6d8 .word 0x0800d6d8
|
|
|
|
0800b854 <RFW_GetPayload>:
|
|
|
|
static void RFW_GetPayload( uint8_t Offset, uint8_t Length )
|
|
{
|
|
800b854: b5b0 push {r4, r5, r7, lr}
|
|
800b856: b088 sub sp, #32
|
|
800b858: af04 add r7, sp, #16
|
|
800b85a: 4603 mov r3, r0
|
|
800b85c: 460a mov r2, r1
|
|
800b85e: 71fb strb r3, [r7, #7]
|
|
800b860: 4613 mov r3, r2
|
|
800b862: 71bb strb r3, [r7, #6]
|
|
uint8_t crc_result[2];
|
|
/*stop the radio*/
|
|
SUBGRF_SetStandby( STDBY_RC );
|
|
800b864: 2000 movs r0, #0
|
|
800b866: f7fd ffd3 bl 8009810 <SUBGRF_SetStandby>
|
|
/*read data buffer*/
|
|
SUBGRF_ReadBuffer( Offset, ChunkBuffer, Length );
|
|
800b86a: 79ba ldrb r2, [r7, #6]
|
|
800b86c: 79fb ldrb r3, [r7, #7]
|
|
800b86e: 495a ldr r1, [pc, #360] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b870: 4618 mov r0, r3
|
|
800b872: f7fe fdf9 bl 800a468 <SUBGRF_ReadBuffer>
|
|
/*Run the de-whitening on all packet*/
|
|
RFW_WhiteRun( &RFWPacket, ChunkBuffer, Length );
|
|
800b876: 79bb ldrb r3, [r7, #6]
|
|
800b878: 461a mov r2, r3
|
|
800b87a: 4957 ldr r1, [pc, #348] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b87c: 4857 ldr r0, [pc, #348] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b87e: f7ff fd6a bl 800b356 <RFW_WhiteRun>
|
|
if( RFWPacket.Init.CrcEnable == 1 )
|
|
800b882: 4b56 ldr r3, [pc, #344] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b884: 789b ldrb r3, [r3, #2]
|
|
800b886: 2b01 cmp r3, #1
|
|
800b888: d10a bne.n 800b8a0 <RFW_GetPayload+0x4c>
|
|
{
|
|
RFW_CrcRun( &RFWPacket, ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize, crc_result );
|
|
800b88a: 79bb ldrb r3, [r7, #6]
|
|
800b88c: 4a53 ldr r2, [pc, #332] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b88e: 78d2 ldrb r2, [r2, #3]
|
|
800b890: 1a9b subs r3, r3, r2
|
|
800b892: 461a mov r2, r3
|
|
800b894: f107 030c add.w r3, r7, #12
|
|
800b898: 494f ldr r1, [pc, #316] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b89a: 4850 ldr r0, [pc, #320] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b89c: f7ff fda3 bl 800b3e6 <RFW_CrcRun>
|
|
}
|
|
if( RFWPacket.LongPacketModeEnable == 1 )
|
|
800b8a0: 4b4e ldr r3, [pc, #312] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8a2: 7e9b ldrb r3, [r3, #26]
|
|
800b8a4: 2b01 cmp r3, #1
|
|
800b8a6: d10a bne.n 800b8be <RFW_GetPayload+0x6a>
|
|
{
|
|
/*report rx data chunk to application*/
|
|
|
|
RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize );
|
|
800b8a8: 4b4c ldr r3, [pc, #304] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8aa: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800b8ac: 4a4b ldr r2, [pc, #300] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8ae: 78d2 ldrb r2, [r2, #3]
|
|
800b8b0: 79b9 ldrb r1, [r7, #6]
|
|
800b8b2: 1a8a subs r2, r1, r2
|
|
800b8b4: b2d2 uxtb r2, r2
|
|
800b8b6: 4611 mov r1, r2
|
|
800b8b8: 4847 ldr r0, [pc, #284] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b8ba: 4798 blx r3
|
|
800b8bc: e02a b.n 800b914 <RFW_GetPayload+0xc0>
|
|
}
|
|
else
|
|
{
|
|
if( RFWPacket.RxPayloadOffset + Length - RFWPacket.Init.CrcFieldSize < RADIO_BUF_SIZE )
|
|
800b8be: 4b47 ldr r3, [pc, #284] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8c0: 8f1b ldrh r3, [r3, #56] @ 0x38
|
|
800b8c2: 461a mov r2, r3
|
|
800b8c4: 79bb ldrb r3, [r7, #6]
|
|
800b8c6: 4413 add r3, r2
|
|
800b8c8: 4a44 ldr r2, [pc, #272] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8ca: 78d2 ldrb r2, [r2, #3]
|
|
800b8cc: 1a9b subs r3, r3, r2
|
|
800b8ce: 2bfe cmp r3, #254 @ 0xfe
|
|
800b8d0: dc1b bgt.n 800b90a <RFW_GetPayload+0xb6>
|
|
{
|
|
RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize );
|
|
800b8d2: 4b42 ldr r3, [pc, #264] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8d4: 8f1b ldrh r3, [r3, #56] @ 0x38
|
|
800b8d6: 461a mov r2, r3
|
|
800b8d8: 4b41 ldr r3, [pc, #260] @ (800b9e0 <RFW_GetPayload+0x18c>)
|
|
800b8da: 18d0 adds r0, r2, r3
|
|
800b8dc: 79bb ldrb r3, [r7, #6]
|
|
800b8de: b29b uxth r3, r3
|
|
800b8e0: 4a3e ldr r2, [pc, #248] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8e2: 78d2 ldrb r2, [r2, #3]
|
|
800b8e4: 1a9b subs r3, r3, r2
|
|
800b8e6: b29b uxth r3, r3
|
|
800b8e8: 461a mov r2, r3
|
|
800b8ea: 493b ldr r1, [pc, #236] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b8ec: f000 fbfe bl 800c0ec <UTIL_MEM_cpy_8>
|
|
RFWPacket.RxPayloadOffset += Length - RFWPacket.Init.CrcFieldSize;
|
|
800b8f0: 4b3a ldr r3, [pc, #232] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8f2: 8f1a ldrh r2, [r3, #56] @ 0x38
|
|
800b8f4: 79bb ldrb r3, [r7, #6]
|
|
800b8f6: b29b uxth r3, r3
|
|
800b8f8: 4938 ldr r1, [pc, #224] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b8fa: 78c9 ldrb r1, [r1, #3]
|
|
800b8fc: 1a5b subs r3, r3, r1
|
|
800b8fe: b29b uxth r3, r3
|
|
800b900: 4413 add r3, r2
|
|
800b902: b29a uxth r2, r3
|
|
800b904: 4b35 ldr r3, [pc, #212] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b906: 871a strh r2, [r3, #56] @ 0x38
|
|
800b908: e004 b.n 800b914 <RFW_GetPayload+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/*report CRC error*/
|
|
RFWPacket.Init.RadioEvents->RxError( );
|
|
800b90a: 4b34 ldr r3, [pc, #208] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b90c: 691b ldr r3, [r3, #16]
|
|
800b90e: 691b ldr r3, [r3, #16]
|
|
800b910: 4798 blx r3
|
|
800b912: e05d b.n 800b9d0 <RFW_GetPayload+0x17c>
|
|
return;
|
|
}
|
|
}
|
|
TimerStop( RFWPacket.RxTimeoutTimer );
|
|
800b914: 4b31 ldr r3, [pc, #196] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b916: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b918: 4618 mov r0, r3
|
|
800b91a: f001 f93b bl 800cb94 <UTIL_TIMER_Stop>
|
|
/* CRC check*/
|
|
RFW_MW_LOG( TS_ON, VLEVEL_M, "crc_result= 0x%02X%02X, crc_payload=0x%02X%02X\r\n", crc_result[0], crc_result[1],
|
|
800b91e: 7b3b ldrb r3, [r7, #12]
|
|
800b920: 4619 mov r1, r3
|
|
800b922: 7b7b ldrb r3, [r7, #13]
|
|
800b924: 4618 mov r0, r3
|
|
800b926: 79bb ldrb r3, [r7, #6]
|
|
800b928: 3b02 subs r3, #2
|
|
800b92a: 4a2b ldr r2, [pc, #172] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b92c: 5cd3 ldrb r3, [r2, r3]
|
|
800b92e: 461c mov r4, r3
|
|
800b930: 79bb ldrb r3, [r7, #6]
|
|
800b932: 3b01 subs r3, #1
|
|
800b934: 4a28 ldr r2, [pc, #160] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b936: 5cd3 ldrb r3, [r2, r3]
|
|
800b938: 9303 str r3, [sp, #12]
|
|
800b93a: 9402 str r4, [sp, #8]
|
|
800b93c: 9001 str r0, [sp, #4]
|
|
800b93e: 9100 str r1, [sp, #0]
|
|
800b940: 4b28 ldr r3, [pc, #160] @ (800b9e4 <RFW_GetPayload+0x190>)
|
|
800b942: 2201 movs r2, #1
|
|
800b944: 2100 movs r1, #0
|
|
800b946: 2002 movs r0, #2
|
|
800b948: f001 fb1c bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
ChunkBuffer[Length - 2], ChunkBuffer[Length - 1] );
|
|
if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) &&
|
|
800b94c: 7b3a ldrb r2, [r7, #12]
|
|
800b94e: 79bb ldrb r3, [r7, #6]
|
|
800b950: 3b02 subs r3, #2
|
|
800b952: 4921 ldr r1, [pc, #132] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b954: 5ccb ldrb r3, [r1, r3]
|
|
800b956: 429a cmp r2, r3
|
|
800b958: d106 bne.n 800b968 <RFW_GetPayload+0x114>
|
|
( crc_result[1] == ChunkBuffer[Length - 1] ) ) ||
|
|
800b95a: 7b7a ldrb r2, [r7, #13]
|
|
800b95c: 79bb ldrb r3, [r7, #6]
|
|
800b95e: 3b01 subs r3, #1
|
|
800b960: 491d ldr r1, [pc, #116] @ (800b9d8 <RFW_GetPayload+0x184>)
|
|
800b962: 5ccb ldrb r3, [r1, r3]
|
|
if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) &&
|
|
800b964: 429a cmp r2, r3
|
|
800b966: d003 beq.n 800b970 <RFW_GetPayload+0x11c>
|
|
( RFWPacket.Init.CrcEnable == 0 ) )
|
|
800b968: 4b1c ldr r3, [pc, #112] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b96a: 789b ldrb r3, [r3, #2]
|
|
( crc_result[1] == ChunkBuffer[Length - 1] ) ) ||
|
|
800b96c: 2b00 cmp r3, #0
|
|
800b96e: d126 bne.n 800b9be <RFW_GetPayload+0x16a>
|
|
{
|
|
/*read Rssi sampled at Sync*/
|
|
uint8_t rssi_sync = SUBGRF_ReadRegister( 0x06CA );
|
|
800b970: f240 60ca movw r0, #1738 @ 0x6ca
|
|
800b974: f7fe fcf2 bl 800a35c <SUBGRF_ReadRegister>
|
|
800b978: 4603 mov r3, r0
|
|
800b97a: 73fb strb r3, [r7, #15]
|
|
/* Get Carrier Frequency Offset*/
|
|
int32_t cfo;
|
|
SUBGRF_GetCFO( RFWPacket.BitRate, &cfo );
|
|
800b97c: 4b17 ldr r3, [pc, #92] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b97e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800b980: f107 0208 add.w r2, r7, #8
|
|
800b984: 4611 mov r1, r2
|
|
800b986: 4618 mov r0, r3
|
|
800b988: f7fe ff22 bl 800a7d0 <SUBGRF_GetCFO>
|
|
/*ChunkBuffer[1] to remove packet Length*/
|
|
RFWPacket.Init.RadioEvents->RxDone( RxBuffer,
|
|
800b98c: 4b13 ldr r3, [pc, #76] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b98e: 691b ldr r3, [r3, #16]
|
|
800b990: 689c ldr r4, [r3, #8]
|
|
800b992: 4b12 ldr r3, [pc, #72] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b994: 8f19 ldrh r1, [r3, #56] @ 0x38
|
|
800b996: 7bfb ldrb r3, [r7, #15]
|
|
800b998: 085b lsrs r3, r3, #1
|
|
800b99a: b2db uxtb r3, r3
|
|
800b99c: 425b negs r3, r3
|
|
800b99e: b29b uxth r3, r3
|
|
800b9a0: b218 sxth r0, r3
|
|
RFWPacket.RxPayloadOffset,
|
|
-( rssi_sync >> 1 ),
|
|
( int8_t ) DIVR( cfo, 1000 ) );
|
|
800b9a2: 68bb ldr r3, [r7, #8]
|
|
800b9a4: f503 73fa add.w r3, r3, #500 @ 0x1f4
|
|
800b9a8: 4a0f ldr r2, [pc, #60] @ (800b9e8 <RFW_GetPayload+0x194>)
|
|
800b9aa: fb82 5203 smull r5, r2, r2, r3
|
|
800b9ae: 1192 asrs r2, r2, #6
|
|
800b9b0: 17db asrs r3, r3, #31
|
|
800b9b2: 1ad3 subs r3, r2, r3
|
|
RFWPacket.Init.RadioEvents->RxDone( RxBuffer,
|
|
800b9b4: b25b sxtb r3, r3
|
|
800b9b6: 4602 mov r2, r0
|
|
800b9b8: 4809 ldr r0, [pc, #36] @ (800b9e0 <RFW_GetPayload+0x18c>)
|
|
800b9ba: 47a0 blx r4
|
|
{
|
|
800b9bc: e003 b.n 800b9c6 <RFW_GetPayload+0x172>
|
|
}
|
|
else
|
|
{
|
|
/*report CRC error*/
|
|
RFWPacket.Init.RadioEvents->RxError( );
|
|
800b9be: 4b07 ldr r3, [pc, #28] @ (800b9dc <RFW_GetPayload+0x188>)
|
|
800b9c0: 691b ldr r3, [r3, #16]
|
|
800b9c2: 691b ldr r3, [r3, #16]
|
|
800b9c4: 4798 blx r3
|
|
}
|
|
DBG_GPIO_RADIO_RX( RST );
|
|
800b9c6: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
800b9ca: 4808 ldr r0, [pc, #32] @ (800b9ec <RFW_GetPayload+0x198>)
|
|
800b9cc: f7fe ff8d bl 800a8ea <LL_GPIO_ResetOutputPin>
|
|
}
|
|
800b9d0: 3710 adds r7, #16
|
|
800b9d2: 46bd mov sp, r7
|
|
800b9d4: bdb0 pop {r4, r5, r7, pc}
|
|
800b9d6: bf00 nop
|
|
800b9d8: 20000380 .word 0x20000380
|
|
800b9dc: 2000032c .word 0x2000032c
|
|
800b9e0: 20000480 .word 0x20000480
|
|
800b9e4: 0800d708 .word 0x0800d708
|
|
800b9e8: 10624dd3 .word 0x10624dd3
|
|
800b9ec: 48000400 .word 0x48000400
|
|
|
|
0800b9f0 <MX_SubGHz_Phy_Init>:
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
void MX_SubGHz_Phy_Init(void)
|
|
{
|
|
800b9f0: b580 push {r7, lr}
|
|
800b9f2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MX_SubGHz_Phy_Init_1 */
|
|
|
|
/* USER CODE END MX_SubGHz_Phy_Init_1 */
|
|
SystemApp_Init();
|
|
800b9f4: f7f5 f84a bl 8000a8c <SystemApp_Init>
|
|
/* USER CODE BEGIN MX_SubGHz_Phy_Init_1_1 */
|
|
|
|
/* USER CODE END MX_SubGHz_Phy_Init_1_1 */
|
|
SubghzApp_Init();
|
|
800b9f8: f000 f80a bl 800ba10 <SubghzApp_Init>
|
|
/* USER CODE BEGIN MX_SubGHz_Phy_Init_2 */
|
|
|
|
/* USER CODE END MX_SubGHz_Phy_Init_2 */
|
|
}
|
|
800b9fc: bf00 nop
|
|
800b9fe: bd80 pop {r7, pc}
|
|
|
|
0800ba00 <MX_SubGHz_Phy_Process>:
|
|
|
|
void MX_SubGHz_Phy_Process(void)
|
|
{
|
|
800ba00: b580 push {r7, lr}
|
|
800ba02: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MX_SubGHz_Phy_Process_1 */
|
|
|
|
/* USER CODE END MX_SubGHz_Phy_Process_1 */
|
|
UTIL_SEQ_Run(UTIL_SEQ_DEFAULT);
|
|
800ba04: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800ba08: f000 fe82 bl 800c710 <UTIL_SEQ_Run>
|
|
/* USER CODE BEGIN MX_SubGHz_Phy_Process_2 */
|
|
|
|
/* USER CODE END MX_SubGHz_Phy_Process_2 */
|
|
}
|
|
800ba0c: bf00 nop
|
|
800ba0e: bd80 pop {r7, pc}
|
|
|
|
0800ba10 <SubghzApp_Init>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions ---------------------------------------------------------*/
|
|
void SubghzApp_Init(void)
|
|
{
|
|
800ba10: b590 push {r4, r7, lr}
|
|
800ba12: b08d sub sp, #52 @ 0x34
|
|
800ba14: af04 add r7, sp, #16
|
|
#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 ) && (TEST_MODE == RADIO_TX))
|
|
TxConfigGeneric_t TxConfig;
|
|
#else
|
|
#endif /* TEST_MODE */
|
|
/* Get SubGHY_Phy APP version*/
|
|
APP_LOG(TS_OFF, VLEVEL_M, "APPLICATION_VERSION: V%X.%X.%X\r\n",
|
|
800ba16: 2300 movs r3, #0
|
|
800ba18: 9302 str r3, [sp, #8]
|
|
800ba1a: 2304 movs r3, #4
|
|
800ba1c: 9301 str r3, [sp, #4]
|
|
800ba1e: 2301 movs r3, #1
|
|
800ba20: 9300 str r3, [sp, #0]
|
|
800ba22: 4b48 ldr r3, [pc, #288] @ (800bb44 <SubghzApp_Init+0x134>)
|
|
800ba24: 2200 movs r2, #0
|
|
800ba26: 2100 movs r1, #0
|
|
800ba28: 2002 movs r0, #2
|
|
800ba2a: f001 faab bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
(uint8_t)(APP_VERSION_MAIN),
|
|
(uint8_t)(APP_VERSION_SUB1),
|
|
(uint8_t)(APP_VERSION_SUB2));
|
|
|
|
/* Get MW SubGhz_Phy info */
|
|
APP_LOG(TS_OFF, VLEVEL_M, "MW_RADIO_VERSION: V%X.%X.%X\r\n",
|
|
800ba2e: 2301 movs r3, #1
|
|
800ba30: 9302 str r3, [sp, #8]
|
|
800ba32: 2303 movs r3, #3
|
|
800ba34: 9301 str r3, [sp, #4]
|
|
800ba36: 2301 movs r3, #1
|
|
800ba38: 9300 str r3, [sp, #0]
|
|
800ba3a: 4b43 ldr r3, [pc, #268] @ (800bb48 <SubghzApp_Init+0x138>)
|
|
800ba3c: 2200 movs r2, #0
|
|
800ba3e: 2100 movs r1, #0
|
|
800ba40: 2002 movs r0, #2
|
|
800ba42: f001 fa9f bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
(uint8_t)(SUBGHZ_PHY_VERSION_MAIN),
|
|
(uint8_t)(SUBGHZ_PHY_VERSION_SUB1),
|
|
(uint8_t)(SUBGHZ_PHY_VERSION_SUB2));
|
|
|
|
APP_LOG(TS_OFF, VLEVEL_M, "---------------\n\r");
|
|
800ba46: 4b41 ldr r3, [pc, #260] @ (800bb4c <SubghzApp_Init+0x13c>)
|
|
800ba48: 2200 movs r2, #0
|
|
800ba4a: 2100 movs r1, #0
|
|
800ba4c: 2002 movs r0, #2
|
|
800ba4e: f001 fa99 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
#if (( USE_MODEM_LORA == 1 ) && ( USE_MODEM_FSK == 0 ))
|
|
APP_LOG(TS_OFF, VLEVEL_M, "LORA_MODULATION\n\r");
|
|
APP_LOG(TS_OFF, VLEVEL_M, "LORA_BW=%d Hz\n\r", 125000);
|
|
#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 ))
|
|
APP_LOG(TS_OFF, VLEVEL_M, "FSK_MODULATION\n\r");
|
|
800ba52: 4b3f ldr r3, [pc, #252] @ (800bb50 <SubghzApp_Init+0x140>)
|
|
800ba54: 2200 movs r2, #0
|
|
800ba56: 2100 movs r1, #0
|
|
800ba58: 2002 movs r0, #2
|
|
800ba5a: f001 fa93 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
APP_LOG(TS_OFF, VLEVEL_M, "FSK_BW=%d Hz\n\r", FSK_BANDWIDTH);
|
|
800ba5e: f246 13a8 movw r3, #25000 @ 0x61a8
|
|
800ba62: 9300 str r3, [sp, #0]
|
|
800ba64: 4b3b ldr r3, [pc, #236] @ (800bb54 <SubghzApp_Init+0x144>)
|
|
800ba66: 2200 movs r2, #0
|
|
800ba68: 2100 movs r1, #0
|
|
800ba6a: 2002 movs r0, #2
|
|
800ba6c: f001 fa8a bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
APP_LOG(TS_OFF, VLEVEL_M, "FSK_DR=%d bits/s\n\r", FSK_DATARATE);
|
|
800ba70: f242 7310 movw r3, #10000 @ 0x2710
|
|
800ba74: 9300 str r3, [sp, #0]
|
|
800ba76: 4b38 ldr r3, [pc, #224] @ (800bb58 <SubghzApp_Init+0x148>)
|
|
800ba78: 2200 movs r2, #0
|
|
800ba7a: 2100 movs r1, #0
|
|
800ba7c: 2002 movs r0, #2
|
|
800ba7e: f001 fa81 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
#if (TEST_MODE == RADIO_RX)
|
|
APP_LOG(TS_OFF, VLEVEL_M, "Rx Mode\n\r", FSK_DATARATE);
|
|
#elif (TEST_MODE == RADIO_TX)
|
|
APP_LOG(TS_OFF, VLEVEL_M, "Tx Mode\n\r", FSK_DATARATE);
|
|
800ba82: f242 7310 movw r3, #10000 @ 0x2710
|
|
800ba86: 9300 str r3, [sp, #0]
|
|
800ba88: 4b34 ldr r3, [pc, #208] @ (800bb5c <SubghzApp_Init+0x14c>)
|
|
800ba8a: 2200 movs r2, #0
|
|
800ba8c: 2100 movs r1, #0
|
|
800ba8e: 2002 movs r0, #2
|
|
800ba90: f001 fa78 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
#error "Please define a modem in the compiler subghz_phy_app.h."
|
|
#endif /* USE_MODEM_LORA | USE_MODEM_FSK */
|
|
/* USER CODE END SubghzApp_Init_1 */
|
|
|
|
/* Radio initialization */
|
|
RadioEvents.TxDone = OnTxDone;
|
|
800ba94: 4b32 ldr r3, [pc, #200] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800ba96: 4a33 ldr r2, [pc, #204] @ (800bb64 <SubghzApp_Init+0x154>)
|
|
800ba98: 601a str r2, [r3, #0]
|
|
RadioEvents.RxDone = OnRxDone;
|
|
800ba9a: 4b31 ldr r3, [pc, #196] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800ba9c: 4a32 ldr r2, [pc, #200] @ (800bb68 <SubghzApp_Init+0x158>)
|
|
800ba9e: 609a str r2, [r3, #8]
|
|
RadioEvents.TxTimeout = OnTxTimeout;
|
|
800baa0: 4b2f ldr r3, [pc, #188] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800baa2: 4a32 ldr r2, [pc, #200] @ (800bb6c <SubghzApp_Init+0x15c>)
|
|
800baa4: 605a str r2, [r3, #4]
|
|
RadioEvents.RxTimeout = OnRxTimeout;
|
|
800baa6: 4b2e ldr r3, [pc, #184] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800baa8: 4a31 ldr r2, [pc, #196] @ (800bb70 <SubghzApp_Init+0x160>)
|
|
800baaa: 60da str r2, [r3, #12]
|
|
RadioEvents.RxError = OnRxError;
|
|
800baac: 4b2c ldr r3, [pc, #176] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800baae: 4a31 ldr r2, [pc, #196] @ (800bb74 <SubghzApp_Init+0x164>)
|
|
800bab0: 611a str r2, [r3, #16]
|
|
|
|
Radio.Init(&RadioEvents);
|
|
800bab2: 4b31 ldr r3, [pc, #196] @ (800bb78 <SubghzApp_Init+0x168>)
|
|
800bab4: 681b ldr r3, [r3, #0]
|
|
800bab6: 482a ldr r0, [pc, #168] @ (800bb60 <SubghzApp_Init+0x150>)
|
|
800bab8: 4798 blx r3
|
|
|
|
/* USER CODE BEGIN SubghzApp_Init_2 */
|
|
/* Radio Set frequency */
|
|
Radio.SetChannel(RF_FREQUENCY);
|
|
800baba: 4b2f ldr r3, [pc, #188] @ (800bb78 <SubghzApp_Init+0x168>)
|
|
800babc: 68db ldr r3, [r3, #12]
|
|
800babe: 482f ldr r0, [pc, #188] @ (800bb7c <SubghzApp_Init+0x16c>)
|
|
800bac0: 4798 blx r3
|
|
|
|
data_offset = 0;
|
|
800bac2: 4b2f ldr r3, [pc, #188] @ (800bb80 <SubghzApp_Init+0x170>)
|
|
800bac4: 2200 movs r2, #0
|
|
800bac6: 801a strh r2, [r3, #0]
|
|
#else
|
|
(void) Radio.ReceiveLongPacket(0, RX_TIMEOUT_VALUE, RxLongPacketChunk);
|
|
#endif /* APP_LONG_PACKET */
|
|
|
|
#elif (TEST_MODE == RADIO_TX)
|
|
tx_payload_generator();
|
|
800bac8: f000 f9ba bl 800be40 <tx_payload_generator>
|
|
true, 0, 0, LORA_IQ_INVERSION_ON, TX_TIMEOUT_VALUE);
|
|
|
|
Radio.SetMaxPayloadLength(MODEM_LORA, MAX_APP_BUFFER_SIZE);
|
|
#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 ))
|
|
/*fsk modulation*/
|
|
TxConfig.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05;
|
|
800bacc: 2309 movs r3, #9
|
|
800bace: 75fb strb r3, [r7, #23]
|
|
TxConfig.fsk.FrequencyDeviation = FSK_FDEV;
|
|
800bad0: f246 13a8 movw r3, #25000 @ 0x61a8
|
|
800bad4: 61fb str r3, [r7, #28]
|
|
TxConfig.fsk.BitRate = FSK_DATARATE; /*BitRate*/
|
|
800bad6: f242 7310 movw r3, #10000 @ 0x2710
|
|
800bada: 607b str r3, [r7, #4]
|
|
TxConfig.fsk.PreambleLen = 4; /*in Byte */
|
|
800badc: 2304 movs r3, #4
|
|
800bade: 60bb str r3, [r7, #8]
|
|
TxConfig.fsk.SyncWordLength = sizeof(syncword); /*in Byte */
|
|
800bae0: 2303 movs r3, #3
|
|
800bae2: 75bb strb r3, [r7, #22]
|
|
TxConfig.fsk.SyncWord = syncword; /*SyncWord Buffer*/
|
|
800bae4: 4b27 ldr r3, [pc, #156] @ (800bb84 <SubghzApp_Init+0x174>)
|
|
800bae6: 60fb str r3, [r7, #12]
|
|
TxConfig.fsk.whiteSeed = 0x01FF; /*WhiteningSeed */
|
|
800bae8: f240 13ff movw r3, #511 @ 0x1ff
|
|
800baec: 82bb strh r3, [r7, #20]
|
|
#if (APP_LONG_PACKET==0)
|
|
TxConfig.fsk.HeaderType = RADIO_FSK_PACKET_VARIABLE_LENGTH; /*legacy: payload length field is 1 byte long*/
|
|
800baee: 2301 movs r3, #1
|
|
800baf0: 763b strb r3, [r7, #24]
|
|
#else
|
|
TxConfig.fsk.HeaderType = RADIO_FSK_PACKET_2BYTES_LENGTH; /* payload length field is 2 bytes long */
|
|
#endif /* APP_LONG_PACKET */
|
|
TxConfig.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; /* Size of the CRC block in the GFSK packet*/
|
|
800baf2: 23f1 movs r3, #241 @ 0xf1
|
|
800baf4: 767b strb r3, [r7, #25]
|
|
TxConfig.fsk.CrcPolynomial = 0x8005;
|
|
800baf6: f248 0305 movw r3, #32773 @ 0x8005
|
|
800bafa: 823b strh r3, [r7, #16]
|
|
TxConfig.fsk.CrcSeed = 0xFFFF;
|
|
800bafc: f64f 73ff movw r3, #65535 @ 0xffff
|
|
800bb00: 827b strh r3, [r7, #18]
|
|
TxConfig.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING;
|
|
800bb02: 2301 movs r3, #1
|
|
800bb04: 76bb strb r3, [r7, #26]
|
|
if (0UL != Radio.RadioSetTxGenericConfig(GENERIC_FSK, &TxConfig, TX_OUTPUT_POWER, TX_TIMEOUT_VALUE))
|
|
800bb06: 4b1c ldr r3, [pc, #112] @ (800bb78 <SubghzApp_Init+0x168>)
|
|
800bb08: 6f9c ldr r4, [r3, #120] @ 0x78
|
|
800bb0a: 1d39 adds r1, r7, #4
|
|
800bb0c: f640 33b8 movw r3, #3000 @ 0xbb8
|
|
800bb10: 2210 movs r2, #16
|
|
800bb12: 2000 movs r0, #0
|
|
800bb14: 47a0 blx r4
|
|
800bb16: 4603 mov r3, r0
|
|
800bb18: 2b00 cmp r3, #0
|
|
800bb1a: d001 beq.n 800bb20 <SubghzApp_Init+0x110>
|
|
{
|
|
while (1);
|
|
800bb1c: bf00 nop
|
|
800bb1e: e7fd b.n 800bb1c <SubghzApp_Init+0x10c>
|
|
#else
|
|
#error "Please define a modem in the compiler subghz_phy_app.h."
|
|
#endif /* USE_MODEM_LORA | USE_MODEM_FSK */
|
|
|
|
#if (APP_LONG_PACKET==0)
|
|
Radio.Send(data_buffer, payloadLen);
|
|
800bb20: 4b15 ldr r3, [pc, #84] @ (800bb78 <SubghzApp_Init+0x168>)
|
|
800bb22: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800bb24: 4a18 ldr r2, [pc, #96] @ (800bb88 <SubghzApp_Init+0x178>)
|
|
800bb26: 8812 ldrh r2, [r2, #0]
|
|
800bb28: b292 uxth r2, r2
|
|
800bb2a: b2d2 uxtb r2, r2
|
|
800bb2c: 4611 mov r1, r2
|
|
800bb2e: 4817 ldr r0, [pc, #92] @ (800bb8c <SubghzApp_Init+0x17c>)
|
|
800bb30: 4798 blx r3
|
|
#else
|
|
#error should be either Tx or Rx
|
|
#endif /* TEST_MODE */
|
|
|
|
/*register task to to be run in while(1) after Radio IT*/
|
|
UTIL_SEQ_RegTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), UTIL_SEQ_RFU, Per_Process);
|
|
800bb32: 4a17 ldr r2, [pc, #92] @ (800bb90 <SubghzApp_Init+0x180>)
|
|
800bb34: 2100 movs r1, #0
|
|
800bb36: 2001 movs r0, #1
|
|
800bb38: f000 fee6 bl 800c908 <UTIL_SEQ_RegTask>
|
|
/* USER CODE END SubghzApp_Init_2 */
|
|
}
|
|
800bb3c: bf00 nop
|
|
800bb3e: 3724 adds r7, #36 @ 0x24
|
|
800bb40: 46bd mov sp, r7
|
|
800bb42: bd90 pop {r4, r7, pc}
|
|
800bb44: 0800d73c .word 0x0800d73c
|
|
800bb48: 0800d760 .word 0x0800d760
|
|
800bb4c: 0800d784 .word 0x0800d784
|
|
800bb50: 0800d798 .word 0x0800d798
|
|
800bb54: 0800d7ac .word 0x0800d7ac
|
|
800bb58: 0800d7bc .word 0x0800d7bc
|
|
800bb5c: 0800d7d0 .word 0x0800d7d0
|
|
800bb60: 20000580 .word 0x20000580
|
|
800bb64: 0800bb95 .word 0x0800bb95
|
|
800bb68: 0800bbb1 .word 0x0800bbb1
|
|
800bb6c: 0800bc15 .word 0x0800bc15
|
|
800bb70: 0800bc31 .word 0x0800bc31
|
|
800bb74: 0800bc4d .word 0x0800bc4d
|
|
800bb78: 0800d9e0 .word 0x0800d9e0
|
|
800bb7c: 19d094e0 .word 0x19d094e0
|
|
800bb80: 2000099c .word 0x2000099c
|
|
800bb84: 20000010 .word 0x20000010
|
|
800bb88: 2000000a .word 0x2000000a
|
|
800bb8c: 200005b4 .word 0x200005b4
|
|
800bb90: 0800bc69 .word 0x0800bc69
|
|
|
|
0800bb94 <OnTxDone>:
|
|
|
|
/* USER CODE END EF */
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
static void OnTxDone(void)
|
|
{
|
|
800bb94: b580 push {r7, lr}
|
|
800bb96: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OnTxDone */
|
|
RadioTxDone_flag = 1;
|
|
800bb98: 4b04 ldr r3, [pc, #16] @ (800bbac <OnTxDone+0x18>)
|
|
800bb9a: 2201 movs r2, #1
|
|
800bb9c: 601a str r2, [r3, #0]
|
|
UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0);
|
|
800bb9e: 2100 movs r1, #0
|
|
800bba0: 2001 movs r0, #1
|
|
800bba2: f000 fed3 bl 800c94c <UTIL_SEQ_SetTask>
|
|
/* USER CODE END OnTxDone */
|
|
}
|
|
800bba6: bf00 nop
|
|
800bba8: bd80 pop {r7, pc}
|
|
800bbaa: bf00 nop
|
|
800bbac: 2000059c .word 0x2000059c
|
|
|
|
0800bbb0 <OnRxDone>:
|
|
|
|
static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t LoraSnr_FskCfo)
|
|
{
|
|
800bbb0: b580 push {r7, lr}
|
|
800bbb2: b084 sub sp, #16
|
|
800bbb4: af00 add r7, sp, #0
|
|
800bbb6: 60f8 str r0, [r7, #12]
|
|
800bbb8: 4608 mov r0, r1
|
|
800bbba: 4611 mov r1, r2
|
|
800bbbc: 461a mov r2, r3
|
|
800bbbe: 4603 mov r3, r0
|
|
800bbc0: 817b strh r3, [r7, #10]
|
|
800bbc2: 460b mov r3, r1
|
|
800bbc4: 813b strh r3, [r7, #8]
|
|
800bbc6: 4613 mov r3, r2
|
|
800bbc8: 71fb strb r3, [r7, #7]
|
|
/* USER CODE BEGIN OnRxDone */
|
|
last_rx_rssi = rssi;
|
|
800bbca: 4a0d ldr r2, [pc, #52] @ (800bc00 <OnRxDone+0x50>)
|
|
800bbcc: 893b ldrh r3, [r7, #8]
|
|
800bbce: 8013 strh r3, [r2, #0]
|
|
last_rx_cfo = LoraSnr_FskCfo;
|
|
800bbd0: 4a0c ldr r2, [pc, #48] @ (800bc04 <OnRxDone+0x54>)
|
|
800bbd2: 79fb ldrb r3, [r7, #7]
|
|
800bbd4: 7013 strb r3, [r2, #0]
|
|
|
|
/* Set Rxdone flag */
|
|
RadioRxDone_flag = 1;
|
|
800bbd6: 4b0c ldr r3, [pc, #48] @ (800bc08 <OnRxDone+0x58>)
|
|
800bbd8: 2201 movs r2, #1
|
|
800bbda: 601a str r2, [r3, #0]
|
|
/* Run Per process in background*/
|
|
UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0);
|
|
800bbdc: 2100 movs r1, #0
|
|
800bbde: 2001 movs r0, #1
|
|
800bbe0: f000 feb4 bl 800c94c <UTIL_SEQ_SetTask>
|
|
#if (APP_LONG_PACKET==0)
|
|
memcpy(data_buffer, payload, size);
|
|
800bbe4: 897b ldrh r3, [r7, #10]
|
|
800bbe6: 461a mov r2, r3
|
|
800bbe8: 68f9 ldr r1, [r7, #12]
|
|
800bbea: 4808 ldr r0, [pc, #32] @ (800bc0c <OnRxDone+0x5c>)
|
|
800bbec: f001 fc6e bl 800d4cc <memcpy>
|
|
payloadLen = size;
|
|
800bbf0: 4a07 ldr r2, [pc, #28] @ (800bc10 <OnRxDone+0x60>)
|
|
800bbf2: 897b ldrh r3, [r7, #10]
|
|
800bbf4: 8013 strh r3, [r2, #0]
|
|
/*from chunk*/
|
|
payloadLen = data_offset;
|
|
/*payload data are not relevant in long packet mode*/
|
|
#endif /* APP_LONG_PACKET */
|
|
/* USER CODE END OnRxDone */
|
|
}
|
|
800bbf6: bf00 nop
|
|
800bbf8: 3710 adds r7, #16
|
|
800bbfa: 46bd mov sp, r7
|
|
800bbfc: bd80 pop {r7, pc}
|
|
800bbfe: bf00 nop
|
|
800bc00: 200005b0 .word 0x200005b0
|
|
800bc04: 200005b2 .word 0x200005b2
|
|
800bc08: 200005a4 .word 0x200005a4
|
|
800bc0c: 200005b4 .word 0x200005b4
|
|
800bc10: 2000000a .word 0x2000000a
|
|
|
|
0800bc14 <OnTxTimeout>:
|
|
|
|
static void OnTxTimeout(void)
|
|
{
|
|
800bc14: b580 push {r7, lr}
|
|
800bc16: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OnTxTimeout */
|
|
RadioTxTimeout_flag = 1;
|
|
800bc18: 4b04 ldr r3, [pc, #16] @ (800bc2c <OnTxTimeout+0x18>)
|
|
800bc1a: 2201 movs r2, #1
|
|
800bc1c: 601a str r2, [r3, #0]
|
|
/* Run process in background*/
|
|
UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0);
|
|
800bc1e: 2100 movs r1, #0
|
|
800bc20: 2001 movs r0, #1
|
|
800bc22: f000 fe93 bl 800c94c <UTIL_SEQ_SetTask>
|
|
/* USER CODE END OnTxTimeout */
|
|
}
|
|
800bc26: bf00 nop
|
|
800bc28: bd80 pop {r7, pc}
|
|
800bc2a: bf00 nop
|
|
800bc2c: 200005a0 .word 0x200005a0
|
|
|
|
0800bc30 <OnRxTimeout>:
|
|
|
|
static void OnRxTimeout(void)
|
|
{
|
|
800bc30: b580 push {r7, lr}
|
|
800bc32: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OnRxTimeout */
|
|
RadioRxTimeout_flag = 1;
|
|
800bc34: 4b04 ldr r3, [pc, #16] @ (800bc48 <OnRxTimeout+0x18>)
|
|
800bc36: 2201 movs r2, #1
|
|
800bc38: 601a str r2, [r3, #0]
|
|
/* Run Per process in background*/
|
|
UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0);
|
|
800bc3a: 2100 movs r1, #0
|
|
800bc3c: 2001 movs r0, #1
|
|
800bc3e: f000 fe85 bl 800c94c <UTIL_SEQ_SetTask>
|
|
/* USER CODE END OnRxTimeout */
|
|
}
|
|
800bc42: bf00 nop
|
|
800bc44: bd80 pop {r7, pc}
|
|
800bc46: bf00 nop
|
|
800bc48: 200005a8 .word 0x200005a8
|
|
|
|
0800bc4c <OnRxError>:
|
|
|
|
static void OnRxError(void)
|
|
{
|
|
800bc4c: b580 push {r7, lr}
|
|
800bc4e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OnRxError */
|
|
RadioError_flag = 1;
|
|
800bc50: 4b04 ldr r3, [pc, #16] @ (800bc64 <OnRxError+0x18>)
|
|
800bc52: 2201 movs r2, #1
|
|
800bc54: 601a str r2, [r3, #0]
|
|
/* Run Per process in background*/
|
|
UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0);
|
|
800bc56: 2100 movs r1, #0
|
|
800bc58: 2001 movs r0, #1
|
|
800bc5a: f000 fe77 bl 800c94c <UTIL_SEQ_SetTask>
|
|
/* USER CODE END OnRxError */
|
|
}
|
|
800bc5e: bf00 nop
|
|
800bc60: bd80 pop {r7, pc}
|
|
800bc62: bf00 nop
|
|
800bc64: 200005ac .word 0x200005ac
|
|
|
|
0800bc68 <Per_Process>:
|
|
/* APP_TPRINTF("Tx chunk: chunk_size=%d, data_offset=%d\r\n",chunk_size, data_offset); */
|
|
}
|
|
#endif /* APP_LONG_PACKET */
|
|
uint8_t buffer_error = 0;
|
|
static void Per_Process(void)
|
|
{
|
|
800bc68: b580 push {r7, lr}
|
|
800bc6a: b082 sub sp, #8
|
|
800bc6c: af02 add r7, sp, #8
|
|
packetCnt++;
|
|
800bc6e: 4b2b ldr r3, [pc, #172] @ (800bd1c <Per_Process+0xb4>)
|
|
800bc70: 681b ldr r3, [r3, #0]
|
|
800bc72: 3301 adds r3, #1
|
|
800bc74: 4a29 ldr r2, [pc, #164] @ (800bd1c <Per_Process+0xb4>)
|
|
800bc76: 6013 str r3, [r2, #0]
|
|
data_offset = 0;
|
|
800bc78: 4b29 ldr r3, [pc, #164] @ (800bd20 <Per_Process+0xb8>)
|
|
800bc7a: 2200 movs r2, #0
|
|
800bc7c: 801a strh r2, [r3, #0]
|
|
#endif /* APP_LONG_PACKET */
|
|
HAL_Delay(10);
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); /* LED_GREEN */
|
|
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); /* LED_RED */
|
|
#elif (TEST_MODE == RADIO_TX)
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); /* LED_BLUE */
|
|
800bc7e: 2200 movs r2, #0
|
|
800bc80: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
800bc84: 4827 ldr r0, [pc, #156] @ (800bd24 <Per_Process+0xbc>)
|
|
800bc86: f7f6 fd5d bl 8002744 <HAL_GPIO_WritePin>
|
|
if (RadioTxDone_flag == 1)
|
|
800bc8a: 4b27 ldr r3, [pc, #156] @ (800bd28 <Per_Process+0xc0>)
|
|
800bc8c: 681b ldr r3, [r3, #0]
|
|
800bc8e: 2b01 cmp r3, #1
|
|
800bc90: d105 bne.n 800bc9e <Per_Process+0x36>
|
|
{
|
|
APP_TPRINTF("OnTxDone\r\n");
|
|
800bc92: 4b26 ldr r3, [pc, #152] @ (800bd2c <Per_Process+0xc4>)
|
|
800bc94: 2201 movs r2, #1
|
|
800bc96: 2100 movs r1, #0
|
|
800bc98: 2000 movs r0, #0
|
|
800bc9a: f001 f973 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
}
|
|
|
|
if (RadioTxTimeout_flag == 1)
|
|
800bc9e: 4b24 ldr r3, [pc, #144] @ (800bd30 <Per_Process+0xc8>)
|
|
800bca0: 681b ldr r3, [r3, #0]
|
|
800bca2: 2b01 cmp r3, #1
|
|
800bca4: d105 bne.n 800bcb2 <Per_Process+0x4a>
|
|
{
|
|
APP_TPRINTF("OnTxTimeout\r\n");
|
|
800bca6: 4b23 ldr r3, [pc, #140] @ (800bd34 <Per_Process+0xcc>)
|
|
800bca8: 2201 movs r2, #1
|
|
800bcaa: 2100 movs r1, #0
|
|
800bcac: 2000 movs r0, #0
|
|
800bcae: f001 f969 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
}
|
|
|
|
if (RadioError_flag == 1)
|
|
800bcb2: 4b21 ldr r3, [pc, #132] @ (800bd38 <Per_Process+0xd0>)
|
|
800bcb4: 681b ldr r3, [r3, #0]
|
|
800bcb6: 2b01 cmp r3, #1
|
|
800bcb8: d105 bne.n 800bcc6 <Per_Process+0x5e>
|
|
{
|
|
APP_TPRINTF("OnRxError\r\n");
|
|
800bcba: 4b20 ldr r3, [pc, #128] @ (800bd3c <Per_Process+0xd4>)
|
|
800bcbc: 2201 movs r2, #1
|
|
800bcbe: 2100 movs r1, #0
|
|
800bcc0: 2000 movs r0, #0
|
|
800bcc2: f001 f95f bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
}
|
|
/* This delay is only to give enough time to allow DMA to empty printf queue*/
|
|
HAL_Delay(500);
|
|
800bcc6: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
800bcca: f7f4 ff6d bl 8000ba8 <HAL_Delay>
|
|
/* Reset TX Done or timeout flags */
|
|
RadioTxDone_flag = 0;
|
|
800bcce: 4b16 ldr r3, [pc, #88] @ (800bd28 <Per_Process+0xc0>)
|
|
800bcd0: 2200 movs r2, #0
|
|
800bcd2: 601a str r2, [r3, #0]
|
|
RadioTxTimeout_flag = 0;
|
|
800bcd4: 4b16 ldr r3, [pc, #88] @ (800bd30 <Per_Process+0xc8>)
|
|
800bcd6: 2200 movs r2, #0
|
|
800bcd8: 601a str r2, [r3, #0]
|
|
RadioError_flag = 0;
|
|
800bcda: 4b17 ldr r3, [pc, #92] @ (800bd38 <Per_Process+0xd0>)
|
|
800bcdc: 2200 movs r2, #0
|
|
800bcde: 601a str r2, [r3, #0]
|
|
|
|
tx_payload_generator();
|
|
800bce0: f000 f8ae bl 800be40 <tx_payload_generator>
|
|
#if (APP_LONG_PACKET==0)
|
|
Radio.Send(data_buffer, payloadLen);
|
|
800bce4: 4b16 ldr r3, [pc, #88] @ (800bd40 <Per_Process+0xd8>)
|
|
800bce6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800bce8: 4a16 ldr r2, [pc, #88] @ (800bd44 <Per_Process+0xdc>)
|
|
800bcea: 8812 ldrh r2, [r2, #0]
|
|
800bcec: b292 uxth r2, r2
|
|
800bcee: b2d2 uxtb r2, r2
|
|
800bcf0: 4611 mov r1, r2
|
|
800bcf2: 4815 ldr r0, [pc, #84] @ (800bd48 <Per_Process+0xe0>)
|
|
800bcf4: 4798 blx r3
|
|
if (0UL != Radio.TransmitLongPacket(payloadLen, TX_TIMEOUT_VALUE, TxLongPacketGetNextChunk))
|
|
{
|
|
while (1);
|
|
}
|
|
#endif /* APP_LONG_PACKET */
|
|
APP_TPRINTF("Tx %d \r\n", packetCnt);
|
|
800bcf6: 4b09 ldr r3, [pc, #36] @ (800bd1c <Per_Process+0xb4>)
|
|
800bcf8: 681b ldr r3, [r3, #0]
|
|
800bcfa: 9300 str r3, [sp, #0]
|
|
800bcfc: 4b13 ldr r3, [pc, #76] @ (800bd4c <Per_Process+0xe4>)
|
|
800bcfe: 2201 movs r2, #1
|
|
800bd00: 2100 movs r1, #0
|
|
800bd02: 2000 movs r0, #0
|
|
800bd04: f001 f93e bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); /* LED_BLUE */
|
|
800bd08: 2201 movs r2, #1
|
|
800bd0a: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
800bd0e: 4805 ldr r0, [pc, #20] @ (800bd24 <Per_Process+0xbc>)
|
|
800bd10: f7f6 fd18 bl 8002744 <HAL_GPIO_WritePin>
|
|
#endif /* TEST_MODE */
|
|
}
|
|
800bd14: bf00 nop
|
|
800bd16: 46bd mov sp, r7
|
|
800bd18: bd80 pop {r7, pc}
|
|
800bd1a: bf00 nop
|
|
800bd1c: 200009a0 .word 0x200009a0
|
|
800bd20: 2000099c .word 0x2000099c
|
|
800bd24: 48000400 .word 0x48000400
|
|
800bd28: 2000059c .word 0x2000059c
|
|
800bd2c: 0800d7dc .word 0x0800d7dc
|
|
800bd30: 200005a0 .word 0x200005a0
|
|
800bd34: 0800d7e8 .word 0x0800d7e8
|
|
800bd38: 200005ac .word 0x200005ac
|
|
800bd3c: 0800d7f8 .word 0x0800d7f8
|
|
800bd40: 0800d9e0 .word 0x0800d9e0
|
|
800bd44: 2000000a .word 0x2000000a
|
|
800bd48: 200005b4 .word 0x200005b4
|
|
800bd4c: 0800d804 .word 0x0800d804
|
|
|
|
0800bd50 <HAL_GPIO_EXTI_Callback>:
|
|
|
|
#if (TEST_MODE == RADIO_TX)
|
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|
{
|
|
800bd50: b580 push {r7, lr}
|
|
800bd52: b084 sub sp, #16
|
|
800bd54: af02 add r7, sp, #8
|
|
800bd56: 4603 mov r3, r0
|
|
800bd58: 80fb strh r3, [r7, #6]
|
|
switch (GPIO_Pin)
|
|
800bd5a: 88fb ldrh r3, [r7, #6]
|
|
800bd5c: 2b40 cmp r3, #64 @ 0x40
|
|
800bd5e: d03e beq.n 800bdde <HAL_GPIO_EXTI_Callback+0x8e>
|
|
800bd60: 2b40 cmp r3, #64 @ 0x40
|
|
800bd62: dc5b bgt.n 800be1c <HAL_GPIO_EXTI_Callback+0xcc>
|
|
800bd64: 2b01 cmp r3, #1
|
|
800bd66: d002 beq.n 800bd6e <HAL_GPIO_EXTI_Callback+0x1e>
|
|
800bd68: 2b02 cmp r3, #2
|
|
800bd6a: d01c beq.n 800bda6 <HAL_GPIO_EXTI_Callback+0x56>
|
|
{
|
|
APP_TPRINTF("Payload Inc mode\r\n");
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
800bd6c: e056 b.n 800be1c <HAL_GPIO_EXTI_Callback+0xcc>
|
|
payloadLen += 16;
|
|
800bd6e: 4b2e ldr r3, [pc, #184] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bd70: 881b ldrh r3, [r3, #0]
|
|
800bd72: b29b uxth r3, r3
|
|
800bd74: 3310 adds r3, #16
|
|
800bd76: b29a uxth r2, r3
|
|
800bd78: 4b2b ldr r3, [pc, #172] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bd7a: 801a strh r2, [r3, #0]
|
|
if (payloadLen > payloadLenMax)
|
|
800bd7c: 4b2a ldr r3, [pc, #168] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bd7e: 881b ldrh r3, [r3, #0]
|
|
800bd80: b29a uxth r2, r3
|
|
800bd82: 4b2a ldr r3, [pc, #168] @ (800be2c <HAL_GPIO_EXTI_Callback+0xdc>)
|
|
800bd84: 881b ldrh r3, [r3, #0]
|
|
800bd86: 429a cmp r2, r3
|
|
800bd88: d902 bls.n 800bd90 <HAL_GPIO_EXTI_Callback+0x40>
|
|
payloadLen = 16;
|
|
800bd8a: 4b27 ldr r3, [pc, #156] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bd8c: 2210 movs r2, #16
|
|
800bd8e: 801a strh r2, [r3, #0]
|
|
APP_TPRINTF("New Tx Payload Length= %d\r\n", payloadLen);
|
|
800bd90: 4b25 ldr r3, [pc, #148] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bd92: 881b ldrh r3, [r3, #0]
|
|
800bd94: b29b uxth r3, r3
|
|
800bd96: 9300 str r3, [sp, #0]
|
|
800bd98: 4b25 ldr r3, [pc, #148] @ (800be30 <HAL_GPIO_EXTI_Callback+0xe0>)
|
|
800bd9a: 2201 movs r2, #1
|
|
800bd9c: 2100 movs r1, #0
|
|
800bd9e: 2000 movs r0, #0
|
|
800bda0: f001 f8f0 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
800bda4: e03b b.n 800be1e <HAL_GPIO_EXTI_Callback+0xce>
|
|
payloadLen += 1;
|
|
800bda6: 4b20 ldr r3, [pc, #128] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bda8: 881b ldrh r3, [r3, #0]
|
|
800bdaa: b29b uxth r3, r3
|
|
800bdac: 3301 adds r3, #1
|
|
800bdae: b29a uxth r2, r3
|
|
800bdb0: 4b1d ldr r3, [pc, #116] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bdb2: 801a strh r2, [r3, #0]
|
|
if (payloadLen > payloadLenMax)
|
|
800bdb4: 4b1c ldr r3, [pc, #112] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bdb6: 881b ldrh r3, [r3, #0]
|
|
800bdb8: b29a uxth r2, r3
|
|
800bdba: 4b1c ldr r3, [pc, #112] @ (800be2c <HAL_GPIO_EXTI_Callback+0xdc>)
|
|
800bdbc: 881b ldrh r3, [r3, #0]
|
|
800bdbe: 429a cmp r2, r3
|
|
800bdc0: d902 bls.n 800bdc8 <HAL_GPIO_EXTI_Callback+0x78>
|
|
payloadLen = 1;
|
|
800bdc2: 4b19 ldr r3, [pc, #100] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bdc4: 2201 movs r2, #1
|
|
800bdc6: 801a strh r2, [r3, #0]
|
|
APP_TPRINTF("New Tx Payload Length= %d\r\n", payloadLen);
|
|
800bdc8: 4b17 ldr r3, [pc, #92] @ (800be28 <HAL_GPIO_EXTI_Callback+0xd8>)
|
|
800bdca: 881b ldrh r3, [r3, #0]
|
|
800bdcc: b29b uxth r3, r3
|
|
800bdce: 9300 str r3, [sp, #0]
|
|
800bdd0: 4b17 ldr r3, [pc, #92] @ (800be30 <HAL_GPIO_EXTI_Callback+0xe0>)
|
|
800bdd2: 2201 movs r2, #1
|
|
800bdd4: 2100 movs r1, #0
|
|
800bdd6: 2000 movs r0, #0
|
|
800bdd8: f001 f8d4 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
800bddc: e01f b.n 800be1e <HAL_GPIO_EXTI_Callback+0xce>
|
|
TxPayloadMode = (TxPayloadMode + 1) % 2;
|
|
800bdde: 4b15 ldr r3, [pc, #84] @ (800be34 <HAL_GPIO_EXTI_Callback+0xe4>)
|
|
800bde0: 781b ldrb r3, [r3, #0]
|
|
800bde2: b2db uxtb r3, r3
|
|
800bde4: 3301 adds r3, #1
|
|
800bde6: 2b00 cmp r3, #0
|
|
800bde8: f003 0301 and.w r3, r3, #1
|
|
800bdec: bfb8 it lt
|
|
800bdee: 425b neglt r3, r3
|
|
800bdf0: b2da uxtb r2, r3
|
|
800bdf2: 4b10 ldr r3, [pc, #64] @ (800be34 <HAL_GPIO_EXTI_Callback+0xe4>)
|
|
800bdf4: 701a strb r2, [r3, #0]
|
|
if (TxPayloadMode == 1)
|
|
800bdf6: 4b0f ldr r3, [pc, #60] @ (800be34 <HAL_GPIO_EXTI_Callback+0xe4>)
|
|
800bdf8: 781b ldrb r3, [r3, #0]
|
|
800bdfa: b2db uxtb r3, r3
|
|
800bdfc: 2b01 cmp r3, #1
|
|
800bdfe: d106 bne.n 800be0e <HAL_GPIO_EXTI_Callback+0xbe>
|
|
APP_TPRINTF("Payload PRBS9 mode\r\n");
|
|
800be00: 4b0d ldr r3, [pc, #52] @ (800be38 <HAL_GPIO_EXTI_Callback+0xe8>)
|
|
800be02: 2201 movs r2, #1
|
|
800be04: 2100 movs r1, #0
|
|
800be06: 2000 movs r0, #0
|
|
800be08: f001 f8bc bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
800be0c: e007 b.n 800be1e <HAL_GPIO_EXTI_Callback+0xce>
|
|
APP_TPRINTF("Payload Inc mode\r\n");
|
|
800be0e: 4b0b ldr r3, [pc, #44] @ (800be3c <HAL_GPIO_EXTI_Callback+0xec>)
|
|
800be10: 2201 movs r2, #1
|
|
800be12: 2100 movs r1, #0
|
|
800be14: 2000 movs r0, #0
|
|
800be16: f001 f8b5 bl 800cf84 <UTIL_ADV_TRACE_COND_FSend>
|
|
break;
|
|
800be1a: e000 b.n 800be1e <HAL_GPIO_EXTI_Callback+0xce>
|
|
break;
|
|
800be1c: bf00 nop
|
|
}
|
|
}
|
|
800be1e: bf00 nop
|
|
800be20: 3708 adds r7, #8
|
|
800be22: 46bd mov sp, r7
|
|
800be24: bd80 pop {r7, pc}
|
|
800be26: bf00 nop
|
|
800be28: 2000000a .word 0x2000000a
|
|
800be2c: 2000000c .word 0x2000000c
|
|
800be30: 0800d810 .word 0x0800d810
|
|
800be34: 200009a4 .word 0x200009a4
|
|
800be38: 0800d82c .word 0x0800d82c
|
|
800be3c: 0800d844 .word 0x0800d844
|
|
|
|
0800be40 <tx_payload_generator>:
|
|
|
|
static int32_t tx_payload_generator(void)
|
|
{
|
|
800be40: b480 push {r7}
|
|
800be42: b087 sub sp, #28
|
|
800be44: af00 add r7, sp, #0
|
|
if (TxPayloadMode == 1)
|
|
800be46: 4b37 ldr r3, [pc, #220] @ (800bf24 <tx_payload_generator+0xe4>)
|
|
800be48: 781b ldrb r3, [r3, #0]
|
|
800be4a: b2db uxtb r3, r3
|
|
800be4c: 2b01 cmp r3, #1
|
|
800be4e: d14e bne.n 800beee <tx_payload_generator+0xae>
|
|
{
|
|
uint16_t prbs9_val = PRBS9_INIT;
|
|
800be50: 2302 movs r3, #2
|
|
800be52: 82fb strh r3, [r7, #22]
|
|
for (int32_t i = 0; i < payloadLen; i++)
|
|
800be54: 2300 movs r3, #0
|
|
800be56: 613b str r3, [r7, #16]
|
|
800be58: e007 b.n 800be6a <tx_payload_generator+0x2a>
|
|
{
|
|
data_buffer[i] = 0;
|
|
800be5a: 4a33 ldr r2, [pc, #204] @ (800bf28 <tx_payload_generator+0xe8>)
|
|
800be5c: 693b ldr r3, [r7, #16]
|
|
800be5e: 4413 add r3, r2
|
|
800be60: 2200 movs r2, #0
|
|
800be62: 701a strb r2, [r3, #0]
|
|
for (int32_t i = 0; i < payloadLen; i++)
|
|
800be64: 693b ldr r3, [r7, #16]
|
|
800be66: 3301 adds r3, #1
|
|
800be68: 613b str r3, [r7, #16]
|
|
800be6a: 4b30 ldr r3, [pc, #192] @ (800bf2c <tx_payload_generator+0xec>)
|
|
800be6c: 881b ldrh r3, [r3, #0]
|
|
800be6e: b29b uxth r3, r3
|
|
800be70: 461a mov r2, r3
|
|
800be72: 693b ldr r3, [r7, #16]
|
|
800be74: 4293 cmp r3, r2
|
|
800be76: dbf0 blt.n 800be5a <tx_payload_generator+0x1a>
|
|
}
|
|
for (int32_t i = 0; i < payloadLen * 8; i++)
|
|
800be78: 2300 movs r3, #0
|
|
800be7a: 60fb str r3, [r7, #12]
|
|
800be7c: e02f b.n 800bede <tx_payload_generator+0x9e>
|
|
{
|
|
/*fill buffer with prbs9 sequence*/
|
|
int32_t newbit = (((prbs9_val >> 8) ^ (prbs9_val >> 4)) & 1);
|
|
800be7e: 8afb ldrh r3, [r7, #22]
|
|
800be80: 0a1b lsrs r3, r3, #8
|
|
800be82: b29a uxth r2, r3
|
|
800be84: 8afb ldrh r3, [r7, #22]
|
|
800be86: 091b lsrs r3, r3, #4
|
|
800be88: b29b uxth r3, r3
|
|
800be8a: 4053 eors r3, r2
|
|
800be8c: b29b uxth r3, r3
|
|
800be8e: f003 0301 and.w r3, r3, #1
|
|
800be92: 607b str r3, [r7, #4]
|
|
prbs9_val = ((prbs9_val << 1) | newbit) & 0x01ff;
|
|
800be94: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800be98: 005b lsls r3, r3, #1
|
|
800be9a: b21a sxth r2, r3
|
|
800be9c: 687b ldr r3, [r7, #4]
|
|
800be9e: b21b sxth r3, r3
|
|
800bea0: 4313 orrs r3, r2
|
|
800bea2: b21b sxth r3, r3
|
|
800bea4: b29b uxth r3, r3
|
|
800bea6: f3c3 0308 ubfx r3, r3, #0, #9
|
|
800beaa: 82fb strh r3, [r7, #22]
|
|
data_buffer[i / 8] |= ((prbs9_val & 0x1) << (i % 8));
|
|
800beac: 68fb ldr r3, [r7, #12]
|
|
800beae: 2b00 cmp r3, #0
|
|
800beb0: da00 bge.n 800beb4 <tx_payload_generator+0x74>
|
|
800beb2: 3307 adds r3, #7
|
|
800beb4: 10db asrs r3, r3, #3
|
|
800beb6: 4a1c ldr r2, [pc, #112] @ (800bf28 <tx_payload_generator+0xe8>)
|
|
800beb8: 5cd2 ldrb r2, [r2, r3]
|
|
800beba: b251 sxtb r1, r2
|
|
800bebc: 8afa ldrh r2, [r7, #22]
|
|
800bebe: f002 0001 and.w r0, r2, #1
|
|
800bec2: 68fa ldr r2, [r7, #12]
|
|
800bec4: f002 0207 and.w r2, r2, #7
|
|
800bec8: fa00 f202 lsl.w r2, r0, r2
|
|
800becc: b252 sxtb r2, r2
|
|
800bece: 430a orrs r2, r1
|
|
800bed0: b252 sxtb r2, r2
|
|
800bed2: b2d1 uxtb r1, r2
|
|
800bed4: 4a14 ldr r2, [pc, #80] @ (800bf28 <tx_payload_generator+0xe8>)
|
|
800bed6: 54d1 strb r1, [r2, r3]
|
|
for (int32_t i = 0; i < payloadLen * 8; i++)
|
|
800bed8: 68fb ldr r3, [r7, #12]
|
|
800beda: 3301 adds r3, #1
|
|
800bedc: 60fb str r3, [r7, #12]
|
|
800bede: 4b13 ldr r3, [pc, #76] @ (800bf2c <tx_payload_generator+0xec>)
|
|
800bee0: 881b ldrh r3, [r3, #0]
|
|
800bee2: b29b uxth r3, r3
|
|
800bee4: 00db lsls r3, r3, #3
|
|
800bee6: 68fa ldr r2, [r7, #12]
|
|
800bee8: 429a cmp r2, r3
|
|
800beea: dbc8 blt.n 800be7e <tx_payload_generator+0x3e>
|
|
800beec: e013 b.n 800bf16 <tx_payload_generator+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
for (int32_t i = 0; i < payloadLen; i++)
|
|
800beee: 2300 movs r3, #0
|
|
800bef0: 60bb str r3, [r7, #8]
|
|
800bef2: e009 b.n 800bf08 <tx_payload_generator+0xc8>
|
|
{
|
|
data_buffer[i] = i;
|
|
800bef4: 68bb ldr r3, [r7, #8]
|
|
800bef6: b2d9 uxtb r1, r3
|
|
800bef8: 4a0b ldr r2, [pc, #44] @ (800bf28 <tx_payload_generator+0xe8>)
|
|
800befa: 68bb ldr r3, [r7, #8]
|
|
800befc: 4413 add r3, r2
|
|
800befe: 460a mov r2, r1
|
|
800bf00: 701a strb r2, [r3, #0]
|
|
for (int32_t i = 0; i < payloadLen; i++)
|
|
800bf02: 68bb ldr r3, [r7, #8]
|
|
800bf04: 3301 adds r3, #1
|
|
800bf06: 60bb str r3, [r7, #8]
|
|
800bf08: 4b08 ldr r3, [pc, #32] @ (800bf2c <tx_payload_generator+0xec>)
|
|
800bf0a: 881b ldrh r3, [r3, #0]
|
|
800bf0c: b29b uxth r3, r3
|
|
800bf0e: 461a mov r2, r3
|
|
800bf10: 68bb ldr r3, [r7, #8]
|
|
800bf12: 4293 cmp r3, r2
|
|
800bf14: dbee blt.n 800bef4 <tx_payload_generator+0xb4>
|
|
}
|
|
}
|
|
return 0;
|
|
800bf16: 2300 movs r3, #0
|
|
}
|
|
800bf18: 4618 mov r0, r3
|
|
800bf1a: 371c adds r7, #28
|
|
800bf1c: 46bd mov sp, r7
|
|
800bf1e: bc80 pop {r7}
|
|
800bf20: 4770 bx lr
|
|
800bf22: bf00 nop
|
|
800bf24: 200009a4 .word 0x200009a4
|
|
800bf28: 200005b4 .word 0x200005b4
|
|
800bf2c: 2000000a .word 0x2000000a
|
|
|
|
0800bf30 <RBI_Init>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
int32_t RBI_Init(void)
|
|
{
|
|
800bf30: b580 push {r7, lr}
|
|
800bf32: af00 add r7, sp, #0
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_Init();
|
|
800bf34: f7f5 fb76 bl 8001624 <BSP_RADIO_Init>
|
|
800bf38: 4603 mov r3, r0
|
|
/* USER CODE BEGIN RBI_Init_2 */
|
|
#warning user to provide its board code or to call his board driver functions
|
|
/* USER CODE END RBI_Init_2 */
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf3a: 4618 mov r0, r3
|
|
800bf3c: bd80 pop {r7, pc}
|
|
|
|
0800bf3e <RBI_ConfigRFSwitch>:
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
|
|
int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config)
|
|
{
|
|
800bf3e: b580 push {r7, lr}
|
|
800bf40: b082 sub sp, #8
|
|
800bf42: af00 add r7, sp, #0
|
|
800bf44: 4603 mov r3, r0
|
|
800bf46: 71fb strb r3, [r7, #7]
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config);
|
|
800bf48: 79fb ldrb r3, [r7, #7]
|
|
800bf4a: 4618 mov r0, r3
|
|
800bf4c: f7f5 fba8 bl 80016a0 <BSP_RADIO_ConfigRFSwitch>
|
|
800bf50: 4603 mov r3, r0
|
|
/* USER CODE BEGIN RBI_ConfigRFSwitch_2 */
|
|
#warning user to provide its board code or to call his board driver functions
|
|
/* USER CODE END RBI_ConfigRFSwitch_2 */
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf52: 4618 mov r0, r3
|
|
800bf54: 3708 adds r7, #8
|
|
800bf56: 46bd mov sp, r7
|
|
800bf58: bd80 pop {r7, pc}
|
|
|
|
0800bf5a <RBI_GetTxConfig>:
|
|
|
|
int32_t RBI_GetTxConfig(void)
|
|
{
|
|
800bf5a: b580 push {r7, lr}
|
|
800bf5c: af00 add r7, sp, #0
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_GetTxConfig();
|
|
800bf5e: f7f5 fbfb bl 8001758 <BSP_RADIO_GetTxConfig>
|
|
800bf62: 4603 mov r3, r0
|
|
/* USER CODE BEGIN RBI_GetTxConfig_2 */
|
|
#warning user to provide its board code or to call his board driver functions
|
|
/* USER CODE END RBI_GetTxConfig_2 */
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf64: 4618 mov r0, r3
|
|
800bf66: bd80 pop {r7, pc}
|
|
|
|
0800bf68 <RBI_IsTCXO>:
|
|
|
|
int32_t RBI_IsTCXO(void)
|
|
{
|
|
800bf68: b580 push {r7, lr}
|
|
800bf6a: af00 add r7, sp, #0
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_IsTCXO();
|
|
800bf6c: f7f5 fbfb bl 8001766 <BSP_RADIO_IsTCXO>
|
|
800bf70: 4603 mov r3, r0
|
|
/* USER CODE BEGIN RBI_IsTCXO_2 */
|
|
#warning user to provide its board code or to call his board driver functions
|
|
/* USER CODE END RBI_IsTCXO_2 */
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf72: 4618 mov r0, r3
|
|
800bf74: bd80 pop {r7, pc}
|
|
|
|
0800bf76 <RBI_IsDCDC>:
|
|
|
|
int32_t RBI_IsDCDC(void)
|
|
{
|
|
800bf76: b580 push {r7, lr}
|
|
800bf78: af00 add r7, sp, #0
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_IsDCDC();
|
|
800bf7a: f7f5 fbfb bl 8001774 <BSP_RADIO_IsDCDC>
|
|
800bf7e: 4603 mov r3, r0
|
|
/* USER CODE BEGIN RBI_IsDCDC_2 */
|
|
#warning user to provide its board code or to call his board driver functions
|
|
/* USER CODE END RBI_IsDCDC_2 */
|
|
return retcode;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf80: 4618 mov r0, r3
|
|
800bf82: bd80 pop {r7, pc}
|
|
|
|
0800bf84 <RBI_GetRFOMaxPowerConfig>:
|
|
|
|
int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config)
|
|
{
|
|
800bf84: b580 push {r7, lr}
|
|
800bf86: b082 sub sp, #8
|
|
800bf88: af00 add r7, sp, #0
|
|
800bf8a: 4603 mov r3, r0
|
|
800bf8c: 71fb strb r3, [r7, #7]
|
|
* 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending:
|
|
* on board RF switch configuration (pin control, number of port etc)
|
|
* on TCXO configuration
|
|
* on DC/DC configuration
|
|
* on maximum output power that the board can deliver*/
|
|
return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config);
|
|
800bf8e: 79fb ldrb r3, [r7, #7]
|
|
800bf90: 4618 mov r0, r3
|
|
800bf92: f7f5 fbf6 bl 8001782 <BSP_RADIO_GetRFOMaxPowerConfig>
|
|
800bf96: 4603 mov r3, r0
|
|
ret = 22; /*dBm*/
|
|
}
|
|
/* USER CODE END RBI_GetRFOMaxPowerConfig_2 */
|
|
return ret;
|
|
#endif /* USE_BSP_DRIVER */
|
|
}
|
|
800bf98: 4618 mov r0, r3
|
|
800bf9a: 3708 adds r7, #8
|
|
800bf9c: 46bd mov sp, r7
|
|
800bf9e: bd80 pop {r7, pc}
|
|
|
|
0800bfa0 <UTIL_LPM_Init>:
|
|
|
|
/** @addtogroup TINY_LPM_Exported_function
|
|
* @{
|
|
*/
|
|
void UTIL_LPM_Init( void )
|
|
{
|
|
800bfa0: b480 push {r7}
|
|
800bfa2: af00 add r7, sp, #0
|
|
StopModeDisable = UTIL_LPM_NO_BIT_SET;
|
|
800bfa4: 4b04 ldr r3, [pc, #16] @ (800bfb8 <UTIL_LPM_Init+0x18>)
|
|
800bfa6: 2200 movs r2, #0
|
|
800bfa8: 601a str r2, [r3, #0]
|
|
OffModeDisable = UTIL_LPM_NO_BIT_SET;
|
|
800bfaa: 4b04 ldr r3, [pc, #16] @ (800bfbc <UTIL_LPM_Init+0x1c>)
|
|
800bfac: 2200 movs r2, #0
|
|
800bfae: 601a str r2, [r3, #0]
|
|
UTIL_LPM_INIT_CRITICAL_SECTION( );
|
|
}
|
|
800bfb0: bf00 nop
|
|
800bfb2: 46bd mov sp, r7
|
|
800bfb4: bc80 pop {r7}
|
|
800bfb6: 4770 bx lr
|
|
800bfb8: 200009a8 .word 0x200009a8
|
|
800bfbc: 200009ac .word 0x200009ac
|
|
|
|
0800bfc0 <UTIL_LPM_SetStopMode>:
|
|
void UTIL_LPM_DeInit( void )
|
|
{
|
|
}
|
|
|
|
void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state )
|
|
{
|
|
800bfc0: b480 push {r7}
|
|
800bfc2: b087 sub sp, #28
|
|
800bfc4: af00 add r7, sp, #0
|
|
800bfc6: 6078 str r0, [r7, #4]
|
|
800bfc8: 460b mov r3, r1
|
|
800bfca: 70fb strb r3, [r7, #3]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800bfcc: f3ef 8310 mrs r3, PRIMASK
|
|
800bfd0: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800bfd2: 693b ldr r3, [r7, #16]
|
|
UTIL_LPM_ENTER_CRITICAL_SECTION( );
|
|
800bfd4: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800bfd6: b672 cpsid i
|
|
}
|
|
800bfd8: bf00 nop
|
|
|
|
switch( state )
|
|
800bfda: 78fb ldrb r3, [r7, #3]
|
|
800bfdc: 2b00 cmp r3, #0
|
|
800bfde: d008 beq.n 800bff2 <UTIL_LPM_SetStopMode+0x32>
|
|
800bfe0: 2b01 cmp r3, #1
|
|
800bfe2: d10e bne.n 800c002 <UTIL_LPM_SetStopMode+0x42>
|
|
{
|
|
case UTIL_LPM_DISABLE:
|
|
{
|
|
StopModeDisable |= lpm_id_bm;
|
|
800bfe4: 4b0d ldr r3, [pc, #52] @ (800c01c <UTIL_LPM_SetStopMode+0x5c>)
|
|
800bfe6: 681a ldr r2, [r3, #0]
|
|
800bfe8: 687b ldr r3, [r7, #4]
|
|
800bfea: 4313 orrs r3, r2
|
|
800bfec: 4a0b ldr r2, [pc, #44] @ (800c01c <UTIL_LPM_SetStopMode+0x5c>)
|
|
800bfee: 6013 str r3, [r2, #0]
|
|
break;
|
|
800bff0: e008 b.n 800c004 <UTIL_LPM_SetStopMode+0x44>
|
|
}
|
|
case UTIL_LPM_ENABLE:
|
|
{
|
|
StopModeDisable &= ( ~lpm_id_bm );
|
|
800bff2: 687b ldr r3, [r7, #4]
|
|
800bff4: 43da mvns r2, r3
|
|
800bff6: 4b09 ldr r3, [pc, #36] @ (800c01c <UTIL_LPM_SetStopMode+0x5c>)
|
|
800bff8: 681b ldr r3, [r3, #0]
|
|
800bffa: 4013 ands r3, r2
|
|
800bffc: 4a07 ldr r2, [pc, #28] @ (800c01c <UTIL_LPM_SetStopMode+0x5c>)
|
|
800bffe: 6013 str r3, [r2, #0]
|
|
break;
|
|
800c000: e000 b.n 800c004 <UTIL_LPM_SetStopMode+0x44>
|
|
}
|
|
default :
|
|
{
|
|
break;
|
|
800c002: bf00 nop
|
|
800c004: 697b ldr r3, [r7, #20]
|
|
800c006: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c008: 68fb ldr r3, [r7, #12]
|
|
800c00a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c00e: bf00 nop
|
|
}
|
|
}
|
|
|
|
UTIL_LPM_EXIT_CRITICAL_SECTION( );
|
|
}
|
|
800c010: bf00 nop
|
|
800c012: 371c adds r7, #28
|
|
800c014: 46bd mov sp, r7
|
|
800c016: bc80 pop {r7}
|
|
800c018: 4770 bx lr
|
|
800c01a: bf00 nop
|
|
800c01c: 200009a8 .word 0x200009a8
|
|
|
|
0800c020 <UTIL_LPM_SetOffMode>:
|
|
|
|
void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state )
|
|
{
|
|
800c020: b480 push {r7}
|
|
800c022: b087 sub sp, #28
|
|
800c024: af00 add r7, sp, #0
|
|
800c026: 6078 str r0, [r7, #4]
|
|
800c028: 460b mov r3, r1
|
|
800c02a: 70fb strb r3, [r7, #3]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c02c: f3ef 8310 mrs r3, PRIMASK
|
|
800c030: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800c032: 693b ldr r3, [r7, #16]
|
|
UTIL_LPM_ENTER_CRITICAL_SECTION( );
|
|
800c034: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c036: b672 cpsid i
|
|
}
|
|
800c038: bf00 nop
|
|
|
|
switch(state)
|
|
800c03a: 78fb ldrb r3, [r7, #3]
|
|
800c03c: 2b00 cmp r3, #0
|
|
800c03e: d008 beq.n 800c052 <UTIL_LPM_SetOffMode+0x32>
|
|
800c040: 2b01 cmp r3, #1
|
|
800c042: d10e bne.n 800c062 <UTIL_LPM_SetOffMode+0x42>
|
|
{
|
|
case UTIL_LPM_DISABLE:
|
|
{
|
|
OffModeDisable |= lpm_id_bm;
|
|
800c044: 4b0d ldr r3, [pc, #52] @ (800c07c <UTIL_LPM_SetOffMode+0x5c>)
|
|
800c046: 681a ldr r2, [r3, #0]
|
|
800c048: 687b ldr r3, [r7, #4]
|
|
800c04a: 4313 orrs r3, r2
|
|
800c04c: 4a0b ldr r2, [pc, #44] @ (800c07c <UTIL_LPM_SetOffMode+0x5c>)
|
|
800c04e: 6013 str r3, [r2, #0]
|
|
break;
|
|
800c050: e008 b.n 800c064 <UTIL_LPM_SetOffMode+0x44>
|
|
}
|
|
case UTIL_LPM_ENABLE:
|
|
{
|
|
OffModeDisable &= ( ~lpm_id_bm );
|
|
800c052: 687b ldr r3, [r7, #4]
|
|
800c054: 43da mvns r2, r3
|
|
800c056: 4b09 ldr r3, [pc, #36] @ (800c07c <UTIL_LPM_SetOffMode+0x5c>)
|
|
800c058: 681b ldr r3, [r3, #0]
|
|
800c05a: 4013 ands r3, r2
|
|
800c05c: 4a07 ldr r2, [pc, #28] @ (800c07c <UTIL_LPM_SetOffMode+0x5c>)
|
|
800c05e: 6013 str r3, [r2, #0]
|
|
break;
|
|
800c060: e000 b.n 800c064 <UTIL_LPM_SetOffMode+0x44>
|
|
}
|
|
default :
|
|
{
|
|
break;
|
|
800c062: bf00 nop
|
|
800c064: 697b ldr r3, [r7, #20]
|
|
800c066: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c068: 68fb ldr r3, [r7, #12]
|
|
800c06a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c06e: bf00 nop
|
|
}
|
|
}
|
|
|
|
UTIL_LPM_EXIT_CRITICAL_SECTION( );
|
|
}
|
|
800c070: bf00 nop
|
|
800c072: 371c adds r7, #28
|
|
800c074: 46bd mov sp, r7
|
|
800c076: bc80 pop {r7}
|
|
800c078: 4770 bx lr
|
|
800c07a: bf00 nop
|
|
800c07c: 200009ac .word 0x200009ac
|
|
|
|
0800c080 <UTIL_LPM_EnterLowPower>:
|
|
|
|
return mode_selected;
|
|
}
|
|
|
|
void UTIL_LPM_EnterLowPower( void )
|
|
{
|
|
800c080: b580 push {r7, lr}
|
|
800c082: b084 sub sp, #16
|
|
800c084: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c086: f3ef 8310 mrs r3, PRIMASK
|
|
800c08a: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
800c08c: 68bb ldr r3, [r7, #8]
|
|
UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( );
|
|
800c08e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c090: b672 cpsid i
|
|
}
|
|
800c092: bf00 nop
|
|
|
|
if( StopModeDisable != UTIL_LPM_NO_BIT_SET )
|
|
800c094: 4b12 ldr r3, [pc, #72] @ (800c0e0 <UTIL_LPM_EnterLowPower+0x60>)
|
|
800c096: 681b ldr r3, [r3, #0]
|
|
800c098: 2b00 cmp r3, #0
|
|
800c09a: d006 beq.n 800c0aa <UTIL_LPM_EnterLowPower+0x2a>
|
|
{
|
|
/**
|
|
* At least one user disallows Stop Mode
|
|
* SLEEP mode is required
|
|
*/
|
|
UTIL_PowerDriver.EnterSleepMode( );
|
|
800c09c: 4b11 ldr r3, [pc, #68] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c09e: 681b ldr r3, [r3, #0]
|
|
800c0a0: 4798 blx r3
|
|
UTIL_PowerDriver.ExitSleepMode( );
|
|
800c0a2: 4b10 ldr r3, [pc, #64] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c0a4: 685b ldr r3, [r3, #4]
|
|
800c0a6: 4798 blx r3
|
|
800c0a8: e010 b.n 800c0cc <UTIL_LPM_EnterLowPower+0x4c>
|
|
}
|
|
else
|
|
{
|
|
if( OffModeDisable != UTIL_LPM_NO_BIT_SET )
|
|
800c0aa: 4b0f ldr r3, [pc, #60] @ (800c0e8 <UTIL_LPM_EnterLowPower+0x68>)
|
|
800c0ac: 681b ldr r3, [r3, #0]
|
|
800c0ae: 2b00 cmp r3, #0
|
|
800c0b0: d006 beq.n 800c0c0 <UTIL_LPM_EnterLowPower+0x40>
|
|
{
|
|
/**
|
|
* At least one user disallows Off Mode
|
|
* STOP mode is required
|
|
*/
|
|
UTIL_PowerDriver.EnterStopMode( );
|
|
800c0b2: 4b0c ldr r3, [pc, #48] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c0b4: 689b ldr r3, [r3, #8]
|
|
800c0b6: 4798 blx r3
|
|
UTIL_PowerDriver.ExitStopMode( );
|
|
800c0b8: 4b0a ldr r3, [pc, #40] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c0ba: 68db ldr r3, [r3, #12]
|
|
800c0bc: 4798 blx r3
|
|
800c0be: e005 b.n 800c0cc <UTIL_LPM_EnterLowPower+0x4c>
|
|
else
|
|
{
|
|
/**
|
|
* OFF mode is required
|
|
*/
|
|
UTIL_PowerDriver.EnterOffMode( );
|
|
800c0c0: 4b08 ldr r3, [pc, #32] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c0c2: 691b ldr r3, [r3, #16]
|
|
800c0c4: 4798 blx r3
|
|
UTIL_PowerDriver.ExitOffMode( );
|
|
800c0c6: 4b07 ldr r3, [pc, #28] @ (800c0e4 <UTIL_LPM_EnterLowPower+0x64>)
|
|
800c0c8: 695b ldr r3, [r3, #20]
|
|
800c0ca: 4798 blx r3
|
|
800c0cc: 68fb ldr r3, [r7, #12]
|
|
800c0ce: 607b str r3, [r7, #4]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c0d0: 687b ldr r3, [r7, #4]
|
|
800c0d2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c0d6: bf00 nop
|
|
}
|
|
}
|
|
|
|
UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( );
|
|
}
|
|
800c0d8: bf00 nop
|
|
800c0da: 3710 adds r7, #16
|
|
800c0dc: 46bd mov sp, r7
|
|
800c0de: bd80 pop {r7, pc}
|
|
800c0e0: 200009a8 .word 0x200009a8
|
|
800c0e4: 0800d8b0 .word 0x0800d8b0
|
|
800c0e8: 200009ac .word 0x200009ac
|
|
|
|
0800c0ec <UTIL_MEM_cpy_8>:
|
|
/* Global variables ----------------------------------------------------------*/
|
|
/* Private function prototypes -----------------------------------------------*/
|
|
/* Functions Definition ------------------------------------------------------*/
|
|
|
|
void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size )
|
|
{
|
|
800c0ec: b480 push {r7}
|
|
800c0ee: b087 sub sp, #28
|
|
800c0f0: af00 add r7, sp, #0
|
|
800c0f2: 60f8 str r0, [r7, #12]
|
|
800c0f4: 60b9 str r1, [r7, #8]
|
|
800c0f6: 4613 mov r3, r2
|
|
800c0f8: 80fb strh r3, [r7, #6]
|
|
uint8_t* dst8= (uint8_t *) dst;
|
|
800c0fa: 68fb ldr r3, [r7, #12]
|
|
800c0fc: 617b str r3, [r7, #20]
|
|
uint8_t* src8= (uint8_t *) src;
|
|
800c0fe: 68bb ldr r3, [r7, #8]
|
|
800c100: 613b str r3, [r7, #16]
|
|
|
|
while( size-- )
|
|
800c102: e007 b.n 800c114 <UTIL_MEM_cpy_8+0x28>
|
|
{
|
|
*dst8++ = *src8++;
|
|
800c104: 693a ldr r2, [r7, #16]
|
|
800c106: 1c53 adds r3, r2, #1
|
|
800c108: 613b str r3, [r7, #16]
|
|
800c10a: 697b ldr r3, [r7, #20]
|
|
800c10c: 1c59 adds r1, r3, #1
|
|
800c10e: 6179 str r1, [r7, #20]
|
|
800c110: 7812 ldrb r2, [r2, #0]
|
|
800c112: 701a strb r2, [r3, #0]
|
|
while( size-- )
|
|
800c114: 88fb ldrh r3, [r7, #6]
|
|
800c116: 1e5a subs r2, r3, #1
|
|
800c118: 80fa strh r2, [r7, #6]
|
|
800c11a: 2b00 cmp r3, #0
|
|
800c11c: d1f2 bne.n 800c104 <UTIL_MEM_cpy_8+0x18>
|
|
}
|
|
}
|
|
800c11e: bf00 nop
|
|
800c120: bf00 nop
|
|
800c122: 371c adds r7, #28
|
|
800c124: 46bd mov sp, r7
|
|
800c126: bc80 pop {r7}
|
|
800c128: 4770 bx lr
|
|
|
|
0800c12a <UTIL_MEM_set_8>:
|
|
*dst8-- = *src8++;
|
|
}
|
|
}
|
|
|
|
void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size )
|
|
{
|
|
800c12a: b480 push {r7}
|
|
800c12c: b085 sub sp, #20
|
|
800c12e: af00 add r7, sp, #0
|
|
800c130: 6078 str r0, [r7, #4]
|
|
800c132: 460b mov r3, r1
|
|
800c134: 70fb strb r3, [r7, #3]
|
|
800c136: 4613 mov r3, r2
|
|
800c138: 803b strh r3, [r7, #0]
|
|
uint8_t* dst8= (uint8_t *) dst;
|
|
800c13a: 687b ldr r3, [r7, #4]
|
|
800c13c: 60fb str r3, [r7, #12]
|
|
while( size-- )
|
|
800c13e: e004 b.n 800c14a <UTIL_MEM_set_8+0x20>
|
|
{
|
|
*dst8++ = value;
|
|
800c140: 68fb ldr r3, [r7, #12]
|
|
800c142: 1c5a adds r2, r3, #1
|
|
800c144: 60fa str r2, [r7, #12]
|
|
800c146: 78fa ldrb r2, [r7, #3]
|
|
800c148: 701a strb r2, [r3, #0]
|
|
while( size-- )
|
|
800c14a: 883b ldrh r3, [r7, #0]
|
|
800c14c: 1e5a subs r2, r3, #1
|
|
800c14e: 803a strh r2, [r7, #0]
|
|
800c150: 2b00 cmp r3, #0
|
|
800c152: d1f5 bne.n 800c140 <UTIL_MEM_set_8+0x16>
|
|
}
|
|
}
|
|
800c154: bf00 nop
|
|
800c156: bf00 nop
|
|
800c158: 3714 adds r7, #20
|
|
800c15a: 46bd mov sp, r7
|
|
800c15c: bc80 pop {r7}
|
|
800c15e: 4770 bx lr
|
|
|
|
0800c160 <SysTimeAdd>:
|
|
* @addtogroup SYSTIME_exported_function
|
|
* @{
|
|
*/
|
|
|
|
SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b )
|
|
{
|
|
800c160: b082 sub sp, #8
|
|
800c162: b480 push {r7}
|
|
800c164: b087 sub sp, #28
|
|
800c166: af00 add r7, sp, #0
|
|
800c168: 60f8 str r0, [r7, #12]
|
|
800c16a: 1d38 adds r0, r7, #4
|
|
800c16c: e880 0006 stmia.w r0, {r1, r2}
|
|
800c170: 627b str r3, [r7, #36] @ 0x24
|
|
SysTime_t c = { .Seconds = 0, .SubSeconds = 0 };
|
|
800c172: 2300 movs r3, #0
|
|
800c174: 613b str r3, [r7, #16]
|
|
800c176: 2300 movs r3, #0
|
|
800c178: 82bb strh r3, [r7, #20]
|
|
|
|
c.Seconds = a.Seconds + b.Seconds;
|
|
800c17a: 687a ldr r2, [r7, #4]
|
|
800c17c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c17e: 4413 add r3, r2
|
|
800c180: 613b str r3, [r7, #16]
|
|
c.SubSeconds = a.SubSeconds + b.SubSeconds;
|
|
800c182: f9b7 3008 ldrsh.w r3, [r7, #8]
|
|
800c186: b29a uxth r2, r3
|
|
800c188: f9b7 3028 ldrsh.w r3, [r7, #40] @ 0x28
|
|
800c18c: b29b uxth r3, r3
|
|
800c18e: 4413 add r3, r2
|
|
800c190: b29b uxth r3, r3
|
|
800c192: b21b sxth r3, r3
|
|
800c194: 82bb strh r3, [r7, #20]
|
|
if( c.SubSeconds >= 1000 )
|
|
800c196: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
800c19a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
800c19e: db0a blt.n 800c1b6 <SysTimeAdd+0x56>
|
|
{
|
|
c.Seconds++;
|
|
800c1a0: 693b ldr r3, [r7, #16]
|
|
800c1a2: 3301 adds r3, #1
|
|
800c1a4: 613b str r3, [r7, #16]
|
|
c.SubSeconds -= 1000;
|
|
800c1a6: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
800c1aa: b29b uxth r3, r3
|
|
800c1ac: f5a3 737a sub.w r3, r3, #1000 @ 0x3e8
|
|
800c1b0: b29b uxth r3, r3
|
|
800c1b2: b21b sxth r3, r3
|
|
800c1b4: 82bb strh r3, [r7, #20]
|
|
}
|
|
return c;
|
|
800c1b6: 68fb ldr r3, [r7, #12]
|
|
800c1b8: 461a mov r2, r3
|
|
800c1ba: f107 0310 add.w r3, r7, #16
|
|
800c1be: e893 0003 ldmia.w r3, {r0, r1}
|
|
800c1c2: e882 0003 stmia.w r2, {r0, r1}
|
|
}
|
|
800c1c6: 68f8 ldr r0, [r7, #12]
|
|
800c1c8: 371c adds r7, #28
|
|
800c1ca: 46bd mov sp, r7
|
|
800c1cc: bc80 pop {r7}
|
|
800c1ce: b002 add sp, #8
|
|
800c1d0: 4770 bx lr
|
|
...
|
|
|
|
0800c1d4 <SysTimeGet>:
|
|
UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds );
|
|
UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds );
|
|
}
|
|
|
|
SysTime_t SysTimeGet( void )
|
|
{
|
|
800c1d4: b580 push {r7, lr}
|
|
800c1d6: b08a sub sp, #40 @ 0x28
|
|
800c1d8: af02 add r7, sp, #8
|
|
800c1da: 6078 str r0, [r7, #4]
|
|
SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 };
|
|
800c1dc: 2300 movs r3, #0
|
|
800c1de: 61bb str r3, [r7, #24]
|
|
800c1e0: 2300 movs r3, #0
|
|
800c1e2: 83bb strh r3, [r7, #28]
|
|
SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 };
|
|
800c1e4: 2300 movs r3, #0
|
|
800c1e6: 613b str r3, [r7, #16]
|
|
800c1e8: 2300 movs r3, #0
|
|
800c1ea: 82bb strh r3, [r7, #20]
|
|
SysTime_t DeltaTime;
|
|
|
|
calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds );
|
|
800c1ec: 4b14 ldr r3, [pc, #80] @ (800c240 <SysTimeGet+0x6c>)
|
|
800c1ee: 691b ldr r3, [r3, #16]
|
|
800c1f0: f107 0218 add.w r2, r7, #24
|
|
800c1f4: 3204 adds r2, #4
|
|
800c1f6: 4610 mov r0, r2
|
|
800c1f8: 4798 blx r3
|
|
800c1fa: 4603 mov r3, r0
|
|
800c1fc: 61bb str r3, [r7, #24]
|
|
|
|
DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds();
|
|
800c1fe: 4b10 ldr r3, [pc, #64] @ (800c240 <SysTimeGet+0x6c>)
|
|
800c200: 68db ldr r3, [r3, #12]
|
|
800c202: 4798 blx r3
|
|
800c204: 4603 mov r3, r0
|
|
800c206: b21b sxth r3, r3
|
|
800c208: 81bb strh r3, [r7, #12]
|
|
DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds();
|
|
800c20a: 4b0d ldr r3, [pc, #52] @ (800c240 <SysTimeGet+0x6c>)
|
|
800c20c: 685b ldr r3, [r3, #4]
|
|
800c20e: 4798 blx r3
|
|
800c210: 4603 mov r3, r0
|
|
800c212: 60bb str r3, [r7, #8]
|
|
|
|
sysTime = SysTimeAdd( DeltaTime, calendarTime );
|
|
800c214: f107 0010 add.w r0, r7, #16
|
|
800c218: 69fb ldr r3, [r7, #28]
|
|
800c21a: 9300 str r3, [sp, #0]
|
|
800c21c: 69bb ldr r3, [r7, #24]
|
|
800c21e: f107 0208 add.w r2, r7, #8
|
|
800c222: ca06 ldmia r2, {r1, r2}
|
|
800c224: f7ff ff9c bl 800c160 <SysTimeAdd>
|
|
|
|
return sysTime;
|
|
800c228: 687b ldr r3, [r7, #4]
|
|
800c22a: 461a mov r2, r3
|
|
800c22c: f107 0310 add.w r3, r7, #16
|
|
800c230: e893 0003 ldmia.w r3, {r0, r1}
|
|
800c234: e882 0003 stmia.w r2, {r0, r1}
|
|
}
|
|
800c238: 6878 ldr r0, [r7, #4]
|
|
800c23a: 3720 adds r7, #32
|
|
800c23c: 46bd mov sp, r7
|
|
800c23e: bd80 pop {r7, pc}
|
|
800c240: 0800d994 .word 0x0800d994
|
|
|
|
0800c244 <ee_skip_atoi>:
|
|
return sc - s;
|
|
}
|
|
#endif
|
|
|
|
static int ee_skip_atoi(const char **s)
|
|
{
|
|
800c244: b480 push {r7}
|
|
800c246: b085 sub sp, #20
|
|
800c248: af00 add r7, sp, #0
|
|
800c24a: 6078 str r0, [r7, #4]
|
|
int i = 0;
|
|
800c24c: 2300 movs r3, #0
|
|
800c24e: 60fb str r3, [r7, #12]
|
|
while (is_digit(**s)) i = i*10 + *((*s)++) - '0';
|
|
800c250: e00e b.n 800c270 <ee_skip_atoi+0x2c>
|
|
800c252: 68fa ldr r2, [r7, #12]
|
|
800c254: 4613 mov r3, r2
|
|
800c256: 009b lsls r3, r3, #2
|
|
800c258: 4413 add r3, r2
|
|
800c25a: 005b lsls r3, r3, #1
|
|
800c25c: 4618 mov r0, r3
|
|
800c25e: 687b ldr r3, [r7, #4]
|
|
800c260: 681b ldr r3, [r3, #0]
|
|
800c262: 1c59 adds r1, r3, #1
|
|
800c264: 687a ldr r2, [r7, #4]
|
|
800c266: 6011 str r1, [r2, #0]
|
|
800c268: 781b ldrb r3, [r3, #0]
|
|
800c26a: 4403 add r3, r0
|
|
800c26c: 3b30 subs r3, #48 @ 0x30
|
|
800c26e: 60fb str r3, [r7, #12]
|
|
800c270: 687b ldr r3, [r7, #4]
|
|
800c272: 681b ldr r3, [r3, #0]
|
|
800c274: 781b ldrb r3, [r3, #0]
|
|
800c276: 2b2f cmp r3, #47 @ 0x2f
|
|
800c278: d904 bls.n 800c284 <ee_skip_atoi+0x40>
|
|
800c27a: 687b ldr r3, [r7, #4]
|
|
800c27c: 681b ldr r3, [r3, #0]
|
|
800c27e: 781b ldrb r3, [r3, #0]
|
|
800c280: 2b39 cmp r3, #57 @ 0x39
|
|
800c282: d9e6 bls.n 800c252 <ee_skip_atoi+0xe>
|
|
return i;
|
|
800c284: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800c286: 4618 mov r0, r3
|
|
800c288: 3714 adds r7, #20
|
|
800c28a: 46bd mov sp, r7
|
|
800c28c: bc80 pop {r7}
|
|
800c28e: 4770 bx lr
|
|
|
|
0800c290 <ee_number>:
|
|
|
|
#define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0)
|
|
|
|
static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type)
|
|
{
|
|
800c290: b480 push {r7}
|
|
800c292: b099 sub sp, #100 @ 0x64
|
|
800c294: af00 add r7, sp, #0
|
|
800c296: 60f8 str r0, [r7, #12]
|
|
800c298: 60b9 str r1, [r7, #8]
|
|
800c29a: 607a str r2, [r7, #4]
|
|
800c29c: 603b str r3, [r7, #0]
|
|
char c;
|
|
char sign, tmp[66];
|
|
char *dig = lower_digits;
|
|
800c29e: 4b71 ldr r3, [pc, #452] @ (800c464 <ee_number+0x1d4>)
|
|
800c2a0: 681b ldr r3, [r3, #0]
|
|
800c2a2: 65bb str r3, [r7, #88] @ 0x58
|
|
int i;
|
|
|
|
if (type & UPPERCASE) dig = upper_digits;
|
|
800c2a4: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800c2a6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800c2aa: 2b00 cmp r3, #0
|
|
800c2ac: d002 beq.n 800c2b4 <ee_number+0x24>
|
|
800c2ae: 4b6e ldr r3, [pc, #440] @ (800c468 <ee_number+0x1d8>)
|
|
800c2b0: 681b ldr r3, [r3, #0]
|
|
800c2b2: 65bb str r3, [r7, #88] @ 0x58
|
|
#ifdef TINY_PRINTF
|
|
#else
|
|
if (type & LEFT) type &= ~ZEROPAD;
|
|
#endif
|
|
if (base < 2 || base > 36) return 0;
|
|
800c2b4: 683b ldr r3, [r7, #0]
|
|
800c2b6: 2b01 cmp r3, #1
|
|
800c2b8: dd02 ble.n 800c2c0 <ee_number+0x30>
|
|
800c2ba: 683b ldr r3, [r7, #0]
|
|
800c2bc: 2b24 cmp r3, #36 @ 0x24
|
|
800c2be: dd01 ble.n 800c2c4 <ee_number+0x34>
|
|
800c2c0: 2300 movs r3, #0
|
|
800c2c2: e0ca b.n 800c45a <ee_number+0x1ca>
|
|
|
|
c = (type & ZEROPAD) ? '0' : ' ';
|
|
800c2c4: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800c2c6: f003 0301 and.w r3, r3, #1
|
|
800c2ca: 2b00 cmp r3, #0
|
|
800c2cc: d001 beq.n 800c2d2 <ee_number+0x42>
|
|
800c2ce: 2330 movs r3, #48 @ 0x30
|
|
800c2d0: e000 b.n 800c2d4 <ee_number+0x44>
|
|
800c2d2: 2320 movs r3, #32
|
|
800c2d4: f887 3053 strb.w r3, [r7, #83] @ 0x53
|
|
sign = 0;
|
|
800c2d8: 2300 movs r3, #0
|
|
800c2da: f887 305f strb.w r3, [r7, #95] @ 0x5f
|
|
if (type & SIGN)
|
|
800c2de: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800c2e0: f003 0302 and.w r3, r3, #2
|
|
800c2e4: 2b00 cmp r3, #0
|
|
800c2e6: d00b beq.n 800c300 <ee_number+0x70>
|
|
{
|
|
if (num < 0)
|
|
800c2e8: 687b ldr r3, [r7, #4]
|
|
800c2ea: 2b00 cmp r3, #0
|
|
800c2ec: da08 bge.n 800c300 <ee_number+0x70>
|
|
{
|
|
sign = '-';
|
|
800c2ee: 232d movs r3, #45 @ 0x2d
|
|
800c2f0: f887 305f strb.w r3, [r7, #95] @ 0x5f
|
|
num = -num;
|
|
800c2f4: 687b ldr r3, [r7, #4]
|
|
800c2f6: 425b negs r3, r3
|
|
800c2f8: 607b str r3, [r7, #4]
|
|
size--;
|
|
800c2fa: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800c2fc: 3b01 subs r3, #1
|
|
800c2fe: 66bb str r3, [r7, #104] @ 0x68
|
|
else if (base == 8)
|
|
size--;
|
|
}
|
|
#endif
|
|
|
|
i = 0;
|
|
800c300: 2300 movs r3, #0
|
|
800c302: 657b str r3, [r7, #84] @ 0x54
|
|
|
|
if (num == 0)
|
|
800c304: 687b ldr r3, [r7, #4]
|
|
800c306: 2b00 cmp r3, #0
|
|
800c308: d11e bne.n 800c348 <ee_number+0xb8>
|
|
tmp[i++] = '0';
|
|
800c30a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800c30c: 1c5a adds r2, r3, #1
|
|
800c30e: 657a str r2, [r7, #84] @ 0x54
|
|
800c310: 3360 adds r3, #96 @ 0x60
|
|
800c312: 443b add r3, r7
|
|
800c314: 2230 movs r2, #48 @ 0x30
|
|
800c316: f803 2c50 strb.w r2, [r3, #-80]
|
|
800c31a: e018 b.n 800c34e <ee_number+0xbe>
|
|
else
|
|
{
|
|
while (num != 0)
|
|
{
|
|
tmp[i++] = dig[((unsigned long) num) % (unsigned) base];
|
|
800c31c: 687b ldr r3, [r7, #4]
|
|
800c31e: 683a ldr r2, [r7, #0]
|
|
800c320: fbb3 f1f2 udiv r1, r3, r2
|
|
800c324: fb01 f202 mul.w r2, r1, r2
|
|
800c328: 1a9b subs r3, r3, r2
|
|
800c32a: 6dba ldr r2, [r7, #88] @ 0x58
|
|
800c32c: 441a add r2, r3
|
|
800c32e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800c330: 1c59 adds r1, r3, #1
|
|
800c332: 6579 str r1, [r7, #84] @ 0x54
|
|
800c334: 7812 ldrb r2, [r2, #0]
|
|
800c336: 3360 adds r3, #96 @ 0x60
|
|
800c338: 443b add r3, r7
|
|
800c33a: f803 2c50 strb.w r2, [r3, #-80]
|
|
num = ((unsigned long) num) / (unsigned) base;
|
|
800c33e: 687a ldr r2, [r7, #4]
|
|
800c340: 683b ldr r3, [r7, #0]
|
|
800c342: fbb2 f3f3 udiv r3, r2, r3
|
|
800c346: 607b str r3, [r7, #4]
|
|
while (num != 0)
|
|
800c348: 687b ldr r3, [r7, #4]
|
|
800c34a: 2b00 cmp r3, #0
|
|
800c34c: d1e6 bne.n 800c31c <ee_number+0x8c>
|
|
}
|
|
}
|
|
|
|
if (i > precision) precision = i;
|
|
800c34e: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800c350: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800c352: 429a cmp r2, r3
|
|
800c354: dd01 ble.n 800c35a <ee_number+0xca>
|
|
800c356: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800c358: 66fb str r3, [r7, #108] @ 0x6c
|
|
size -= precision;
|
|
800c35a: 6eba ldr r2, [r7, #104] @ 0x68
|
|
800c35c: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800c35e: 1ad3 subs r3, r2, r3
|
|
800c360: 66bb str r3, [r7, #104] @ 0x68
|
|
if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' ');
|
|
800c362: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800c364: f003 0301 and.w r3, r3, #1
|
|
800c368: 2b00 cmp r3, #0
|
|
800c36a: d112 bne.n 800c392 <ee_number+0x102>
|
|
800c36c: e00c b.n 800c388 <ee_number+0xf8>
|
|
800c36e: 68fb ldr r3, [r7, #12]
|
|
800c370: 1c5a adds r2, r3, #1
|
|
800c372: 60fa str r2, [r7, #12]
|
|
800c374: 2220 movs r2, #32
|
|
800c376: 701a strb r2, [r3, #0]
|
|
800c378: 68bb ldr r3, [r7, #8]
|
|
800c37a: 3b01 subs r3, #1
|
|
800c37c: 60bb str r3, [r7, #8]
|
|
800c37e: 68bb ldr r3, [r7, #8]
|
|
800c380: 2b00 cmp r3, #0
|
|
800c382: d101 bne.n 800c388 <ee_number+0xf8>
|
|
800c384: 68fb ldr r3, [r7, #12]
|
|
800c386: e068 b.n 800c45a <ee_number+0x1ca>
|
|
800c388: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800c38a: 1e5a subs r2, r3, #1
|
|
800c38c: 66ba str r2, [r7, #104] @ 0x68
|
|
800c38e: 2b00 cmp r3, #0
|
|
800c390: dced bgt.n 800c36e <ee_number+0xde>
|
|
if (sign) ASSIGN_STR(sign);
|
|
800c392: f897 305f ldrb.w r3, [r7, #95] @ 0x5f
|
|
800c396: 2b00 cmp r3, #0
|
|
800c398: d01b beq.n 800c3d2 <ee_number+0x142>
|
|
800c39a: 68fb ldr r3, [r7, #12]
|
|
800c39c: 1c5a adds r2, r3, #1
|
|
800c39e: 60fa str r2, [r7, #12]
|
|
800c3a0: f897 205f ldrb.w r2, [r7, #95] @ 0x5f
|
|
800c3a4: 701a strb r2, [r3, #0]
|
|
800c3a6: 68bb ldr r3, [r7, #8]
|
|
800c3a8: 3b01 subs r3, #1
|
|
800c3aa: 60bb str r3, [r7, #8]
|
|
800c3ac: 68bb ldr r3, [r7, #8]
|
|
800c3ae: 2b00 cmp r3, #0
|
|
800c3b0: d10f bne.n 800c3d2 <ee_number+0x142>
|
|
800c3b2: 68fb ldr r3, [r7, #12]
|
|
800c3b4: e051 b.n 800c45a <ee_number+0x1ca>
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef TINY_PRINTF
|
|
while (size-- > 0) ASSIGN_STR(c);
|
|
800c3b6: 68fb ldr r3, [r7, #12]
|
|
800c3b8: 1c5a adds r2, r3, #1
|
|
800c3ba: 60fa str r2, [r7, #12]
|
|
800c3bc: f897 2053 ldrb.w r2, [r7, #83] @ 0x53
|
|
800c3c0: 701a strb r2, [r3, #0]
|
|
800c3c2: 68bb ldr r3, [r7, #8]
|
|
800c3c4: 3b01 subs r3, #1
|
|
800c3c6: 60bb str r3, [r7, #8]
|
|
800c3c8: 68bb ldr r3, [r7, #8]
|
|
800c3ca: 2b00 cmp r3, #0
|
|
800c3cc: d101 bne.n 800c3d2 <ee_number+0x142>
|
|
800c3ce: 68fb ldr r3, [r7, #12]
|
|
800c3d0: e043 b.n 800c45a <ee_number+0x1ca>
|
|
800c3d2: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800c3d4: 1e5a subs r2, r3, #1
|
|
800c3d6: 66ba str r2, [r7, #104] @ 0x68
|
|
800c3d8: 2b00 cmp r3, #0
|
|
800c3da: dcec bgt.n 800c3b6 <ee_number+0x126>
|
|
#else
|
|
if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c);
|
|
#endif
|
|
while (i < precision--) ASSIGN_STR('0');
|
|
800c3dc: e00c b.n 800c3f8 <ee_number+0x168>
|
|
800c3de: 68fb ldr r3, [r7, #12]
|
|
800c3e0: 1c5a adds r2, r3, #1
|
|
800c3e2: 60fa str r2, [r7, #12]
|
|
800c3e4: 2230 movs r2, #48 @ 0x30
|
|
800c3e6: 701a strb r2, [r3, #0]
|
|
800c3e8: 68bb ldr r3, [r7, #8]
|
|
800c3ea: 3b01 subs r3, #1
|
|
800c3ec: 60bb str r3, [r7, #8]
|
|
800c3ee: 68bb ldr r3, [r7, #8]
|
|
800c3f0: 2b00 cmp r3, #0
|
|
800c3f2: d101 bne.n 800c3f8 <ee_number+0x168>
|
|
800c3f4: 68fb ldr r3, [r7, #12]
|
|
800c3f6: e030 b.n 800c45a <ee_number+0x1ca>
|
|
800c3f8: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800c3fa: 1e5a subs r2, r3, #1
|
|
800c3fc: 66fa str r2, [r7, #108] @ 0x6c
|
|
800c3fe: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800c400: 429a cmp r2, r3
|
|
800c402: dbec blt.n 800c3de <ee_number+0x14e>
|
|
while (i-- > 0) ASSIGN_STR(tmp[i]);
|
|
800c404: e010 b.n 800c428 <ee_number+0x198>
|
|
800c406: 68fb ldr r3, [r7, #12]
|
|
800c408: 1c5a adds r2, r3, #1
|
|
800c40a: 60fa str r2, [r7, #12]
|
|
800c40c: f107 0110 add.w r1, r7, #16
|
|
800c410: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800c412: 440a add r2, r1
|
|
800c414: 7812 ldrb r2, [r2, #0]
|
|
800c416: 701a strb r2, [r3, #0]
|
|
800c418: 68bb ldr r3, [r7, #8]
|
|
800c41a: 3b01 subs r3, #1
|
|
800c41c: 60bb str r3, [r7, #8]
|
|
800c41e: 68bb ldr r3, [r7, #8]
|
|
800c420: 2b00 cmp r3, #0
|
|
800c422: d101 bne.n 800c428 <ee_number+0x198>
|
|
800c424: 68fb ldr r3, [r7, #12]
|
|
800c426: e018 b.n 800c45a <ee_number+0x1ca>
|
|
800c428: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800c42a: 1e5a subs r2, r3, #1
|
|
800c42c: 657a str r2, [r7, #84] @ 0x54
|
|
800c42e: 2b00 cmp r3, #0
|
|
800c430: dce9 bgt.n 800c406 <ee_number+0x176>
|
|
while (size-- > 0) ASSIGN_STR(' ');
|
|
800c432: e00c b.n 800c44e <ee_number+0x1be>
|
|
800c434: 68fb ldr r3, [r7, #12]
|
|
800c436: 1c5a adds r2, r3, #1
|
|
800c438: 60fa str r2, [r7, #12]
|
|
800c43a: 2220 movs r2, #32
|
|
800c43c: 701a strb r2, [r3, #0]
|
|
800c43e: 68bb ldr r3, [r7, #8]
|
|
800c440: 3b01 subs r3, #1
|
|
800c442: 60bb str r3, [r7, #8]
|
|
800c444: 68bb ldr r3, [r7, #8]
|
|
800c446: 2b00 cmp r3, #0
|
|
800c448: d101 bne.n 800c44e <ee_number+0x1be>
|
|
800c44a: 68fb ldr r3, [r7, #12]
|
|
800c44c: e005 b.n 800c45a <ee_number+0x1ca>
|
|
800c44e: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800c450: 1e5a subs r2, r3, #1
|
|
800c452: 66ba str r2, [r7, #104] @ 0x68
|
|
800c454: 2b00 cmp r3, #0
|
|
800c456: dced bgt.n 800c434 <ee_number+0x1a4>
|
|
|
|
return str;
|
|
800c458: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800c45a: 4618 mov r0, r3
|
|
800c45c: 3764 adds r7, #100 @ 0x64
|
|
800c45e: 46bd mov sp, r7
|
|
800c460: bc80 pop {r7}
|
|
800c462: 4770 bx lr
|
|
800c464: 20000014 .word 0x20000014
|
|
800c468: 20000018 .word 0x20000018
|
|
|
|
0800c46c <tiny_vsnprintf_like>:
|
|
|
|
#define CHECK_STR_SIZE(_buf, _str, _size) \
|
|
if ((((_str) - (_buf)) >= ((_size)-1))) { break; }
|
|
|
|
int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args)
|
|
{
|
|
800c46c: b580 push {r7, lr}
|
|
800c46e: b092 sub sp, #72 @ 0x48
|
|
800c470: af04 add r7, sp, #16
|
|
800c472: 60f8 str r0, [r7, #12]
|
|
800c474: 60b9 str r1, [r7, #8]
|
|
800c476: 607a str r2, [r7, #4]
|
|
800c478: 603b str r3, [r7, #0]
|
|
|
|
int field_width; // Width of output field
|
|
int precision; // Min. # of digits for integers; max number of chars for from string
|
|
int qualifier; // 'h', 'l', or 'L' for integer fields
|
|
|
|
if (size <= 0)
|
|
800c47a: 68bb ldr r3, [r7, #8]
|
|
800c47c: 2b00 cmp r3, #0
|
|
800c47e: dc01 bgt.n 800c484 <tiny_vsnprintf_like+0x18>
|
|
{
|
|
return 0;
|
|
800c480: 2300 movs r3, #0
|
|
800c482: e13e b.n 800c702 <tiny_vsnprintf_like+0x296>
|
|
}
|
|
|
|
for (str = buf; *fmt || ((str - buf) >= size-1); fmt++)
|
|
800c484: 68fb ldr r3, [r7, #12]
|
|
800c486: 62fb str r3, [r7, #44] @ 0x2c
|
|
800c488: e128 b.n 800c6dc <tiny_vsnprintf_like+0x270>
|
|
{
|
|
CHECK_STR_SIZE(buf, str, size);
|
|
800c48a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800c48c: 68fb ldr r3, [r7, #12]
|
|
800c48e: 1ad2 subs r2, r2, r3
|
|
800c490: 68bb ldr r3, [r7, #8]
|
|
800c492: 3b01 subs r3, #1
|
|
800c494: 429a cmp r2, r3
|
|
800c496: f280 812e bge.w 800c6f6 <tiny_vsnprintf_like+0x28a>
|
|
|
|
if (*fmt != '%')
|
|
800c49a: 687b ldr r3, [r7, #4]
|
|
800c49c: 781b ldrb r3, [r3, #0]
|
|
800c49e: 2b25 cmp r3, #37 @ 0x25
|
|
800c4a0: d006 beq.n 800c4b0 <tiny_vsnprintf_like+0x44>
|
|
{
|
|
*str++ = *fmt;
|
|
800c4a2: 687a ldr r2, [r7, #4]
|
|
800c4a4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c4a6: 1c59 adds r1, r3, #1
|
|
800c4a8: 62f9 str r1, [r7, #44] @ 0x2c
|
|
800c4aa: 7812 ldrb r2, [r2, #0]
|
|
800c4ac: 701a strb r2, [r3, #0]
|
|
continue;
|
|
800c4ae: e112 b.n 800c6d6 <tiny_vsnprintf_like+0x26a>
|
|
}
|
|
|
|
// Process flags
|
|
flags = 0;
|
|
800c4b0: 2300 movs r3, #0
|
|
800c4b2: 623b str r3, [r7, #32]
|
|
#ifdef TINY_PRINTF
|
|
/* Support %0, but not %-, %+, %space and %# */
|
|
fmt++;
|
|
800c4b4: 687b ldr r3, [r7, #4]
|
|
800c4b6: 3301 adds r3, #1
|
|
800c4b8: 607b str r3, [r7, #4]
|
|
if (*fmt == '0')
|
|
800c4ba: 687b ldr r3, [r7, #4]
|
|
800c4bc: 781b ldrb r3, [r3, #0]
|
|
800c4be: 2b30 cmp r3, #48 @ 0x30
|
|
800c4c0: d103 bne.n 800c4ca <tiny_vsnprintf_like+0x5e>
|
|
{
|
|
flags |= ZEROPAD;
|
|
800c4c2: 6a3b ldr r3, [r7, #32]
|
|
800c4c4: f043 0301 orr.w r3, r3, #1
|
|
800c4c8: 623b str r3, [r7, #32]
|
|
case '0': flags |= ZEROPAD; goto repeat;
|
|
}
|
|
#endif
|
|
|
|
// Get field width
|
|
field_width = -1;
|
|
800c4ca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800c4ce: 61fb str r3, [r7, #28]
|
|
if (is_digit(*fmt))
|
|
800c4d0: 687b ldr r3, [r7, #4]
|
|
800c4d2: 781b ldrb r3, [r3, #0]
|
|
800c4d4: 2b2f cmp r3, #47 @ 0x2f
|
|
800c4d6: d908 bls.n 800c4ea <tiny_vsnprintf_like+0x7e>
|
|
800c4d8: 687b ldr r3, [r7, #4]
|
|
800c4da: 781b ldrb r3, [r3, #0]
|
|
800c4dc: 2b39 cmp r3, #57 @ 0x39
|
|
800c4de: d804 bhi.n 800c4ea <tiny_vsnprintf_like+0x7e>
|
|
field_width = ee_skip_atoi(&fmt);
|
|
800c4e0: 1d3b adds r3, r7, #4
|
|
800c4e2: 4618 mov r0, r3
|
|
800c4e4: f7ff feae bl 800c244 <ee_skip_atoi>
|
|
800c4e8: 61f8 str r0, [r7, #28]
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// Get the precision
|
|
precision = -1;
|
|
800c4ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800c4ee: 61bb str r3, [r7, #24]
|
|
if (precision < 0) precision = 0;
|
|
}
|
|
#endif
|
|
|
|
// Get the conversion qualifier
|
|
qualifier = -1;
|
|
800c4f0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800c4f4: 617b str r3, [r7, #20]
|
|
fmt++;
|
|
}
|
|
#endif
|
|
|
|
// Default base
|
|
base = 10;
|
|
800c4f6: 230a movs r3, #10
|
|
800c4f8: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
switch (*fmt)
|
|
800c4fa: 687b ldr r3, [r7, #4]
|
|
800c4fc: 781b ldrb r3, [r3, #0]
|
|
800c4fe: 3b58 subs r3, #88 @ 0x58
|
|
800c500: 2b20 cmp r3, #32
|
|
800c502: f200 8094 bhi.w 800c62e <tiny_vsnprintf_like+0x1c2>
|
|
800c506: a201 add r2, pc, #4 @ (adr r2, 800c50c <tiny_vsnprintf_like+0xa0>)
|
|
800c508: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c50c: 0800c617 .word 0x0800c617
|
|
800c510: 0800c62f .word 0x0800c62f
|
|
800c514: 0800c62f .word 0x0800c62f
|
|
800c518: 0800c62f .word 0x0800c62f
|
|
800c51c: 0800c62f .word 0x0800c62f
|
|
800c520: 0800c62f .word 0x0800c62f
|
|
800c524: 0800c62f .word 0x0800c62f
|
|
800c528: 0800c62f .word 0x0800c62f
|
|
800c52c: 0800c62f .word 0x0800c62f
|
|
800c530: 0800c62f .word 0x0800c62f
|
|
800c534: 0800c62f .word 0x0800c62f
|
|
800c538: 0800c59b .word 0x0800c59b
|
|
800c53c: 0800c625 .word 0x0800c625
|
|
800c540: 0800c62f .word 0x0800c62f
|
|
800c544: 0800c62f .word 0x0800c62f
|
|
800c548: 0800c62f .word 0x0800c62f
|
|
800c54c: 0800c62f .word 0x0800c62f
|
|
800c550: 0800c625 .word 0x0800c625
|
|
800c554: 0800c62f .word 0x0800c62f
|
|
800c558: 0800c62f .word 0x0800c62f
|
|
800c55c: 0800c62f .word 0x0800c62f
|
|
800c560: 0800c62f .word 0x0800c62f
|
|
800c564: 0800c62f .word 0x0800c62f
|
|
800c568: 0800c62f .word 0x0800c62f
|
|
800c56c: 0800c62f .word 0x0800c62f
|
|
800c570: 0800c62f .word 0x0800c62f
|
|
800c574: 0800c62f .word 0x0800c62f
|
|
800c578: 0800c5bb .word 0x0800c5bb
|
|
800c57c: 0800c62f .word 0x0800c62f
|
|
800c580: 0800c67b .word 0x0800c67b
|
|
800c584: 0800c62f .word 0x0800c62f
|
|
800c588: 0800c62f .word 0x0800c62f
|
|
800c58c: 0800c61f .word 0x0800c61f
|
|
case 'c':
|
|
#ifdef TINY_PRINTF
|
|
#else
|
|
if (!(flags & LEFT))
|
|
#endif
|
|
while (--field_width > 0) *str++ = ' ';
|
|
800c590: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c592: 1c5a adds r2, r3, #1
|
|
800c594: 62fa str r2, [r7, #44] @ 0x2c
|
|
800c596: 2220 movs r2, #32
|
|
800c598: 701a strb r2, [r3, #0]
|
|
800c59a: 69fb ldr r3, [r7, #28]
|
|
800c59c: 3b01 subs r3, #1
|
|
800c59e: 61fb str r3, [r7, #28]
|
|
800c5a0: 69fb ldr r3, [r7, #28]
|
|
800c5a2: 2b00 cmp r3, #0
|
|
800c5a4: dcf4 bgt.n 800c590 <tiny_vsnprintf_like+0x124>
|
|
*str++ = (unsigned char) va_arg(args, int);
|
|
800c5a6: 683b ldr r3, [r7, #0]
|
|
800c5a8: 1d1a adds r2, r3, #4
|
|
800c5aa: 603a str r2, [r7, #0]
|
|
800c5ac: 6819 ldr r1, [r3, #0]
|
|
800c5ae: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c5b0: 1c5a adds r2, r3, #1
|
|
800c5b2: 62fa str r2, [r7, #44] @ 0x2c
|
|
800c5b4: b2ca uxtb r2, r1
|
|
800c5b6: 701a strb r2, [r3, #0]
|
|
#ifdef TINY_PRINTF
|
|
#else
|
|
while (--field_width > 0) *str++ = ' ';
|
|
#endif
|
|
continue;
|
|
800c5b8: e08d b.n 800c6d6 <tiny_vsnprintf_like+0x26a>
|
|
|
|
case 's':
|
|
s = va_arg(args, char *);
|
|
800c5ba: 683b ldr r3, [r7, #0]
|
|
800c5bc: 1d1a adds r2, r3, #4
|
|
800c5be: 603a str r2, [r7, #0]
|
|
800c5c0: 681b ldr r3, [r3, #0]
|
|
800c5c2: 627b str r3, [r7, #36] @ 0x24
|
|
if (!s) s = "<NULL>";
|
|
800c5c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c5c6: 2b00 cmp r3, #0
|
|
800c5c8: d101 bne.n 800c5ce <tiny_vsnprintf_like+0x162>
|
|
800c5ca: 4b50 ldr r3, [pc, #320] @ (800c70c <tiny_vsnprintf_like+0x2a0>)
|
|
800c5cc: 627b str r3, [r7, #36] @ 0x24
|
|
#ifdef TINY_PRINTF
|
|
len = strlen(s);
|
|
800c5ce: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
800c5d0: f7f3 fdd2 bl 8000178 <strlen>
|
|
800c5d4: 4603 mov r3, r0
|
|
800c5d6: 613b str r3, [r7, #16]
|
|
#else
|
|
len = strnlen(s, precision);
|
|
if (!(flags & LEFT))
|
|
#endif
|
|
while (len < field_width--) *str++ = ' ';
|
|
800c5d8: e004 b.n 800c5e4 <tiny_vsnprintf_like+0x178>
|
|
800c5da: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c5dc: 1c5a adds r2, r3, #1
|
|
800c5de: 62fa str r2, [r7, #44] @ 0x2c
|
|
800c5e0: 2220 movs r2, #32
|
|
800c5e2: 701a strb r2, [r3, #0]
|
|
800c5e4: 69fb ldr r3, [r7, #28]
|
|
800c5e6: 1e5a subs r2, r3, #1
|
|
800c5e8: 61fa str r2, [r7, #28]
|
|
800c5ea: 693a ldr r2, [r7, #16]
|
|
800c5ec: 429a cmp r2, r3
|
|
800c5ee: dbf4 blt.n 800c5da <tiny_vsnprintf_like+0x16e>
|
|
for (i = 0; i < len; ++i) *str++ = *s++;
|
|
800c5f0: 2300 movs r3, #0
|
|
800c5f2: 62bb str r3, [r7, #40] @ 0x28
|
|
800c5f4: e00a b.n 800c60c <tiny_vsnprintf_like+0x1a0>
|
|
800c5f6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800c5f8: 1c53 adds r3, r2, #1
|
|
800c5fa: 627b str r3, [r7, #36] @ 0x24
|
|
800c5fc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c5fe: 1c59 adds r1, r3, #1
|
|
800c600: 62f9 str r1, [r7, #44] @ 0x2c
|
|
800c602: 7812 ldrb r2, [r2, #0]
|
|
800c604: 701a strb r2, [r3, #0]
|
|
800c606: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800c608: 3301 adds r3, #1
|
|
800c60a: 62bb str r3, [r7, #40] @ 0x28
|
|
800c60c: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800c60e: 693b ldr r3, [r7, #16]
|
|
800c610: 429a cmp r2, r3
|
|
800c612: dbf0 blt.n 800c5f6 <tiny_vsnprintf_like+0x18a>
|
|
#ifdef TINY_PRINTF
|
|
#else
|
|
while (len < field_width--) *str++ = ' ';
|
|
#endif
|
|
continue;
|
|
800c614: e05f b.n 800c6d6 <tiny_vsnprintf_like+0x26a>
|
|
base = 8;
|
|
break;
|
|
#endif
|
|
|
|
case 'X':
|
|
flags |= UPPERCASE;
|
|
800c616: 6a3b ldr r3, [r7, #32]
|
|
800c618: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
800c61c: 623b str r3, [r7, #32]
|
|
|
|
case 'x':
|
|
base = 16;
|
|
800c61e: 2310 movs r3, #16
|
|
800c620: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
800c622: e02b b.n 800c67c <tiny_vsnprintf_like+0x210>
|
|
|
|
case 'd':
|
|
case 'i':
|
|
flags |= SIGN;
|
|
800c624: 6a3b ldr r3, [r7, #32]
|
|
800c626: f043 0302 orr.w r3, r3, #2
|
|
800c62a: 623b str r3, [r7, #32]
|
|
|
|
case 'u':
|
|
break;
|
|
800c62c: e025 b.n 800c67a <tiny_vsnprintf_like+0x20e>
|
|
continue;
|
|
|
|
#endif
|
|
|
|
default:
|
|
if (*fmt != '%') *str++ = '%';
|
|
800c62e: 687b ldr r3, [r7, #4]
|
|
800c630: 781b ldrb r3, [r3, #0]
|
|
800c632: 2b25 cmp r3, #37 @ 0x25
|
|
800c634: d004 beq.n 800c640 <tiny_vsnprintf_like+0x1d4>
|
|
800c636: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c638: 1c5a adds r2, r3, #1
|
|
800c63a: 62fa str r2, [r7, #44] @ 0x2c
|
|
800c63c: 2225 movs r2, #37 @ 0x25
|
|
800c63e: 701a strb r2, [r3, #0]
|
|
CHECK_STR_SIZE(buf, str, size);
|
|
800c640: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800c642: 68fb ldr r3, [r7, #12]
|
|
800c644: 1ad2 subs r2, r2, r3
|
|
800c646: 68bb ldr r3, [r7, #8]
|
|
800c648: 3b01 subs r3, #1
|
|
800c64a: 429a cmp r2, r3
|
|
800c64c: da16 bge.n 800c67c <tiny_vsnprintf_like+0x210>
|
|
if (*fmt)
|
|
800c64e: 687b ldr r3, [r7, #4]
|
|
800c650: 781b ldrb r3, [r3, #0]
|
|
800c652: 2b00 cmp r3, #0
|
|
800c654: d006 beq.n 800c664 <tiny_vsnprintf_like+0x1f8>
|
|
*str++ = *fmt;
|
|
800c656: 687a ldr r2, [r7, #4]
|
|
800c658: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c65a: 1c59 adds r1, r3, #1
|
|
800c65c: 62f9 str r1, [r7, #44] @ 0x2c
|
|
800c65e: 7812 ldrb r2, [r2, #0]
|
|
800c660: 701a strb r2, [r3, #0]
|
|
800c662: e002 b.n 800c66a <tiny_vsnprintf_like+0x1fe>
|
|
else
|
|
--fmt;
|
|
800c664: 687b ldr r3, [r7, #4]
|
|
800c666: 3b01 subs r3, #1
|
|
800c668: 607b str r3, [r7, #4]
|
|
CHECK_STR_SIZE(buf, str, size);
|
|
800c66a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800c66c: 68fb ldr r3, [r7, #12]
|
|
800c66e: 1ad2 subs r2, r2, r3
|
|
800c670: 68bb ldr r3, [r7, #8]
|
|
800c672: 3b01 subs r3, #1
|
|
800c674: 429a cmp r2, r3
|
|
800c676: db2d blt.n 800c6d4 <tiny_vsnprintf_like+0x268>
|
|
800c678: e000 b.n 800c67c <tiny_vsnprintf_like+0x210>
|
|
break;
|
|
800c67a: bf00 nop
|
|
continue;
|
|
}
|
|
|
|
if (qualifier == 'l')
|
|
800c67c: 697b ldr r3, [r7, #20]
|
|
800c67e: 2b6c cmp r3, #108 @ 0x6c
|
|
800c680: d105 bne.n 800c68e <tiny_vsnprintf_like+0x222>
|
|
num = va_arg(args, unsigned long);
|
|
800c682: 683b ldr r3, [r7, #0]
|
|
800c684: 1d1a adds r2, r3, #4
|
|
800c686: 603a str r2, [r7, #0]
|
|
800c688: 681b ldr r3, [r3, #0]
|
|
800c68a: 637b str r3, [r7, #52] @ 0x34
|
|
800c68c: e00f b.n 800c6ae <tiny_vsnprintf_like+0x242>
|
|
else if (flags & SIGN)
|
|
800c68e: 6a3b ldr r3, [r7, #32]
|
|
800c690: f003 0302 and.w r3, r3, #2
|
|
800c694: 2b00 cmp r3, #0
|
|
800c696: d005 beq.n 800c6a4 <tiny_vsnprintf_like+0x238>
|
|
num = va_arg(args, int);
|
|
800c698: 683b ldr r3, [r7, #0]
|
|
800c69a: 1d1a adds r2, r3, #4
|
|
800c69c: 603a str r2, [r7, #0]
|
|
800c69e: 681b ldr r3, [r3, #0]
|
|
800c6a0: 637b str r3, [r7, #52] @ 0x34
|
|
800c6a2: e004 b.n 800c6ae <tiny_vsnprintf_like+0x242>
|
|
else
|
|
num = va_arg(args, unsigned int);
|
|
800c6a4: 683b ldr r3, [r7, #0]
|
|
800c6a6: 1d1a adds r2, r3, #4
|
|
800c6a8: 603a str r2, [r7, #0]
|
|
800c6aa: 681b ldr r3, [r3, #0]
|
|
800c6ac: 637b str r3, [r7, #52] @ 0x34
|
|
|
|
str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags);
|
|
800c6ae: 68bb ldr r3, [r7, #8]
|
|
800c6b0: 1e5a subs r2, r3, #1
|
|
800c6b2: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800c6b4: 68fb ldr r3, [r7, #12]
|
|
800c6b6: 1acb subs r3, r1, r3
|
|
800c6b8: 1ad1 subs r1, r2, r3
|
|
800c6ba: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800c6bc: 6a3b ldr r3, [r7, #32]
|
|
800c6be: 9302 str r3, [sp, #8]
|
|
800c6c0: 69bb ldr r3, [r7, #24]
|
|
800c6c2: 9301 str r3, [sp, #4]
|
|
800c6c4: 69fb ldr r3, [r7, #28]
|
|
800c6c6: 9300 str r3, [sp, #0]
|
|
800c6c8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c6ca: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800c6cc: f7ff fde0 bl 800c290 <ee_number>
|
|
800c6d0: 62f8 str r0, [r7, #44] @ 0x2c
|
|
800c6d2: e000 b.n 800c6d6 <tiny_vsnprintf_like+0x26a>
|
|
continue;
|
|
800c6d4: bf00 nop
|
|
for (str = buf; *fmt || ((str - buf) >= size-1); fmt++)
|
|
800c6d6: 687b ldr r3, [r7, #4]
|
|
800c6d8: 3301 adds r3, #1
|
|
800c6da: 607b str r3, [r7, #4]
|
|
800c6dc: 687b ldr r3, [r7, #4]
|
|
800c6de: 781b ldrb r3, [r3, #0]
|
|
800c6e0: 2b00 cmp r3, #0
|
|
800c6e2: f47f aed2 bne.w 800c48a <tiny_vsnprintf_like+0x1e>
|
|
800c6e6: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800c6e8: 68fb ldr r3, [r7, #12]
|
|
800c6ea: 1ad2 subs r2, r2, r3
|
|
800c6ec: 68bb ldr r3, [r7, #8]
|
|
800c6ee: 3b01 subs r3, #1
|
|
800c6f0: 429a cmp r2, r3
|
|
800c6f2: f6bf aeca bge.w 800c48a <tiny_vsnprintf_like+0x1e>
|
|
}
|
|
|
|
*str = '\0';
|
|
800c6f6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c6f8: 2200 movs r2, #0
|
|
800c6fa: 701a strb r2, [r3, #0]
|
|
return str - buf;
|
|
800c6fc: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800c6fe: 68fb ldr r3, [r7, #12]
|
|
800c700: 1ad3 subs r3, r2, r3
|
|
}
|
|
800c702: 4618 mov r0, r3
|
|
800c704: 3738 adds r7, #56 @ 0x38
|
|
800c706: 46bd mov sp, r7
|
|
800c708: bd80 pop {r7, pc}
|
|
800c70a: bf00 nop
|
|
800c70c: 0800d8a8 .word 0x0800d8a8
|
|
|
|
0800c710 <UTIL_SEQ_Run>:
|
|
* That is the reason why many variables that are used only in that function are declared static.
|
|
* Note: These variables could have been declared static in the function.
|
|
*
|
|
*/
|
|
void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm )
|
|
{
|
|
800c710: b580 push {r7, lr}
|
|
800c712: b090 sub sp, #64 @ 0x40
|
|
800c714: af00 add r7, sp, #0
|
|
800c716: 6078 str r0, [r7, #4]
|
|
/*
|
|
* When this function is nested, the mask to be applied cannot be larger than the first call
|
|
* The mask is always getting smaller and smaller
|
|
* A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task
|
|
*/
|
|
super_mask_backup = SuperMask;
|
|
800c718: 4b73 ldr r3, [pc, #460] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c71a: 681b ldr r3, [r3, #0]
|
|
800c71c: 62bb str r3, [r7, #40] @ 0x28
|
|
SuperMask &= Mask_bm;
|
|
800c71e: 4b72 ldr r3, [pc, #456] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c720: 681a ldr r2, [r3, #0]
|
|
800c722: 687b ldr r3, [r7, #4]
|
|
800c724: 4013 ands r3, r2
|
|
800c726: 4a70 ldr r2, [pc, #448] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c728: 6013 str r3, [r2, #0]
|
|
* TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask
|
|
* SuperMask that comes from UTIL_SEQ_Run
|
|
* If the waited event is there, exit from UTIL_SEQ_Run() to return to the
|
|
* waiting task
|
|
*/
|
|
local_taskset = TaskSet;
|
|
800c72a: 4b70 ldr r3, [pc, #448] @ (800c8ec <UTIL_SEQ_Run+0x1dc>)
|
|
800c72c: 681b ldr r3, [r3, #0]
|
|
800c72e: 63bb str r3, [r7, #56] @ 0x38
|
|
local_evtset = EvtSet;
|
|
800c730: 4b6f ldr r3, [pc, #444] @ (800c8f0 <UTIL_SEQ_Run+0x1e0>)
|
|
800c732: 681b ldr r3, [r3, #0]
|
|
800c734: 637b str r3, [r7, #52] @ 0x34
|
|
local_taskmask = TaskMask;
|
|
800c736: 4b6f ldr r3, [pc, #444] @ (800c8f4 <UTIL_SEQ_Run+0x1e4>)
|
|
800c738: 681b ldr r3, [r3, #0]
|
|
800c73a: 633b str r3, [r7, #48] @ 0x30
|
|
local_evtwaited = EvtWaited;
|
|
800c73c: 4b6e ldr r3, [pc, #440] @ (800c8f8 <UTIL_SEQ_Run+0x1e8>)
|
|
800c73e: 681b ldr r3, [r3, #0]
|
|
800c740: 62fb str r3, [r7, #44] @ 0x2c
|
|
while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U))
|
|
800c742: e08d b.n 800c860 <UTIL_SEQ_Run+0x150>
|
|
{
|
|
counter = 0U;
|
|
800c744: 2300 movs r3, #0
|
|
800c746: 63fb str r3, [r7, #60] @ 0x3c
|
|
/*
|
|
* When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending
|
|
* on the priority parameter given from UTIL_SEQ_SetTask()
|
|
* The while loop is looking for a flag set from the highest priority maskr to the lower
|
|
*/
|
|
while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U)
|
|
800c748: e002 b.n 800c750 <UTIL_SEQ_Run+0x40>
|
|
{
|
|
counter++;
|
|
800c74a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c74c: 3301 adds r3, #1
|
|
800c74e: 63fb str r3, [r7, #60] @ 0x3c
|
|
while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U)
|
|
800c750: 4a6a ldr r2, [pc, #424] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c752: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c754: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
800c758: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c75a: 401a ands r2, r3
|
|
800c75c: 4b62 ldr r3, [pc, #392] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c75e: 681b ldr r3, [r3, #0]
|
|
800c760: 4013 ands r3, r2
|
|
800c762: 2b00 cmp r3, #0
|
|
800c764: d0f1 beq.n 800c74a <UTIL_SEQ_Run+0x3a>
|
|
}
|
|
|
|
current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask;
|
|
800c766: 4a65 ldr r2, [pc, #404] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c768: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c76a: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
800c76e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c770: 401a ands r2, r3
|
|
800c772: 4b5d ldr r3, [pc, #372] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c774: 681b ldr r3, [r3, #0]
|
|
800c776: 4013 ands r3, r2
|
|
800c778: 627b str r3, [r7, #36] @ 0x24
|
|
* so that the second one can be executed.
|
|
* Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask
|
|
*
|
|
* In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once
|
|
*/
|
|
if ((TaskPrio[counter].round_robin & current_task_set) == 0U)
|
|
800c77a: 4a60 ldr r2, [pc, #384] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c77c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c77e: 00db lsls r3, r3, #3
|
|
800c780: 4413 add r3, r2
|
|
800c782: 685a ldr r2, [r3, #4]
|
|
800c784: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c786: 4013 ands r3, r2
|
|
800c788: 2b00 cmp r3, #0
|
|
800c78a: d106 bne.n 800c79a <UTIL_SEQ_Run+0x8a>
|
|
{
|
|
TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET;
|
|
800c78c: 4a5b ldr r2, [pc, #364] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c78e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c790: 00db lsls r3, r3, #3
|
|
800c792: 4413 add r3, r2
|
|
800c794: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800c798: 605a str r2, [r3, #4]
|
|
/*
|
|
* Read the flag index of the task to be executed
|
|
* Once the index is read, the associated task will be executed even though a higher priority stack is requested
|
|
* before task execution.
|
|
*/
|
|
CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin));
|
|
800c79a: 4a58 ldr r2, [pc, #352] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c79c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c79e: 00db lsls r3, r3, #3
|
|
800c7a0: 4413 add r3, r2
|
|
800c7a2: 685a ldr r2, [r3, #4]
|
|
800c7a4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c7a6: 4013 ands r3, r2
|
|
800c7a8: 4618 mov r0, r3
|
|
800c7aa: f000 f907 bl 800c9bc <SEQ_BitPosition>
|
|
800c7ae: 4603 mov r3, r0
|
|
800c7b0: 461a mov r2, r3
|
|
800c7b2: 4b53 ldr r3, [pc, #332] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c7b4: 601a str r2, [r3, #0]
|
|
|
|
/*
|
|
* remove from the roun_robin mask the task that has been selected to be executed
|
|
*/
|
|
TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx);
|
|
800c7b6: 4a51 ldr r2, [pc, #324] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c7b8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c7ba: 00db lsls r3, r3, #3
|
|
800c7bc: 4413 add r3, r2
|
|
800c7be: 685a ldr r2, [r3, #4]
|
|
800c7c0: 4b4f ldr r3, [pc, #316] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c7c2: 681b ldr r3, [r3, #0]
|
|
800c7c4: 2101 movs r1, #1
|
|
800c7c6: fa01 f303 lsl.w r3, r1, r3
|
|
800c7ca: 43db mvns r3, r3
|
|
800c7cc: 401a ands r2, r3
|
|
800c7ce: 494b ldr r1, [pc, #300] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c7d0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c7d2: 00db lsls r3, r3, #3
|
|
800c7d4: 440b add r3, r1
|
|
800c7d6: 605a str r2, [r3, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c7d8: f3ef 8310 mrs r3, PRIMASK
|
|
800c7dc: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
800c7de: 69bb ldr r3, [r7, #24]
|
|
|
|
UTIL_SEQ_ENTER_CRITICAL_SECTION( );
|
|
800c7e0: 623b str r3, [r7, #32]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c7e2: b672 cpsid i
|
|
}
|
|
800c7e4: bf00 nop
|
|
/* remove from the list or pending task the one that has been selected to be executed */
|
|
TaskSet &= ~(1U << CurrentTaskIdx);
|
|
800c7e6: 4b46 ldr r3, [pc, #280] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c7e8: 681b ldr r3, [r3, #0]
|
|
800c7ea: 2201 movs r2, #1
|
|
800c7ec: fa02 f303 lsl.w r3, r2, r3
|
|
800c7f0: 43da mvns r2, r3
|
|
800c7f2: 4b3e ldr r3, [pc, #248] @ (800c8ec <UTIL_SEQ_Run+0x1dc>)
|
|
800c7f4: 681b ldr r3, [r3, #0]
|
|
800c7f6: 4013 ands r3, r2
|
|
800c7f8: 4a3c ldr r2, [pc, #240] @ (800c8ec <UTIL_SEQ_Run+0x1dc>)
|
|
800c7fa: 6013 str r3, [r2, #0]
|
|
/* remove from all priority mask the task that has been selected to be executed */
|
|
for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--)
|
|
800c7fc: 2301 movs r3, #1
|
|
800c7fe: 63fb str r3, [r7, #60] @ 0x3c
|
|
800c800: e013 b.n 800c82a <UTIL_SEQ_Run+0x11a>
|
|
{
|
|
TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx);
|
|
800c802: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c804: 3b01 subs r3, #1
|
|
800c806: 4a3d ldr r2, [pc, #244] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c808: f852 1033 ldr.w r1, [r2, r3, lsl #3]
|
|
800c80c: 4b3c ldr r3, [pc, #240] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c80e: 681b ldr r3, [r3, #0]
|
|
800c810: 2201 movs r2, #1
|
|
800c812: fa02 f303 lsl.w r3, r2, r3
|
|
800c816: 43da mvns r2, r3
|
|
800c818: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c81a: 3b01 subs r3, #1
|
|
800c81c: 400a ands r2, r1
|
|
800c81e: 4937 ldr r1, [pc, #220] @ (800c8fc <UTIL_SEQ_Run+0x1ec>)
|
|
800c820: f841 2033 str.w r2, [r1, r3, lsl #3]
|
|
for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--)
|
|
800c824: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c826: 3b01 subs r3, #1
|
|
800c828: 63fb str r3, [r7, #60] @ 0x3c
|
|
800c82a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c82c: 2b00 cmp r3, #0
|
|
800c82e: d1e8 bne.n 800c802 <UTIL_SEQ_Run+0xf2>
|
|
800c830: 6a3b ldr r3, [r7, #32]
|
|
800c832: 617b str r3, [r7, #20]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c834: 697b ldr r3, [r7, #20]
|
|
800c836: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c83a: bf00 nop
|
|
}
|
|
UTIL_SEQ_EXIT_CRITICAL_SECTION( );
|
|
|
|
/* Execute the task */
|
|
TaskCb[CurrentTaskIdx]( );
|
|
800c83c: 4b30 ldr r3, [pc, #192] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c83e: 681b ldr r3, [r3, #0]
|
|
800c840: 4a30 ldr r2, [pc, #192] @ (800c904 <UTIL_SEQ_Run+0x1f4>)
|
|
800c842: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c846: 4798 blx r3
|
|
|
|
local_taskset = TaskSet;
|
|
800c848: 4b28 ldr r3, [pc, #160] @ (800c8ec <UTIL_SEQ_Run+0x1dc>)
|
|
800c84a: 681b ldr r3, [r3, #0]
|
|
800c84c: 63bb str r3, [r7, #56] @ 0x38
|
|
local_evtset = EvtSet;
|
|
800c84e: 4b28 ldr r3, [pc, #160] @ (800c8f0 <UTIL_SEQ_Run+0x1e0>)
|
|
800c850: 681b ldr r3, [r3, #0]
|
|
800c852: 637b str r3, [r7, #52] @ 0x34
|
|
local_taskmask = TaskMask;
|
|
800c854: 4b27 ldr r3, [pc, #156] @ (800c8f4 <UTIL_SEQ_Run+0x1e4>)
|
|
800c856: 681b ldr r3, [r3, #0]
|
|
800c858: 633b str r3, [r7, #48] @ 0x30
|
|
local_evtwaited = EvtWaited;
|
|
800c85a: 4b27 ldr r3, [pc, #156] @ (800c8f8 <UTIL_SEQ_Run+0x1e8>)
|
|
800c85c: 681b ldr r3, [r3, #0]
|
|
800c85e: 62fb str r3, [r7, #44] @ 0x2c
|
|
while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U))
|
|
800c860: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800c862: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c864: 401a ands r2, r3
|
|
800c866: 4b20 ldr r3, [pc, #128] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c868: 681b ldr r3, [r3, #0]
|
|
800c86a: 4013 ands r3, r2
|
|
800c86c: 2b00 cmp r3, #0
|
|
800c86e: d005 beq.n 800c87c <UTIL_SEQ_Run+0x16c>
|
|
800c870: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800c872: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c874: 4013 ands r3, r2
|
|
800c876: 2b00 cmp r3, #0
|
|
800c878: f43f af64 beq.w 800c744 <UTIL_SEQ_Run+0x34>
|
|
}
|
|
|
|
/* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */
|
|
CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING;
|
|
800c87c: 4b20 ldr r3, [pc, #128] @ (800c900 <UTIL_SEQ_Run+0x1f0>)
|
|
800c87e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800c882: 601a str r2, [r3, #0]
|
|
UTIL_SEQ_PreIdle( );
|
|
800c884: f000 f88e bl 800c9a4 <UTIL_SEQ_PreIdle>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c888: f3ef 8310 mrs r3, PRIMASK
|
|
800c88c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800c88e: 693b ldr r3, [r7, #16]
|
|
|
|
UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( );
|
|
800c890: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c892: b672 cpsid i
|
|
}
|
|
800c894: bf00 nop
|
|
local_taskset = TaskSet;
|
|
800c896: 4b15 ldr r3, [pc, #84] @ (800c8ec <UTIL_SEQ_Run+0x1dc>)
|
|
800c898: 681b ldr r3, [r3, #0]
|
|
800c89a: 63bb str r3, [r7, #56] @ 0x38
|
|
local_evtset = EvtSet;
|
|
800c89c: 4b14 ldr r3, [pc, #80] @ (800c8f0 <UTIL_SEQ_Run+0x1e0>)
|
|
800c89e: 681b ldr r3, [r3, #0]
|
|
800c8a0: 637b str r3, [r7, #52] @ 0x34
|
|
local_taskmask = TaskMask;
|
|
800c8a2: 4b14 ldr r3, [pc, #80] @ (800c8f4 <UTIL_SEQ_Run+0x1e4>)
|
|
800c8a4: 681b ldr r3, [r3, #0]
|
|
800c8a6: 633b str r3, [r7, #48] @ 0x30
|
|
if ((local_taskset & local_taskmask & SuperMask) == 0U)
|
|
800c8a8: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800c8aa: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c8ac: 401a ands r2, r3
|
|
800c8ae: 4b0e ldr r3, [pc, #56] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c8b0: 681b ldr r3, [r3, #0]
|
|
800c8b2: 4013 ands r3, r2
|
|
800c8b4: 2b00 cmp r3, #0
|
|
800c8b6: d107 bne.n 800c8c8 <UTIL_SEQ_Run+0x1b8>
|
|
{
|
|
if ((local_evtset & EvtWaited)== 0U)
|
|
800c8b8: 4b0f ldr r3, [pc, #60] @ (800c8f8 <UTIL_SEQ_Run+0x1e8>)
|
|
800c8ba: 681a ldr r2, [r3, #0]
|
|
800c8bc: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800c8be: 4013 ands r3, r2
|
|
800c8c0: 2b00 cmp r3, #0
|
|
800c8c2: d101 bne.n 800c8c8 <UTIL_SEQ_Run+0x1b8>
|
|
{
|
|
UTIL_SEQ_Idle( );
|
|
800c8c4: f7f4 f906 bl 8000ad4 <UTIL_SEQ_Idle>
|
|
800c8c8: 69fb ldr r3, [r7, #28]
|
|
800c8ca: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c8cc: 68fb ldr r3, [r7, #12]
|
|
800c8ce: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c8d2: bf00 nop
|
|
}
|
|
}
|
|
UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( );
|
|
|
|
UTIL_SEQ_PostIdle( );
|
|
800c8d4: f000 f86c bl 800c9b0 <UTIL_SEQ_PostIdle>
|
|
|
|
/* restore the mask from UTIL_SEQ_Run() */
|
|
SuperMask = super_mask_backup;
|
|
800c8d8: 4a03 ldr r2, [pc, #12] @ (800c8e8 <UTIL_SEQ_Run+0x1d8>)
|
|
800c8da: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800c8dc: 6013 str r3, [r2, #0]
|
|
|
|
return;
|
|
800c8de: bf00 nop
|
|
}
|
|
800c8e0: 3740 adds r7, #64 @ 0x40
|
|
800c8e2: 46bd mov sp, r7
|
|
800c8e4: bd80 pop {r7, pc}
|
|
800c8e6: bf00 nop
|
|
800c8e8: 20000020 .word 0x20000020
|
|
800c8ec: 200009b0 .word 0x200009b0
|
|
800c8f0: 200009b4 .word 0x200009b4
|
|
800c8f4: 2000001c .word 0x2000001c
|
|
800c8f8: 200009b8 .word 0x200009b8
|
|
800c8fc: 200009c4 .word 0x200009c4
|
|
800c900: 200009bc .word 0x200009bc
|
|
800c904: 200009c0 .word 0x200009c0
|
|
|
|
0800c908 <UTIL_SEQ_RegTask>:
|
|
|
|
void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void ))
|
|
{
|
|
800c908: b580 push {r7, lr}
|
|
800c90a: b088 sub sp, #32
|
|
800c90c: af00 add r7, sp, #0
|
|
800c90e: 60f8 str r0, [r7, #12]
|
|
800c910: 60b9 str r1, [r7, #8]
|
|
800c912: 607a str r2, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c914: f3ef 8310 mrs r3, PRIMASK
|
|
800c918: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800c91a: 697b ldr r3, [r7, #20]
|
|
(void)Flags;
|
|
UTIL_SEQ_ENTER_CRITICAL_SECTION();
|
|
800c91c: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c91e: b672 cpsid i
|
|
}
|
|
800c920: bf00 nop
|
|
|
|
TaskCb[SEQ_BitPosition(TaskId_bm)] = Task;
|
|
800c922: 68f8 ldr r0, [r7, #12]
|
|
800c924: f000 f84a bl 800c9bc <SEQ_BitPosition>
|
|
800c928: 4603 mov r3, r0
|
|
800c92a: 4619 mov r1, r3
|
|
800c92c: 4a06 ldr r2, [pc, #24] @ (800c948 <UTIL_SEQ_RegTask+0x40>)
|
|
800c92e: 687b ldr r3, [r7, #4]
|
|
800c930: f842 3021 str.w r3, [r2, r1, lsl #2]
|
|
800c934: 69fb ldr r3, [r7, #28]
|
|
800c936: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c938: 69bb ldr r3, [r7, #24]
|
|
800c93a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c93e: bf00 nop
|
|
|
|
UTIL_SEQ_EXIT_CRITICAL_SECTION();
|
|
|
|
return;
|
|
800c940: bf00 nop
|
|
}
|
|
800c942: 3720 adds r7, #32
|
|
800c944: 46bd mov sp, r7
|
|
800c946: bd80 pop {r7, pc}
|
|
800c948: 200009c0 .word 0x200009c0
|
|
|
|
0800c94c <UTIL_SEQ_SetTask>:
|
|
|
|
void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm , uint32_t Task_Prio )
|
|
{
|
|
800c94c: b480 push {r7}
|
|
800c94e: b087 sub sp, #28
|
|
800c950: af00 add r7, sp, #0
|
|
800c952: 6078 str r0, [r7, #4]
|
|
800c954: 6039 str r1, [r7, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800c956: f3ef 8310 mrs r3, PRIMASK
|
|
800c95a: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800c95c: 68fb ldr r3, [r7, #12]
|
|
UTIL_SEQ_ENTER_CRITICAL_SECTION( );
|
|
800c95e: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800c960: b672 cpsid i
|
|
}
|
|
800c962: bf00 nop
|
|
|
|
TaskSet |= TaskId_bm;
|
|
800c964: 4b0d ldr r3, [pc, #52] @ (800c99c <UTIL_SEQ_SetTask+0x50>)
|
|
800c966: 681a ldr r2, [r3, #0]
|
|
800c968: 687b ldr r3, [r7, #4]
|
|
800c96a: 4313 orrs r3, r2
|
|
800c96c: 4a0b ldr r2, [pc, #44] @ (800c99c <UTIL_SEQ_SetTask+0x50>)
|
|
800c96e: 6013 str r3, [r2, #0]
|
|
TaskPrio[Task_Prio].priority |= TaskId_bm;
|
|
800c970: 4a0b ldr r2, [pc, #44] @ (800c9a0 <UTIL_SEQ_SetTask+0x54>)
|
|
800c972: 683b ldr r3, [r7, #0]
|
|
800c974: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
800c978: 687b ldr r3, [r7, #4]
|
|
800c97a: 431a orrs r2, r3
|
|
800c97c: 4908 ldr r1, [pc, #32] @ (800c9a0 <UTIL_SEQ_SetTask+0x54>)
|
|
800c97e: 683b ldr r3, [r7, #0]
|
|
800c980: f841 2033 str.w r2, [r1, r3, lsl #3]
|
|
800c984: 697b ldr r3, [r7, #20]
|
|
800c986: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800c988: 693b ldr r3, [r7, #16]
|
|
800c98a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800c98e: bf00 nop
|
|
|
|
UTIL_SEQ_EXIT_CRITICAL_SECTION( );
|
|
|
|
return;
|
|
800c990: bf00 nop
|
|
}
|
|
800c992: 371c adds r7, #28
|
|
800c994: 46bd mov sp, r7
|
|
800c996: bc80 pop {r7}
|
|
800c998: 4770 bx lr
|
|
800c99a: bf00 nop
|
|
800c99c: 200009b0 .word 0x200009b0
|
|
800c9a0: 200009c4 .word 0x200009c4
|
|
|
|
0800c9a4 <UTIL_SEQ_PreIdle>:
|
|
{
|
|
return;
|
|
}
|
|
|
|
__WEAK void UTIL_SEQ_PreIdle( void )
|
|
{
|
|
800c9a4: b480 push {r7}
|
|
800c9a6: af00 add r7, sp, #0
|
|
/*
|
|
* Unless specified by the application, there is nothing to be done
|
|
*/
|
|
return;
|
|
800c9a8: bf00 nop
|
|
}
|
|
800c9aa: 46bd mov sp, r7
|
|
800c9ac: bc80 pop {r7}
|
|
800c9ae: 4770 bx lr
|
|
|
|
0800c9b0 <UTIL_SEQ_PostIdle>:
|
|
|
|
__WEAK void UTIL_SEQ_PostIdle( void )
|
|
{
|
|
800c9b0: b480 push {r7}
|
|
800c9b2: af00 add r7, sp, #0
|
|
/*
|
|
* Unless specified by the application, there is nothing to be done
|
|
*/
|
|
return;
|
|
800c9b4: bf00 nop
|
|
}
|
|
800c9b6: 46bd mov sp, r7
|
|
800c9b8: bc80 pop {r7}
|
|
800c9ba: 4770 bx lr
|
|
|
|
0800c9bc <SEQ_BitPosition>:
|
|
* @brief return the position of the first bit set to 1
|
|
* @param Value 32 bit value
|
|
* @retval bit position
|
|
*/
|
|
uint8_t SEQ_BitPosition(uint32_t Value)
|
|
{
|
|
800c9bc: b480 push {r7}
|
|
800c9be: b085 sub sp, #20
|
|
800c9c0: af00 add r7, sp, #0
|
|
800c9c2: 6078 str r0, [r7, #4]
|
|
uint8_t n = 0U;
|
|
800c9c4: 2300 movs r3, #0
|
|
800c9c6: 73fb strb r3, [r7, #15]
|
|
uint32_t lvalue = Value;
|
|
800c9c8: 687b ldr r3, [r7, #4]
|
|
800c9ca: 60bb str r3, [r7, #8]
|
|
|
|
if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; }
|
|
800c9cc: 68bb ldr r3, [r7, #8]
|
|
800c9ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800c9d2: d204 bcs.n 800c9de <SEQ_BitPosition+0x22>
|
|
800c9d4: 2310 movs r3, #16
|
|
800c9d6: 73fb strb r3, [r7, #15]
|
|
800c9d8: 68bb ldr r3, [r7, #8]
|
|
800c9da: 041b lsls r3, r3, #16
|
|
800c9dc: 60bb str r3, [r7, #8]
|
|
if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; }
|
|
800c9de: 68bb ldr r3, [r7, #8]
|
|
800c9e0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
800c9e4: d205 bcs.n 800c9f2 <SEQ_BitPosition+0x36>
|
|
800c9e6: 7bfb ldrb r3, [r7, #15]
|
|
800c9e8: 3308 adds r3, #8
|
|
800c9ea: 73fb strb r3, [r7, #15]
|
|
800c9ec: 68bb ldr r3, [r7, #8]
|
|
800c9ee: 021b lsls r3, r3, #8
|
|
800c9f0: 60bb str r3, [r7, #8]
|
|
if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; }
|
|
800c9f2: 68bb ldr r3, [r7, #8]
|
|
800c9f4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
800c9f8: d205 bcs.n 800ca06 <SEQ_BitPosition+0x4a>
|
|
800c9fa: 7bfb ldrb r3, [r7, #15]
|
|
800c9fc: 3304 adds r3, #4
|
|
800c9fe: 73fb strb r3, [r7, #15]
|
|
800ca00: 68bb ldr r3, [r7, #8]
|
|
800ca02: 011b lsls r3, r3, #4
|
|
800ca04: 60bb str r3, [r7, #8]
|
|
|
|
n += SEQ_clz_table_4bit[lvalue >> (32-4)];
|
|
800ca06: 68bb ldr r3, [r7, #8]
|
|
800ca08: 0f1b lsrs r3, r3, #28
|
|
800ca0a: 4a07 ldr r2, [pc, #28] @ (800ca28 <SEQ_BitPosition+0x6c>)
|
|
800ca0c: 5cd2 ldrb r2, [r2, r3]
|
|
800ca0e: 7bfb ldrb r3, [r7, #15]
|
|
800ca10: 4413 add r3, r2
|
|
800ca12: 73fb strb r3, [r7, #15]
|
|
|
|
return (uint8_t)(31U-n);
|
|
800ca14: 7bfb ldrb r3, [r7, #15]
|
|
800ca16: f1c3 031f rsb r3, r3, #31
|
|
800ca1a: b2db uxtb r3, r3
|
|
}
|
|
800ca1c: 4618 mov r0, r3
|
|
800ca1e: 3714 adds r7, #20
|
|
800ca20: 46bd mov sp, r7
|
|
800ca22: bc80 pop {r7}
|
|
800ca24: 4770 bx lr
|
|
800ca26: bf00 nop
|
|
800ca28: 0800db20 .word 0x0800db20
|
|
|
|
0800ca2c <UTIL_TIMER_Init>:
|
|
* @addtogroup TIMER_SERVER_exported_function
|
|
* @{
|
|
*/
|
|
|
|
UTIL_TIMER_Status_t UTIL_TIMER_Init(void)
|
|
{
|
|
800ca2c: b580 push {r7, lr}
|
|
800ca2e: af00 add r7, sp, #0
|
|
UTIL_TIMER_INIT_CRITICAL_SECTION();
|
|
TimerListHead = NULL;
|
|
800ca30: 4b04 ldr r3, [pc, #16] @ (800ca44 <UTIL_TIMER_Init+0x18>)
|
|
800ca32: 2200 movs r2, #0
|
|
800ca34: 601a str r2, [r3, #0]
|
|
return UTIL_TimerDriver.InitTimer();
|
|
800ca36: 4b04 ldr r3, [pc, #16] @ (800ca48 <UTIL_TIMER_Init+0x1c>)
|
|
800ca38: 681b ldr r3, [r3, #0]
|
|
800ca3a: 4798 blx r3
|
|
800ca3c: 4603 mov r3, r0
|
|
}
|
|
800ca3e: 4618 mov r0, r3
|
|
800ca40: bd80 pop {r7, pc}
|
|
800ca42: bf00 nop
|
|
800ca44: 200009cc .word 0x200009cc
|
|
800ca48: 0800d968 .word 0x0800d968
|
|
|
|
0800ca4c <UTIL_TIMER_Create>:
|
|
{
|
|
return UTIL_TimerDriver.DeInitTimer();
|
|
}
|
|
|
|
UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument)
|
|
{
|
|
800ca4c: b580 push {r7, lr}
|
|
800ca4e: b084 sub sp, #16
|
|
800ca50: af00 add r7, sp, #0
|
|
800ca52: 60f8 str r0, [r7, #12]
|
|
800ca54: 60b9 str r1, [r7, #8]
|
|
800ca56: 603b str r3, [r7, #0]
|
|
800ca58: 4613 mov r3, r2
|
|
800ca5a: 71fb strb r3, [r7, #7]
|
|
if((TimerObject != NULL) && (Callback != NULL))
|
|
800ca5c: 68fb ldr r3, [r7, #12]
|
|
800ca5e: 2b00 cmp r3, #0
|
|
800ca60: d023 beq.n 800caaa <UTIL_TIMER_Create+0x5e>
|
|
800ca62: 683b ldr r3, [r7, #0]
|
|
800ca64: 2b00 cmp r3, #0
|
|
800ca66: d020 beq.n 800caaa <UTIL_TIMER_Create+0x5e>
|
|
{
|
|
TimerObject->Timestamp = 0U;
|
|
800ca68: 68fb ldr r3, [r7, #12]
|
|
800ca6a: 2200 movs r2, #0
|
|
800ca6c: 601a str r2, [r3, #0]
|
|
TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue);
|
|
800ca6e: 4b11 ldr r3, [pc, #68] @ (800cab4 <UTIL_TIMER_Create+0x68>)
|
|
800ca70: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800ca72: 68b8 ldr r0, [r7, #8]
|
|
800ca74: 4798 blx r3
|
|
800ca76: 4602 mov r2, r0
|
|
800ca78: 68fb ldr r3, [r7, #12]
|
|
800ca7a: 605a str r2, [r3, #4]
|
|
TimerObject->IsPending = 0U;
|
|
800ca7c: 68fb ldr r3, [r7, #12]
|
|
800ca7e: 2200 movs r2, #0
|
|
800ca80: 721a strb r2, [r3, #8]
|
|
TimerObject->IsRunning = 0U;
|
|
800ca82: 68fb ldr r3, [r7, #12]
|
|
800ca84: 2200 movs r2, #0
|
|
800ca86: 725a strb r2, [r3, #9]
|
|
TimerObject->IsReloadStopped = 0U;
|
|
800ca88: 68fb ldr r3, [r7, #12]
|
|
800ca8a: 2200 movs r2, #0
|
|
800ca8c: 729a strb r2, [r3, #10]
|
|
TimerObject->Callback = Callback;
|
|
800ca8e: 68fb ldr r3, [r7, #12]
|
|
800ca90: 683a ldr r2, [r7, #0]
|
|
800ca92: 60da str r2, [r3, #12]
|
|
TimerObject->argument = Argument;
|
|
800ca94: 68fb ldr r3, [r7, #12]
|
|
800ca96: 69ba ldr r2, [r7, #24]
|
|
800ca98: 611a str r2, [r3, #16]
|
|
TimerObject->Mode = Mode;
|
|
800ca9a: 68fb ldr r3, [r7, #12]
|
|
800ca9c: 79fa ldrb r2, [r7, #7]
|
|
800ca9e: 72da strb r2, [r3, #11]
|
|
TimerObject->Next = NULL;
|
|
800caa0: 68fb ldr r3, [r7, #12]
|
|
800caa2: 2200 movs r2, #0
|
|
800caa4: 615a str r2, [r3, #20]
|
|
return UTIL_TIMER_OK;
|
|
800caa6: 2300 movs r3, #0
|
|
800caa8: e000 b.n 800caac <UTIL_TIMER_Create+0x60>
|
|
}
|
|
else
|
|
{
|
|
return UTIL_TIMER_INVALID_PARAM;
|
|
800caaa: 2301 movs r3, #1
|
|
}
|
|
}
|
|
800caac: 4618 mov r0, r3
|
|
800caae: 3710 adds r7, #16
|
|
800cab0: 46bd mov sp, r7
|
|
800cab2: bd80 pop {r7, pc}
|
|
800cab4: 0800d968 .word 0x0800d968
|
|
|
|
0800cab8 <UTIL_TIMER_Start>:
|
|
|
|
UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject)
|
|
{
|
|
800cab8: b580 push {r7, lr}
|
|
800caba: b08a sub sp, #40 @ 0x28
|
|
800cabc: af00 add r7, sp, #0
|
|
800cabe: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
800cac0: 2300 movs r3, #0
|
|
800cac2: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint32_t elapsedTime;
|
|
uint32_t minValue;
|
|
uint32_t ticks;
|
|
|
|
if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U))
|
|
800cac6: 687b ldr r3, [r7, #4]
|
|
800cac8: 2b00 cmp r3, #0
|
|
800caca: d056 beq.n 800cb7a <UTIL_TIMER_Start+0xc2>
|
|
800cacc: 6878 ldr r0, [r7, #4]
|
|
800cace: f000 f9a9 bl 800ce24 <TimerExists>
|
|
800cad2: 4603 mov r3, r0
|
|
800cad4: f083 0301 eor.w r3, r3, #1
|
|
800cad8: b2db uxtb r3, r3
|
|
800cada: 2b00 cmp r3, #0
|
|
800cadc: d04d beq.n 800cb7a <UTIL_TIMER_Start+0xc2>
|
|
800cade: 687b ldr r3, [r7, #4]
|
|
800cae0: 7a5b ldrb r3, [r3, #9]
|
|
800cae2: 2b00 cmp r3, #0
|
|
800cae4: d149 bne.n 800cb7a <UTIL_TIMER_Start+0xc2>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800cae6: f3ef 8310 mrs r3, PRIMASK
|
|
800caea: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800caec: 693b ldr r3, [r7, #16]
|
|
{
|
|
UTIL_TIMER_ENTER_CRITICAL_SECTION();
|
|
800caee: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800caf0: b672 cpsid i
|
|
}
|
|
800caf2: bf00 nop
|
|
ticks = TimerObject->ReloadValue;
|
|
800caf4: 687b ldr r3, [r7, #4]
|
|
800caf6: 685b ldr r3, [r3, #4]
|
|
800caf8: 623b str r3, [r7, #32]
|
|
minValue = UTIL_TimerDriver.GetMinimumTimeout( );
|
|
800cafa: 4b24 ldr r3, [pc, #144] @ (800cb8c <UTIL_TIMER_Start+0xd4>)
|
|
800cafc: 6a1b ldr r3, [r3, #32]
|
|
800cafe: 4798 blx r3
|
|
800cb00: 61b8 str r0, [r7, #24]
|
|
|
|
if( ticks < minValue )
|
|
800cb02: 6a3a ldr r2, [r7, #32]
|
|
800cb04: 69bb ldr r3, [r7, #24]
|
|
800cb06: 429a cmp r2, r3
|
|
800cb08: d201 bcs.n 800cb0e <UTIL_TIMER_Start+0x56>
|
|
{
|
|
ticks = minValue;
|
|
800cb0a: 69bb ldr r3, [r7, #24]
|
|
800cb0c: 623b str r3, [r7, #32]
|
|
}
|
|
|
|
TimerObject->Timestamp = ticks;
|
|
800cb0e: 687b ldr r3, [r7, #4]
|
|
800cb10: 6a3a ldr r2, [r7, #32]
|
|
800cb12: 601a str r2, [r3, #0]
|
|
TimerObject->IsPending = 0U;
|
|
800cb14: 687b ldr r3, [r7, #4]
|
|
800cb16: 2200 movs r2, #0
|
|
800cb18: 721a strb r2, [r3, #8]
|
|
TimerObject->IsRunning = 1U;
|
|
800cb1a: 687b ldr r3, [r7, #4]
|
|
800cb1c: 2201 movs r2, #1
|
|
800cb1e: 725a strb r2, [r3, #9]
|
|
TimerObject->IsReloadStopped = 0U;
|
|
800cb20: 687b ldr r3, [r7, #4]
|
|
800cb22: 2200 movs r2, #0
|
|
800cb24: 729a strb r2, [r3, #10]
|
|
if( TimerListHead == NULL )
|
|
800cb26: 4b1a ldr r3, [pc, #104] @ (800cb90 <UTIL_TIMER_Start+0xd8>)
|
|
800cb28: 681b ldr r3, [r3, #0]
|
|
800cb2a: 2b00 cmp r3, #0
|
|
800cb2c: d106 bne.n 800cb3c <UTIL_TIMER_Start+0x84>
|
|
{
|
|
UTIL_TimerDriver.SetTimerContext();
|
|
800cb2e: 4b17 ldr r3, [pc, #92] @ (800cb8c <UTIL_TIMER_Start+0xd4>)
|
|
800cb30: 691b ldr r3, [r3, #16]
|
|
800cb32: 4798 blx r3
|
|
TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */
|
|
800cb34: 6878 ldr r0, [r7, #4]
|
|
800cb36: f000 f9eb bl 800cf10 <TimerInsertNewHeadTimer>
|
|
800cb3a: e017 b.n 800cb6c <UTIL_TIMER_Start+0xb4>
|
|
}
|
|
else
|
|
{
|
|
elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( );
|
|
800cb3c: 4b13 ldr r3, [pc, #76] @ (800cb8c <UTIL_TIMER_Start+0xd4>)
|
|
800cb3e: 699b ldr r3, [r3, #24]
|
|
800cb40: 4798 blx r3
|
|
800cb42: 6178 str r0, [r7, #20]
|
|
TimerObject->Timestamp += elapsedTime;
|
|
800cb44: 687b ldr r3, [r7, #4]
|
|
800cb46: 681a ldr r2, [r3, #0]
|
|
800cb48: 697b ldr r3, [r7, #20]
|
|
800cb4a: 441a add r2, r3
|
|
800cb4c: 687b ldr r3, [r7, #4]
|
|
800cb4e: 601a str r2, [r3, #0]
|
|
|
|
if( TimerObject->Timestamp < TimerListHead->Timestamp )
|
|
800cb50: 687b ldr r3, [r7, #4]
|
|
800cb52: 681a ldr r2, [r3, #0]
|
|
800cb54: 4b0e ldr r3, [pc, #56] @ (800cb90 <UTIL_TIMER_Start+0xd8>)
|
|
800cb56: 681b ldr r3, [r3, #0]
|
|
800cb58: 681b ldr r3, [r3, #0]
|
|
800cb5a: 429a cmp r2, r3
|
|
800cb5c: d203 bcs.n 800cb66 <UTIL_TIMER_Start+0xae>
|
|
{
|
|
TimerInsertNewHeadTimer( TimerObject);
|
|
800cb5e: 6878 ldr r0, [r7, #4]
|
|
800cb60: f000 f9d6 bl 800cf10 <TimerInsertNewHeadTimer>
|
|
800cb64: e002 b.n 800cb6c <UTIL_TIMER_Start+0xb4>
|
|
}
|
|
else
|
|
{
|
|
TimerInsertTimer( TimerObject);
|
|
800cb66: 6878 ldr r0, [r7, #4]
|
|
800cb68: f000 f9a2 bl 800ceb0 <TimerInsertTimer>
|
|
800cb6c: 69fb ldr r3, [r7, #28]
|
|
800cb6e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800cb70: 68fb ldr r3, [r7, #12]
|
|
800cb72: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800cb76: bf00 nop
|
|
{
|
|
800cb78: e002 b.n 800cb80 <UTIL_TIMER_Start+0xc8>
|
|
}
|
|
UTIL_TIMER_EXIT_CRITICAL_SECTION();
|
|
}
|
|
else
|
|
{
|
|
ret = UTIL_TIMER_INVALID_PARAM;
|
|
800cb7a: 2301 movs r3, #1
|
|
800cb7c: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
return ret;
|
|
800cb80: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
800cb84: 4618 mov r0, r3
|
|
800cb86: 3728 adds r7, #40 @ 0x28
|
|
800cb88: 46bd mov sp, r7
|
|
800cb8a: bd80 pop {r7, pc}
|
|
800cb8c: 0800d968 .word 0x0800d968
|
|
800cb90: 200009cc .word 0x200009cc
|
|
|
|
0800cb94 <UTIL_TIMER_Stop>:
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject )
|
|
{
|
|
800cb94: b580 push {r7, lr}
|
|
800cb96: b088 sub sp, #32
|
|
800cb98: af00 add r7, sp, #0
|
|
800cb9a: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
800cb9c: 2300 movs r3, #0
|
|
800cb9e: 77fb strb r3, [r7, #31]
|
|
|
|
if (NULL != TimerObject)
|
|
800cba0: 687b ldr r3, [r7, #4]
|
|
800cba2: 2b00 cmp r3, #0
|
|
800cba4: d05b beq.n 800cc5e <UTIL_TIMER_Stop+0xca>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800cba6: f3ef 8310 mrs r3, PRIMASK
|
|
800cbaa: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800cbac: 68fb ldr r3, [r7, #12]
|
|
{
|
|
UTIL_TIMER_ENTER_CRITICAL_SECTION();
|
|
800cbae: 613b str r3, [r7, #16]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800cbb0: b672 cpsid i
|
|
}
|
|
800cbb2: bf00 nop
|
|
UTIL_TIMER_Object_t* prev = TimerListHead;
|
|
800cbb4: 4b2d ldr r3, [pc, #180] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbb6: 681b ldr r3, [r3, #0]
|
|
800cbb8: 61bb str r3, [r7, #24]
|
|
UTIL_TIMER_Object_t* cur = TimerListHead;
|
|
800cbba: 4b2c ldr r3, [pc, #176] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbbc: 681b ldr r3, [r3, #0]
|
|
800cbbe: 617b str r3, [r7, #20]
|
|
TimerObject->IsReloadStopped = 1U;
|
|
800cbc0: 687b ldr r3, [r7, #4]
|
|
800cbc2: 2201 movs r2, #1
|
|
800cbc4: 729a strb r2, [r3, #10]
|
|
|
|
/* List is empty or the Obj to stop does not exist */
|
|
if(NULL != TimerListHead)
|
|
800cbc6: 4b29 ldr r3, [pc, #164] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbc8: 681b ldr r3, [r3, #0]
|
|
800cbca: 2b00 cmp r3, #0
|
|
800cbcc: d041 beq.n 800cc52 <UTIL_TIMER_Stop+0xbe>
|
|
{
|
|
TimerObject->IsRunning = 0U;
|
|
800cbce: 687b ldr r3, [r7, #4]
|
|
800cbd0: 2200 movs r2, #0
|
|
800cbd2: 725a strb r2, [r3, #9]
|
|
|
|
if( TimerListHead == TimerObject ) /* Stop the Head */
|
|
800cbd4: 4b25 ldr r3, [pc, #148] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbd6: 681b ldr r3, [r3, #0]
|
|
800cbd8: 687a ldr r2, [r7, #4]
|
|
800cbda: 429a cmp r2, r3
|
|
800cbdc: d134 bne.n 800cc48 <UTIL_TIMER_Stop+0xb4>
|
|
{
|
|
TimerListHead->IsPending = 0;
|
|
800cbde: 4b23 ldr r3, [pc, #140] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbe0: 681b ldr r3, [r3, #0]
|
|
800cbe2: 2200 movs r2, #0
|
|
800cbe4: 721a strb r2, [r3, #8]
|
|
if( TimerListHead->Next != NULL )
|
|
800cbe6: 4b21 ldr r3, [pc, #132] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbe8: 681b ldr r3, [r3, #0]
|
|
800cbea: 695b ldr r3, [r3, #20]
|
|
800cbec: 2b00 cmp r3, #0
|
|
800cbee: d00a beq.n 800cc06 <UTIL_TIMER_Stop+0x72>
|
|
{
|
|
TimerListHead = TimerListHead->Next;
|
|
800cbf0: 4b1e ldr r3, [pc, #120] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbf2: 681b ldr r3, [r3, #0]
|
|
800cbf4: 695b ldr r3, [r3, #20]
|
|
800cbf6: 4a1d ldr r2, [pc, #116] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbf8: 6013 str r3, [r2, #0]
|
|
TimerSetTimeout( TimerListHead );
|
|
800cbfa: 4b1c ldr r3, [pc, #112] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cbfc: 681b ldr r3, [r3, #0]
|
|
800cbfe: 4618 mov r0, r3
|
|
800cc00: f000 f92c bl 800ce5c <TimerSetTimeout>
|
|
800cc04: e023 b.n 800cc4e <UTIL_TIMER_Stop+0xba>
|
|
}
|
|
else
|
|
{
|
|
UTIL_TimerDriver.StopTimerEvt( );
|
|
800cc06: 4b1a ldr r3, [pc, #104] @ (800cc70 <UTIL_TIMER_Stop+0xdc>)
|
|
800cc08: 68db ldr r3, [r3, #12]
|
|
800cc0a: 4798 blx r3
|
|
TimerListHead = NULL;
|
|
800cc0c: 4b17 ldr r3, [pc, #92] @ (800cc6c <UTIL_TIMER_Stop+0xd8>)
|
|
800cc0e: 2200 movs r2, #0
|
|
800cc10: 601a str r2, [r3, #0]
|
|
800cc12: e01c b.n 800cc4e <UTIL_TIMER_Stop+0xba>
|
|
}
|
|
else /* Stop an object within the list */
|
|
{
|
|
while( cur != NULL )
|
|
{
|
|
if( cur == TimerObject )
|
|
800cc14: 697a ldr r2, [r7, #20]
|
|
800cc16: 687b ldr r3, [r7, #4]
|
|
800cc18: 429a cmp r2, r3
|
|
800cc1a: d110 bne.n 800cc3e <UTIL_TIMER_Stop+0xaa>
|
|
{
|
|
if( cur->Next != NULL )
|
|
800cc1c: 697b ldr r3, [r7, #20]
|
|
800cc1e: 695b ldr r3, [r3, #20]
|
|
800cc20: 2b00 cmp r3, #0
|
|
800cc22: d006 beq.n 800cc32 <UTIL_TIMER_Stop+0x9e>
|
|
{
|
|
cur = cur->Next;
|
|
800cc24: 697b ldr r3, [r7, #20]
|
|
800cc26: 695b ldr r3, [r3, #20]
|
|
800cc28: 617b str r3, [r7, #20]
|
|
prev->Next = cur;
|
|
800cc2a: 69bb ldr r3, [r7, #24]
|
|
800cc2c: 697a ldr r2, [r7, #20]
|
|
800cc2e: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
cur = NULL;
|
|
prev->Next = cur;
|
|
}
|
|
break;
|
|
800cc30: e00d b.n 800cc4e <UTIL_TIMER_Stop+0xba>
|
|
cur = NULL;
|
|
800cc32: 2300 movs r3, #0
|
|
800cc34: 617b str r3, [r7, #20]
|
|
prev->Next = cur;
|
|
800cc36: 69bb ldr r3, [r7, #24]
|
|
800cc38: 697a ldr r2, [r7, #20]
|
|
800cc3a: 615a str r2, [r3, #20]
|
|
break;
|
|
800cc3c: e007 b.n 800cc4e <UTIL_TIMER_Stop+0xba>
|
|
}
|
|
else
|
|
{
|
|
prev = cur;
|
|
800cc3e: 697b ldr r3, [r7, #20]
|
|
800cc40: 61bb str r3, [r7, #24]
|
|
cur = cur->Next;
|
|
800cc42: 697b ldr r3, [r7, #20]
|
|
800cc44: 695b ldr r3, [r3, #20]
|
|
800cc46: 617b str r3, [r7, #20]
|
|
while( cur != NULL )
|
|
800cc48: 697b ldr r3, [r7, #20]
|
|
800cc4a: 2b00 cmp r3, #0
|
|
800cc4c: d1e2 bne.n 800cc14 <UTIL_TIMER_Stop+0x80>
|
|
}
|
|
}
|
|
}
|
|
ret = UTIL_TIMER_OK;
|
|
800cc4e: 2300 movs r3, #0
|
|
800cc50: 77fb strb r3, [r7, #31]
|
|
800cc52: 693b ldr r3, [r7, #16]
|
|
800cc54: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800cc56: 68bb ldr r3, [r7, #8]
|
|
800cc58: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800cc5c: e001 b.n 800cc62 <UTIL_TIMER_Stop+0xce>
|
|
}
|
|
UTIL_TIMER_EXIT_CRITICAL_SECTION();
|
|
}
|
|
else
|
|
{
|
|
ret = UTIL_TIMER_INVALID_PARAM;
|
|
800cc5e: 2301 movs r3, #1
|
|
800cc60: 77fb strb r3, [r7, #31]
|
|
}
|
|
return ret;
|
|
800cc62: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
800cc64: 4618 mov r0, r3
|
|
800cc66: 3720 adds r7, #32
|
|
800cc68: 46bd mov sp, r7
|
|
800cc6a: bd80 pop {r7, pc}
|
|
800cc6c: 200009cc .word 0x200009cc
|
|
800cc70: 0800d968 .word 0x0800d968
|
|
|
|
0800cc74 <UTIL_TIMER_SetPeriod>:
|
|
|
|
UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue)
|
|
{
|
|
800cc74: b580 push {r7, lr}
|
|
800cc76: b084 sub sp, #16
|
|
800cc78: af00 add r7, sp, #0
|
|
800cc7a: 6078 str r0, [r7, #4]
|
|
800cc7c: 6039 str r1, [r7, #0]
|
|
UTIL_TIMER_Status_t ret = UTIL_TIMER_OK;
|
|
800cc7e: 2300 movs r3, #0
|
|
800cc80: 73fb strb r3, [r7, #15]
|
|
|
|
if(NULL == TimerObject)
|
|
800cc82: 687b ldr r3, [r7, #4]
|
|
800cc84: 2b00 cmp r3, #0
|
|
800cc86: d102 bne.n 800cc8e <UTIL_TIMER_SetPeriod+0x1a>
|
|
{
|
|
ret = UTIL_TIMER_INVALID_PARAM;
|
|
800cc88: 2301 movs r3, #1
|
|
800cc8a: 73fb strb r3, [r7, #15]
|
|
800cc8c: e014 b.n 800ccb8 <UTIL_TIMER_SetPeriod+0x44>
|
|
}
|
|
else
|
|
{
|
|
TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue);
|
|
800cc8e: 4b0d ldr r3, [pc, #52] @ (800ccc4 <UTIL_TIMER_SetPeriod+0x50>)
|
|
800cc90: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800cc92: 6838 ldr r0, [r7, #0]
|
|
800cc94: 4798 blx r3
|
|
800cc96: 4602 mov r2, r0
|
|
800cc98: 687b ldr r3, [r7, #4]
|
|
800cc9a: 605a str r2, [r3, #4]
|
|
if(TimerExists(TimerObject))
|
|
800cc9c: 6878 ldr r0, [r7, #4]
|
|
800cc9e: f000 f8c1 bl 800ce24 <TimerExists>
|
|
800cca2: 4603 mov r3, r0
|
|
800cca4: 2b00 cmp r3, #0
|
|
800cca6: d007 beq.n 800ccb8 <UTIL_TIMER_SetPeriod+0x44>
|
|
{
|
|
(void)UTIL_TIMER_Stop(TimerObject);
|
|
800cca8: 6878 ldr r0, [r7, #4]
|
|
800ccaa: f7ff ff73 bl 800cb94 <UTIL_TIMER_Stop>
|
|
ret = UTIL_TIMER_Start(TimerObject);
|
|
800ccae: 6878 ldr r0, [r7, #4]
|
|
800ccb0: f7ff ff02 bl 800cab8 <UTIL_TIMER_Start>
|
|
800ccb4: 4603 mov r3, r0
|
|
800ccb6: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
return ret;
|
|
800ccb8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800ccba: 4618 mov r0, r3
|
|
800ccbc: 3710 adds r7, #16
|
|
800ccbe: 46bd mov sp, r7
|
|
800ccc0: bd80 pop {r7, pc}
|
|
800ccc2: bf00 nop
|
|
800ccc4: 0800d968 .word 0x0800d968
|
|
|
|
0800ccc8 <UTIL_TIMER_IRQ_Handler>:
|
|
}
|
|
return NextTimer;
|
|
}
|
|
|
|
void UTIL_TIMER_IRQ_Handler( void )
|
|
{
|
|
800ccc8: b590 push {r4, r7, lr}
|
|
800ccca: b089 sub sp, #36 @ 0x24
|
|
800cccc: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800ccce: f3ef 8310 mrs r3, PRIMASK
|
|
800ccd2: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
800ccd4: 68bb ldr r3, [r7, #8]
|
|
UTIL_TIMER_Object_t* cur;
|
|
uint32_t old, now, DeltaContext;
|
|
|
|
UTIL_TIMER_ENTER_CRITICAL_SECTION();
|
|
800ccd6: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800ccd8: b672 cpsid i
|
|
}
|
|
800ccda: bf00 nop
|
|
|
|
old = UTIL_TimerDriver.GetTimerContext( );
|
|
800ccdc: 4b38 ldr r3, [pc, #224] @ (800cdc0 <UTIL_TIMER_IRQ_Handler+0xf8>)
|
|
800ccde: 695b ldr r3, [r3, #20]
|
|
800cce0: 4798 blx r3
|
|
800cce2: 6178 str r0, [r7, #20]
|
|
now = UTIL_TimerDriver.SetTimerContext( );
|
|
800cce4: 4b36 ldr r3, [pc, #216] @ (800cdc0 <UTIL_TIMER_IRQ_Handler+0xf8>)
|
|
800cce6: 691b ldr r3, [r3, #16]
|
|
800cce8: 4798 blx r3
|
|
800ccea: 6138 str r0, [r7, #16]
|
|
|
|
DeltaContext = now - old; /*intentional wrap around */
|
|
800ccec: 693a ldr r2, [r7, #16]
|
|
800ccee: 697b ldr r3, [r7, #20]
|
|
800ccf0: 1ad3 subs r3, r2, r3
|
|
800ccf2: 60fb str r3, [r7, #12]
|
|
|
|
/* update timeStamp based upon new Time Reference*/
|
|
/* because delta context should never exceed 2^32*/
|
|
if ( TimerListHead != NULL )
|
|
800ccf4: 4b33 ldr r3, [pc, #204] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800ccf6: 681b ldr r3, [r3, #0]
|
|
800ccf8: 2b00 cmp r3, #0
|
|
800ccfa: d037 beq.n 800cd6c <UTIL_TIMER_IRQ_Handler+0xa4>
|
|
{
|
|
cur = TimerListHead;
|
|
800ccfc: 4b31 ldr r3, [pc, #196] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800ccfe: 681b ldr r3, [r3, #0]
|
|
800cd00: 61fb str r3, [r7, #28]
|
|
do {
|
|
if (cur->Timestamp > DeltaContext)
|
|
800cd02: 69fb ldr r3, [r7, #28]
|
|
800cd04: 681b ldr r3, [r3, #0]
|
|
800cd06: 68fa ldr r2, [r7, #12]
|
|
800cd08: 429a cmp r2, r3
|
|
800cd0a: d206 bcs.n 800cd1a <UTIL_TIMER_IRQ_Handler+0x52>
|
|
{
|
|
cur->Timestamp -= DeltaContext;
|
|
800cd0c: 69fb ldr r3, [r7, #28]
|
|
800cd0e: 681a ldr r2, [r3, #0]
|
|
800cd10: 68fb ldr r3, [r7, #12]
|
|
800cd12: 1ad2 subs r2, r2, r3
|
|
800cd14: 69fb ldr r3, [r7, #28]
|
|
800cd16: 601a str r2, [r3, #0]
|
|
800cd18: e002 b.n 800cd20 <UTIL_TIMER_IRQ_Handler+0x58>
|
|
}
|
|
else
|
|
{
|
|
cur->Timestamp = 0;
|
|
800cd1a: 69fb ldr r3, [r7, #28]
|
|
800cd1c: 2200 movs r2, #0
|
|
800cd1e: 601a str r2, [r3, #0]
|
|
}
|
|
cur = cur->Next;
|
|
800cd20: 69fb ldr r3, [r7, #28]
|
|
800cd22: 695b ldr r3, [r3, #20]
|
|
800cd24: 61fb str r3, [r7, #28]
|
|
} while(cur != NULL);
|
|
800cd26: 69fb ldr r3, [r7, #28]
|
|
800cd28: 2b00 cmp r3, #0
|
|
800cd2a: d1ea bne.n 800cd02 <UTIL_TIMER_IRQ_Handler+0x3a>
|
|
}
|
|
|
|
/* Execute expired timer and update the list */
|
|
while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( ))))
|
|
800cd2c: e01e b.n 800cd6c <UTIL_TIMER_IRQ_Handler+0xa4>
|
|
{
|
|
cur = TimerListHead;
|
|
800cd2e: 4b25 ldr r3, [pc, #148] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd30: 681b ldr r3, [r3, #0]
|
|
800cd32: 61fb str r3, [r7, #28]
|
|
TimerListHead = TimerListHead->Next;
|
|
800cd34: 4b23 ldr r3, [pc, #140] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd36: 681b ldr r3, [r3, #0]
|
|
800cd38: 695b ldr r3, [r3, #20]
|
|
800cd3a: 4a22 ldr r2, [pc, #136] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd3c: 6013 str r3, [r2, #0]
|
|
cur->IsPending = 0;
|
|
800cd3e: 69fb ldr r3, [r7, #28]
|
|
800cd40: 2200 movs r2, #0
|
|
800cd42: 721a strb r2, [r3, #8]
|
|
cur->IsRunning = 0;
|
|
800cd44: 69fb ldr r3, [r7, #28]
|
|
800cd46: 2200 movs r2, #0
|
|
800cd48: 725a strb r2, [r3, #9]
|
|
cur->Callback(cur->argument);
|
|
800cd4a: 69fb ldr r3, [r7, #28]
|
|
800cd4c: 68db ldr r3, [r3, #12]
|
|
800cd4e: 69fa ldr r2, [r7, #28]
|
|
800cd50: 6912 ldr r2, [r2, #16]
|
|
800cd52: 4610 mov r0, r2
|
|
800cd54: 4798 blx r3
|
|
if(( cur->Mode == UTIL_TIMER_PERIODIC) && (cur->IsReloadStopped == 0U))
|
|
800cd56: 69fb ldr r3, [r7, #28]
|
|
800cd58: 7adb ldrb r3, [r3, #11]
|
|
800cd5a: 2b01 cmp r3, #1
|
|
800cd5c: d106 bne.n 800cd6c <UTIL_TIMER_IRQ_Handler+0xa4>
|
|
800cd5e: 69fb ldr r3, [r7, #28]
|
|
800cd60: 7a9b ldrb r3, [r3, #10]
|
|
800cd62: 2b00 cmp r3, #0
|
|
800cd64: d102 bne.n 800cd6c <UTIL_TIMER_IRQ_Handler+0xa4>
|
|
{
|
|
(void)UTIL_TIMER_Start(cur);
|
|
800cd66: 69f8 ldr r0, [r7, #28]
|
|
800cd68: f7ff fea6 bl 800cab8 <UTIL_TIMER_Start>
|
|
while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( ))))
|
|
800cd6c: 4b15 ldr r3, [pc, #84] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd6e: 681b ldr r3, [r3, #0]
|
|
800cd70: 2b00 cmp r3, #0
|
|
800cd72: d00d beq.n 800cd90 <UTIL_TIMER_IRQ_Handler+0xc8>
|
|
800cd74: 4b13 ldr r3, [pc, #76] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd76: 681b ldr r3, [r3, #0]
|
|
800cd78: 681b ldr r3, [r3, #0]
|
|
800cd7a: 2b00 cmp r3, #0
|
|
800cd7c: d0d7 beq.n 800cd2e <UTIL_TIMER_IRQ_Handler+0x66>
|
|
800cd7e: 4b11 ldr r3, [pc, #68] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd80: 681b ldr r3, [r3, #0]
|
|
800cd82: 681c ldr r4, [r3, #0]
|
|
800cd84: 4b0e ldr r3, [pc, #56] @ (800cdc0 <UTIL_TIMER_IRQ_Handler+0xf8>)
|
|
800cd86: 699b ldr r3, [r3, #24]
|
|
800cd88: 4798 blx r3
|
|
800cd8a: 4603 mov r3, r0
|
|
800cd8c: 429c cmp r4, r3
|
|
800cd8e: d3ce bcc.n 800cd2e <UTIL_TIMER_IRQ_Handler+0x66>
|
|
}
|
|
}
|
|
|
|
/* start the next TimerListHead if it exists and it is not pending*/
|
|
if(( TimerListHead != NULL ) && (TimerListHead->IsPending == 0U))
|
|
800cd90: 4b0c ldr r3, [pc, #48] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd92: 681b ldr r3, [r3, #0]
|
|
800cd94: 2b00 cmp r3, #0
|
|
800cd96: d009 beq.n 800cdac <UTIL_TIMER_IRQ_Handler+0xe4>
|
|
800cd98: 4b0a ldr r3, [pc, #40] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cd9a: 681b ldr r3, [r3, #0]
|
|
800cd9c: 7a1b ldrb r3, [r3, #8]
|
|
800cd9e: 2b00 cmp r3, #0
|
|
800cda0: d104 bne.n 800cdac <UTIL_TIMER_IRQ_Handler+0xe4>
|
|
{
|
|
TimerSetTimeout( TimerListHead );
|
|
800cda2: 4b08 ldr r3, [pc, #32] @ (800cdc4 <UTIL_TIMER_IRQ_Handler+0xfc>)
|
|
800cda4: 681b ldr r3, [r3, #0]
|
|
800cda6: 4618 mov r0, r3
|
|
800cda8: f000 f858 bl 800ce5c <TimerSetTimeout>
|
|
800cdac: 69bb ldr r3, [r7, #24]
|
|
800cdae: 607b str r3, [r7, #4]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800cdb0: 687b ldr r3, [r7, #4]
|
|
800cdb2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800cdb6: bf00 nop
|
|
}
|
|
UTIL_TIMER_EXIT_CRITICAL_SECTION();
|
|
}
|
|
800cdb8: bf00 nop
|
|
800cdba: 3724 adds r7, #36 @ 0x24
|
|
800cdbc: 46bd mov sp, r7
|
|
800cdbe: bd90 pop {r4, r7, pc}
|
|
800cdc0: 0800d968 .word 0x0800d968
|
|
800cdc4: 200009cc .word 0x200009cc
|
|
|
|
0800cdc8 <UTIL_TIMER_GetCurrentTime>:
|
|
|
|
UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void)
|
|
{
|
|
800cdc8: b580 push {r7, lr}
|
|
800cdca: b082 sub sp, #8
|
|
800cdcc: af00 add r7, sp, #0
|
|
uint32_t now = UTIL_TimerDriver.GetTimerValue( );
|
|
800cdce: 4b06 ldr r3, [pc, #24] @ (800cde8 <UTIL_TIMER_GetCurrentTime+0x20>)
|
|
800cdd0: 69db ldr r3, [r3, #28]
|
|
800cdd2: 4798 blx r3
|
|
800cdd4: 6078 str r0, [r7, #4]
|
|
return UTIL_TimerDriver.Tick2ms(now);
|
|
800cdd6: 4b04 ldr r3, [pc, #16] @ (800cde8 <UTIL_TIMER_GetCurrentTime+0x20>)
|
|
800cdd8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800cdda: 6878 ldr r0, [r7, #4]
|
|
800cddc: 4798 blx r3
|
|
800cdde: 4603 mov r3, r0
|
|
}
|
|
800cde0: 4618 mov r0, r3
|
|
800cde2: 3708 adds r7, #8
|
|
800cde4: 46bd mov sp, r7
|
|
800cde6: bd80 pop {r7, pc}
|
|
800cde8: 0800d968 .word 0x0800d968
|
|
|
|
0800cdec <UTIL_TIMER_GetElapsedTime>:
|
|
|
|
UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past )
|
|
{
|
|
800cdec: b580 push {r7, lr}
|
|
800cdee: b084 sub sp, #16
|
|
800cdf0: af00 add r7, sp, #0
|
|
800cdf2: 6078 str r0, [r7, #4]
|
|
uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( );
|
|
800cdf4: 4b0a ldr r3, [pc, #40] @ (800ce20 <UTIL_TIMER_GetElapsedTime+0x34>)
|
|
800cdf6: 69db ldr r3, [r3, #28]
|
|
800cdf8: 4798 blx r3
|
|
800cdfa: 60f8 str r0, [r7, #12]
|
|
uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past );
|
|
800cdfc: 4b08 ldr r3, [pc, #32] @ (800ce20 <UTIL_TIMER_GetElapsedTime+0x34>)
|
|
800cdfe: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800ce00: 6878 ldr r0, [r7, #4]
|
|
800ce02: 4798 blx r3
|
|
800ce04: 60b8 str r0, [r7, #8]
|
|
/* intentional wrap around. Works Ok if tick duation below 1ms */
|
|
return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks );
|
|
800ce06: 4b06 ldr r3, [pc, #24] @ (800ce20 <UTIL_TIMER_GetElapsedTime+0x34>)
|
|
800ce08: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800ce0a: 68f9 ldr r1, [r7, #12]
|
|
800ce0c: 68ba ldr r2, [r7, #8]
|
|
800ce0e: 1a8a subs r2, r1, r2
|
|
800ce10: 4610 mov r0, r2
|
|
800ce12: 4798 blx r3
|
|
800ce14: 4603 mov r3, r0
|
|
}
|
|
800ce16: 4618 mov r0, r3
|
|
800ce18: 3710 adds r7, #16
|
|
800ce1a: 46bd mov sp, r7
|
|
800ce1c: bd80 pop {r7, pc}
|
|
800ce1e: bf00 nop
|
|
800ce20: 0800d968 .word 0x0800d968
|
|
|
|
0800ce24 <TimerExists>:
|
|
*
|
|
* @param TimerObject Structure containing the timer object parameters
|
|
* @retval 1 (the object is already in the list) or 0
|
|
*/
|
|
bool TimerExists( UTIL_TIMER_Object_t *TimerObject )
|
|
{
|
|
800ce24: b480 push {r7}
|
|
800ce26: b085 sub sp, #20
|
|
800ce28: af00 add r7, sp, #0
|
|
800ce2a: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Object_t* cur = TimerListHead;
|
|
800ce2c: 4b0a ldr r3, [pc, #40] @ (800ce58 <TimerExists+0x34>)
|
|
800ce2e: 681b ldr r3, [r3, #0]
|
|
800ce30: 60fb str r3, [r7, #12]
|
|
|
|
while( cur != NULL )
|
|
800ce32: e008 b.n 800ce46 <TimerExists+0x22>
|
|
{
|
|
if( cur == TimerObject )
|
|
800ce34: 68fa ldr r2, [r7, #12]
|
|
800ce36: 687b ldr r3, [r7, #4]
|
|
800ce38: 429a cmp r2, r3
|
|
800ce3a: d101 bne.n 800ce40 <TimerExists+0x1c>
|
|
{
|
|
return true;
|
|
800ce3c: 2301 movs r3, #1
|
|
800ce3e: e006 b.n 800ce4e <TimerExists+0x2a>
|
|
}
|
|
cur = cur->Next;
|
|
800ce40: 68fb ldr r3, [r7, #12]
|
|
800ce42: 695b ldr r3, [r3, #20]
|
|
800ce44: 60fb str r3, [r7, #12]
|
|
while( cur != NULL )
|
|
800ce46: 68fb ldr r3, [r7, #12]
|
|
800ce48: 2b00 cmp r3, #0
|
|
800ce4a: d1f3 bne.n 800ce34 <TimerExists+0x10>
|
|
}
|
|
return false;
|
|
800ce4c: 2300 movs r3, #0
|
|
}
|
|
800ce4e: 4618 mov r0, r3
|
|
800ce50: 3714 adds r7, #20
|
|
800ce52: 46bd mov sp, r7
|
|
800ce54: bc80 pop {r7}
|
|
800ce56: 4770 bx lr
|
|
800ce58: 200009cc .word 0x200009cc
|
|
|
|
0800ce5c <TimerSetTimeout>:
|
|
* @brief Sets a timeout with the duration "timestamp"
|
|
*
|
|
* @param TimerObject Structure containing the timer object parameters
|
|
*/
|
|
void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject )
|
|
{
|
|
800ce5c: b590 push {r4, r7, lr}
|
|
800ce5e: b085 sub sp, #20
|
|
800ce60: af00 add r7, sp, #0
|
|
800ce62: 6078 str r0, [r7, #4]
|
|
uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( );
|
|
800ce64: 4b11 ldr r3, [pc, #68] @ (800ceac <TimerSetTimeout+0x50>)
|
|
800ce66: 6a1b ldr r3, [r3, #32]
|
|
800ce68: 4798 blx r3
|
|
800ce6a: 60f8 str r0, [r7, #12]
|
|
TimerObject->IsPending = 1;
|
|
800ce6c: 687b ldr r3, [r7, #4]
|
|
800ce6e: 2201 movs r2, #1
|
|
800ce70: 721a strb r2, [r3, #8]
|
|
|
|
/* In case deadline too soon */
|
|
if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) )
|
|
800ce72: 687b ldr r3, [r7, #4]
|
|
800ce74: 681c ldr r4, [r3, #0]
|
|
800ce76: 4b0d ldr r3, [pc, #52] @ (800ceac <TimerSetTimeout+0x50>)
|
|
800ce78: 699b ldr r3, [r3, #24]
|
|
800ce7a: 4798 blx r3
|
|
800ce7c: 4602 mov r2, r0
|
|
800ce7e: 68fb ldr r3, [r7, #12]
|
|
800ce80: 4413 add r3, r2
|
|
800ce82: 429c cmp r4, r3
|
|
800ce84: d207 bcs.n 800ce96 <TimerSetTimeout+0x3a>
|
|
{
|
|
TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks;
|
|
800ce86: 4b09 ldr r3, [pc, #36] @ (800ceac <TimerSetTimeout+0x50>)
|
|
800ce88: 699b ldr r3, [r3, #24]
|
|
800ce8a: 4798 blx r3
|
|
800ce8c: 4602 mov r2, r0
|
|
800ce8e: 68fb ldr r3, [r7, #12]
|
|
800ce90: 441a add r2, r3
|
|
800ce92: 687b ldr r3, [r7, #4]
|
|
800ce94: 601a str r2, [r3, #0]
|
|
}
|
|
UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp );
|
|
800ce96: 4b05 ldr r3, [pc, #20] @ (800ceac <TimerSetTimeout+0x50>)
|
|
800ce98: 689b ldr r3, [r3, #8]
|
|
800ce9a: 687a ldr r2, [r7, #4]
|
|
800ce9c: 6812 ldr r2, [r2, #0]
|
|
800ce9e: 4610 mov r0, r2
|
|
800cea0: 4798 blx r3
|
|
}
|
|
800cea2: bf00 nop
|
|
800cea4: 3714 adds r7, #20
|
|
800cea6: 46bd mov sp, r7
|
|
800cea8: bd90 pop {r4, r7, pc}
|
|
800ceaa: bf00 nop
|
|
800ceac: 0800d968 .word 0x0800d968
|
|
|
|
0800ceb0 <TimerInsertTimer>:
|
|
* next timer to expire.
|
|
*
|
|
* @param TimerObject Structure containing the timer object parameters
|
|
*/
|
|
void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject)
|
|
{
|
|
800ceb0: b480 push {r7}
|
|
800ceb2: b085 sub sp, #20
|
|
800ceb4: af00 add r7, sp, #0
|
|
800ceb6: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Object_t* cur = TimerListHead;
|
|
800ceb8: 4b14 ldr r3, [pc, #80] @ (800cf0c <TimerInsertTimer+0x5c>)
|
|
800ceba: 681b ldr r3, [r3, #0]
|
|
800cebc: 60fb str r3, [r7, #12]
|
|
UTIL_TIMER_Object_t* next = TimerListHead->Next;
|
|
800cebe: 4b13 ldr r3, [pc, #76] @ (800cf0c <TimerInsertTimer+0x5c>)
|
|
800cec0: 681b ldr r3, [r3, #0]
|
|
800cec2: 695b ldr r3, [r3, #20]
|
|
800cec4: 60bb str r3, [r7, #8]
|
|
|
|
while (cur->Next != NULL )
|
|
800cec6: e012 b.n 800ceee <TimerInsertTimer+0x3e>
|
|
{
|
|
if( TimerObject->Timestamp > next->Timestamp )
|
|
800cec8: 687b ldr r3, [r7, #4]
|
|
800ceca: 681a ldr r2, [r3, #0]
|
|
800cecc: 68bb ldr r3, [r7, #8]
|
|
800cece: 681b ldr r3, [r3, #0]
|
|
800ced0: 429a cmp r2, r3
|
|
800ced2: d905 bls.n 800cee0 <TimerInsertTimer+0x30>
|
|
{
|
|
cur = next;
|
|
800ced4: 68bb ldr r3, [r7, #8]
|
|
800ced6: 60fb str r3, [r7, #12]
|
|
next = next->Next;
|
|
800ced8: 68bb ldr r3, [r7, #8]
|
|
800ceda: 695b ldr r3, [r3, #20]
|
|
800cedc: 60bb str r3, [r7, #8]
|
|
800cede: e006 b.n 800ceee <TimerInsertTimer+0x3e>
|
|
}
|
|
else
|
|
{
|
|
cur->Next = TimerObject;
|
|
800cee0: 68fb ldr r3, [r7, #12]
|
|
800cee2: 687a ldr r2, [r7, #4]
|
|
800cee4: 615a str r2, [r3, #20]
|
|
TimerObject->Next = next;
|
|
800cee6: 687b ldr r3, [r7, #4]
|
|
800cee8: 68ba ldr r2, [r7, #8]
|
|
800ceea: 615a str r2, [r3, #20]
|
|
return;
|
|
800ceec: e009 b.n 800cf02 <TimerInsertTimer+0x52>
|
|
while (cur->Next != NULL )
|
|
800ceee: 68fb ldr r3, [r7, #12]
|
|
800cef0: 695b ldr r3, [r3, #20]
|
|
800cef2: 2b00 cmp r3, #0
|
|
800cef4: d1e8 bne.n 800cec8 <TimerInsertTimer+0x18>
|
|
|
|
}
|
|
}
|
|
cur->Next = TimerObject;
|
|
800cef6: 68fb ldr r3, [r7, #12]
|
|
800cef8: 687a ldr r2, [r7, #4]
|
|
800cefa: 615a str r2, [r3, #20]
|
|
TimerObject->Next = NULL;
|
|
800cefc: 687b ldr r3, [r7, #4]
|
|
800cefe: 2200 movs r2, #0
|
|
800cf00: 615a str r2, [r3, #20]
|
|
}
|
|
800cf02: 3714 adds r7, #20
|
|
800cf04: 46bd mov sp, r7
|
|
800cf06: bc80 pop {r7}
|
|
800cf08: 4770 bx lr
|
|
800cf0a: bf00 nop
|
|
800cf0c: 200009cc .word 0x200009cc
|
|
|
|
0800cf10 <TimerInsertNewHeadTimer>:
|
|
*
|
|
* @remark The list is automatically sorted. The list head always contains the
|
|
* next timer to expire.
|
|
*/
|
|
void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject )
|
|
{
|
|
800cf10: b580 push {r7, lr}
|
|
800cf12: b084 sub sp, #16
|
|
800cf14: af00 add r7, sp, #0
|
|
800cf16: 6078 str r0, [r7, #4]
|
|
UTIL_TIMER_Object_t* cur = TimerListHead;
|
|
800cf18: 4b0b ldr r3, [pc, #44] @ (800cf48 <TimerInsertNewHeadTimer+0x38>)
|
|
800cf1a: 681b ldr r3, [r3, #0]
|
|
800cf1c: 60fb str r3, [r7, #12]
|
|
|
|
if( cur != NULL )
|
|
800cf1e: 68fb ldr r3, [r7, #12]
|
|
800cf20: 2b00 cmp r3, #0
|
|
800cf22: d002 beq.n 800cf2a <TimerInsertNewHeadTimer+0x1a>
|
|
{
|
|
cur->IsPending = 0;
|
|
800cf24: 68fb ldr r3, [r7, #12]
|
|
800cf26: 2200 movs r2, #0
|
|
800cf28: 721a strb r2, [r3, #8]
|
|
}
|
|
|
|
TimerObject->Next = cur;
|
|
800cf2a: 687b ldr r3, [r7, #4]
|
|
800cf2c: 68fa ldr r2, [r7, #12]
|
|
800cf2e: 615a str r2, [r3, #20]
|
|
TimerListHead = TimerObject;
|
|
800cf30: 4a05 ldr r2, [pc, #20] @ (800cf48 <TimerInsertNewHeadTimer+0x38>)
|
|
800cf32: 687b ldr r3, [r7, #4]
|
|
800cf34: 6013 str r3, [r2, #0]
|
|
TimerSetTimeout( TimerListHead );
|
|
800cf36: 4b04 ldr r3, [pc, #16] @ (800cf48 <TimerInsertNewHeadTimer+0x38>)
|
|
800cf38: 681b ldr r3, [r3, #0]
|
|
800cf3a: 4618 mov r0, r3
|
|
800cf3c: f7ff ff8e bl 800ce5c <TimerSetTimeout>
|
|
}
|
|
800cf40: bf00 nop
|
|
800cf42: 3710 adds r7, #16
|
|
800cf44: 46bd mov sp, r7
|
|
800cf46: bd80 pop {r7, pc}
|
|
800cf48: 200009cc .word 0x200009cc
|
|
|
|
0800cf4c <UTIL_ADV_TRACE_Init>:
|
|
|
|
/** @addtogroup ADV_TRACE_exported_function
|
|
* @{
|
|
*/
|
|
UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void)
|
|
{
|
|
800cf4c: b580 push {r7, lr}
|
|
800cf4e: af00 add r7, sp, #0
|
|
/* initialize the Ptr for Read/Write */
|
|
(void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Ctx, 0x0, sizeof(ADV_TRACE_Context));
|
|
800cf50: 2218 movs r2, #24
|
|
800cf52: 2100 movs r1, #0
|
|
800cf54: 4807 ldr r0, [pc, #28] @ (800cf74 <UTIL_ADV_TRACE_Init+0x28>)
|
|
800cf56: f7ff f8e8 bl 800c12a <UTIL_MEM_set_8>
|
|
(void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Buffer, 0x0, sizeof(ADV_TRACE_Buffer));
|
|
800cf5a: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800cf5e: 2100 movs r1, #0
|
|
800cf60: 4805 ldr r0, [pc, #20] @ (800cf78 <UTIL_ADV_TRACE_Init+0x2c>)
|
|
800cf62: f7ff f8e2 bl 800c12a <UTIL_MEM_set_8>
|
|
#endif
|
|
/* Allocate Lock resource */
|
|
UTIL_ADV_TRACE_INIT_CRITICAL_SECTION();
|
|
|
|
/* Initialize the Low Level interface */
|
|
return UTIL_TraceDriver.Init(TRACE_TxCpltCallback);
|
|
800cf66: 4b05 ldr r3, [pc, #20] @ (800cf7c <UTIL_ADV_TRACE_Init+0x30>)
|
|
800cf68: 681b ldr r3, [r3, #0]
|
|
800cf6a: 4805 ldr r0, [pc, #20] @ (800cf80 <UTIL_ADV_TRACE_Init+0x34>)
|
|
800cf6c: 4798 blx r3
|
|
800cf6e: 4603 mov r3, r0
|
|
}
|
|
800cf70: 4618 mov r0, r3
|
|
800cf72: bd80 pop {r7, pc}
|
|
800cf74: 200009d0 .word 0x200009d0
|
|
800cf78: 200009e8 .word 0x200009e8
|
|
800cf7c: 0800d9a8 .word 0x0800d9a8
|
|
800cf80: 0800d1c9 .word 0x0800d1c9
|
|
|
|
0800cf84 <UTIL_ADV_TRACE_COND_FSend>:
|
|
return UTIL_TraceDriver.StartRx(UserCallback);
|
|
}
|
|
|
|
#if defined(UTIL_ADV_TRACE_CONDITIONNAL)
|
|
UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const char *strFormat, ...)
|
|
{
|
|
800cf84: b408 push {r3}
|
|
800cf86: b580 push {r7, lr}
|
|
800cf88: b08d sub sp, #52 @ 0x34
|
|
800cf8a: af00 add r7, sp, #0
|
|
800cf8c: 60f8 str r0, [r7, #12]
|
|
800cf8e: 60b9 str r1, [r7, #8]
|
|
800cf90: 607a str r2, [r7, #4]
|
|
va_list vaArgs;
|
|
#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE)
|
|
uint8_t buf[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE];
|
|
uint16_t timestamp_size = 0u;
|
|
800cf92: 2300 movs r3, #0
|
|
800cf94: 82fb strh r3, [r7, #22]
|
|
uint16_t writepos;
|
|
uint16_t idx;
|
|
#else
|
|
uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE+UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE];
|
|
#endif
|
|
uint16_t buff_size = 0u;
|
|
800cf96: 2300 movs r3, #0
|
|
800cf98: 85bb strh r3, [r7, #44] @ 0x2c
|
|
|
|
/* check verbose level */
|
|
if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel))
|
|
800cf9a: 4b37 ldr r3, [pc, #220] @ (800d078 <UTIL_ADV_TRACE_COND_FSend+0xf4>)
|
|
800cf9c: 7a1b ldrb r3, [r3, #8]
|
|
800cf9e: 461a mov r2, r3
|
|
800cfa0: 68fb ldr r3, [r7, #12]
|
|
800cfa2: 4293 cmp r3, r2
|
|
800cfa4: d902 bls.n 800cfac <UTIL_ADV_TRACE_COND_FSend+0x28>
|
|
{
|
|
return UTIL_ADV_TRACE_GIVEUP;
|
|
800cfa6: f06f 0304 mvn.w r3, #4
|
|
800cfaa: e05e b.n 800d06a <UTIL_ADV_TRACE_COND_FSend+0xe6>
|
|
}
|
|
|
|
if((Region & ADV_TRACE_Ctx.RegionMask) != Region)
|
|
800cfac: 4b32 ldr r3, [pc, #200] @ (800d078 <UTIL_ADV_TRACE_COND_FSend+0xf4>)
|
|
800cfae: 68da ldr r2, [r3, #12]
|
|
800cfb0: 68bb ldr r3, [r7, #8]
|
|
800cfb2: 4013 ands r3, r2
|
|
800cfb4: 68ba ldr r2, [r7, #8]
|
|
800cfb6: 429a cmp r2, r3
|
|
800cfb8: d002 beq.n 800cfc0 <UTIL_ADV_TRACE_COND_FSend+0x3c>
|
|
{
|
|
return UTIL_ADV_TRACE_REGIONMASKED;
|
|
800cfba: f06f 0305 mvn.w r3, #5
|
|
800cfbe: e054 b.n 800d06a <UTIL_ADV_TRACE_COND_FSend+0xe6>
|
|
}
|
|
|
|
#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE)
|
|
if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u))
|
|
800cfc0: 4b2d ldr r3, [pc, #180] @ (800d078 <UTIL_ADV_TRACE_COND_FSend+0xf4>)
|
|
800cfc2: 685b ldr r3, [r3, #4]
|
|
800cfc4: 2b00 cmp r3, #0
|
|
800cfc6: d00a beq.n 800cfde <UTIL_ADV_TRACE_COND_FSend+0x5a>
|
|
800cfc8: 687b ldr r3, [r7, #4]
|
|
800cfca: 2b00 cmp r3, #0
|
|
800cfcc: d007 beq.n 800cfde <UTIL_ADV_TRACE_COND_FSend+0x5a>
|
|
{
|
|
ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size);
|
|
800cfce: 4b2a ldr r3, [pc, #168] @ (800d078 <UTIL_ADV_TRACE_COND_FSend+0xf4>)
|
|
800cfd0: 685b ldr r3, [r3, #4]
|
|
800cfd2: f107 0116 add.w r1, r7, #22
|
|
800cfd6: f107 0218 add.w r2, r7, #24
|
|
800cfda: 4610 mov r0, r2
|
|
800cfdc: 4798 blx r3
|
|
}
|
|
|
|
va_start( vaArgs, strFormat);
|
|
800cfde: f107 0340 add.w r3, r7, #64 @ 0x40
|
|
800cfe2: 62bb str r3, [r7, #40] @ 0x28
|
|
buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs);
|
|
800cfe4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cfe6: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
800cfe8: f44f 7180 mov.w r1, #256 @ 0x100
|
|
800cfec: 4823 ldr r0, [pc, #140] @ (800d07c <UTIL_ADV_TRACE_COND_FSend+0xf8>)
|
|
800cfee: f7ff fa3d bl 800c46c <tiny_vsnprintf_like>
|
|
800cff2: 4603 mov r3, r0
|
|
800cff4: 85bb strh r3, [r7, #44] @ 0x2c
|
|
|
|
TRACE_Lock();
|
|
800cff6: f000 f9f1 bl 800d3dc <TRACE_Lock>
|
|
|
|
/* if allocation is ok, write data into the buffer */
|
|
if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1)
|
|
800cffa: 8afa ldrh r2, [r7, #22]
|
|
800cffc: 8dbb ldrh r3, [r7, #44] @ 0x2c
|
|
800cffe: 4413 add r3, r2
|
|
800d000: b29b uxth r3, r3
|
|
800d002: f107 0214 add.w r2, r7, #20
|
|
800d006: 4611 mov r1, r2
|
|
800d008: 4618 mov r0, r3
|
|
800d00a: f000 f969 bl 800d2e0 <TRACE_AllocateBufer>
|
|
800d00e: 4603 mov r3, r0
|
|
800d010: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d014: d025 beq.n 800d062 <UTIL_ADV_TRACE_COND_FSend+0xde>
|
|
}
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
#endif
|
|
|
|
/* copy the timestamp */
|
|
for (idx = 0u; idx < timestamp_size; idx++)
|
|
800d016: 2300 movs r3, #0
|
|
800d018: 85fb strh r3, [r7, #46] @ 0x2e
|
|
800d01a: e00e b.n 800d03a <UTIL_ADV_TRACE_COND_FSend+0xb6>
|
|
{
|
|
ADV_TRACE_Buffer[writepos] = buf[idx];
|
|
800d01c: 8dfb ldrh r3, [r7, #46] @ 0x2e
|
|
800d01e: 8aba ldrh r2, [r7, #20]
|
|
800d020: 3330 adds r3, #48 @ 0x30
|
|
800d022: 443b add r3, r7
|
|
800d024: f813 1c18 ldrb.w r1, [r3, #-24]
|
|
800d028: 4b15 ldr r3, [pc, #84] @ (800d080 <UTIL_ADV_TRACE_COND_FSend+0xfc>)
|
|
800d02a: 5499 strb r1, [r3, r2]
|
|
writepos = writepos + 1u;
|
|
800d02c: 8abb ldrh r3, [r7, #20]
|
|
800d02e: 3301 adds r3, #1
|
|
800d030: b29b uxth r3, r3
|
|
800d032: 82bb strh r3, [r7, #20]
|
|
for (idx = 0u; idx < timestamp_size; idx++)
|
|
800d034: 8dfb ldrh r3, [r7, #46] @ 0x2e
|
|
800d036: 3301 adds r3, #1
|
|
800d038: 85fb strh r3, [r7, #46] @ 0x2e
|
|
800d03a: 8afb ldrh r3, [r7, #22]
|
|
800d03c: 8dfa ldrh r2, [r7, #46] @ 0x2e
|
|
800d03e: 429a cmp r2, r3
|
|
800d040: d3ec bcc.n 800d01c <UTIL_ADV_TRACE_COND_FSend+0x98>
|
|
}
|
|
|
|
/* copy the data */
|
|
(void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs);
|
|
800d042: 8abb ldrh r3, [r7, #20]
|
|
800d044: 461a mov r2, r3
|
|
800d046: 4b0e ldr r3, [pc, #56] @ (800d080 <UTIL_ADV_TRACE_COND_FSend+0xfc>)
|
|
800d048: 18d0 adds r0, r2, r3
|
|
800d04a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800d04c: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
800d04e: f44f 7180 mov.w r1, #256 @ 0x100
|
|
800d052: f7ff fa0b bl 800c46c <tiny_vsnprintf_like>
|
|
va_end(vaArgs);
|
|
|
|
TRACE_UnLock();
|
|
800d056: f000 f9df bl 800d418 <TRACE_UnLock>
|
|
|
|
return TRACE_Send();
|
|
800d05a: f000 f831 bl 800d0c0 <TRACE_Send>
|
|
800d05e: 4603 mov r3, r0
|
|
800d060: e003 b.n 800d06a <UTIL_ADV_TRACE_COND_FSend+0xe6>
|
|
}
|
|
|
|
va_end(vaArgs);
|
|
TRACE_UnLock();
|
|
800d062: f000 f9d9 bl 800d418 <TRACE_UnLock>
|
|
ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION;
|
|
}
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
#endif
|
|
|
|
return UTIL_ADV_TRACE_MEM_FULL;
|
|
800d066: f06f 0302 mvn.w r3, #2
|
|
buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs);
|
|
va_end(vaArgs);
|
|
|
|
return UTIL_ADV_TRACE_Send(buf, buff_size);
|
|
#endif
|
|
}
|
|
800d06a: 4618 mov r0, r3
|
|
800d06c: 3734 adds r7, #52 @ 0x34
|
|
800d06e: 46bd mov sp, r7
|
|
800d070: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
800d074: b001 add sp, #4
|
|
800d076: 4770 bx lr
|
|
800d078: 200009d0 .word 0x200009d0
|
|
800d07c: 20000be8 .word 0x20000be8
|
|
800d080: 200009e8 .word 0x200009e8
|
|
|
|
0800d084 <UTIL_ADV_TRACE_RegisterTimeStampFunction>:
|
|
}
|
|
#endif
|
|
|
|
#if defined(UTIL_ADV_TRACE_CONDITIONNAL)
|
|
void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb)
|
|
{
|
|
800d084: b480 push {r7}
|
|
800d086: b083 sub sp, #12
|
|
800d088: af00 add r7, sp, #0
|
|
800d08a: 6078 str r0, [r7, #4]
|
|
ADV_TRACE_Ctx.timestamp_func = *cb;
|
|
800d08c: 4a03 ldr r2, [pc, #12] @ (800d09c <UTIL_ADV_TRACE_RegisterTimeStampFunction+0x18>)
|
|
800d08e: 687b ldr r3, [r7, #4]
|
|
800d090: 6053 str r3, [r2, #4]
|
|
}
|
|
800d092: bf00 nop
|
|
800d094: 370c adds r7, #12
|
|
800d096: 46bd mov sp, r7
|
|
800d098: bc80 pop {r7}
|
|
800d09a: 4770 bx lr
|
|
800d09c: 200009d0 .word 0x200009d0
|
|
|
|
0800d0a0 <UTIL_ADV_TRACE_SetVerboseLevel>:
|
|
|
|
void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level)
|
|
{
|
|
800d0a0: b480 push {r7}
|
|
800d0a2: b083 sub sp, #12
|
|
800d0a4: af00 add r7, sp, #0
|
|
800d0a6: 4603 mov r3, r0
|
|
800d0a8: 71fb strb r3, [r7, #7]
|
|
ADV_TRACE_Ctx.CurrentVerboseLevel = Level;
|
|
800d0aa: 4a04 ldr r2, [pc, #16] @ (800d0bc <UTIL_ADV_TRACE_SetVerboseLevel+0x1c>)
|
|
800d0ac: 79fb ldrb r3, [r7, #7]
|
|
800d0ae: 7213 strb r3, [r2, #8]
|
|
}
|
|
800d0b0: bf00 nop
|
|
800d0b2: 370c adds r7, #12
|
|
800d0b4: 46bd mov sp, r7
|
|
800d0b6: bc80 pop {r7}
|
|
800d0b8: 4770 bx lr
|
|
800d0ba: bf00 nop
|
|
800d0bc: 200009d0 .word 0x200009d0
|
|
|
|
0800d0c0 <TRACE_Send>:
|
|
/**
|
|
* @brief send the data of the trace to low layer
|
|
* @retval Status based on @ref UTIL_ADV_TRACE_Status_t
|
|
*/
|
|
static UTIL_ADV_TRACE_Status_t TRACE_Send(void)
|
|
{
|
|
800d0c0: b580 push {r7, lr}
|
|
800d0c2: b088 sub sp, #32
|
|
800d0c4: af00 add r7, sp, #0
|
|
UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK;
|
|
800d0c6: 2300 movs r3, #0
|
|
800d0c8: 77fb strb r3, [r7, #31]
|
|
uint8_t *ptr = NULL;
|
|
800d0ca: 2300 movs r3, #0
|
|
800d0cc: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800d0ce: f3ef 8310 mrs r3, PRIMASK
|
|
800d0d2: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800d0d4: 693b ldr r3, [r7, #16]
|
|
|
|
UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION();
|
|
800d0d6: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800d0d8: b672 cpsid i
|
|
}
|
|
800d0da: bf00 nop
|
|
|
|
if(TRACE_IsLocked() == 0u)
|
|
800d0dc: f000 f9ba bl 800d454 <TRACE_IsLocked>
|
|
800d0e0: 4603 mov r3, r0
|
|
800d0e2: 2b00 cmp r3, #0
|
|
800d0e4: d15d bne.n 800d1a2 <TRACE_Send+0xe2>
|
|
{
|
|
TRACE_Lock();
|
|
800d0e6: f000 f979 bl 800d3dc <TRACE_Lock>
|
|
|
|
if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr)
|
|
800d0ea: 4b34 ldr r3, [pc, #208] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d0ec: 8a1a ldrh r2, [r3, #16]
|
|
800d0ee: 4b33 ldr r3, [pc, #204] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d0f0: 8a5b ldrh r3, [r3, #18]
|
|
800d0f2: 429a cmp r2, r3
|
|
800d0f4: d04d beq.n 800d192 <TRACE_Send+0xd2>
|
|
{
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status)
|
|
800d0f6: 4b31 ldr r3, [pc, #196] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d0f8: 789b ldrb r3, [r3, #2]
|
|
800d0fa: 2b01 cmp r3, #1
|
|
800d0fc: d117 bne.n 800d12e <TRACE_Send+0x6e>
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr);
|
|
800d0fe: 4b2f ldr r3, [pc, #188] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d100: 881a ldrh r2, [r3, #0]
|
|
800d102: 4b2e ldr r3, [pc, #184] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d104: 8a1b ldrh r3, [r3, #16]
|
|
800d106: 1ad3 subs r3, r2, r3
|
|
800d108: b29a uxth r2, r3
|
|
800d10a: 4b2c ldr r3, [pc, #176] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d10c: 829a strh r2, [r3, #20]
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER;
|
|
800d10e: 4b2b ldr r3, [pc, #172] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d110: 2202 movs r2, #2
|
|
800d112: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.unchunk_enabled = 0;
|
|
800d114: 4b29 ldr r3, [pc, #164] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d116: 2200 movs r2, #0
|
|
800d118: 801a strh r2, [r3, #0]
|
|
|
|
UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr);
|
|
|
|
if(0u == ADV_TRACE_Ctx.TraceSentSize)
|
|
800d11a: 4b28 ldr r3, [pc, #160] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d11c: 8a9b ldrh r3, [r3, #20]
|
|
800d11e: 2b00 cmp r3, #0
|
|
800d120: d105 bne.n 800d12e <TRACE_Send+0x6e>
|
|
{
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE;
|
|
800d122: 4b26 ldr r3, [pc, #152] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d124: 2200 movs r2, #0
|
|
800d126: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.TraceRdPtr = 0;
|
|
800d128: 4b24 ldr r3, [pc, #144] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d12a: 2200 movs r2, #0
|
|
800d12c: 821a strh r2, [r3, #16]
|
|
}
|
|
}
|
|
|
|
if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status)
|
|
800d12e: 4b23 ldr r3, [pc, #140] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d130: 789b ldrb r3, [r3, #2]
|
|
800d132: 2b00 cmp r3, #0
|
|
800d134: d115 bne.n 800d162 <TRACE_Send+0xa2>
|
|
{
|
|
#endif
|
|
if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr)
|
|
800d136: 4b21 ldr r3, [pc, #132] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d138: 8a5a ldrh r2, [r3, #18]
|
|
800d13a: 4b20 ldr r3, [pc, #128] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d13c: 8a1b ldrh r3, [r3, #16]
|
|
800d13e: 429a cmp r2, r3
|
|
800d140: d908 bls.n 800d154 <TRACE_Send+0x94>
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d142: 4b1e ldr r3, [pc, #120] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d144: 8a5a ldrh r2, [r3, #18]
|
|
800d146: 4b1d ldr r3, [pc, #116] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d148: 8a1b ldrh r3, [r3, #16]
|
|
800d14a: 1ad3 subs r3, r2, r3
|
|
800d14c: b29a uxth r2, r3
|
|
800d14e: 4b1b ldr r3, [pc, #108] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d150: 829a strh r2, [r3, #20]
|
|
800d152: e006 b.n 800d162 <TRACE_Send+0xa2>
|
|
}
|
|
else /* TraceRdPtr > TraceWrPtr */
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d154: 4b19 ldr r3, [pc, #100] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d156: 8a1b ldrh r3, [r3, #16]
|
|
800d158: f5c3 7300 rsb r3, r3, #512 @ 0x200
|
|
800d15c: b29a uxth r2, r3
|
|
800d15e: 4b17 ldr r3, [pc, #92] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d160: 829a strh r2, [r3, #20]
|
|
|
|
}
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
}
|
|
#endif
|
|
ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr];
|
|
800d162: 4b16 ldr r3, [pc, #88] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d164: 8a1b ldrh r3, [r3, #16]
|
|
800d166: 461a mov r2, r3
|
|
800d168: 4b15 ldr r3, [pc, #84] @ (800d1c0 <TRACE_Send+0x100>)
|
|
800d16a: 4413 add r3, r2
|
|
800d16c: 61bb str r3, [r7, #24]
|
|
800d16e: 697b ldr r3, [r7, #20]
|
|
800d170: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d172: 68fb ldr r3, [r7, #12]
|
|
800d174: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d178: bf00 nop
|
|
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
UTIL_ADV_TRACE_PreSendHook();
|
|
800d17a: f7f3 fcd1 bl 8000b20 <UTIL_ADV_TRACE_PreSendHook>
|
|
|
|
UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize);
|
|
ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize);
|
|
800d17e: 4b11 ldr r3, [pc, #68] @ (800d1c4 <TRACE_Send+0x104>)
|
|
800d180: 68db ldr r3, [r3, #12]
|
|
800d182: 4a0e ldr r2, [pc, #56] @ (800d1bc <TRACE_Send+0xfc>)
|
|
800d184: 8a92 ldrh r2, [r2, #20]
|
|
800d186: 4611 mov r1, r2
|
|
800d188: 69b8 ldr r0, [r7, #24]
|
|
800d18a: 4798 blx r3
|
|
800d18c: 4603 mov r3, r0
|
|
800d18e: 77fb strb r3, [r7, #31]
|
|
800d190: e00d b.n 800d1ae <TRACE_Send+0xee>
|
|
}
|
|
else
|
|
{
|
|
TRACE_UnLock();
|
|
800d192: f000 f941 bl 800d418 <TRACE_UnLock>
|
|
800d196: 697b ldr r3, [r7, #20]
|
|
800d198: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d19a: 68bb ldr r3, [r7, #8]
|
|
800d19c: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d1a0: e005 b.n 800d1ae <TRACE_Send+0xee>
|
|
800d1a2: 697b ldr r3, [r7, #20]
|
|
800d1a4: 607b str r3, [r7, #4]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d1a6: 687b ldr r3, [r7, #4]
|
|
800d1a8: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d1ac: bf00 nop
|
|
else
|
|
{
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
}
|
|
|
|
return ret;
|
|
800d1ae: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
800d1b2: 4618 mov r0, r3
|
|
800d1b4: 3720 adds r7, #32
|
|
800d1b6: 46bd mov sp, r7
|
|
800d1b8: bd80 pop {r7, pc}
|
|
800d1ba: bf00 nop
|
|
800d1bc: 200009d0 .word 0x200009d0
|
|
800d1c0: 200009e8 .word 0x200009e8
|
|
800d1c4: 0800d9a8 .word 0x0800d9a8
|
|
|
|
0800d1c8 <TRACE_TxCpltCallback>:
|
|
* @brief Tx callback called by the low layer level to inform a transfer complete
|
|
* @param Ptr pointer not used only for HAL compatibility
|
|
* @retval none
|
|
*/
|
|
static void TRACE_TxCpltCallback(void *Ptr)
|
|
{
|
|
800d1c8: b580 push {r7, lr}
|
|
800d1ca: b088 sub sp, #32
|
|
800d1cc: af00 add r7, sp, #0
|
|
800d1ce: 6078 str r0, [r7, #4]
|
|
uint8_t *ptr = NULL;
|
|
800d1d0: 2300 movs r3, #0
|
|
800d1d2: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800d1d4: f3ef 8310 mrs r3, PRIMASK
|
|
800d1d8: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800d1da: 697b ldr r3, [r7, #20]
|
|
UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION();
|
|
800d1dc: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800d1de: b672 cpsid i
|
|
}
|
|
800d1e0: bf00 nop
|
|
ADV_TRACE_Ctx.TraceSentSize = 0u;
|
|
}
|
|
#endif
|
|
|
|
#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE)
|
|
if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status)
|
|
800d1e2: 4b3c ldr r3, [pc, #240] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d1e4: 789b ldrb r3, [r3, #2]
|
|
800d1e6: 2b02 cmp r3, #2
|
|
800d1e8: d106 bne.n 800d1f8 <TRACE_TxCpltCallback+0x30>
|
|
{
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE;
|
|
800d1ea: 4b3a ldr r3, [pc, #232] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d1ec: 2200 movs r2, #0
|
|
800d1ee: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.TraceRdPtr = 0;
|
|
800d1f0: 4b38 ldr r3, [pc, #224] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d1f2: 2200 movs r2, #0
|
|
800d1f4: 821a strh r2, [r3, #16]
|
|
800d1f6: e00a b.n 800d20e <TRACE_TxCpltCallback+0x46>
|
|
UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n");
|
|
}
|
|
else
|
|
{
|
|
ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE;
|
|
800d1f8: 4b36 ldr r3, [pc, #216] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d1fa: 8a1a ldrh r2, [r3, #16]
|
|
800d1fc: 4b35 ldr r3, [pc, #212] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d1fe: 8a9b ldrh r3, [r3, #20]
|
|
800d200: 4413 add r3, r2
|
|
800d202: b29b uxth r3, r3
|
|
800d204: f3c3 0308 ubfx r3, r3, #0, #9
|
|
800d208: b29a uxth r2, r3
|
|
800d20a: 4b32 ldr r3, [pc, #200] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d20c: 821a strh r2, [r3, #16]
|
|
UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock))
|
|
800d20e: 4b31 ldr r3, [pc, #196] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d210: 8a1a ldrh r2, [r3, #16]
|
|
800d212: 4b30 ldr r3, [pc, #192] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d214: 8a5b ldrh r3, [r3, #18]
|
|
800d216: 429a cmp r2, r3
|
|
800d218: d04d beq.n 800d2b6 <TRACE_TxCpltCallback+0xee>
|
|
800d21a: 4b2e ldr r3, [pc, #184] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d21c: 8adb ldrh r3, [r3, #22]
|
|
800d21e: 2b01 cmp r3, #1
|
|
800d220: d149 bne.n 800d2b6 <TRACE_TxCpltCallback+0xee>
|
|
{
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status)
|
|
800d222: 4b2c ldr r3, [pc, #176] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d224: 789b ldrb r3, [r3, #2]
|
|
800d226: 2b01 cmp r3, #1
|
|
800d228: d117 bne.n 800d25a <TRACE_TxCpltCallback+0x92>
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d22a: 4b2a ldr r3, [pc, #168] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d22c: 881a ldrh r2, [r3, #0]
|
|
800d22e: 4b29 ldr r3, [pc, #164] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d230: 8a1b ldrh r3, [r3, #16]
|
|
800d232: 1ad3 subs r3, r2, r3
|
|
800d234: b29a uxth r2, r3
|
|
800d236: 4b27 ldr r3, [pc, #156] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d238: 829a strh r2, [r3, #20]
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER;
|
|
800d23a: 4b26 ldr r3, [pc, #152] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d23c: 2202 movs r2, #2
|
|
800d23e: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.unchunk_enabled = 0;
|
|
800d240: 4b24 ldr r3, [pc, #144] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d242: 2200 movs r2, #0
|
|
800d244: 801a strh r2, [r3, #0]
|
|
|
|
UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr);
|
|
|
|
if(0u == ADV_TRACE_Ctx.TraceSentSize)
|
|
800d246: 4b23 ldr r3, [pc, #140] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d248: 8a9b ldrh r3, [r3, #20]
|
|
800d24a: 2b00 cmp r3, #0
|
|
800d24c: d105 bne.n 800d25a <TRACE_TxCpltCallback+0x92>
|
|
{
|
|
/* this case occurs when an ongoing write aligned the Rd position with chunk position */
|
|
/* in that case the unchunk is forgot */
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE;
|
|
800d24e: 4b21 ldr r3, [pc, #132] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d250: 2200 movs r2, #0
|
|
800d252: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.TraceRdPtr = 0;
|
|
800d254: 4b1f ldr r3, [pc, #124] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d256: 2200 movs r2, #0
|
|
800d258: 821a strh r2, [r3, #16]
|
|
}
|
|
}
|
|
|
|
if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status)
|
|
800d25a: 4b1e ldr r3, [pc, #120] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d25c: 789b ldrb r3, [r3, #2]
|
|
800d25e: 2b00 cmp r3, #0
|
|
800d260: d115 bne.n 800d28e <TRACE_TxCpltCallback+0xc6>
|
|
{
|
|
#endif
|
|
if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr)
|
|
800d262: 4b1c ldr r3, [pc, #112] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d264: 8a5a ldrh r2, [r3, #18]
|
|
800d266: 4b1b ldr r3, [pc, #108] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d268: 8a1b ldrh r3, [r3, #16]
|
|
800d26a: 429a cmp r2, r3
|
|
800d26c: d908 bls.n 800d280 <TRACE_TxCpltCallback+0xb8>
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d26e: 4b19 ldr r3, [pc, #100] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d270: 8a5a ldrh r2, [r3, #18]
|
|
800d272: 4b18 ldr r3, [pc, #96] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d274: 8a1b ldrh r3, [r3, #16]
|
|
800d276: 1ad3 subs r3, r2, r3
|
|
800d278: b29a uxth r2, r3
|
|
800d27a: 4b16 ldr r3, [pc, #88] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d27c: 829a strh r2, [r3, #20]
|
|
800d27e: e006 b.n 800d28e <TRACE_TxCpltCallback+0xc6>
|
|
}
|
|
else /* TraceRdPtr > TraceWrPtr */
|
|
{
|
|
ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d280: 4b14 ldr r3, [pc, #80] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d282: 8a1b ldrh r3, [r3, #16]
|
|
800d284: f5c3 7300 rsb r3, r3, #512 @ 0x200
|
|
800d288: b29a uxth r2, r3
|
|
800d28a: 4b12 ldr r3, [pc, #72] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d28c: 829a strh r2, [r3, #20]
|
|
}
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
}
|
|
#endif
|
|
ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr];
|
|
800d28e: 4b11 ldr r3, [pc, #68] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d290: 8a1b ldrh r3, [r3, #16]
|
|
800d292: 461a mov r2, r3
|
|
800d294: 4b10 ldr r3, [pc, #64] @ (800d2d8 <TRACE_TxCpltCallback+0x110>)
|
|
800d296: 4413 add r3, r2
|
|
800d298: 61fb str r3, [r7, #28]
|
|
800d29a: 69bb ldr r3, [r7, #24]
|
|
800d29c: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d29e: 693b ldr r3, [r7, #16]
|
|
800d2a0: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d2a4: bf00 nop
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize);
|
|
UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize);
|
|
800d2a6: 4b0d ldr r3, [pc, #52] @ (800d2dc <TRACE_TxCpltCallback+0x114>)
|
|
800d2a8: 68db ldr r3, [r3, #12]
|
|
800d2aa: 4a0a ldr r2, [pc, #40] @ (800d2d4 <TRACE_TxCpltCallback+0x10c>)
|
|
800d2ac: 8a92 ldrh r2, [r2, #20]
|
|
800d2ae: 4611 mov r1, r2
|
|
800d2b0: 69f8 ldr r0, [r7, #28]
|
|
800d2b2: 4798 blx r3
|
|
800d2b4: e00a b.n 800d2cc <TRACE_TxCpltCallback+0x104>
|
|
800d2b6: 69bb ldr r3, [r7, #24]
|
|
800d2b8: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d2ba: 68fb ldr r3, [r7, #12]
|
|
800d2bc: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d2c0: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
UTIL_ADV_TRACE_PostSendHook();
|
|
800d2c2: f7f3 fc35 bl 8000b30 <UTIL_ADV_TRACE_PostSendHook>
|
|
TRACE_UnLock();
|
|
800d2c6: f000 f8a7 bl 800d418 <TRACE_UnLock>
|
|
}
|
|
}
|
|
800d2ca: bf00 nop
|
|
800d2cc: bf00 nop
|
|
800d2ce: 3720 adds r7, #32
|
|
800d2d0: 46bd mov sp, r7
|
|
800d2d2: bd80 pop {r7, pc}
|
|
800d2d4: 200009d0 .word 0x200009d0
|
|
800d2d8: 200009e8 .word 0x200009e8
|
|
800d2dc: 0800d9a8 .word 0x0800d9a8
|
|
|
|
0800d2e0 <TRACE_AllocateBufer>:
|
|
* @param Size to allocate within fifo
|
|
* @param Pos position within the fifo
|
|
* @retval write position inside the buffer is -1 no space available.
|
|
*/
|
|
static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos)
|
|
{
|
|
800d2e0: b480 push {r7}
|
|
800d2e2: b087 sub sp, #28
|
|
800d2e4: af00 add r7, sp, #0
|
|
800d2e6: 4603 mov r3, r0
|
|
800d2e8: 6039 str r1, [r7, #0]
|
|
800d2ea: 80fb strh r3, [r7, #6]
|
|
uint16_t freesize;
|
|
int16_t ret = -1;
|
|
800d2ec: f64f 73ff movw r3, #65535 @ 0xffff
|
|
800d2f0: 82bb strh r3, [r7, #20]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800d2f2: f3ef 8310 mrs r3, PRIMASK
|
|
800d2f6: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800d2f8: 68fb ldr r3, [r7, #12]
|
|
|
|
UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION();
|
|
800d2fa: 613b str r3, [r7, #16]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800d2fc: b672 cpsid i
|
|
}
|
|
800d2fe: bf00 nop
|
|
|
|
if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr)
|
|
800d300: 4b35 ldr r3, [pc, #212] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d302: 8a5a ldrh r2, [r3, #18]
|
|
800d304: 4b34 ldr r3, [pc, #208] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d306: 8a1b ldrh r3, [r3, #16]
|
|
800d308: 429a cmp r2, r3
|
|
800d30a: d11b bne.n 800d344 <TRACE_AllocateBufer+0x64>
|
|
{
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr);
|
|
800d30c: 4b32 ldr r3, [pc, #200] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d30e: 8a5b ldrh r3, [r3, #18]
|
|
800d310: f5c3 7300 rsb r3, r3, #512 @ 0x200
|
|
800d314: 82fb strh r3, [r7, #22]
|
|
if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size))
|
|
800d316: 88fa ldrh r2, [r7, #6]
|
|
800d318: 8afb ldrh r3, [r7, #22]
|
|
800d31a: 429a cmp r2, r3
|
|
800d31c: d33a bcc.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
800d31e: 4b2e ldr r3, [pc, #184] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d320: 8a1b ldrh r3, [r3, #16]
|
|
800d322: 88fa ldrh r2, [r7, #6]
|
|
800d324: 429a cmp r2, r3
|
|
800d326: d235 bcs.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
{
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED;
|
|
800d328: 4b2b ldr r3, [pc, #172] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d32a: 2201 movs r2, #1
|
|
800d32c: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr;
|
|
800d32e: 4b2a ldr r3, [pc, #168] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d330: 8a5a ldrh r2, [r3, #18]
|
|
800d332: 4b29 ldr r3, [pc, #164] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d334: 801a strh r2, [r3, #0]
|
|
freesize = ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d336: 4b28 ldr r3, [pc, #160] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d338: 8a1b ldrh r3, [r3, #16]
|
|
800d33a: 82fb strh r3, [r7, #22]
|
|
ADV_TRACE_Ctx.TraceWrPtr = 0;
|
|
800d33c: 4b26 ldr r3, [pc, #152] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d33e: 2200 movs r2, #0
|
|
800d340: 825a strh r2, [r3, #18]
|
|
800d342: e027 b.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE
|
|
if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr)
|
|
800d344: 4b24 ldr r3, [pc, #144] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d346: 8a5a ldrh r2, [r3, #18]
|
|
800d348: 4b23 ldr r3, [pc, #140] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d34a: 8a1b ldrh r3, [r3, #16]
|
|
800d34c: 429a cmp r2, r3
|
|
800d34e: d91b bls.n 800d388 <TRACE_AllocateBufer+0xa8>
|
|
{
|
|
freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr);
|
|
800d350: 4b21 ldr r3, [pc, #132] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d352: 8a5b ldrh r3, [r3, #18]
|
|
800d354: f5c3 7300 rsb r3, r3, #512 @ 0x200
|
|
800d358: 82fb strh r3, [r7, #22]
|
|
if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size))
|
|
800d35a: 88fa ldrh r2, [r7, #6]
|
|
800d35c: 8afb ldrh r3, [r7, #22]
|
|
800d35e: 429a cmp r2, r3
|
|
800d360: d318 bcc.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
800d362: 4b1d ldr r3, [pc, #116] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d364: 8a1b ldrh r3, [r3, #16]
|
|
800d366: 88fa ldrh r2, [r7, #6]
|
|
800d368: 429a cmp r2, r3
|
|
800d36a: d213 bcs.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
{
|
|
ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED;
|
|
800d36c: 4b1a ldr r3, [pc, #104] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d36e: 2201 movs r2, #1
|
|
800d370: 709a strb r2, [r3, #2]
|
|
ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr;
|
|
800d372: 4b19 ldr r3, [pc, #100] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d374: 8a5a ldrh r2, [r3, #18]
|
|
800d376: 4b18 ldr r3, [pc, #96] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d378: 801a strh r2, [r3, #0]
|
|
freesize = ADV_TRACE_Ctx.TraceRdPtr;
|
|
800d37a: 4b17 ldr r3, [pc, #92] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d37c: 8a1b ldrh r3, [r3, #16]
|
|
800d37e: 82fb strh r3, [r7, #22]
|
|
ADV_TRACE_Ctx.TraceWrPtr = 0;
|
|
800d380: 4b15 ldr r3, [pc, #84] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d382: 2200 movs r2, #0
|
|
800d384: 825a strh r2, [r3, #18]
|
|
800d386: e005 b.n 800d394 <TRACE_AllocateBufer+0xb4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr);
|
|
800d388: 4b13 ldr r3, [pc, #76] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d38a: 8a1a ldrh r2, [r3, #16]
|
|
800d38c: 4b12 ldr r3, [pc, #72] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d38e: 8a5b ldrh r3, [r3, #18]
|
|
800d390: 1ad3 subs r3, r2, r3
|
|
800d392: 82fb strh r3, [r7, #22]
|
|
freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
if(freesize > Size)
|
|
800d394: 8afa ldrh r2, [r7, #22]
|
|
800d396: 88fb ldrh r3, [r7, #6]
|
|
800d398: 429a cmp r2, r3
|
|
800d39a: d90f bls.n 800d3bc <TRACE_AllocateBufer+0xdc>
|
|
{
|
|
*Pos = ADV_TRACE_Ctx.TraceWrPtr;
|
|
800d39c: 4b0e ldr r3, [pc, #56] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d39e: 8a5a ldrh r2, [r3, #18]
|
|
800d3a0: 683b ldr r3, [r7, #0]
|
|
800d3a2: 801a strh r2, [r3, #0]
|
|
ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE;
|
|
800d3a4: 4b0c ldr r3, [pc, #48] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d3a6: 8a5a ldrh r2, [r3, #18]
|
|
800d3a8: 88fb ldrh r3, [r7, #6]
|
|
800d3aa: 4413 add r3, r2
|
|
800d3ac: b29b uxth r3, r3
|
|
800d3ae: f3c3 0308 ubfx r3, r3, #0, #9
|
|
800d3b2: b29a uxth r2, r3
|
|
800d3b4: 4b08 ldr r3, [pc, #32] @ (800d3d8 <TRACE_AllocateBufer+0xf8>)
|
|
800d3b6: 825a strh r2, [r3, #18]
|
|
ret = 0;
|
|
800d3b8: 2300 movs r3, #0
|
|
800d3ba: 82bb strh r3, [r7, #20]
|
|
800d3bc: 693b ldr r3, [r7, #16]
|
|
800d3be: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d3c0: 68bb ldr r3, [r7, #8]
|
|
800d3c2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d3c6: bf00 nop
|
|
}
|
|
}
|
|
#endif
|
|
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
return ret;
|
|
800d3c8: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
}
|
|
800d3cc: 4618 mov r0, r3
|
|
800d3ce: 371c adds r7, #28
|
|
800d3d0: 46bd mov sp, r7
|
|
800d3d2: bc80 pop {r7}
|
|
800d3d4: 4770 bx lr
|
|
800d3d6: bf00 nop
|
|
800d3d8: 200009d0 .word 0x200009d0
|
|
|
|
0800d3dc <TRACE_Lock>:
|
|
/**
|
|
* @brief Lock the trace buffer.
|
|
* @retval None.
|
|
*/
|
|
static void TRACE_Lock(void)
|
|
{
|
|
800d3dc: b480 push {r7}
|
|
800d3de: b085 sub sp, #20
|
|
800d3e0: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800d3e2: f3ef 8310 mrs r3, PRIMASK
|
|
800d3e6: 607b str r3, [r7, #4]
|
|
return(result);
|
|
800d3e8: 687b ldr r3, [r7, #4]
|
|
UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION();
|
|
800d3ea: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800d3ec: b672 cpsid i
|
|
}
|
|
800d3ee: bf00 nop
|
|
ADV_TRACE_Ctx.TraceLock++;
|
|
800d3f0: 4b08 ldr r3, [pc, #32] @ (800d414 <TRACE_Lock+0x38>)
|
|
800d3f2: 8adb ldrh r3, [r3, #22]
|
|
800d3f4: 3301 adds r3, #1
|
|
800d3f6: b29a uxth r2, r3
|
|
800d3f8: 4b06 ldr r3, [pc, #24] @ (800d414 <TRACE_Lock+0x38>)
|
|
800d3fa: 82da strh r2, [r3, #22]
|
|
800d3fc: 68fb ldr r3, [r7, #12]
|
|
800d3fe: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d400: 68bb ldr r3, [r7, #8]
|
|
800d402: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d406: bf00 nop
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
}
|
|
800d408: bf00 nop
|
|
800d40a: 3714 adds r7, #20
|
|
800d40c: 46bd mov sp, r7
|
|
800d40e: bc80 pop {r7}
|
|
800d410: 4770 bx lr
|
|
800d412: bf00 nop
|
|
800d414: 200009d0 .word 0x200009d0
|
|
|
|
0800d418 <TRACE_UnLock>:
|
|
/**
|
|
* @brief UnLock the trace buffer.
|
|
* @retval None.
|
|
*/
|
|
static void TRACE_UnLock(void)
|
|
{
|
|
800d418: b480 push {r7}
|
|
800d41a: b085 sub sp, #20
|
|
800d41c: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800d41e: f3ef 8310 mrs r3, PRIMASK
|
|
800d422: 607b str r3, [r7, #4]
|
|
return(result);
|
|
800d424: 687b ldr r3, [r7, #4]
|
|
UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION();
|
|
800d426: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800d428: b672 cpsid i
|
|
}
|
|
800d42a: bf00 nop
|
|
ADV_TRACE_Ctx.TraceLock--;
|
|
800d42c: 4b08 ldr r3, [pc, #32] @ (800d450 <TRACE_UnLock+0x38>)
|
|
800d42e: 8adb ldrh r3, [r3, #22]
|
|
800d430: 3b01 subs r3, #1
|
|
800d432: b29a uxth r2, r3
|
|
800d434: 4b06 ldr r3, [pc, #24] @ (800d450 <TRACE_UnLock+0x38>)
|
|
800d436: 82da strh r2, [r3, #22]
|
|
800d438: 68fb ldr r3, [r7, #12]
|
|
800d43a: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800d43c: 68bb ldr r3, [r7, #8]
|
|
800d43e: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800d442: bf00 nop
|
|
UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION();
|
|
}
|
|
800d444: bf00 nop
|
|
800d446: 3714 adds r7, #20
|
|
800d448: 46bd mov sp, r7
|
|
800d44a: bc80 pop {r7}
|
|
800d44c: 4770 bx lr
|
|
800d44e: bf00 nop
|
|
800d450: 200009d0 .word 0x200009d0
|
|
|
|
0800d454 <TRACE_IsLocked>:
|
|
/**
|
|
* @brief UnLock the trace buffer.
|
|
* @retval None.
|
|
*/
|
|
static uint32_t TRACE_IsLocked(void)
|
|
{
|
|
800d454: b480 push {r7}
|
|
800d456: af00 add r7, sp, #0
|
|
return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u);
|
|
800d458: 4b05 ldr r3, [pc, #20] @ (800d470 <TRACE_IsLocked+0x1c>)
|
|
800d45a: 8adb ldrh r3, [r3, #22]
|
|
800d45c: 2b00 cmp r3, #0
|
|
800d45e: bf14 ite ne
|
|
800d460: 2301 movne r3, #1
|
|
800d462: 2300 moveq r3, #0
|
|
800d464: b2db uxtb r3, r3
|
|
}
|
|
800d466: 4618 mov r0, r3
|
|
800d468: 46bd mov sp, r7
|
|
800d46a: bc80 pop {r7}
|
|
800d46c: 4770 bx lr
|
|
800d46e: bf00 nop
|
|
800d470: 200009d0 .word 0x200009d0
|
|
|
|
0800d474 <memset>:
|
|
800d474: 4402 add r2, r0
|
|
800d476: 4603 mov r3, r0
|
|
800d478: 4293 cmp r3, r2
|
|
800d47a: d100 bne.n 800d47e <memset+0xa>
|
|
800d47c: 4770 bx lr
|
|
800d47e: f803 1b01 strb.w r1, [r3], #1
|
|
800d482: e7f9 b.n 800d478 <memset+0x4>
|
|
|
|
0800d484 <__libc_init_array>:
|
|
800d484: b570 push {r4, r5, r6, lr}
|
|
800d486: 4d0d ldr r5, [pc, #52] @ (800d4bc <__libc_init_array+0x38>)
|
|
800d488: 4c0d ldr r4, [pc, #52] @ (800d4c0 <__libc_init_array+0x3c>)
|
|
800d48a: 1b64 subs r4, r4, r5
|
|
800d48c: 10a4 asrs r4, r4, #2
|
|
800d48e: 2600 movs r6, #0
|
|
800d490: 42a6 cmp r6, r4
|
|
800d492: d109 bne.n 800d4a8 <__libc_init_array+0x24>
|
|
800d494: 4d0b ldr r5, [pc, #44] @ (800d4c4 <__libc_init_array+0x40>)
|
|
800d496: 4c0c ldr r4, [pc, #48] @ (800d4c8 <__libc_init_array+0x44>)
|
|
800d498: f000 f826 bl 800d4e8 <_init>
|
|
800d49c: 1b64 subs r4, r4, r5
|
|
800d49e: 10a4 asrs r4, r4, #2
|
|
800d4a0: 2600 movs r6, #0
|
|
800d4a2: 42a6 cmp r6, r4
|
|
800d4a4: d105 bne.n 800d4b2 <__libc_init_array+0x2e>
|
|
800d4a6: bd70 pop {r4, r5, r6, pc}
|
|
800d4a8: f855 3b04 ldr.w r3, [r5], #4
|
|
800d4ac: 4798 blx r3
|
|
800d4ae: 3601 adds r6, #1
|
|
800d4b0: e7ee b.n 800d490 <__libc_init_array+0xc>
|
|
800d4b2: f855 3b04 ldr.w r3, [r5], #4
|
|
800d4b6: 4798 blx r3
|
|
800d4b8: 3601 adds r6, #1
|
|
800d4ba: e7f2 b.n 800d4a2 <__libc_init_array+0x1e>
|
|
800d4bc: 0800db38 .word 0x0800db38
|
|
800d4c0: 0800db38 .word 0x0800db38
|
|
800d4c4: 0800db38 .word 0x0800db38
|
|
800d4c8: 0800db3c .word 0x0800db3c
|
|
|
|
0800d4cc <memcpy>:
|
|
800d4cc: 440a add r2, r1
|
|
800d4ce: 4291 cmp r1, r2
|
|
800d4d0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
800d4d4: d100 bne.n 800d4d8 <memcpy+0xc>
|
|
800d4d6: 4770 bx lr
|
|
800d4d8: b510 push {r4, lr}
|
|
800d4da: f811 4b01 ldrb.w r4, [r1], #1
|
|
800d4de: f803 4f01 strb.w r4, [r3, #1]!
|
|
800d4e2: 4291 cmp r1, r2
|
|
800d4e4: d1f9 bne.n 800d4da <memcpy+0xe>
|
|
800d4e6: bd10 pop {r4, pc}
|
|
|
|
0800d4e8 <_init>:
|
|
800d4e8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d4ea: bf00 nop
|
|
800d4ec: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800d4ee: bc08 pop {r3}
|
|
800d4f0: 469e mov lr, r3
|
|
800d4f2: 4770 bx lr
|
|
|
|
0800d4f4 <_fini>:
|
|
800d4f4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d4f6: bf00 nop
|
|
800d4f8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800d4fa: bc08 pop {r3}
|
|
800d4fc: 469e mov lr, r3
|
|
800d4fe: 4770 bx lr
|