SubGHz_Phy_Per_My_Test.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000138 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000ef80 08000140 08000140 00001140 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000d40 0800f0c0 0800f0c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800fe00 0800fe00 0001108c 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800fe00 0800fe00 00010e00 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800fe08 0800fe08 0001108c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800fe08 0800fe08 00010e08 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800fe0c 0800fe0c 00010e0c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000008c 20000000 0800fe10 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000fdc 2000008c 0800fe9c 0001108c 2**2 ALLOC 10 ._user_heap_stack 00000a00 20001068 0800fe9c 00012068 2**0 ALLOC 11 .ARM.attributes 0000002a 00000000 00000000 0001108c 2**0 CONTENTS, READONLY 12 .debug_info 00024226 00000000 00000000 000110b6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00006081 00000000 00000000 000352dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00002108 00000000 00000000 0003b360 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 000018d7 00000000 00000000 0003d468 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00023a3b 00000000 00000000 0003ed3f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00022f57 00000000 00000000 0006277a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c680e 00000000 00000000 000856d1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014bedf 2**0 CONTENTS, READONLY 20 .debug_frame 00008bd0 00000000 00000000 0014bf24 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000005f 00000000 00000000 00154af4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000140 <__do_global_dtors_aux>: 8000140: b510 push {r4, lr} 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) 8000144: 7823 ldrb r3, [r4, #0] 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) 800014e: f3af 8000 nop.w 8000152: 2301 movs r3, #1 8000154: 7023 strb r3, [r4, #0] 8000156: bd10 pop {r4, pc} 8000158: 2000008c .word 0x2000008c 800015c: 00000000 .word 0x00000000 8000160: 0800f0a8 .word 0x0800f0a8 08000164 : 8000164: b508 push {r3, lr} 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 ) 8000168: b11b cbz r3, 8000172 800016a: 4903 ldr r1, [pc, #12] @ (8000178 ) 800016c: 4803 ldr r0, [pc, #12] @ (800017c ) 800016e: f3af 8000 nop.w 8000172: bd08 pop {r3, pc} 8000174: 00000000 .word 0x00000000 8000178: 20000090 .word 0x20000090 800017c: 0800f0a8 .word 0x0800f0a8 08000180 : 8000180: f810 2b01 ldrb.w r2, [r0], #1 8000184: f811 3b01 ldrb.w r3, [r1], #1 8000188: 2a01 cmp r2, #1 800018a: bf28 it cs 800018c: 429a cmpcs r2, r3 800018e: d0f7 beq.n 8000180 8000190: 1ad0 subs r0, r2, r3 8000192: 4770 bx lr 08000194 : 8000194: 4603 mov r3, r0 8000196: f813 2b01 ldrb.w r2, [r3], #1 800019a: 2a00 cmp r2, #0 800019c: d1fb bne.n 8000196 800019e: 1a18 subs r0, r3, r0 80001a0: 3801 subs r0, #1 80001a2: 4770 bx lr ... 080001b0 : 80001b0: f001 01ff and.w r1, r1, #255 @ 0xff 80001b4: 2a10 cmp r2, #16 80001b6: db2b blt.n 8000210 80001b8: f010 0f07 tst.w r0, #7 80001bc: d008 beq.n 80001d0 80001be: f810 3b01 ldrb.w r3, [r0], #1 80001c2: 3a01 subs r2, #1 80001c4: 428b cmp r3, r1 80001c6: d02d beq.n 8000224 80001c8: f010 0f07 tst.w r0, #7 80001cc: b342 cbz r2, 8000220 80001ce: d1f6 bne.n 80001be 80001d0: b4f0 push {r4, r5, r6, r7} 80001d2: ea41 2101 orr.w r1, r1, r1, lsl #8 80001d6: ea41 4101 orr.w r1, r1, r1, lsl #16 80001da: f022 0407 bic.w r4, r2, #7 80001de: f07f 0700 mvns.w r7, #0 80001e2: 2300 movs r3, #0 80001e4: e8f0 5602 ldrd r5, r6, [r0], #8 80001e8: 3c08 subs r4, #8 80001ea: ea85 0501 eor.w r5, r5, r1 80001ee: ea86 0601 eor.w r6, r6, r1 80001f2: fa85 f547 uadd8 r5, r5, r7 80001f6: faa3 f587 sel r5, r3, r7 80001fa: fa86 f647 uadd8 r6, r6, r7 80001fe: faa5 f687 sel r6, r5, r7 8000202: b98e cbnz r6, 8000228 8000204: d1ee bne.n 80001e4 8000206: bcf0 pop {r4, r5, r6, r7} 8000208: f001 01ff and.w r1, r1, #255 @ 0xff 800020c: f002 0207 and.w r2, r2, #7 8000210: b132 cbz r2, 8000220 8000212: f810 3b01 ldrb.w r3, [r0], #1 8000216: 3a01 subs r2, #1 8000218: ea83 0301 eor.w r3, r3, r1 800021c: b113 cbz r3, 8000224 800021e: d1f8 bne.n 8000212 8000220: 2000 movs r0, #0 8000222: 4770 bx lr 8000224: 3801 subs r0, #1 8000226: 4770 bx lr 8000228: 2d00 cmp r5, #0 800022a: bf06 itte eq 800022c: 4635 moveq r5, r6 800022e: 3803 subeq r0, #3 8000230: 3807 subne r0, #7 8000232: f015 0f01 tst.w r5, #1 8000236: d107 bne.n 8000248 8000238: 3001 adds r0, #1 800023a: f415 7f80 tst.w r5, #256 @ 0x100 800023e: bf02 ittt eq 8000240: 3001 addeq r0, #1 8000242: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000246: 3001 addeq r0, #1 8000248: bcf0 pop {r4, r5, r6, r7} 800024a: 3801 subs r0, #1 800024c: 4770 bx lr 800024e: bf00 nop 08000250 <__aeabi_uldivmod>: 8000250: b953 cbnz r3, 8000268 <__aeabi_uldivmod+0x18> 8000252: b94a cbnz r2, 8000268 <__aeabi_uldivmod+0x18> 8000254: 2900 cmp r1, #0 8000256: bf08 it eq 8000258: 2800 cmpeq r0, #0 800025a: bf1c itt ne 800025c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000260: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000264: f000 b988 b.w 8000578 <__aeabi_idiv0> 8000268: f1ad 0c08 sub.w ip, sp, #8 800026c: e96d ce04 strd ip, lr, [sp, #-16]! 8000270: f000 f806 bl 8000280 <__udivmoddi4> 8000274: f8dd e004 ldr.w lr, [sp, #4] 8000278: e9dd 2302 ldrd r2, r3, [sp, #8] 800027c: b004 add sp, #16 800027e: 4770 bx lr 08000280 <__udivmoddi4>: 8000280: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000284: 9d08 ldr r5, [sp, #32] 8000286: 468e mov lr, r1 8000288: 4604 mov r4, r0 800028a: 4688 mov r8, r1 800028c: 2b00 cmp r3, #0 800028e: d14a bne.n 8000326 <__udivmoddi4+0xa6> 8000290: 428a cmp r2, r1 8000292: 4617 mov r7, r2 8000294: d962 bls.n 800035c <__udivmoddi4+0xdc> 8000296: fab2 f682 clz r6, r2 800029a: b14e cbz r6, 80002b0 <__udivmoddi4+0x30> 800029c: f1c6 0320 rsb r3, r6, #32 80002a0: fa01 f806 lsl.w r8, r1, r6 80002a4: fa20 f303 lsr.w r3, r0, r3 80002a8: 40b7 lsls r7, r6 80002aa: ea43 0808 orr.w r8, r3, r8 80002ae: 40b4 lsls r4, r6 80002b0: ea4f 4e17 mov.w lr, r7, lsr #16 80002b4: fa1f fc87 uxth.w ip, r7 80002b8: fbb8 f1fe udiv r1, r8, lr 80002bc: 0c23 lsrs r3, r4, #16 80002be: fb0e 8811 mls r8, lr, r1, r8 80002c2: ea43 4308 orr.w r3, r3, r8, lsl #16 80002c6: fb01 f20c mul.w r2, r1, ip 80002ca: 429a cmp r2, r3 80002cc: d909 bls.n 80002e2 <__udivmoddi4+0x62> 80002ce: 18fb adds r3, r7, r3 80002d0: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 80002d4: f080 80ea bcs.w 80004ac <__udivmoddi4+0x22c> 80002d8: 429a cmp r2, r3 80002da: f240 80e7 bls.w 80004ac <__udivmoddi4+0x22c> 80002de: 3902 subs r1, #2 80002e0: 443b add r3, r7 80002e2: 1a9a subs r2, r3, r2 80002e4: b2a3 uxth r3, r4 80002e6: fbb2 f0fe udiv r0, r2, lr 80002ea: fb0e 2210 mls r2, lr, r0, r2 80002ee: ea43 4302 orr.w r3, r3, r2, lsl #16 80002f2: fb00 fc0c mul.w ip, r0, ip 80002f6: 459c cmp ip, r3 80002f8: d909 bls.n 800030e <__udivmoddi4+0x8e> 80002fa: 18fb adds r3, r7, r3 80002fc: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 8000300: f080 80d6 bcs.w 80004b0 <__udivmoddi4+0x230> 8000304: 459c cmp ip, r3 8000306: f240 80d3 bls.w 80004b0 <__udivmoddi4+0x230> 800030a: 443b add r3, r7 800030c: 3802 subs r0, #2 800030e: ea40 4001 orr.w r0, r0, r1, lsl #16 8000312: eba3 030c sub.w r3, r3, ip 8000316: 2100 movs r1, #0 8000318: b11d cbz r5, 8000322 <__udivmoddi4+0xa2> 800031a: 40f3 lsrs r3, r6 800031c: 2200 movs r2, #0 800031e: e9c5 3200 strd r3, r2, [r5] 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000326: 428b cmp r3, r1 8000328: d905 bls.n 8000336 <__udivmoddi4+0xb6> 800032a: b10d cbz r5, 8000330 <__udivmoddi4+0xb0> 800032c: e9c5 0100 strd r0, r1, [r5] 8000330: 2100 movs r1, #0 8000332: 4608 mov r0, r1 8000334: e7f5 b.n 8000322 <__udivmoddi4+0xa2> 8000336: fab3 f183 clz r1, r3 800033a: 2900 cmp r1, #0 800033c: d146 bne.n 80003cc <__udivmoddi4+0x14c> 800033e: 4573 cmp r3, lr 8000340: d302 bcc.n 8000348 <__udivmoddi4+0xc8> 8000342: 4282 cmp r2, r0 8000344: f200 8105 bhi.w 8000552 <__udivmoddi4+0x2d2> 8000348: 1a84 subs r4, r0, r2 800034a: eb6e 0203 sbc.w r2, lr, r3 800034e: 2001 movs r0, #1 8000350: 4690 mov r8, r2 8000352: 2d00 cmp r5, #0 8000354: d0e5 beq.n 8000322 <__udivmoddi4+0xa2> 8000356: e9c5 4800 strd r4, r8, [r5] 800035a: e7e2 b.n 8000322 <__udivmoddi4+0xa2> 800035c: 2a00 cmp r2, #0 800035e: f000 8090 beq.w 8000482 <__udivmoddi4+0x202> 8000362: fab2 f682 clz r6, r2 8000366: 2e00 cmp r6, #0 8000368: f040 80a4 bne.w 80004b4 <__udivmoddi4+0x234> 800036c: 1a8a subs r2, r1, r2 800036e: 0c03 lsrs r3, r0, #16 8000370: ea4f 4e17 mov.w lr, r7, lsr #16 8000374: b280 uxth r0, r0 8000376: b2bc uxth r4, r7 8000378: 2101 movs r1, #1 800037a: fbb2 fcfe udiv ip, r2, lr 800037e: fb0e 221c mls r2, lr, ip, r2 8000382: ea43 4302 orr.w r3, r3, r2, lsl #16 8000386: fb04 f20c mul.w r2, r4, ip 800038a: 429a cmp r2, r3 800038c: d907 bls.n 800039e <__udivmoddi4+0x11e> 800038e: 18fb adds r3, r7, r3 8000390: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000394: d202 bcs.n 800039c <__udivmoddi4+0x11c> 8000396: 429a cmp r2, r3 8000398: f200 80e0 bhi.w 800055c <__udivmoddi4+0x2dc> 800039c: 46c4 mov ip, r8 800039e: 1a9b subs r3, r3, r2 80003a0: fbb3 f2fe udiv r2, r3, lr 80003a4: fb0e 3312 mls r3, lr, r2, r3 80003a8: ea40 4303 orr.w r3, r0, r3, lsl #16 80003ac: fb02 f404 mul.w r4, r2, r4 80003b0: 429c cmp r4, r3 80003b2: d907 bls.n 80003c4 <__udivmoddi4+0x144> 80003b4: 18fb adds r3, r7, r3 80003b6: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 80003ba: d202 bcs.n 80003c2 <__udivmoddi4+0x142> 80003bc: 429c cmp r4, r3 80003be: f200 80ca bhi.w 8000556 <__udivmoddi4+0x2d6> 80003c2: 4602 mov r2, r0 80003c4: 1b1b subs r3, r3, r4 80003c6: ea42 400c orr.w r0, r2, ip, lsl #16 80003ca: e7a5 b.n 8000318 <__udivmoddi4+0x98> 80003cc: f1c1 0620 rsb r6, r1, #32 80003d0: 408b lsls r3, r1 80003d2: fa22 f706 lsr.w r7, r2, r6 80003d6: 431f orrs r7, r3 80003d8: fa0e f401 lsl.w r4, lr, r1 80003dc: fa20 f306 lsr.w r3, r0, r6 80003e0: fa2e fe06 lsr.w lr, lr, r6 80003e4: ea4f 4917 mov.w r9, r7, lsr #16 80003e8: 4323 orrs r3, r4 80003ea: fa00 f801 lsl.w r8, r0, r1 80003ee: fa1f fc87 uxth.w ip, r7 80003f2: fbbe f0f9 udiv r0, lr, r9 80003f6: 0c1c lsrs r4, r3, #16 80003f8: fb09 ee10 mls lr, r9, r0, lr 80003fc: ea44 440e orr.w r4, r4, lr, lsl #16 8000400: fb00 fe0c mul.w lr, r0, ip 8000404: 45a6 cmp lr, r4 8000406: fa02 f201 lsl.w r2, r2, r1 800040a: d909 bls.n 8000420 <__udivmoddi4+0x1a0> 800040c: 193c adds r4, r7, r4 800040e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 8000412: f080 809c bcs.w 800054e <__udivmoddi4+0x2ce> 8000416: 45a6 cmp lr, r4 8000418: f240 8099 bls.w 800054e <__udivmoddi4+0x2ce> 800041c: 3802 subs r0, #2 800041e: 443c add r4, r7 8000420: eba4 040e sub.w r4, r4, lr 8000424: fa1f fe83 uxth.w lr, r3 8000428: fbb4 f3f9 udiv r3, r4, r9 800042c: fb09 4413 mls r4, r9, r3, r4 8000430: ea4e 4404 orr.w r4, lr, r4, lsl #16 8000434: fb03 fc0c mul.w ip, r3, ip 8000438: 45a4 cmp ip, r4 800043a: d908 bls.n 800044e <__udivmoddi4+0x1ce> 800043c: 193c adds r4, r7, r4 800043e: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 8000442: f080 8082 bcs.w 800054a <__udivmoddi4+0x2ca> 8000446: 45a4 cmp ip, r4 8000448: d97f bls.n 800054a <__udivmoddi4+0x2ca> 800044a: 3b02 subs r3, #2 800044c: 443c add r4, r7 800044e: ea43 4000 orr.w r0, r3, r0, lsl #16 8000452: eba4 040c sub.w r4, r4, ip 8000456: fba0 ec02 umull lr, ip, r0, r2 800045a: 4564 cmp r4, ip 800045c: 4673 mov r3, lr 800045e: 46e1 mov r9, ip 8000460: d362 bcc.n 8000528 <__udivmoddi4+0x2a8> 8000462: d05f beq.n 8000524 <__udivmoddi4+0x2a4> 8000464: b15d cbz r5, 800047e <__udivmoddi4+0x1fe> 8000466: ebb8 0203 subs.w r2, r8, r3 800046a: eb64 0409 sbc.w r4, r4, r9 800046e: fa04 f606 lsl.w r6, r4, r6 8000472: fa22 f301 lsr.w r3, r2, r1 8000476: 431e orrs r6, r3 8000478: 40cc lsrs r4, r1 800047a: e9c5 6400 strd r6, r4, [r5] 800047e: 2100 movs r1, #0 8000480: e74f b.n 8000322 <__udivmoddi4+0xa2> 8000482: fbb1 fcf2 udiv ip, r1, r2 8000486: 0c01 lsrs r1, r0, #16 8000488: ea41 410e orr.w r1, r1, lr, lsl #16 800048c: b280 uxth r0, r0 800048e: ea40 4201 orr.w r2, r0, r1, lsl #16 8000492: 463b mov r3, r7 8000494: 4638 mov r0, r7 8000496: 463c mov r4, r7 8000498: 46b8 mov r8, r7 800049a: 46be mov lr, r7 800049c: 2620 movs r6, #32 800049e: fbb1 f1f7 udiv r1, r1, r7 80004a2: eba2 0208 sub.w r2, r2, r8 80004a6: ea41 410c orr.w r1, r1, ip, lsl #16 80004aa: e766 b.n 800037a <__udivmoddi4+0xfa> 80004ac: 4601 mov r1, r0 80004ae: e718 b.n 80002e2 <__udivmoddi4+0x62> 80004b0: 4610 mov r0, r2 80004b2: e72c b.n 800030e <__udivmoddi4+0x8e> 80004b4: f1c6 0220 rsb r2, r6, #32 80004b8: fa2e f302 lsr.w r3, lr, r2 80004bc: 40b7 lsls r7, r6 80004be: 40b1 lsls r1, r6 80004c0: fa20 f202 lsr.w r2, r0, r2 80004c4: ea4f 4e17 mov.w lr, r7, lsr #16 80004c8: 430a orrs r2, r1 80004ca: fbb3 f8fe udiv r8, r3, lr 80004ce: b2bc uxth r4, r7 80004d0: fb0e 3318 mls r3, lr, r8, r3 80004d4: 0c11 lsrs r1, r2, #16 80004d6: ea41 4103 orr.w r1, r1, r3, lsl #16 80004da: fb08 f904 mul.w r9, r8, r4 80004de: 40b0 lsls r0, r6 80004e0: 4589 cmp r9, r1 80004e2: ea4f 4310 mov.w r3, r0, lsr #16 80004e6: b280 uxth r0, r0 80004e8: d93e bls.n 8000568 <__udivmoddi4+0x2e8> 80004ea: 1879 adds r1, r7, r1 80004ec: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004f0: d201 bcs.n 80004f6 <__udivmoddi4+0x276> 80004f2: 4589 cmp r9, r1 80004f4: d81f bhi.n 8000536 <__udivmoddi4+0x2b6> 80004f6: eba1 0109 sub.w r1, r1, r9 80004fa: fbb1 f9fe udiv r9, r1, lr 80004fe: fb09 f804 mul.w r8, r9, r4 8000502: fb0e 1119 mls r1, lr, r9, r1 8000506: b292 uxth r2, r2 8000508: ea42 4201 orr.w r2, r2, r1, lsl #16 800050c: 4542 cmp r2, r8 800050e: d229 bcs.n 8000564 <__udivmoddi4+0x2e4> 8000510: 18ba adds r2, r7, r2 8000512: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 8000516: d2c4 bcs.n 80004a2 <__udivmoddi4+0x222> 8000518: 4542 cmp r2, r8 800051a: d2c2 bcs.n 80004a2 <__udivmoddi4+0x222> 800051c: f1a9 0102 sub.w r1, r9, #2 8000520: 443a add r2, r7 8000522: e7be b.n 80004a2 <__udivmoddi4+0x222> 8000524: 45f0 cmp r8, lr 8000526: d29d bcs.n 8000464 <__udivmoddi4+0x1e4> 8000528: ebbe 0302 subs.w r3, lr, r2 800052c: eb6c 0c07 sbc.w ip, ip, r7 8000530: 3801 subs r0, #1 8000532: 46e1 mov r9, ip 8000534: e796 b.n 8000464 <__udivmoddi4+0x1e4> 8000536: eba7 0909 sub.w r9, r7, r9 800053a: 4449 add r1, r9 800053c: f1a8 0c02 sub.w ip, r8, #2 8000540: fbb1 f9fe udiv r9, r1, lr 8000544: fb09 f804 mul.w r8, r9, r4 8000548: e7db b.n 8000502 <__udivmoddi4+0x282> 800054a: 4673 mov r3, lr 800054c: e77f b.n 800044e <__udivmoddi4+0x1ce> 800054e: 4650 mov r0, sl 8000550: e766 b.n 8000420 <__udivmoddi4+0x1a0> 8000552: 4608 mov r0, r1 8000554: e6fd b.n 8000352 <__udivmoddi4+0xd2> 8000556: 443b add r3, r7 8000558: 3a02 subs r2, #2 800055a: e733 b.n 80003c4 <__udivmoddi4+0x144> 800055c: f1ac 0c02 sub.w ip, ip, #2 8000560: 443b add r3, r7 8000562: e71c b.n 800039e <__udivmoddi4+0x11e> 8000564: 4649 mov r1, r9 8000566: e79c b.n 80004a2 <__udivmoddi4+0x222> 8000568: eba1 0109 sub.w r1, r1, r9 800056c: 46c4 mov ip, r8 800056e: fbb1 f9fe udiv r9, r1, lr 8000572: fb09 f804 mul.w r8, r9, r4 8000576: e7c4 b.n 8000502 <__udivmoddi4+0x282> 08000578 <__aeabi_idiv0>: 8000578: 4770 bx lr 800057a: bf00 nop 0800057c : * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { 800057c: b480 push {r7} 800057e: b085 sub sp, #20 8000580: af00 add r7, sp, #0 8000582: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, Periphs); 8000584: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000588: 6c9a ldr r2, [r3, #72] @ 0x48 800058a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800058e: 687b ldr r3, [r7, #4] 8000590: 4313 orrs r3, r2 8000592: 648b str r3, [r1, #72] @ 0x48 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 8000594: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000598: 6c9a ldr r2, [r3, #72] @ 0x48 800059a: 687b ldr r3, [r7, #4] 800059c: 4013 ands r3, r2 800059e: 60fb str r3, [r7, #12] (void)tmpreg; 80005a0: 68fb ldr r3, [r7, #12] } 80005a2: bf00 nop 80005a4: 3714 adds r7, #20 80005a6: 46bd mov sp, r7 80005a8: bc80 pop {r7} 80005aa: 4770 bx lr 080005ac : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 80005ac: b580 push {r7, lr} 80005ae: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 80005b0: 2004 movs r0, #4 80005b2: f7ff ffe3 bl 800057c __HAL_RCC_DMA1_CLK_ENABLE(); 80005b6: 2001 movs r0, #1 80005b8: f7ff ffe0 bl 800057c /* DMA interrupt init */ /* DMA1_Channel5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); 80005bc: 2200 movs r2, #0 80005be: 2102 movs r1, #2 80005c0: 200f movs r0, #15 80005c2: f001 fadc bl 8001b7e HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); 80005c6: 200f movs r0, #15 80005c8: f001 faf3 bl 8001bb2 } 80005cc: bf00 nop 80005ce: bd80 pop {r7, pc} 080005d0 : * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { 80005d0: b480 push {r7} 80005d2: b085 sub sp, #20 80005d4: af00 add r7, sp, #0 80005d6: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, Periphs); 80005d8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80005dc: 6cda ldr r2, [r3, #76] @ 0x4c 80005de: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80005e2: 687b ldr r3, [r7, #4] 80005e4: 4313 orrs r3, r2 80005e6: 64cb str r3, [r1, #76] @ 0x4c /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80005e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80005ec: 6cda ldr r2, [r3, #76] @ 0x4c 80005ee: 687b ldr r3, [r7, #4] 80005f0: 4013 ands r3, r2 80005f2: 60fb str r3, [r7, #12] (void)tmpreg; 80005f4: 68fb ldr r3, [r7, #12] } 80005f6: bf00 nop 80005f8: 3714 adds r7, #20 80005fa: 46bd mov sp, r7 80005fc: bc80 pop {r7} 80005fe: 4770 bx lr 08000600 : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 8000600: b580 push {r7, lr} 8000602: b086 sub sp, #24 8000604: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000606: 1d3b adds r3, r7, #4 8000608: 2200 movs r2, #0 800060a: 601a str r2, [r3, #0] 800060c: 605a str r2, [r3, #4] 800060e: 609a str r2, [r3, #8] 8000610: 60da str r2, [r3, #12] 8000612: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8000614: 2002 movs r0, #2 8000616: f7ff ffdb bl 80005d0 __HAL_RCC_GPIOC_CLK_ENABLE(); 800061a: 2004 movs r0, #4 800061c: f7ff ffd8 bl 80005d0 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000620: 2001 movs r0, #1 8000622: f7ff ffd5 bl 80005d0 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED1_Pin|LED2_Pin|PROB2_Pin|PROB1_Pin 8000626: 2200 movs r2, #0 8000628: f44f 413a mov.w r1, #47616 @ 0xba00 800062c: 4829 ldr r0, [pc, #164] @ (80006d4 ) 800062e: f002 f92f bl 8002890 |LED3_Pin, GPIO_PIN_RESET); /*Configure GPIO pins : LED1_Pin LED2_Pin LED3_Pin */ GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin; 8000632: f44f 430a mov.w r3, #35328 @ 0x8a00 8000636: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000638: 2301 movs r3, #1 800063a: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 800063c: 2300 movs r3, #0 800063e: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000640: 2302 movs r3, #2 8000642: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000644: 1d3b adds r3, r7, #4 8000646: 4619 mov r1, r3 8000648: 4822 ldr r0, [pc, #136] @ (80006d4 ) 800064a: f001 fef3 bl 8002434 /*Configure GPIO pins : BUT1_Pin BUT2_Pin */ GPIO_InitStruct.Pin = BUT1_Pin|BUT2_Pin; 800064e: 2303 movs r3, #3 8000650: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8000652: f44f 1304 mov.w r3, #2162688 @ 0x210000 8000656: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000658: 2301 movs r3, #1 800065a: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800065c: 1d3b adds r3, r7, #4 800065e: 4619 mov r1, r3 8000660: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000664: f001 fee6 bl 8002434 /*Configure GPIO pins : PROB2_Pin PROB1_Pin */ GPIO_InitStruct.Pin = PROB2_Pin|PROB1_Pin; 8000668: f44f 5340 mov.w r3, #12288 @ 0x3000 800066c: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800066e: 2301 movs r3, #1 8000670: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000672: 2300 movs r3, #0 8000674: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000676: 2303 movs r3, #3 8000678: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800067a: 1d3b adds r3, r7, #4 800067c: 4619 mov r1, r3 800067e: 4815 ldr r0, [pc, #84] @ (80006d4 ) 8000680: f001 fed8 bl 8002434 /*Configure GPIO pin : BUT3_Pin */ GPIO_InitStruct.Pin = BUT3_Pin; 8000684: 2340 movs r3, #64 @ 0x40 8000686: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8000688: f44f 1304 mov.w r3, #2162688 @ 0x210000 800068c: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_PULLUP; 800068e: 2301 movs r3, #1 8000690: 60fb str r3, [r7, #12] HAL_GPIO_Init(BUT3_GPIO_Port, &GPIO_InitStruct); 8000692: 1d3b adds r3, r7, #4 8000694: 4619 mov r1, r3 8000696: 4810 ldr r0, [pc, #64] @ (80006d8 ) 8000698: f001 fecc bl 8002434 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); 800069c: 2200 movs r2, #0 800069e: 2100 movs r1, #0 80006a0: 2006 movs r0, #6 80006a2: f001 fa6c bl 8001b7e HAL_NVIC_EnableIRQ(EXTI0_IRQn); 80006a6: 2006 movs r0, #6 80006a8: f001 fa83 bl 8001bb2 HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0); 80006ac: 2200 movs r2, #0 80006ae: 2100 movs r1, #0 80006b0: 2007 movs r0, #7 80006b2: f001 fa64 bl 8001b7e HAL_NVIC_EnableIRQ(EXTI1_IRQn); 80006b6: 2007 movs r0, #7 80006b8: f001 fa7b bl 8001bb2 HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0); 80006bc: 2200 movs r2, #0 80006be: 2100 movs r1, #0 80006c0: 2016 movs r0, #22 80006c2: f001 fa5c bl 8001b7e HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 80006c6: 2016 movs r0, #22 80006c8: f001 fa73 bl 8001bb2 } 80006cc: bf00 nop 80006ce: 3718 adds r7, #24 80006d0: 46bd mov sp, r7 80006d2: bd80 pop {r7, pc} 80006d4: 48000400 .word 0x48000400 80006d8: 48000800 .word 0x48000800 080006dc : * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH * @arg @ref LL_RCC_LSEDRIVE_HIGH * @retval None */ __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) { 80006dc: b480 push {r7} 80006de: b083 sub sp, #12 80006e0: af00 add r7, sp, #0 80006e2: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 80006e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80006e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80006ec: f023 0218 bic.w r2, r3, #24 80006f0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80006f4: 687b ldr r3, [r7, #4] 80006f6: 4313 orrs r3, r2 80006f8: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 80006fc: bf00 nop 80006fe: 370c adds r7, #12 8000700: 46bd mov sp, r7 8000702: bc80 pop {r7} 8000704: 4770 bx lr 08000706
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000706: b580 push {r7, lr} 8000708: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800070a: f001 f911 bl 8001930 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800070e: f000 f807 bl 8000720 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000712: f7ff ff75 bl 8000600 MX_SubGHz_Phy_Init(); 8000716: f00b fb65 bl 800bde4 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { /* USER CODE END WHILE */ MX_SubGHz_Phy_Process(); 800071a: f00b fb6b bl 800bdf4 800071e: e7fc b.n 800071a 08000720 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000720: b580 push {r7, lr} 8000722: b09a sub sp, #104 @ 0x68 8000724: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000726: f107 0320 add.w r3, r7, #32 800072a: 2248 movs r2, #72 @ 0x48 800072c: 2100 movs r1, #0 800072e: 4618 mov r0, r3 8000730: f00e f82a bl 800e788 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000734: 1d3b adds r3, r7, #4 8000736: 2200 movs r2, #0 8000738: 601a str r2, [r3, #0] 800073a: 605a str r2, [r3, #4] 800073c: 609a str r2, [r3, #8] 800073e: 60da str r2, [r3, #12] 8000740: 611a str r2, [r3, #16] 8000742: 615a str r2, [r3, #20] 8000744: 619a str r2, [r3, #24] /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 8000746: f002 f8dd bl 8002904 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); 800074a: 2000 movs r0, #0 800074c: f7ff ffc6 bl 80006dc /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000750: 4b1e ldr r3, [pc, #120] @ (80007cc ) 8000752: 681b ldr r3, [r3, #0] 8000754: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8000758: 4a1c ldr r2, [pc, #112] @ (80007cc ) 800075a: f443 7300 orr.w r3, r3, #512 @ 0x200 800075e: 6013 str r3, [r2, #0] 8000760: 4b1a ldr r3, [pc, #104] @ (80007cc ) 8000762: 681b ldr r3, [r3, #0] 8000764: f403 63c0 and.w r3, r3, #1536 @ 0x600 8000768: 603b str r3, [r7, #0] 800076a: 683b ldr r3, [r7, #0] /** Initializes the CPU, AHB and APB buses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; 800076c: 2324 movs r3, #36 @ 0x24 800076e: 623b str r3, [r7, #32] RCC_OscInitStruct.LSEState = RCC_LSE_ON; 8000770: 2381 movs r3, #129 @ 0x81 8000772: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.MSIState = RCC_MSI_ON; 8000774: 2301 movs r3, #1 8000776: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; 8000778: 2300 movs r3, #0 800077a: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; 800077c: 23b0 movs r3, #176 @ 0xb0 800077e: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000780: 2300 movs r3, #0 8000782: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000784: f107 0320 add.w r3, r7, #32 8000788: 4618 mov r0, r3 800078a: f002 fc2f bl 8002fec 800078e: 4603 mov r3, r0 8000790: 2b00 cmp r3, #0 8000792: d001 beq.n 8000798 { Error_Handler(); 8000794: f000 f81c bl 80007d0 } /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK 8000798: 234f movs r3, #79 @ 0x4f 800079a: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 |RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; 800079c: 2300 movs r3, #0 800079e: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80007a0: 2300 movs r3, #0 80007a2: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80007a4: 2300 movs r3, #0 80007a6: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80007a8: 2300 movs r3, #0 80007aa: 617b str r3, [r7, #20] RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; 80007ac: 2300 movs r3, #0 80007ae: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80007b0: 1d3b adds r3, r7, #4 80007b2: 2102 movs r1, #2 80007b4: 4618 mov r0, r3 80007b6: f002 ff9b bl 80036f0 80007ba: 4603 mov r3, r0 80007bc: 2b00 cmp r3, #0 80007be: d001 beq.n 80007c4 { Error_Handler(); 80007c0: f000 f806 bl 80007d0 } } 80007c4: bf00 nop 80007c6: 3768 adds r7, #104 @ 0x68 80007c8: 46bd mov sp, r7 80007ca: bd80 pop {r7, pc} 80007cc: 58000400 .word 0x58000400 080007d0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80007d0: b480 push {r7} 80007d2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80007d4: b672 cpsid i } 80007d6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80007d8: bf00 nop 80007da: e7fd b.n 80007d8 080007dc : * @brief Enable RTC * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ __STATIC_INLINE void LL_RCC_EnableRTC(void) { 80007dc: b480 push {r7} 80007de: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 80007e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80007e4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80007e8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80007ec: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80007f0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 80007f4: bf00 nop 80007f6: 46bd mov sp, r7 80007f8: bc80 pop {r7} 80007fa: 4770 bx lr 080007fc : * @arg @ref LL_APB1_GRP1_PERIPH_DAC * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { 80007fc: b480 push {r7} 80007fe: b085 sub sp, #20 8000800: af00 add r7, sp, #0 8000802: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR1, Periphs); 8000804: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000808: 6d9a ldr r2, [r3, #88] @ 0x58 800080a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800080e: 687b ldr r3, [r7, #4] 8000810: 4313 orrs r3, r2 8000812: 658b str r3, [r1, #88] @ 0x58 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 8000814: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000818: 6d9a ldr r2, [r3, #88] @ 0x58 800081a: 687b ldr r3, [r7, #4] 800081c: 4013 ands r3, r2 800081e: 60fb str r3, [r7, #12] (void)tmpreg; 8000820: 68fb ldr r3, [r7, #12] } 8000822: bf00 nop 8000824: 3714 adds r7, #20 8000826: 46bd mov sp, r7 8000828: bc80 pop {r7} 800082a: 4770 bx lr 0800082c : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800082c: b580 push {r7, lr} 800082e: b08c sub sp, #48 @ 0x30 8000830: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ RTC_AlarmTypeDef sAlarm = {0}; 8000832: 1d3b adds r3, r7, #4 8000834: 222c movs r2, #44 @ 0x2c 8000836: 2100 movs r1, #0 8000838: 4618 mov r0, r3 800083a: f00d ffa5 bl 800e788 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800083e: 4b22 ldr r3, [pc, #136] @ (80008c8 ) 8000840: 4a22 ldr r2, [pc, #136] @ (80008cc ) 8000842: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_PREDIV_A; 8000844: 4b20 ldr r3, [pc, #128] @ (80008c8 ) 8000846: 221f movs r2, #31 8000848: 609a str r2, [r3, #8] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; 800084a: 4b1f ldr r3, [pc, #124] @ (80008c8 ) 800084c: 2200 movs r2, #0 800084e: 611a str r2, [r3, #16] hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; 8000850: 4b1d ldr r3, [pc, #116] @ (80008c8 ) 8000852: 2200 movs r2, #0 8000854: 615a str r2, [r3, #20] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 8000856: 4b1c ldr r3, [pc, #112] @ (80008c8 ) 8000858: 2200 movs r2, #0 800085a: 619a str r2, [r3, #24] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 800085c: 4b1a ldr r3, [pc, #104] @ (80008c8 ) 800085e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8000862: 61da str r2, [r3, #28] hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; 8000864: 4b18 ldr r3, [pc, #96] @ (80008c8 ) 8000866: 2200 movs r2, #0 8000868: 621a str r2, [r3, #32] hrtc.Init.BinMode = RTC_BINARY_ONLY; 800086a: 4b17 ldr r3, [pc, #92] @ (80008c8 ) 800086c: f44f 7280 mov.w r2, #256 @ 0x100 8000870: 625a str r2, [r3, #36] @ 0x24 if (HAL_RTC_Init(&hrtc) != HAL_OK) 8000872: 4815 ldr r0, [pc, #84] @ (80008c8 ) 8000874: f003 fc16 bl 80040a4 8000878: 4603 mov r3, r0 800087a: 2b00 cmp r3, #0 800087c: d001 beq.n 8000882 { Error_Handler(); 800087e: f7ff ffa7 bl 80007d0 /* USER CODE END Check_RTC_BKUP */ /** Initialize RTC and set the Time and Date */ if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK) 8000882: 4811 ldr r0, [pc, #68] @ (80008c8 ) 8000884: f003 ff16 bl 80046b4 8000888: 4603 mov r3, r0 800088a: 2b00 cmp r3, #0 800088c: d001 beq.n 8000892 { Error_Handler(); 800088e: f7ff ff9f bl 80007d0 } /** Enable the Alarm A */ sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; 8000892: 2300 movs r3, #0 8000894: 623b str r3, [r7, #32] sAlarm.AlarmTime.SubSeconds = 0x0; 8000896: 2300 movs r3, #0 8000898: 60bb str r3, [r7, #8] sAlarm.AlarmMask = RTC_ALARMMASK_NONE; 800089a: 2300 movs r3, #0 800089c: 61bb str r3, [r7, #24] sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; 800089e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80008a2: 61fb str r3, [r7, #28] sAlarm.Alarm = RTC_ALARM_A; 80008a4: f44f 7380 mov.w r3, #256 @ 0x100 80008a8: 62fb str r3, [r7, #44] @ 0x2c if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, 0) != HAL_OK) 80008aa: 1d3b adds r3, r7, #4 80008ac: 2200 movs r2, #0 80008ae: 4619 mov r1, r3 80008b0: 4805 ldr r0, [pc, #20] @ (80008c8 ) 80008b2: f003 fc83 bl 80041bc 80008b6: 4603 mov r3, r0 80008b8: 2b00 cmp r3, #0 80008ba: d001 beq.n 80008c0 { Error_Handler(); 80008bc: f7ff ff88 bl 80007d0 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 80008c0: bf00 nop 80008c2: 3730 adds r7, #48 @ 0x30 80008c4: 46bd mov sp, r7 80008c6: bd80 pop {r7, pc} 80008c8: 200000a8 .word 0x200000a8 80008cc: 40002800 .word 0x40002800 080008d0 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 80008d0: b580 push {r7, lr} 80008d2: b090 sub sp, #64 @ 0x40 80008d4: af00 add r7, sp, #0 80008d6: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80008d8: f107 0308 add.w r3, r7, #8 80008dc: 2238 movs r2, #56 @ 0x38 80008de: 2100 movs r1, #0 80008e0: 4618 mov r0, r3 80008e2: f00d ff51 bl 800e788 if(rtcHandle->Instance==RTC) 80008e6: 687b ldr r3, [r7, #4] 80008e8: 681b ldr r3, [r3, #0] 80008ea: 4a16 ldr r2, [pc, #88] @ (8000944 ) 80008ec: 4293 cmp r3, r2 80008ee: d125 bne.n 800093c /* USER CODE END RTC_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; 80008f0: f44f 3380 mov.w r3, #65536 @ 0x10000 80008f4: 60bb str r3, [r7, #8] PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 80008f6: f44f 7380 mov.w r3, #256 @ 0x100 80008fa: 63fb str r3, [r7, #60] @ 0x3c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80008fc: f107 0308 add.w r3, r7, #8 8000900: 4618 mov r0, r3 8000902: f003 fab5 bl 8003e70 8000906: 4603 mov r3, r0 8000908: 2b00 cmp r3, #0 800090a: d001 beq.n 8000910 { Error_Handler(); 800090c: f7ff ff60 bl 80007d0 } /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 8000910: f7ff ff64 bl 80007dc __HAL_RCC_RTCAPB_CLK_ENABLE(); 8000914: f44f 6080 mov.w r0, #1024 @ 0x400 8000918: f7ff ff70 bl 80007fc /* RTC interrupt Init */ HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0); 800091c: 2200 movs r2, #0 800091e: 2100 movs r1, #0 8000920: 2002 movs r0, #2 8000922: f001 f92c bl 8001b7e HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); 8000926: 2002 movs r0, #2 8000928: f001 f943 bl 8001bb2 HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); 800092c: 2200 movs r2, #0 800092e: 2100 movs r1, #0 8000930: 202a movs r0, #42 @ 0x2a 8000932: f001 f924 bl 8001b7e HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); 8000936: 202a movs r0, #42 @ 0x2a 8000938: f001 f93b bl 8001bb2 /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800093c: bf00 nop 800093e: 3740 adds r7, #64 @ 0x40 8000940: 46bd mov sp, r7 8000942: bd80 pop {r7, pc} 8000944: 40002800 .word 0x40002800 08000948 : * @brief Clear standby and stop flags for CPU1 * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void) { 8000948: b480 push {r7} 800094a: af00 add r7, sp, #0 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); 800094c: 4b03 ldr r3, [pc, #12] @ (800095c ) 800094e: 2201 movs r2, #1 8000950: f8c3 2088 str.w r2, [r3, #136] @ 0x88 } 8000954: bf00 nop 8000956: 46bd mov sp, r7 8000958: bc80 pop {r7} 800095a: 4770 bx lr 800095c: 58000400 .word 0x58000400 08000960 : /* USER CODE END PFP */ /* Exported functions --------------------------------------------------------*/ void PWR_EnterOffMode(void) { 8000960: b480 push {r7} 8000962: af00 add r7, sp, #0 /* USER CODE BEGIN EnterOffMode_1 */ /* USER CODE END EnterOffMode_1 */ } 8000964: bf00 nop 8000966: 46bd mov sp, r7 8000968: bc80 pop {r7} 800096a: 4770 bx lr 0800096c : void PWR_ExitOffMode(void) { 800096c: b480 push {r7} 800096e: af00 add r7, sp, #0 /* USER CODE BEGIN ExitOffMode_1 */ /* USER CODE END ExitOffMode_1 */ } 8000970: bf00 nop 8000972: 46bd mov sp, r7 8000974: bc80 pop {r7} 8000976: 4770 bx lr 08000978 : void PWR_EnterStopMode(void) { 8000978: b580 push {r7, lr} 800097a: af00 add r7, sp, #0 /* USER CODE BEGIN EnterStopMode_1 */ /* USER CODE END EnterStopMode_1 */ HAL_SuspendTick(); 800097c: f000 fff8 bl 8001970 /* Clear Status Flag before entering STOP/STANDBY Mode */ LL_PWR_ClearFlag_C1STOP_C1STB(); 8000980: f7ff ffe2 bl 8000948 /* USER CODE BEGIN EnterStopMode_2 */ /* USER CODE END EnterStopMode_2 */ HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); 8000984: 2001 movs r0, #1 8000986: f002 f84f bl 8002a28 /* USER CODE BEGIN EnterStopMode_3 */ /* USER CODE END EnterStopMode_3 */ } 800098a: bf00 nop 800098c: bd80 pop {r7, pc} 0800098e : void PWR_ExitStopMode(void) { 800098e: b580 push {r7, lr} 8000990: af00 add r7, sp, #0 /* USER CODE BEGIN ExitStopMode_1 */ /* USER CODE END ExitStopMode_1 */ /* Resume sysTick : work around for debugger problem in dual core */ HAL_ResumeTick(); 8000992: f000 fffb bl 800198c ADC interface DAC interface USARTx, TIMx, i2Cx, SPIx SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */ /* Resume not retained USARTx and DMA */ vcom_Resume(); 8000996: f000 fe47 bl 8001628 /* USER CODE BEGIN ExitStopMode_2 */ /* USER CODE END ExitStopMode_2 */ } 800099a: bf00 nop 800099c: bd80 pop {r7, pc} 0800099e : void PWR_EnterSleepMode(void) { 800099e: b580 push {r7, lr} 80009a0: af00 add r7, sp, #0 /* USER CODE BEGIN EnterSleepMode_1 */ /* USER CODE END EnterSleepMode_1 */ /* Suspend sysTick */ HAL_SuspendTick(); 80009a2: f000 ffe5 bl 8001970 /* USER CODE BEGIN EnterSleepMode_2 */ /* USER CODE END EnterSleepMode_2 */ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); 80009a6: 2101 movs r1, #1 80009a8: 2000 movs r0, #0 80009aa: f001 ffb9 bl 8002920 /* USER CODE BEGIN EnterSleepMode_3 */ /* USER CODE END EnterSleepMode_3 */ } 80009ae: bf00 nop 80009b0: bd80 pop {r7, pc} 080009b2 : void PWR_ExitSleepMode(void) { 80009b2: b580 push {r7, lr} 80009b4: af00 add r7, sp, #0 /* USER CODE BEGIN ExitSleepMode_1 */ /* USER CODE END ExitSleepMode_1 */ /* Resume sysTick */ HAL_ResumeTick(); 80009b6: f000 ffe9 bl 800198c /* USER CODE BEGIN ExitSleepMode_2 */ /* USER CODE END ExitSleepMode_2 */ } 80009ba: bf00 nop 80009bc: bd80 pop {r7, pc} 080009be : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80009be: b480 push {r7} 80009c0: af00 add r7, sp, #0 /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80009c2: bf00 nop 80009c4: 46bd mov sp, r7 80009c6: bc80 pop {r7} 80009c8: 4770 bx lr 080009ca : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80009ca: b480 push {r7} 80009cc: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80009ce: bf00 nop 80009d0: e7fd b.n 80009ce 080009d2 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80009d2: b480 push {r7} 80009d4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80009d6: bf00 nop 80009d8: e7fd b.n 80009d6 080009da : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80009da: b480 push {r7} 80009dc: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80009de: bf00 nop 80009e0: e7fd b.n 80009de 080009e2 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80009e2: b480 push {r7} 80009e4: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80009e6: bf00 nop 80009e8: e7fd b.n 80009e6 080009ea : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80009ea: b480 push {r7} 80009ec: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80009ee: bf00 nop 80009f0: e7fd b.n 80009ee 080009f2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80009f2: b480 push {r7} 80009f4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80009f6: bf00 nop 80009f8: 46bd mov sp, r7 80009fa: bc80 pop {r7} 80009fc: 4770 bx lr 080009fe : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80009fe: b480 push {r7} 8000a00: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000a02: bf00 nop 8000a04: 46bd mov sp, r7 8000a06: bc80 pop {r7} 8000a08: 4770 bx lr 08000a0a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000a0a: b480 push {r7} 8000a0c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000a0e: bf00 nop 8000a10: 46bd mov sp, r7 8000a12: bc80 pop {r7} 8000a14: 4770 bx lr 08000a16 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000a16: b480 push {r7} 8000a18: af00 add r7, sp, #0 /* USER CODE END SysTick_IRQn 0 */ /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000a1a: bf00 nop 8000a1c: 46bd mov sp, r7 8000a1e: bc80 pop {r7} 8000a20: 4770 bx lr ... 08000a24 : /** * @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts. */ void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void) { 8000a24: b580 push {r7, lr} 8000a26: af00 add r7, sp, #0 /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ HAL_RTCEx_SSRUIRQHandler(&hrtc); 8000a28: 4802 ldr r0, [pc, #8] @ (8000a34 ) 8000a2a: f003 fe7f bl 800472c /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ } 8000a2e: bf00 nop 8000a30: bd80 pop {r7, pc} 8000a32: bf00 nop 8000a34: 200000a8 .word 0x200000a8 08000a38 : /** * @brief This function handles EXTI Line 0 Interrupt. */ void EXTI0_IRQHandler(void) { 8000a38: b580 push {r7, lr} 8000a3a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI0_IRQn 0 */ /* USER CODE END EXTI0_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(BUT1_Pin); 8000a3c: 2001 movs r0, #1 8000a3e: f001 ff3f bl 80028c0 /* USER CODE BEGIN EXTI0_IRQn 1 */ /* USER CODE END EXTI0_IRQn 1 */ } 8000a42: bf00 nop 8000a44: bd80 pop {r7, pc} 08000a46 : /** * @brief This function handles EXTI Line 1 Interrupt. */ void EXTI1_IRQHandler(void) { 8000a46: b580 push {r7, lr} 8000a48: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI1_IRQn 0 */ /* USER CODE END EXTI1_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(BUT2_Pin); 8000a4a: 2002 movs r0, #2 8000a4c: f001 ff38 bl 80028c0 /* USER CODE BEGIN EXTI1_IRQn 1 */ /* USER CODE END EXTI1_IRQn 1 */ } 8000a50: bf00 nop 8000a52: bd80 pop {r7, pc} 08000a54 : /** * @brief This function handles DMA1 Channel 5 Interrupt. */ void DMA1_Channel5_IRQHandler(void) { 8000a54: b580 push {r7, lr} 8000a56: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ /* USER CODE END DMA1_Channel5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000a58: 4802 ldr r0, [pc, #8] @ (8000a64 ) 8000a5a: f001 fb41 bl 80020e0 /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ /* USER CODE END DMA1_Channel5_IRQn 1 */ } 8000a5e: bf00 nop 8000a60: bd80 pop {r7, pc} 8000a62: bf00 nop 8000a64: 20000190 .word 0x20000190 08000a68 : /** * @brief This function handles EXTI Lines [9:5] Interrupt. */ void EXTI9_5_IRQHandler(void) { 8000a68: b580 push {r7, lr} 8000a6a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(BUT3_Pin); 8000a6c: 2040 movs r0, #64 @ 0x40 8000a6e: f001 ff27 bl 80028c0 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 8000a72: bf00 nop 8000a74: bd80 pop {r7, pc} ... 08000a78 : /** * @brief This function handles USART2 Interrupt. */ void USART2_IRQHandler(void) { 8000a78: b580 push {r7, lr} 8000a7a: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000a7c: 4802 ldr r0, [pc, #8] @ (8000a88 ) 8000a7e: f004 fdfb bl 8005678 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000a82: bf00 nop 8000a84: bd80 pop {r7, pc} 8000a86: bf00 nop 8000a88: 200000fc .word 0x200000fc 08000a8c : /** * @brief This function handles RTC Alarms (A and B) Interrupt. */ void RTC_Alarm_IRQHandler(void) { 8000a8c: b580 push {r7, lr} 8000a8e: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Alarm_IRQn 0 */ /* USER CODE END RTC_Alarm_IRQn 0 */ HAL_RTC_AlarmIRQHandler(&hrtc); 8000a90: 4802 ldr r0, [pc, #8] @ (8000a9c ) 8000a92: f003 fcfb bl 800448c /* USER CODE BEGIN RTC_Alarm_IRQn 1 */ /* USER CODE END RTC_Alarm_IRQn 1 */ } 8000a96: bf00 nop 8000a98: bd80 pop {r7, pc} 8000a9a: bf00 nop 8000a9c: 200000a8 .word 0x200000a8 08000aa0 : /** * @brief This function handles SUBGHZ Radio Interrupt. */ void SUBGHZ_Radio_IRQHandler(void) { 8000aa0: b580 push {r7, lr} 8000aa2: af00 add r7, sp, #0 /* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */ /* USER CODE END SUBGHZ_Radio_IRQn 0 */ HAL_SUBGHZ_IRQHandler(&hsubghz); 8000aa4: 4802 ldr r0, [pc, #8] @ (8000ab0 ) 8000aa6: f004 f9af bl 8004e08 /* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */ /* USER CODE END SUBGHZ_Radio_IRQn 1 */ } 8000aaa: bf00 nop 8000aac: bd80 pop {r7, pc} 8000aae: bf00 nop 8000ab0: 200000e0 .word 0x200000e0 08000ab4 : * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI * @retval None */ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) { 8000ab4: b480 push {r7} 8000ab6: b085 sub sp, #20 8000ab8: af00 add r7, sp, #0 8000aba: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB3ENR, Periphs); 8000abc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000ac0: 6e5a ldr r2, [r3, #100] @ 0x64 8000ac2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 4313 orrs r3, r2 8000aca: 664b str r3, [r1, #100] @ 0x64 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB3ENR, Periphs); 8000acc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000ad0: 6e5a ldr r2, [r3, #100] @ 0x64 8000ad2: 687b ldr r3, [r7, #4] 8000ad4: 4013 ands r3, r2 8000ad6: 60fb str r3, [r7, #12] (void)tmpreg; 8000ad8: 68fb ldr r3, [r7, #12] } 8000ada: bf00 nop 8000adc: 3714 adds r7, #20 8000ade: 46bd mov sp, r7 8000ae0: bc80 pop {r7} 8000ae2: 4770 bx lr 08000ae4 : SUBGHZ_HandleTypeDef hsubghz; /* SUBGHZ init function */ void MX_SUBGHZ_Init(void) { 8000ae4: b580 push {r7, lr} 8000ae6: af00 add r7, sp, #0 /* USER CODE END SUBGHZ_Init 0 */ /* USER CODE BEGIN SUBGHZ_Init 1 */ /* USER CODE END SUBGHZ_Init 1 */ hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_4; 8000ae8: 4b06 ldr r3, [pc, #24] @ (8000b04 ) 8000aea: 2208 movs r2, #8 8000aec: 601a str r2, [r3, #0] if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) 8000aee: 4805 ldr r0, [pc, #20] @ (8000b04 ) 8000af0: f003 ff08 bl 8004904 8000af4: 4603 mov r3, r0 8000af6: 2b00 cmp r3, #0 8000af8: d001 beq.n 8000afe { Error_Handler(); 8000afa: f7ff fe69 bl 80007d0 } /* USER CODE BEGIN SUBGHZ_Init 2 */ /* USER CODE END SUBGHZ_Init 2 */ } 8000afe: bf00 nop 8000b00: bd80 pop {r7, pc} 8000b02: bf00 nop 8000b04: 200000e0 .word 0x200000e0 08000b08 : void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle) { 8000b08: b580 push {r7, lr} 8000b0a: b082 sub sp, #8 8000b0c: af00 add r7, sp, #0 8000b0e: 6078 str r0, [r7, #4] /* USER CODE BEGIN SUBGHZ_MspInit 0 */ /* USER CODE END SUBGHZ_MspInit 0 */ /* SUBGHZ clock enable */ __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); 8000b10: 2001 movs r0, #1 8000b12: f7ff ffcf bl 8000ab4 /* SUBGHZ interrupt Init */ HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0); 8000b16: 2200 movs r2, #0 8000b18: 2100 movs r1, #0 8000b1a: 2032 movs r0, #50 @ 0x32 8000b1c: f001 f82f bl 8001b7e HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn); 8000b20: 2032 movs r0, #50 @ 0x32 8000b22: f001 f846 bl 8001bb2 /* USER CODE BEGIN SUBGHZ_MspInit 1 */ /* USER CODE END SUBGHZ_MspInit 1 */ } 8000b26: bf00 nop 8000b28: 3708 adds r7, #8 8000b2a: 46bd mov sp, r7 8000b2c: bd80 pop {r7, pc} 08000b2e : { 8000b2e: b480 push {r7} 8000b30: b083 sub sp, #12 8000b32: af00 add r7, sp, #0 8000b34: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 8000b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000b3a: 689b ldr r3, [r3, #8] 8000b3c: f423 4200 bic.w r2, r3, #32768 @ 0x8000 8000b40: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8000b44: 687b ldr r3, [r7, #4] 8000b46: 4313 orrs r3, r2 8000b48: 608b str r3, [r1, #8] } 8000b4a: bf00 nop 8000b4c: 370c adds r7, #12 8000b4e: 46bd mov sp, r7 8000b50: bc80 pop {r7} 8000b52: 4770 bx lr 08000b54 : /* USER CODE END PFP */ /* Exported functions ---------------------------------------------------------*/ void SystemApp_Init(void) { 8000b54: b580 push {r7, lr} 8000b56: af00 add r7, sp, #0 /* USER CODE BEGIN SystemApp_Init_1 */ /* USER CODE END SystemApp_Init_1 */ /* Ensure that MSI is wake-up system clock */ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI); 8000b58: 2000 movs r0, #0 8000b5a: f7ff ffe8 bl 8000b2e /*Initialize timer and RTC*/ UTIL_TIMER_Init(); 8000b5e: f00c ffb7 bl 800dad0 SYS_TimerInitialisedFlag = 1; 8000b62: 4b0c ldr r3, [pc, #48] @ (8000b94 ) 8000b64: 2201 movs r2, #1 8000b66: 701a strb r2, [r3, #0] /* Initializes the SW probes pins and the monitor RF pins via Alternate Function */ DBG_Init(); 8000b68: f000 f8ba bl 8000ce0 /*Initialize the terminal */ UTIL_ADV_TRACE_Init(); 8000b6c: f00d fa40 bl 800dff0 UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow); 8000b70: 4809 ldr r0, [pc, #36] @ (8000b98 ) 8000b72: f00d fad9 bl 800e128 /*Set verbose LEVEL*/ UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL); 8000b76: 2002 movs r0, #2 8000b78: f00d fae4 bl 800e144 /*Init low power manager*/ UTIL_LPM_Init(); 8000b7c: f00c fab0 bl 800d0e0 /* Disable Stand-by mode */ UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); 8000b80: 2101 movs r1, #1 8000b82: 2001 movs r0, #1 8000b84: f00c faec bl 800d160 #if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1) /* Disable Stop Mode */ UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); 8000b88: 2101 movs r1, #1 8000b8a: 2001 movs r0, #1 8000b8c: f00c fab8 bl 800d100 #endif /* LOW_POWER_DISABLE */ /* USER CODE BEGIN SystemApp_Init_2 */ /* USER CODE END SystemApp_Init_2 */ } 8000b90: bf00 nop 8000b92: bd80 pop {r7, pc} 8000b94: 200000ec .word 0x200000ec 8000b98: 08000ba9 .word 0x08000ba9 08000b9c : /** * @brief redefines __weak function in stm32_seq.c such to enter low power */ void UTIL_SEQ_Idle(void) { 8000b9c: b580 push {r7, lr} 8000b9e: af00 add r7, sp, #0 /* USER CODE BEGIN UTIL_SEQ_Idle_1 */ /* USER CODE END UTIL_SEQ_Idle_1 */ UTIL_LPM_EnterLowPower(); 8000ba0: f00c fb0e bl 800d1c0 /* USER CODE BEGIN UTIL_SEQ_Idle_2 */ /* USER CODE END UTIL_SEQ_Idle_2 */ } 8000ba4: bf00 nop 8000ba6: bd80 pop {r7, pc} 08000ba8 : /* USER CODE END EF */ /* Private functions ---------------------------------------------------------*/ static void TimestampNow(uint8_t *buff, uint16_t *size) { 8000ba8: b580 push {r7, lr} 8000baa: b086 sub sp, #24 8000bac: af02 add r7, sp, #8 8000bae: 6078 str r0, [r7, #4] 8000bb0: 6039 str r1, [r7, #0] /* USER CODE BEGIN TimestampNow_1 */ /* USER CODE END TimestampNow_1 */ SysTime_t curtime = SysTimeGet(); 8000bb2: f107 0308 add.w r3, r7, #8 8000bb6: 4618 mov r0, r3 8000bb8: f00c fbac bl 800d314 tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds); 8000bbc: 68bb ldr r3, [r7, #8] 8000bbe: f9b7 200c ldrsh.w r2, [r7, #12] 8000bc2: 9200 str r2, [sp, #0] 8000bc4: 4a07 ldr r2, [pc, #28] @ (8000be4 ) 8000bc6: 2110 movs r1, #16 8000bc8: 6878 ldr r0, [r7, #4] 8000bca: f000 f81d bl 8000c08 *size = strlen((char *)buff); 8000bce: 6878 ldr r0, [r7, #4] 8000bd0: f7ff fae0 bl 8000194 8000bd4: 4603 mov r3, r0 8000bd6: b29a uxth r2, r3 8000bd8: 683b ldr r3, [r7, #0] 8000bda: 801a strh r2, [r3, #0] /* USER CODE BEGIN TimestampNow_2 */ /* USER CODE END TimestampNow_2 */ } 8000bdc: bf00 nop 8000bde: 3710 adds r7, #16 8000be0: 46bd mov sp, r7 8000be2: bd80 pop {r7, pc} 8000be4: 0800f0c0 .word 0x0800f0c0 08000be8 : /* Disable StopMode when traces need to be printed */ void UTIL_ADV_TRACE_PreSendHook(void) { 8000be8: b580 push {r7, lr} 8000bea: af00 add r7, sp, #0 /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */ /* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */ UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE); 8000bec: 2101 movs r1, #1 8000bee: 2002 movs r0, #2 8000bf0: f00c fa86 bl 800d100 /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */ /* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */ } 8000bf4: bf00 nop 8000bf6: bd80 pop {r7, pc} 08000bf8 : /* Re-enable StopMode when traces have been printed */ void UTIL_ADV_TRACE_PostSendHook(void) { 8000bf8: b580 push {r7, lr} 8000bfa: af00 add r7, sp, #0 /* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */ /* USER CODE END UTIL_LPM_SetStopMode_1 */ UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE); 8000bfc: 2100 movs r1, #0 8000bfe: 2002 movs r0, #2 8000c00: f00c fa7e bl 800d100 /* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */ /* USER CODE END UTIL_LPM_SetStopMode_2 */ } 8000c04: bf00 nop 8000c06: bd80 pop {r7, pc} 08000c08 : static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...) { 8000c08: b40c push {r2, r3} 8000c0a: b580 push {r7, lr} 8000c0c: b084 sub sp, #16 8000c0e: af00 add r7, sp, #0 8000c10: 6078 str r0, [r7, #4] 8000c12: 6039 str r1, [r7, #0] /* USER CODE BEGIN tiny_snprintf_like_1 */ /* USER CODE END tiny_snprintf_like_1 */ va_list vaArgs; va_start(vaArgs, strFormat); 8000c14: f107 031c add.w r3, r7, #28 8000c18: 60fb str r3, [r7, #12] UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs); 8000c1a: 6839 ldr r1, [r7, #0] 8000c1c: 68fb ldr r3, [r7, #12] 8000c1e: 69ba ldr r2, [r7, #24] 8000c20: 6878 ldr r0, [r7, #4] 8000c22: f00c fcc3 bl 800d5ac va_end(vaArgs); /* USER CODE BEGIN tiny_snprintf_like_2 */ /* USER CODE END tiny_snprintf_like_2 */ } 8000c26: bf00 nop 8000c28: 3710 adds r7, #16 8000c2a: 46bd mov sp, r7 8000c2c: e8bd 4080 ldmia.w sp!, {r7, lr} 8000c30: b002 add sp, #8 8000c32: 4770 bx lr 08000c34 : /** * @note This function overwrites the __weak one from HAL */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000c34: b480 push {r7} 8000c36: b083 sub sp, #12 8000c38: af00 add r7, sp, #0 8000c3a: 6078 str r0, [r7, #4] /*Don't enable SysTick if TIMER_IF is based on other counters (e.g. RTC) */ /* USER CODE BEGIN HAL_InitTick_1 */ /* USER CODE END HAL_InitTick_1 */ return HAL_OK; 8000c3c: 2300 movs r3, #0 /* USER CODE BEGIN HAL_InitTick_2 */ /* USER CODE END HAL_InitTick_2 */ } 8000c3e: 4618 mov r0, r3 8000c40: 370c adds r7, #12 8000c42: 46bd mov sp, r7 8000c44: bc80 pop {r7} 8000c46: 4770 bx lr 08000c48 : /** * @note This function overwrites the __weak one from HAL */ uint32_t HAL_GetTick(void) { 8000c48: b580 push {r7, lr} 8000c4a: b082 sub sp, #8 8000c4c: af00 add r7, sp, #0 uint32_t ret = 0; 8000c4e: 2300 movs r3, #0 8000c50: 607b str r3, [r7, #4] /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ /* USER CODE BEGIN HAL_GetTick_1 */ /* USER CODE END HAL_GetTick_1 */ if (SYS_TimerInitialisedFlag == 0) 8000c52: 4b06 ldr r3, [pc, #24] @ (8000c6c ) 8000c54: 781b ldrb r3, [r3, #0] 8000c56: 2b00 cmp r3, #0 8000c58: d002 beq.n 8000c60 /* USER CODE END HAL_GetTick_EarlyCall */ } else { ret = TIMER_IF_GetTimerValue(); 8000c5a: f000 f97b bl 8000f54 8000c5e: 6078 str r0, [r7, #4] } /* USER CODE BEGIN HAL_GetTick_2 */ /* USER CODE END HAL_GetTick_2 */ return ret; 8000c60: 687b ldr r3, [r7, #4] } 8000c62: 4618 mov r0, r3 8000c64: 3708 adds r7, #8 8000c66: 46bd mov sp, r7 8000c68: bd80 pop {r7, pc} 8000c6a: bf00 nop 8000c6c: 200000ec .word 0x200000ec 08000c70 : /** * @note This function overwrites the __weak one from HAL */ void HAL_Delay(__IO uint32_t Delay) { 8000c70: b580 push {r7, lr} 8000c72: b082 sub sp, #8 8000c74: af00 add r7, sp, #0 8000c76: 6078 str r0, [r7, #4] /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ /* USER CODE BEGIN HAL_Delay_1 */ /* USER CODE END HAL_Delay_1 */ TIMER_IF_DelayMs(Delay); 8000c78: 687b ldr r3, [r7, #4] 8000c7a: 4618 mov r0, r3 8000c7c: f000 f9f1 bl 8001062 /* USER CODE BEGIN HAL_Delay_2 */ /* USER CODE END HAL_Delay_2 */ } 8000c80: bf00 nop 8000c82: 3708 adds r7, #8 8000c84: 46bd mov sp, r7 8000c86: bd80 pop {r7, pc} 08000c88 : { 8000c88: b480 push {r7} 8000c8a: b085 sub sp, #20 8000c8c: af00 add r7, sp, #0 8000c8e: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 8000c90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000c94: 6cda ldr r2, [r3, #76] @ 0x4c 8000c96: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 4313 orrs r3, r2 8000c9e: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 8000ca0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8000ca4: 6cda ldr r2, [r3, #76] @ 0x4c 8000ca6: 687b ldr r3, [r7, #4] 8000ca8: 4013 ands r3, r2 8000caa: 60fb str r3, [r7, #12] (void)tmpreg; 8000cac: 68fb ldr r3, [r7, #12] } 8000cae: bf00 nop 8000cb0: 3714 adds r7, #20 8000cb2: 46bd mov sp, r7 8000cb4: bc80 pop {r7} 8000cb6: 4770 bx lr 08000cb8 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { 8000cb8: b480 push {r7} 8000cba: b083 sub sp, #12 8000cbc: af00 add r7, sp, #0 8000cbe: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); 8000cc0: 4b06 ldr r3, [pc, #24] @ (8000cdc ) 8000cc2: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 8000cc6: 4905 ldr r1, [pc, #20] @ (8000cdc ) 8000cc8: 687b ldr r3, [r7, #4] 8000cca: 4313 orrs r3, r2 8000ccc: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 8000cd0: bf00 nop 8000cd2: 370c adds r7, #12 8000cd4: 46bd mov sp, r7 8000cd6: bc80 pop {r7} 8000cd8: 4770 bx lr 8000cda: bf00 nop 8000cdc: 58000800 .word 0x58000800 08000ce0 : /** * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function */ void DBG_Init(void) { 8000ce0: b580 push {r7, lr} 8000ce2: b086 sub sp, #24 8000ce4: af00 add r7, sp, #0 HAL_DBGMCU_DisableDBGSleepMode(); HAL_DBGMCU_DisableDBGStopMode(); HAL_DBGMCU_DisableDBGStandbyMode(); #elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 ) /*Debug power up request wakeup CBDGPWRUPREQ*/ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46); 8000ce6: f44f 4080 mov.w r0, #16384 @ 0x4000 8000cea: f7ff ffe5 bl 8000cb8 /* Disabled HAL_DBGMCU_ */ HAL_DBGMCU_EnableDBGSleepMode(); 8000cee: f000 fe5b bl 80019a8 HAL_DBGMCU_EnableDBGStopMode(); 8000cf2: f000 fe5f bl 80019b4 HAL_DBGMCU_EnableDBGStandbyMode(); 8000cf6: f000 fe63 bl 80019c0 #elif !defined (DEBUGGER_ENABLED) #error "DEBUGGER_ENABLED not defined or out of range <0,1>" #endif /* DEBUGGER_OFF */ GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000cfa: 1d3b adds r3, r7, #4 8000cfc: 2200 movs r2, #0 8000cfe: 601a str r2, [r3, #0] 8000d00: 605a str r2, [r3, #4] 8000d02: 609a str r2, [r3, #8] 8000d04: 60da str r2, [r3, #12] 8000d06: 611a str r2, [r3, #16] /* Configure the GPIO pin */ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d08: 2301 movs r3, #1 8000d0a: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d0c: 2300 movs r3, #0 8000d0e: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000d10: 2303 movs r3, #3 8000d12: 613b str r3, [r7, #16] /* Enable the GPIO Clock */ PROBE_LINE1_CLK_ENABLE(); 8000d14: 2002 movs r0, #2 8000d16: f7ff ffb7 bl 8000c88 PROBE_LINE2_CLK_ENABLE(); 8000d1a: 2002 movs r0, #2 8000d1c: f7ff ffb4 bl 8000c88 GPIO_InitStruct.Pin = PROBE_LINE1_PIN; 8000d20: f44f 5380 mov.w r3, #4096 @ 0x1000 8000d24: 607b str r3, [r7, #4] HAL_GPIO_Init(PROBE_LINE1_PORT, &GPIO_InitStruct); 8000d26: 1d3b adds r3, r7, #4 8000d28: 4619 mov r1, r3 8000d2a: 480d ldr r0, [pc, #52] @ (8000d60 ) 8000d2c: f001 fb82 bl 8002434 GPIO_InitStruct.Pin = PROBE_LINE2_PIN; 8000d30: f44f 5300 mov.w r3, #8192 @ 0x2000 8000d34: 607b str r3, [r7, #4] HAL_GPIO_Init(PROBE_LINE2_PORT, &GPIO_InitStruct); 8000d36: 1d3b adds r3, r7, #4 8000d38: 4619 mov r1, r3 8000d3a: 4809 ldr r0, [pc, #36] @ (8000d60 ) 8000d3c: f001 fb7a bl 8002434 /* Reset probe Pins */ HAL_GPIO_WritePin(PROBE_LINE1_PORT, PROBE_LINE1_PIN, GPIO_PIN_RESET); 8000d40: 2200 movs r2, #0 8000d42: f44f 5180 mov.w r1, #4096 @ 0x1000 8000d46: 4806 ldr r0, [pc, #24] @ (8000d60 ) 8000d48: f001 fda2 bl 8002890 HAL_GPIO_WritePin(PROBE_LINE2_PORT, PROBE_LINE2_PIN, GPIO_PIN_RESET); 8000d4c: 2200 movs r2, #0 8000d4e: f44f 5100 mov.w r1, #8192 @ 0x2000 8000d52: 4803 ldr r0, [pc, #12] @ (8000d60 ) 8000d54: f001 fd9c bl 8002890 #endif /* DEBUG_RF_BUSY_ENABLED */ /* USER CODE BEGIN DBG_Init_3 */ /* USER CODE END DBG_Init_3 */ } 8000d58: bf00 nop 8000d5a: 3718 adds r7, #24 8000d5c: 46bd mov sp, r7 8000d5e: bd80 pop {r7, pc} 8000d60: 48000400 .word 0x48000400 08000d64 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8000d64: b580 push {r7, lr} 8000d66: b086 sub sp, #24 8000d68: af00 add r7, sp, #0 8000d6a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8000d6c: 4a14 ldr r2, [pc, #80] @ (8000dc0 <_sbrk+0x5c>) 8000d6e: 4b15 ldr r3, [pc, #84] @ (8000dc4 <_sbrk+0x60>) 8000d70: 1ad3 subs r3, r2, r3 8000d72: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8000d74: 697b ldr r3, [r7, #20] 8000d76: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8000d78: 4b13 ldr r3, [pc, #76] @ (8000dc8 <_sbrk+0x64>) 8000d7a: 681b ldr r3, [r3, #0] 8000d7c: 2b00 cmp r3, #0 8000d7e: d102 bne.n 8000d86 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8000d80: 4b11 ldr r3, [pc, #68] @ (8000dc8 <_sbrk+0x64>) 8000d82: 4a12 ldr r2, [pc, #72] @ (8000dcc <_sbrk+0x68>) 8000d84: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8000d86: 4b10 ldr r3, [pc, #64] @ (8000dc8 <_sbrk+0x64>) 8000d88: 681a ldr r2, [r3, #0] 8000d8a: 687b ldr r3, [r7, #4] 8000d8c: 4413 add r3, r2 8000d8e: 693a ldr r2, [r7, #16] 8000d90: 429a cmp r2, r3 8000d92: d207 bcs.n 8000da4 <_sbrk+0x40> { errno = ENOMEM; 8000d94: f00d fd12 bl 800e7bc <__errno> 8000d98: 4603 mov r3, r0 8000d9a: 220c movs r2, #12 8000d9c: 601a str r2, [r3, #0] return (void *)-1; 8000d9e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8000da2: e009 b.n 8000db8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8000da4: 4b08 ldr r3, [pc, #32] @ (8000dc8 <_sbrk+0x64>) 8000da6: 681b ldr r3, [r3, #0] 8000da8: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8000daa: 4b07 ldr r3, [pc, #28] @ (8000dc8 <_sbrk+0x64>) 8000dac: 681a ldr r2, [r3, #0] 8000dae: 687b ldr r3, [r7, #4] 8000db0: 4413 add r3, r2 8000db2: 4a05 ldr r2, [pc, #20] @ (8000dc8 <_sbrk+0x64>) 8000db4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8000db6: 68fb ldr r3, [r7, #12] } 8000db8: 4618 mov r0, r3 8000dba: 3718 adds r7, #24 8000dbc: 46bd mov sp, r7 8000dbe: bd80 pop {r7, pc} 8000dc0: 20010000 .word 0x20010000 8000dc4: 00000800 .word 0x00000800 8000dc8: 200000f0 .word 0x200000f0 8000dcc: 20001068 .word 0x20001068 08000dd0 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 8000dd0: b480 push {r7} 8000dd2: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ #endif } 8000dd4: bf00 nop 8000dd6: 46bd mov sp, r7 8000dd8: bc80 pop {r7} 8000dda: 4770 bx lr 08000ddc : * @param RTCx RTC Instance * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { 8000ddc: b480 push {r7} 8000dde: b083 sub sp, #12 8000de0: af00 add r7, sp, #0 8000de2: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); 8000de4: 687b ldr r3, [r7, #4] 8000de6: 689b ldr r3, [r3, #8] } 8000de8: 4618 mov r0, r3 8000dea: 370c adds r7, #12 8000dec: 46bd mov sp, r7 8000dee: bc80 pop {r7} 8000df0: 4770 bx lr ... 08000df4 : /* USER CODE END PFP */ /* Exported functions ---------------------------------------------------------*/ UTIL_TIMER_Status_t TIMER_IF_Init(void) { 8000df4: b580 push {r7, lr} 8000df6: b082 sub sp, #8 8000df8: af00 add r7, sp, #0 UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 8000dfa: 2300 movs r3, #0 8000dfc: 71fb strb r3, [r7, #7] /* USER CODE BEGIN TIMER_IF_Init */ /* USER CODE END TIMER_IF_Init */ if (RTC_Initialized == false) 8000dfe: 4b14 ldr r3, [pc, #80] @ (8000e50 ) 8000e00: 781b ldrb r3, [r3, #0] 8000e02: f083 0301 eor.w r3, r3, #1 8000e06: b2db uxtb r3, r3 8000e08: 2b00 cmp r3, #0 8000e0a: d01b beq.n 8000e44 { hrtc.IsEnabled.RtcFeatures = UINT32_MAX; 8000e0c: 4b11 ldr r3, [pc, #68] @ (8000e54 ) 8000e0e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000e12: 631a str r2, [r3, #48] @ 0x30 /*Init RTC*/ MX_RTC_Init(); 8000e14: f7ff fd0a bl 800082c /*Stop Timer */ TIMER_IF_StopTimer(); 8000e18: f000 f856 bl 8000ec8 /** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */ HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); 8000e1c: f44f 7180 mov.w r1, #256 @ 0x100 8000e20: 480c ldr r0, [pc, #48] @ (8000e54 ) 8000e22: f003 fad7 bl 80043d4 /*overload RTC feature enable*/ hrtc.IsEnabled.RtcFeatures = UINT32_MAX; 8000e26: 4b0b ldr r3, [pc, #44] @ (8000e54 ) 8000e28: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000e2c: 631a str r2, [r3, #48] @ 0x30 /*Enable Direct Read of the calendar registers (not through Shadow) */ HAL_RTCEx_EnableBypassShadow(&hrtc); 8000e2e: 4809 ldr r0, [pc, #36] @ (8000e54 ) 8000e30: f003 fc0e bl 8004650 /*Initialize MSB ticks*/ TIMER_IF_BkUp_Write_MSBticks(0); 8000e34: 2000 movs r0, #0 8000e36: f000 f9d3 bl 80011e0 TIMER_IF_SetTimerContext(); 8000e3a: f000 f85f bl 8000efc /* Register a task to associate to UTIL_TIMER_Irq() interrupt */ UTIL_TIMER_IRQ_MAP_INIT(); RTC_Initialized = true; 8000e3e: 4b04 ldr r3, [pc, #16] @ (8000e50 ) 8000e40: 2201 movs r2, #1 8000e42: 701a strb r2, [r3, #0] } /* USER CODE BEGIN TIMER_IF_Init_Last */ /* USER CODE END TIMER_IF_Init_Last */ return ret; 8000e44: 79fb ldrb r3, [r7, #7] } 8000e46: 4618 mov r0, r3 8000e48: 3708 adds r7, #8 8000e4a: 46bd mov sp, r7 8000e4c: bd80 pop {r7, pc} 8000e4e: bf00 nop 8000e50: 200000f4 .word 0x200000f4 8000e54: 200000a8 .word 0x200000a8 08000e58 : UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout) { 8000e58: b580 push {r7, lr} 8000e5a: b08e sub sp, #56 @ 0x38 8000e5c: af00 add r7, sp, #0 8000e5e: 6078 str r0, [r7, #4] UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 8000e60: 2300 movs r3, #0 8000e62: f887 3037 strb.w r3, [r7, #55] @ 0x37 /* USER CODE BEGIN TIMER_IF_StartTimer */ /* USER CODE END TIMER_IF_StartTimer */ RTC_AlarmTypeDef sAlarm = {0}; 8000e66: f107 0308 add.w r3, r7, #8 8000e6a: 222c movs r2, #44 @ 0x2c 8000e6c: 2100 movs r1, #0 8000e6e: 4618 mov r0, r3 8000e70: f00d fc8a bl 800e788 /*Stop timer if one is already started*/ TIMER_IF_StopTimer(); 8000e74: f000 f828 bl 8000ec8 timeout += RtcTimerContext; 8000e78: 4b11 ldr r3, [pc, #68] @ (8000ec0 ) 8000e7a: 681b ldr r3, [r3, #0] 8000e7c: 687a ldr r2, [r7, #4] 8000e7e: 4413 add r3, r2 8000e80: 607b str r3, [r7, #4] TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout); /* starts timer*/ sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; 8000e82: 2300 movs r3, #0 8000e84: 627b str r3, [r7, #36] @ 0x24 sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout; 8000e86: 687b ldr r3, [r7, #4] 8000e88: 43db mvns r3, r3 8000e8a: 60fb str r3, [r7, #12] sAlarm.AlarmMask = RTC_ALARMMASK_NONE; 8000e8c: 2300 movs r3, #0 8000e8e: 61fb str r3, [r7, #28] sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; 8000e90: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8000e94: 623b str r3, [r7, #32] sAlarm.Alarm = RTC_ALARM_A; 8000e96: f44f 7380 mov.w r3, #256 @ 0x100 8000e9a: 633b str r3, [r7, #48] @ 0x30 if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) 8000e9c: f107 0308 add.w r3, r7, #8 8000ea0: 2201 movs r2, #1 8000ea2: 4619 mov r1, r3 8000ea4: 4807 ldr r0, [pc, #28] @ (8000ec4 ) 8000ea6: f003 f989 bl 80041bc 8000eaa: 4603 mov r3, r0 8000eac: 2b00 cmp r3, #0 8000eae: d001 beq.n 8000eb4 { Error_Handler(); 8000eb0: f7ff fc8e bl 80007d0 } /* USER CODE BEGIN TIMER_IF_StartTimer_Last */ /* USER CODE END TIMER_IF_StartTimer_Last */ return ret; 8000eb4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 } 8000eb8: 4618 mov r0, r3 8000eba: 3738 adds r7, #56 @ 0x38 8000ebc: 46bd mov sp, r7 8000ebe: bd80 pop {r7, pc} 8000ec0: 200000f8 .word 0x200000f8 8000ec4: 200000a8 .word 0x200000a8 08000ec8 : UTIL_TIMER_Status_t TIMER_IF_StopTimer(void) { 8000ec8: b580 push {r7, lr} 8000eca: b082 sub sp, #8 8000ecc: af00 add r7, sp, #0 UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 8000ece: 2300 movs r3, #0 8000ed0: 71fb strb r3, [r7, #7] /* USER CODE BEGIN TIMER_IF_StopTimer */ /* USER CODE END TIMER_IF_StopTimer */ /* Clear RTC Alarm Flag */ __HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF); 8000ed2: 4b08 ldr r3, [pc, #32] @ (8000ef4 ) 8000ed4: 2201 movs r2, #1 8000ed6: 65da str r2, [r3, #92] @ 0x5c /* Disable the Alarm A interrupt */ HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); 8000ed8: f44f 7180 mov.w r1, #256 @ 0x100 8000edc: 4806 ldr r0, [pc, #24] @ (8000ef8 ) 8000ede: f003 fa79 bl 80043d4 /*overload RTC feature enable*/ hrtc.IsEnabled.RtcFeatures = UINT32_MAX; 8000ee2: 4b05 ldr r3, [pc, #20] @ (8000ef8 ) 8000ee4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000ee8: 631a str r2, [r3, #48] @ 0x30 /* USER CODE BEGIN TIMER_IF_StopTimer_Last */ /* USER CODE END TIMER_IF_StopTimer_Last */ return ret; 8000eea: 79fb ldrb r3, [r7, #7] } 8000eec: 4618 mov r0, r3 8000eee: 3708 adds r7, #8 8000ef0: 46bd mov sp, r7 8000ef2: bd80 pop {r7, pc} 8000ef4: 40002800 .word 0x40002800 8000ef8: 200000a8 .word 0x200000a8 08000efc : uint32_t TIMER_IF_SetTimerContext(void) { 8000efc: b580 push {r7, lr} 8000efe: af00 add r7, sp, #0 /*store time context*/ RtcTimerContext = GetTimerTicks(); 8000f00: f000 f98e bl 8001220 8000f04: 4603 mov r3, r0 8000f06: 4a03 ldr r2, [pc, #12] @ (8000f14 ) 8000f08: 6013 str r3, [r2, #0] /* USER CODE END TIMER_IF_SetTimerContext */ TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext); /*return time context*/ return RtcTimerContext; 8000f0a: 4b02 ldr r3, [pc, #8] @ (8000f14 ) 8000f0c: 681b ldr r3, [r3, #0] } 8000f0e: 4618 mov r0, r3 8000f10: bd80 pop {r7, pc} 8000f12: bf00 nop 8000f14: 200000f8 .word 0x200000f8 08000f18 : uint32_t TIMER_IF_GetTimerContext(void) { 8000f18: b480 push {r7} 8000f1a: af00 add r7, sp, #0 /* USER CODE END TIMER_IF_GetTimerContext */ TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext); /*return time context*/ return RtcTimerContext; 8000f1c: 4b02 ldr r3, [pc, #8] @ (8000f28 ) 8000f1e: 681b ldr r3, [r3, #0] } 8000f20: 4618 mov r0, r3 8000f22: 46bd mov sp, r7 8000f24: bc80 pop {r7} 8000f26: 4770 bx lr 8000f28: 200000f8 .word 0x200000f8 08000f2c : uint32_t TIMER_IF_GetTimerElapsedTime(void) { 8000f2c: b580 push {r7, lr} 8000f2e: b082 sub sp, #8 8000f30: af00 add r7, sp, #0 uint32_t ret = 0; 8000f32: 2300 movs r3, #0 8000f34: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */ /* USER CODE END TIMER_IF_GetTimerElapsedTime */ ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext)); 8000f36: f000 f973 bl 8001220 8000f3a: 4602 mov r2, r0 8000f3c: 4b04 ldr r3, [pc, #16] @ (8000f50 ) 8000f3e: 681b ldr r3, [r3, #0] 8000f40: 1ad3 subs r3, r2, r3 8000f42: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */ /* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */ return ret; 8000f44: 687b ldr r3, [r7, #4] } 8000f46: 4618 mov r0, r3 8000f48: 3708 adds r7, #8 8000f4a: 46bd mov sp, r7 8000f4c: bd80 pop {r7, pc} 8000f4e: bf00 nop 8000f50: 200000f8 .word 0x200000f8 08000f54 : uint32_t TIMER_IF_GetTimerValue(void) { 8000f54: b580 push {r7, lr} 8000f56: b082 sub sp, #8 8000f58: af00 add r7, sp, #0 uint32_t ret = 0; 8000f5a: 2300 movs r3, #0 8000f5c: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_GetTimerValue */ /* USER CODE END TIMER_IF_GetTimerValue */ if (RTC_Initialized == true) 8000f5e: 4b06 ldr r3, [pc, #24] @ (8000f78 ) 8000f60: 781b ldrb r3, [r3, #0] 8000f62: 2b00 cmp r3, #0 8000f64: d002 beq.n 8000f6c { ret = GetTimerTicks(); 8000f66: f000 f95b bl 8001220 8000f6a: 6078 str r0, [r7, #4] } /* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */ /* USER CODE END TIMER_IF_GetTimerValue_Last */ return ret; 8000f6c: 687b ldr r3, [r7, #4] } 8000f6e: 4618 mov r0, r3 8000f70: 3708 adds r7, #8 8000f72: 46bd mov sp, r7 8000f74: bd80 pop {r7, pc} 8000f76: bf00 nop 8000f78: 200000f4 .word 0x200000f4 08000f7c : uint32_t TIMER_IF_GetMinimumTimeout(void) { 8000f7c: b480 push {r7} 8000f7e: b083 sub sp, #12 8000f80: af00 add r7, sp, #0 uint32_t ret = 0; 8000f82: 2300 movs r3, #0 8000f84: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */ /* USER CODE END TIMER_IF_GetMinimumTimeout */ ret = (MIN_ALARM_DELAY); 8000f86: 2303 movs r3, #3 8000f88: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */ /* USER CODE END TIMER_IF_GetMinimumTimeout_Last */ return ret; 8000f8a: 687b ldr r3, [r7, #4] } 8000f8c: 4618 mov r0, r3 8000f8e: 370c adds r7, #12 8000f90: 46bd mov sp, r7 8000f92: bc80 pop {r7} 8000f94: 4770 bx lr 08000f96 : uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec) { 8000f96: b5b0 push {r4, r5, r7, lr} 8000f98: b084 sub sp, #16 8000f9a: af00 add r7, sp, #0 8000f9c: 6078 str r0, [r7, #4] uint32_t ret = 0; 8000f9e: 2100 movs r1, #0 8000fa0: 60f9 str r1, [r7, #12] /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */ /* USER CODE END TIMER_IF_Convert_ms2Tick */ ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000)); 8000fa2: 6879 ldr r1, [r7, #4] 8000fa4: 2000 movs r0, #0 8000fa6: 460a mov r2, r1 8000fa8: 4603 mov r3, r0 8000faa: 0d95 lsrs r5, r2, #22 8000fac: 0294 lsls r4, r2, #10 8000fae: f44f 727a mov.w r2, #1000 @ 0x3e8 8000fb2: f04f 0300 mov.w r3, #0 8000fb6: 4620 mov r0, r4 8000fb8: 4629 mov r1, r5 8000fba: f7ff f949 bl 8000250 <__aeabi_uldivmod> 8000fbe: 4602 mov r2, r0 8000fc0: 460b mov r3, r1 8000fc2: 4613 mov r3, r2 8000fc4: 60fb str r3, [r7, #12] /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */ /* USER CODE END TIMER_IF_Convert_ms2Tick_Last */ return ret; 8000fc6: 68fb ldr r3, [r7, #12] } 8000fc8: 4618 mov r0, r3 8000fca: 3710 adds r7, #16 8000fcc: 46bd mov sp, r7 8000fce: bdb0 pop {r4, r5, r7, pc} 08000fd0 : uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick) { 8000fd0: e92d 0fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp} 8000fd4: b085 sub sp, #20 8000fd6: af00 add r7, sp, #0 8000fd8: 6078 str r0, [r7, #4] uint32_t ret = 0; 8000fda: 2100 movs r1, #0 8000fdc: 60f9 str r1, [r7, #12] /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */ /* USER CODE END TIMER_IF_Convert_Tick2ms */ ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S)); 8000fde: 6879 ldr r1, [r7, #4] 8000fe0: 2000 movs r0, #0 8000fe2: 460c mov r4, r1 8000fe4: 4605 mov r5, r0 8000fe6: 4620 mov r0, r4 8000fe8: 4629 mov r1, r5 8000fea: f04f 0a00 mov.w sl, #0 8000fee: f04f 0b00 mov.w fp, #0 8000ff2: ea4f 1b41 mov.w fp, r1, lsl #5 8000ff6: ea4b 6bd0 orr.w fp, fp, r0, lsr #27 8000ffa: ea4f 1a40 mov.w sl, r0, lsl #5 8000ffe: 4650 mov r0, sl 8001000: 4659 mov r1, fp 8001002: 1b02 subs r2, r0, r4 8001004: eb61 0305 sbc.w r3, r1, r5 8001008: f04f 0000 mov.w r0, #0 800100c: f04f 0100 mov.w r1, #0 8001010: 0099 lsls r1, r3, #2 8001012: ea41 7192 orr.w r1, r1, r2, lsr #30 8001016: 0090 lsls r0, r2, #2 8001018: 4602 mov r2, r0 800101a: 460b mov r3, r1 800101c: eb12 0804 adds.w r8, r2, r4 8001020: eb43 0905 adc.w r9, r3, r5 8001024: f04f 0200 mov.w r2, #0 8001028: f04f 0300 mov.w r3, #0 800102c: ea4f 03c9 mov.w r3, r9, lsl #3 8001030: ea43 7358 orr.w r3, r3, r8, lsr #29 8001034: ea4f 02c8 mov.w r2, r8, lsl #3 8001038: 4690 mov r8, r2 800103a: 4699 mov r9, r3 800103c: 4640 mov r0, r8 800103e: 4649 mov r1, r9 8001040: f04f 0200 mov.w r2, #0 8001044: f04f 0300 mov.w r3, #0 8001048: 0a82 lsrs r2, r0, #10 800104a: ea42 5281 orr.w r2, r2, r1, lsl #22 800104e: 0a8b lsrs r3, r1, #10 8001050: 4613 mov r3, r2 8001052: 60fb str r3, [r7, #12] /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */ /* USER CODE END TIMER_IF_Convert_Tick2ms_Last */ return ret; 8001054: 68fb ldr r3, [r7, #12] } 8001056: 4618 mov r0, r3 8001058: 3714 adds r7, #20 800105a: 46bd mov sp, r7 800105c: e8bd 0fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp} 8001060: 4770 bx lr 08001062 : void TIMER_IF_DelayMs(uint32_t delay) { 8001062: b580 push {r7, lr} 8001064: b084 sub sp, #16 8001066: af00 add r7, sp, #0 8001068: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_DelayMs */ /* USER CODE END TIMER_IF_DelayMs */ uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay); 800106a: 6878 ldr r0, [r7, #4] 800106c: f7ff ff93 bl 8000f96 8001070: 60f8 str r0, [r7, #12] uint32_t timeout = GetTimerTicks(); 8001072: f000 f8d5 bl 8001220 8001076: 60b8 str r0, [r7, #8] /* Wait delay ms */ while (((GetTimerTicks() - timeout)) < delayTicks) 8001078: e000 b.n 800107c { __NOP(); 800107a: bf00 nop while (((GetTimerTicks() - timeout)) < delayTicks) 800107c: f000 f8d0 bl 8001220 8001080: 4602 mov r2, r0 8001082: 68bb ldr r3, [r7, #8] 8001084: 1ad3 subs r3, r2, r3 8001086: 68fa ldr r2, [r7, #12] 8001088: 429a cmp r2, r3 800108a: d8f6 bhi.n 800107a } /* USER CODE BEGIN TIMER_IF_DelayMs_Last */ /* USER CODE END TIMER_IF_DelayMs_Last */ } 800108c: bf00 nop 800108e: bf00 nop 8001090: 3710 adds r7, #16 8001092: 46bd mov sp, r7 8001094: bd80 pop {r7, pc} 08001096 : void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { 8001096: b580 push {r7, lr} 8001098: b082 sub sp, #8 800109a: af00 add r7, sp, #0 800109c: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback */ /* USER CODE END HAL_RTC_AlarmAEventCallback */ UTIL_TIMER_IRQ_MAP_PROCESS(); 800109e: f00c fe65 bl 800dd6c /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback_Last */ /* USER CODE END HAL_RTC_AlarmAEventCallback_Last */ } 80010a2: bf00 nop 80010a4: 3708 adds r7, #8 80010a6: 46bd mov sp, r7 80010a8: bd80 pop {r7, pc} 080010aa : void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) { 80010aa: b580 push {r7, lr} 80010ac: b084 sub sp, #16 80010ae: af00 add r7, sp, #0 80010b0: 6078 str r0, [r7, #4] /* USER CODE END HAL_RTCEx_SSRUEventCallback */ /*called every 48 days with 1024 ticks per seconds*/ TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks()); /*Increment MSBticks*/ uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks(); 80010b2: f000 f8a5 bl 8001200 80010b6: 60f8 str r0, [r7, #12] TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1); 80010b8: 68fb ldr r3, [r7, #12] 80010ba: 3301 adds r3, #1 80010bc: 4618 mov r0, r3 80010be: f000 f88f bl 80011e0 /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */ /* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */ } 80010c2: bf00 nop 80010c4: 3710 adds r7, #16 80010c6: 46bd mov sp, r7 80010c8: bd80 pop {r7, pc} 080010ca : uint32_t TIMER_IF_GetTime(uint16_t *mSeconds) { 80010ca: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80010ce: b08c sub sp, #48 @ 0x30 80010d0: af00 add r7, sp, #0 80010d2: 6178 str r0, [r7, #20] uint32_t seconds = 0; 80010d4: 2300 movs r3, #0 80010d6: 62fb str r3, [r7, #44] @ 0x2c /* USER CODE BEGIN TIMER_IF_GetTime */ /* USER CODE END TIMER_IF_GetTime */ uint64_t ticks; uint32_t timerValueLsb = GetTimerTicks(); 80010d8: f000 f8a2 bl 8001220 80010dc: 62b8 str r0, [r7, #40] @ 0x28 uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks(); 80010de: f000 f88f bl 8001200 80010e2: 6278 str r0, [r7, #36] @ 0x24 ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb; 80010e4: 6a7b ldr r3, [r7, #36] @ 0x24 80010e6: 2200 movs r2, #0 80010e8: 60bb str r3, [r7, #8] 80010ea: 60fa str r2, [r7, #12] 80010ec: f04f 0200 mov.w r2, #0 80010f0: f04f 0300 mov.w r3, #0 80010f4: 68b9 ldr r1, [r7, #8] 80010f6: 000b movs r3, r1 80010f8: 2200 movs r2, #0 80010fa: 6ab9 ldr r1, [r7, #40] @ 0x28 80010fc: 2000 movs r0, #0 80010fe: 460c mov r4, r1 8001100: 4605 mov r5, r0 8001102: eb12 0804 adds.w r8, r2, r4 8001106: eb43 0905 adc.w r9, r3, r5 800110a: e9c7 8906 strd r8, r9, [r7, #24] seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S); 800110e: e9d7 0106 ldrd r0, r1, [r7, #24] 8001112: f04f 0200 mov.w r2, #0 8001116: f04f 0300 mov.w r3, #0 800111a: 0a82 lsrs r2, r0, #10 800111c: ea42 5281 orr.w r2, r2, r1, lsl #22 8001120: 0a8b lsrs r3, r1, #10 8001122: 4613 mov r3, r2 8001124: 62fb str r3, [r7, #44] @ 0x2c ticks = (uint32_t) ticks & RTC_PREDIV_S; 8001126: 69bb ldr r3, [r7, #24] 8001128: 2200 movs r2, #0 800112a: 603b str r3, [r7, #0] 800112c: 607a str r2, [r7, #4] 800112e: 683b ldr r3, [r7, #0] 8001130: f3c3 0a09 ubfx sl, r3, #0, #10 8001134: f04f 0b00 mov.w fp, #0 8001138: e9c7 ab06 strd sl, fp, [r7, #24] *mSeconds = TIMER_IF_Convert_Tick2ms(ticks); 800113c: 69bb ldr r3, [r7, #24] 800113e: 4618 mov r0, r3 8001140: f7ff ff46 bl 8000fd0 8001144: 4603 mov r3, r0 8001146: b29a uxth r2, r3 8001148: 697b ldr r3, [r7, #20] 800114a: 801a strh r2, [r3, #0] /* USER CODE BEGIN TIMER_IF_GetTime_Last */ /* USER CODE END TIMER_IF_GetTime_Last */ return seconds; 800114c: 6afb ldr r3, [r7, #44] @ 0x2c } 800114e: 4618 mov r0, r3 8001150: 3730 adds r7, #48 @ 0x30 8001152: 46bd mov sp, r7 8001154: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 08001158 : void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds) { 8001158: b580 push {r7, lr} 800115a: b082 sub sp, #8 800115c: af00 add r7, sp, #0 800115e: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */ /* USER CODE END TIMER_IF_BkUp_Write_Seconds */ HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds); 8001160: 687a ldr r2, [r7, #4] 8001162: 2100 movs r1, #0 8001164: 4803 ldr r0, [pc, #12] @ (8001174 ) 8001166: f003 fb05 bl 8004774 /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */ /* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */ } 800116a: bf00 nop 800116c: 3708 adds r7, #8 800116e: 46bd mov sp, r7 8001170: bd80 pop {r7, pc} 8001172: bf00 nop 8001174: 200000a8 .word 0x200000a8 08001178 : void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds) { 8001178: b580 push {r7, lr} 800117a: b082 sub sp, #8 800117c: af00 add r7, sp, #0 800117e: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */ /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */ HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds); 8001180: 687a ldr r2, [r7, #4] 8001182: 2101 movs r1, #1 8001184: 4803 ldr r0, [pc, #12] @ (8001194 ) 8001186: f003 faf5 bl 8004774 /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */ /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */ } 800118a: bf00 nop 800118c: 3708 adds r7, #8 800118e: 46bd mov sp, r7 8001190: bd80 pop {r7, pc} 8001192: bf00 nop 8001194: 200000a8 .word 0x200000a8 08001198 : uint32_t TIMER_IF_BkUp_Read_Seconds(void) { 8001198: b580 push {r7, lr} 800119a: b082 sub sp, #8 800119c: af00 add r7, sp, #0 uint32_t ret = 0; 800119e: 2300 movs r3, #0 80011a0: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */ /* USER CODE END TIMER_IF_BkUp_Read_Seconds */ ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS); 80011a2: 2100 movs r1, #0 80011a4: 4804 ldr r0, [pc, #16] @ (80011b8 ) 80011a6: f003 fafd bl 80047a4 80011aa: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */ /* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */ return ret; 80011ac: 687b ldr r3, [r7, #4] } 80011ae: 4618 mov r0, r3 80011b0: 3708 adds r7, #8 80011b2: 46bd mov sp, r7 80011b4: bd80 pop {r7, pc} 80011b6: bf00 nop 80011b8: 200000a8 .word 0x200000a8 080011bc : uint32_t TIMER_IF_BkUp_Read_SubSeconds(void) { 80011bc: b580 push {r7, lr} 80011be: b082 sub sp, #8 80011c0: af00 add r7, sp, #0 uint32_t ret = 0; 80011c2: 2300 movs r3, #0 80011c4: 607b str r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */ /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */ ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS); 80011c6: 2101 movs r1, #1 80011c8: 4804 ldr r0, [pc, #16] @ (80011dc ) 80011ca: f003 faeb bl 80047a4 80011ce: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */ /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */ return ret; 80011d0: 687b ldr r3, [r7, #4] } 80011d2: 4618 mov r0, r3 80011d4: 3708 adds r7, #8 80011d6: 46bd mov sp, r7 80011d8: bd80 pop {r7, pc} 80011da: bf00 nop 80011dc: 200000a8 .word 0x200000a8 080011e0 : /* USER CODE END EF */ /* Private functions ---------------------------------------------------------*/ static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks) { 80011e0: b580 push {r7, lr} 80011e2: b082 sub sp, #8 80011e4: af00 add r7, sp, #0 80011e6: 6078 str r0, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */ /* USER CODE END TIMER_IF_BkUp_Write_MSBticks */ HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks); 80011e8: 687a ldr r2, [r7, #4] 80011ea: 2102 movs r1, #2 80011ec: 4803 ldr r0, [pc, #12] @ (80011fc ) 80011ee: f003 fac1 bl 8004774 /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */ /* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */ } 80011f2: bf00 nop 80011f4: 3708 adds r7, #8 80011f6: 46bd mov sp, r7 80011f8: bd80 pop {r7, pc} 80011fa: bf00 nop 80011fc: 200000a8 .word 0x200000a8 08001200 : static uint32_t TIMER_IF_BkUp_Read_MSBticks(void) { 8001200: b580 push {r7, lr} 8001202: b082 sub sp, #8 8001204: af00 add r7, sp, #0 /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */ /* USER CODE END TIMER_IF_BkUp_Read_MSBticks */ uint32_t MSBticks; MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS); 8001206: 2102 movs r1, #2 8001208: 4804 ldr r0, [pc, #16] @ (800121c ) 800120a: f003 facb bl 80047a4 800120e: 6078 str r0, [r7, #4] return MSBticks; 8001210: 687b ldr r3, [r7, #4] /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */ /* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */ } 8001212: 4618 mov r0, r3 8001214: 3708 adds r7, #8 8001216: 46bd mov sp, r7 8001218: bd80 pop {r7, pc} 800121a: bf00 nop 800121c: 200000a8 .word 0x200000a8 08001220 : static inline uint32_t GetTimerTicks(void) { 8001220: b580 push {r7, lr} 8001222: b082 sub sp, #8 8001224: af00 add r7, sp, #0 /* USER CODE BEGIN GetTimerTicks */ /* USER CODE END GetTimerTicks */ uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC); 8001226: 480b ldr r0, [pc, #44] @ (8001254 ) 8001228: f7ff fdd8 bl 8000ddc 800122c: 6078 str r0, [r7, #4] /* read twice to make sure value it valid*/ while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) 800122e: e003 b.n 8001238 { ssr = LL_RTC_TIME_GetSubSecond(RTC); 8001230: 4808 ldr r0, [pc, #32] @ (8001254 ) 8001232: f7ff fdd3 bl 8000ddc 8001236: 6078 str r0, [r7, #4] while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) 8001238: 4806 ldr r0, [pc, #24] @ (8001254 ) 800123a: f7ff fdcf bl 8000ddc 800123e: 4602 mov r2, r0 8001240: 687b ldr r3, [r7, #4] 8001242: 4293 cmp r3, r2 8001244: d1f4 bne.n 8001230 } return UINT32_MAX - ssr; 8001246: 687b ldr r3, [r7, #4] 8001248: 43db mvns r3, r3 /* USER CODE BEGIN GetTimerTicks_Last */ /* USER CODE END GetTimerTicks_Last */ } 800124a: 4618 mov r0, r3 800124c: 3708 adds r7, #8 800124e: 46bd mov sp, r7 8001250: bd80 pop {r7, pc} 8001252: bf00 nop 8001254: 40002800 .word 0x40002800 08001258 : { 8001258: b480 push {r7} 800125a: b085 sub sp, #20 800125c: af00 add r7, sp, #0 800125e: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 8001260: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001264: 6cda ldr r2, [r3, #76] @ 0x4c 8001266: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800126a: 687b ldr r3, [r7, #4] 800126c: 4313 orrs r3, r2 800126e: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 8001270: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001274: 6cda ldr r2, [r3, #76] @ 0x4c 8001276: 687b ldr r3, [r7, #4] 8001278: 4013 ands r3, r2 800127a: 60fb str r3, [r7, #12] (void)tmpreg; 800127c: 68fb ldr r3, [r7, #12] } 800127e: bf00 nop 8001280: 3714 adds r7, #20 8001282: 46bd mov sp, r7 8001284: bc80 pop {r7} 8001286: 4770 bx lr 08001288 : { 8001288: b480 push {r7} 800128a: b085 sub sp, #20 800128c: af00 add r7, sp, #0 800128e: 6078 str r0, [r7, #4] SET_BIT(RCC->APB1ENR1, Periphs); 8001290: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001294: 6d9a ldr r2, [r3, #88] @ 0x58 8001296: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800129a: 687b ldr r3, [r7, #4] 800129c: 4313 orrs r3, r2 800129e: 658b str r3, [r1, #88] @ 0x58 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 80012a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80012a4: 6d9a ldr r2, [r3, #88] @ 0x58 80012a6: 687b ldr r3, [r7, #4] 80012a8: 4013 ands r3, r2 80012aa: 60fb str r3, [r7, #12] (void)tmpreg; 80012ac: 68fb ldr r3, [r7, #12] } 80012ae: bf00 nop 80012b0: 3714 adds r7, #20 80012b2: 46bd mov sp, r7 80012b4: bc80 pop {r7} 80012b6: 4770 bx lr 080012b8 : { 80012b8: b480 push {r7} 80012ba: b083 sub sp, #12 80012bc: af00 add r7, sp, #0 80012be: 6078 str r0, [r7, #4] CLEAR_BIT(RCC->APB1ENR1, Periphs); 80012c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80012c4: 6d9a ldr r2, [r3, #88] @ 0x58 80012c6: 687b ldr r3, [r7, #4] 80012c8: 43db mvns r3, r3 80012ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80012ce: 4013 ands r3, r2 80012d0: 658b str r3, [r1, #88] @ 0x58 } 80012d2: bf00 nop 80012d4: 370c adds r7, #12 80012d6: 46bd mov sp, r7 80012d8: bc80 pop {r7} 80012da: 4770 bx lr 080012dc : DMA_HandleTypeDef hdma_usart2_tx; /* USART2 init function */ void MX_USART2_UART_Init(void) { 80012dc: b580 push {r7, lr} 80012de: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80012e0: 4b22 ldr r3, [pc, #136] @ (800136c ) 80012e2: 4a23 ldr r2, [pc, #140] @ (8001370 ) 80012e4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80012e6: 4b21 ldr r3, [pc, #132] @ (800136c ) 80012e8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80012ec: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80012ee: 4b1f ldr r3, [pc, #124] @ (800136c ) 80012f0: 2200 movs r2, #0 80012f2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80012f4: 4b1d ldr r3, [pc, #116] @ (800136c ) 80012f6: 2200 movs r2, #0 80012f8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80012fa: 4b1c ldr r3, [pc, #112] @ (800136c ) 80012fc: 2200 movs r2, #0 80012fe: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001300: 4b1a ldr r3, [pc, #104] @ (800136c ) 8001302: 220c movs r2, #12 8001304: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001306: 4b19 ldr r3, [pc, #100] @ (800136c ) 8001308: 2200 movs r2, #0 800130a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800130c: 4b17 ldr r3, [pc, #92] @ (800136c ) 800130e: 2200 movs r2, #0 8001310: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8001312: 4b16 ldr r3, [pc, #88] @ (800136c ) 8001314: 2200 movs r2, #0 8001316: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001318: 4b14 ldr r3, [pc, #80] @ (800136c ) 800131a: 2200 movs r2, #0 800131c: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 800131e: 4b13 ldr r3, [pc, #76] @ (800136c ) 8001320: 2200 movs r2, #0 8001322: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8001324: 4811 ldr r0, [pc, #68] @ (800136c ) 8001326: f003 ff40 bl 80051aa 800132a: 4603 mov r3, r0 800132c: 2b00 cmp r3, #0 800132e: d001 beq.n 8001334 { Error_Handler(); 8001330: f7ff fa4e bl 80007d0 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001334: 2100 movs r1, #0 8001336: 480d ldr r0, [pc, #52] @ (800136c ) 8001338: f006 f9bb bl 80076b2 800133c: 4603 mov r3, r0 800133e: 2b00 cmp r3, #0 8001340: d001 beq.n 8001346 { Error_Handler(); 8001342: f7ff fa45 bl 80007d0 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001346: 2100 movs r1, #0 8001348: 4808 ldr r0, [pc, #32] @ (800136c ) 800134a: f006 f9f0 bl 800772e 800134e: 4603 mov r3, r0 8001350: 2b00 cmp r3, #0 8001352: d001 beq.n 8001358 { Error_Handler(); 8001354: f7ff fa3c bl 80007d0 } if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) 8001358: 4804 ldr r0, [pc, #16] @ (800136c ) 800135a: f006 f96f bl 800763c 800135e: 4603 mov r3, r0 8001360: 2b00 cmp r3, #0 8001362: d001 beq.n 8001368 { Error_Handler(); 8001364: f7ff fa34 bl 80007d0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001368: bf00 nop 800136a: bd80 pop {r7, pc} 800136c: 200000fc .word 0x200000fc 8001370: 40004400 .word 0x40004400 08001374 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001374: b580 push {r7, lr} 8001376: b096 sub sp, #88 @ 0x58 8001378: af00 add r7, sp, #0 800137a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800137c: f107 0344 add.w r3, r7, #68 @ 0x44 8001380: 2200 movs r2, #0 8001382: 601a str r2, [r3, #0] 8001384: 605a str r2, [r3, #4] 8001386: 609a str r2, [r3, #8] 8001388: 60da str r2, [r3, #12] 800138a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800138c: f107 030c add.w r3, r7, #12 8001390: 2238 movs r2, #56 @ 0x38 8001392: 2100 movs r1, #0 8001394: 4618 mov r0, r3 8001396: f00d f9f7 bl 800e788 if(uartHandle->Instance==USART2) 800139a: 687b ldr r3, [r7, #4] 800139c: 681b ldr r3, [r3, #0] 800139e: 4a33 ldr r2, [pc, #204] @ (800146c ) 80013a0: 4293 cmp r3, r2 80013a2: d15f bne.n 8001464 /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; 80013a4: 2302 movs r3, #2 80013a6: 60fb str r3, [r7, #12] PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK; 80013a8: 4b31 ldr r3, [pc, #196] @ (8001470 ) 80013aa: 617b str r3, [r7, #20] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80013ac: f107 030c add.w r3, r7, #12 80013b0: 4618 mov r0, r3 80013b2: f002 fd5d bl 8003e70 80013b6: 4603 mov r3, r0 80013b8: 2b00 cmp r3, #0 80013ba: d001 beq.n 80013c0 { Error_Handler(); 80013bc: f7ff fa08 bl 80007d0 } /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 80013c0: f44f 3000 mov.w r0, #131072 @ 0x20000 80013c4: f7ff ff60 bl 8001288 __HAL_RCC_GPIOA_CLK_ENABLE(); 80013c8: 2001 movs r0, #1 80013ca: f7ff ff45 bl 8001258 /**USART2 GPIO Configuration PA3 ------> USART2_RX PA2 ------> USART2_TX */ GPIO_InitStruct.Pin = USARTx_RX_Pin|USARTx_TX_Pin; 80013ce: 230c movs r3, #12 80013d0: 647b str r3, [r7, #68] @ 0x44 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013d2: 2302 movs r3, #2 80013d4: 64bb str r3, [r7, #72] @ 0x48 GPIO_InitStruct.Pull = GPIO_NOPULL; 80013d6: 2300 movs r3, #0 80013d8: 64fb str r3, [r7, #76] @ 0x4c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013da: 2303 movs r3, #3 80013dc: 653b str r3, [r7, #80] @ 0x50 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 80013de: 2307 movs r3, #7 80013e0: 657b str r3, [r7, #84] @ 0x54 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80013e2: f107 0344 add.w r3, r7, #68 @ 0x44 80013e6: 4619 mov r1, r3 80013e8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80013ec: f001 f822 bl 8002434 /* USART2 DMA Init */ /* USART2_TX Init */ hdma_usart2_tx.Instance = DMA1_Channel5; 80013f0: 4b20 ldr r3, [pc, #128] @ (8001474 ) 80013f2: 4a21 ldr r2, [pc, #132] @ (8001478 ) 80013f4: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; 80013f6: 4b1f ldr r3, [pc, #124] @ (8001474 ) 80013f8: 2214 movs r2, #20 80013fa: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80013fc: 4b1d ldr r3, [pc, #116] @ (8001474 ) 80013fe: 2210 movs r2, #16 8001400: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001402: 4b1c ldr r3, [pc, #112] @ (8001474 ) 8001404: 2200 movs r2, #0 8001406: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8001408: 4b1a ldr r3, [pc, #104] @ (8001474 ) 800140a: 2280 movs r2, #128 @ 0x80 800140c: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800140e: 4b19 ldr r3, [pc, #100] @ (8001474 ) 8001410: 2200 movs r2, #0 8001412: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001414: 4b17 ldr r3, [pc, #92] @ (8001474 ) 8001416: 2200 movs r2, #0 8001418: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800141a: 4b16 ldr r3, [pc, #88] @ (8001474 ) 800141c: 2200 movs r2, #0 800141e: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001420: 4b14 ldr r3, [pc, #80] @ (8001474 ) 8001422: 2200 movs r2, #0 8001424: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001426: 4813 ldr r0, [pc, #76] @ (8001474 ) 8001428: f000 fbe0 bl 8001bec 800142c: 4603 mov r3, r0 800142e: 2b00 cmp r3, #0 8001430: d001 beq.n 8001436 { Error_Handler(); 8001432: f7ff f9cd bl 80007d0 } if (HAL_DMA_ConfigChannelAttributes(&hdma_usart2_tx, DMA_CHANNEL_NPRIV) != HAL_OK) 8001436: 2110 movs r1, #16 8001438: 480e ldr r0, [pc, #56] @ (8001474 ) 800143a: f000 ff22 bl 8002282 800143e: 4603 mov r3, r0 8001440: 2b00 cmp r3, #0 8001442: d001 beq.n 8001448 { Error_Handler(); 8001444: f7ff f9c4 bl 80007d0 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001448: 687b ldr r3, [r7, #4] 800144a: 4a0a ldr r2, [pc, #40] @ (8001474 ) 800144c: 67da str r2, [r3, #124] @ 0x7c 800144e: 4a09 ldr r2, [pc, #36] @ (8001474 ) 8001450: 687b ldr r3, [r7, #4] 8001452: 6293 str r3, [r2, #40] @ 0x28 /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); 8001454: 2200 movs r2, #0 8001456: 2102 movs r1, #2 8001458: 2025 movs r0, #37 @ 0x25 800145a: f000 fb90 bl 8001b7e HAL_NVIC_EnableIRQ(USART2_IRQn); 800145e: 2025 movs r0, #37 @ 0x25 8001460: f000 fba7 bl 8001bb2 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001464: bf00 nop 8001466: 3758 adds r7, #88 @ 0x58 8001468: 46bd mov sp, r7 800146a: bd80 pop {r7, pc} 800146c: 40004400 .word 0x40004400 8001470: 000c0004 .word 0x000c0004 8001474: 20000190 .word 0x20000190 8001478: 40020058 .word 0x40020058 0800147c : void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { 800147c: b580 push {r7, lr} 800147e: b082 sub sp, #8 8001480: af00 add r7, sp, #0 8001482: 6078 str r0, [r7, #4] if(uartHandle->Instance==USART2) 8001484: 687b ldr r3, [r7, #4] 8001486: 681b ldr r3, [r3, #0] 8001488: 4a0b ldr r2, [pc, #44] @ (80014b8 ) 800148a: 4293 cmp r3, r2 800148c: d110 bne.n 80014b0 { /* USER CODE BEGIN USART2_MspDeInit 0 */ /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); 800148e: f44f 3000 mov.w r0, #131072 @ 0x20000 8001492: f7ff ff11 bl 80012b8 /**USART2 GPIO Configuration PA3 ------> USART2_RX PA2 ------> USART2_TX */ HAL_GPIO_DeInit(GPIOA, USARTx_RX_Pin|USARTx_TX_Pin); 8001496: 210c movs r1, #12 8001498: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800149c: f001 f92a bl 80026f4 /* USART2 DMA DeInit */ HAL_DMA_DeInit(uartHandle->hdmatx); 80014a0: 687b ldr r3, [r7, #4] 80014a2: 6fdb ldr r3, [r3, #124] @ 0x7c 80014a4: 4618 mov r0, r3 80014a6: f000 fc49 bl 8001d3c /* USART2 interrupt Deinit */ HAL_NVIC_DisableIRQ(USART2_IRQn); 80014aa: 2025 movs r0, #37 @ 0x25 80014ac: f000 fb8f bl 8001bce /* USER CODE BEGIN USART2_MspDeInit 1 */ /* USER CODE END USART2_MspDeInit 1 */ } } 80014b0: bf00 nop 80014b2: 3708 adds r7, #8 80014b4: 46bd mov sp, r7 80014b6: bd80 pop {r7, pc} 80014b8: 40004400 .word 0x40004400 080014bc : { 80014bc: b480 push {r7} 80014be: b083 sub sp, #12 80014c0: af00 add r7, sp, #0 80014c2: 6078 str r0, [r7, #4] SET_BIT(RCC->APB1RSTR1, Periphs); 80014c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80014c8: 6b9a ldr r2, [r3, #56] @ 0x38 80014ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80014ce: 687b ldr r3, [r7, #4] 80014d0: 4313 orrs r3, r2 80014d2: 638b str r3, [r1, #56] @ 0x38 } 80014d4: bf00 nop 80014d6: 370c adds r7, #12 80014d8: 46bd mov sp, r7 80014da: bc80 pop {r7} 80014dc: 4770 bx lr 080014de : { 80014de: b480 push {r7} 80014e0: b083 sub sp, #12 80014e2: af00 add r7, sp, #0 80014e4: 6078 str r0, [r7, #4] CLEAR_BIT(RCC->APB1RSTR1, Periphs); 80014e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80014ea: 6b9a ldr r2, [r3, #56] @ 0x38 80014ec: 687b ldr r3, [r7, #4] 80014ee: 43db mvns r3, r3 80014f0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80014f4: 4013 ands r3, r2 80014f6: 638b str r3, [r1, #56] @ 0x38 } 80014f8: bf00 nop 80014fa: 370c adds r7, #12 80014fc: 46bd mov sp, r7 80014fe: bc80 pop {r7} 8001500: 4770 bx lr ... 08001504 : { 8001504: b480 push {r7} 8001506: b083 sub sp, #12 8001508: af00 add r7, sp, #0 800150a: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR1, ExtiLine); 800150c: 4b06 ldr r3, [pc, #24] @ (8001528 ) 800150e: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8001512: 4905 ldr r1, [pc, #20] @ (8001528 ) 8001514: 687b ldr r3, [r7, #4] 8001516: 4313 orrs r3, r2 8001518: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } 800151c: bf00 nop 800151e: 370c adds r7, #12 8001520: 46bd mov sp, r7 8001522: bc80 pop {r7} 8001524: 4770 bx lr 8001526: bf00 nop 8001528: 58000800 .word 0x58000800 0800152c : /* USER CODE END PFP */ /* Exported functions --------------------------------------------------------*/ UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)) { 800152c: b580 push {r7, lr} 800152e: b082 sub sp, #8 8001530: af00 add r7, sp, #0 8001532: 6078 str r0, [r7, #4] /* USER CODE BEGIN vcom_Init_1 */ /* USER CODE END vcom_Init_1 */ TxCpltCallback = cb; 8001534: 4a07 ldr r2, [pc, #28] @ (8001554 ) 8001536: 687b ldr r3, [r7, #4] 8001538: 6013 str r3, [r2, #0] MX_DMA_Init(); 800153a: f7ff f837 bl 80005ac MX_USART2_UART_Init(); 800153e: f7ff fecd bl 80012dc LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_27); 8001542: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8001546: f7ff ffdd bl 8001504 return UTIL_ADV_TRACE_OK; 800154a: 2300 movs r3, #0 /* USER CODE BEGIN vcom_Init_2 */ /* USER CODE END vcom_Init_2 */ } 800154c: 4618 mov r0, r3 800154e: 3708 adds r7, #8 8001550: 46bd mov sp, r7 8001552: bd80 pop {r7, pc} 8001554: 200001f4 .word 0x200001f4 08001558 : UTIL_ADV_TRACE_Status_t vcom_DeInit(void) { 8001558: b580 push {r7, lr} 800155a: af00 add r7, sp, #0 /* USER CODE BEGIN vcom_DeInit_1 */ /* USER CODE END vcom_DeInit_1 */ /* ##-1- Reset peripherals ################################################## */ __HAL_RCC_USART2_FORCE_RESET(); 800155c: f44f 3000 mov.w r0, #131072 @ 0x20000 8001560: f7ff ffac bl 80014bc __HAL_RCC_USART2_RELEASE_RESET(); 8001564: f44f 3000 mov.w r0, #131072 @ 0x20000 8001568: f7ff ffb9 bl 80014de /* ##-2- MspDeInit ################################################## */ HAL_UART_MspDeInit(&huart2); 800156c: 4804 ldr r0, [pc, #16] @ (8001580 ) 800156e: f7ff ff85 bl 800147c /* ##-3- Disable the NVIC for DMA ########################################### */ /* USER CODE BEGIN 1 */ HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn); 8001572: 200f movs r0, #15 8001574: f000 fb2b bl 8001bce return UTIL_ADV_TRACE_OK; 8001578: 2300 movs r3, #0 /* USER CODE END 1 */ /* USER CODE BEGIN vcom_DeInit_2 */ /* USER CODE END vcom_DeInit_2 */ } 800157a: 4618 mov r0, r3 800157c: bd80 pop {r7, pc} 800157e: bf00 nop 8001580: 200000fc .word 0x200000fc 08001584 : /* USER CODE END vcom_Trace_2 */ } UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size) { 8001584: b580 push {r7, lr} 8001586: b082 sub sp, #8 8001588: af00 add r7, sp, #0 800158a: 6078 str r0, [r7, #4] 800158c: 460b mov r3, r1 800158e: 807b strh r3, [r7, #2] /* USER CODE BEGIN vcom_Trace_DMA_1 */ /* USER CODE END vcom_Trace_DMA_1 */ HAL_UART_Transmit_DMA(&huart2, p_data, size); 8001590: 887b ldrh r3, [r7, #2] 8001592: 461a mov r2, r3 8001594: 6879 ldr r1, [r7, #4] 8001596: 4804 ldr r0, [pc, #16] @ (80015a8 ) 8001598: f003 ff3c bl 8005414 return UTIL_ADV_TRACE_OK; 800159c: 2300 movs r3, #0 /* USER CODE BEGIN vcom_Trace_DMA_2 */ /* USER CODE END vcom_Trace_DMA_2 */ } 800159e: 4618 mov r0, r3 80015a0: 3708 adds r7, #8 80015a2: 46bd mov sp, r7 80015a4: bd80 pop {r7, pc} 80015a6: bf00 nop 80015a8: 200000fc .word 0x200000fc 080015ac : UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)) { 80015ac: b580 push {r7, lr} 80015ae: b084 sub sp, #16 80015b0: af00 add r7, sp, #0 80015b2: 6078 str r0, [r7, #4] /* USER CODE END vcom_ReceiveInit_1 */ UART_WakeUpTypeDef WakeUpSelection; /*record call back*/ RxCpltCallback = RxCb; 80015b4: 4a19 ldr r2, [pc, #100] @ (800161c ) 80015b6: 687b ldr r3, [r7, #4] 80015b8: 6013 str r3, [r2, #0] /*Set wakeUp event on start bit*/ WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; 80015ba: f44f 1300 mov.w r3, #2097152 @ 0x200000 80015be: 60bb str r3, [r7, #8] HAL_UARTEx_StopModeWakeUpSourceConfig(&huart2, WakeUpSelection); 80015c0: f107 0308 add.w r3, r7, #8 80015c4: e893 0006 ldmia.w r3, {r1, r2} 80015c8: 4815 ldr r0, [pc, #84] @ (8001620 ) 80015ca: f005 ffaa bl 8007522 /* Make sure that no UART transfer is on-going */ while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_BUSY) == SET); 80015ce: bf00 nop 80015d0: 4b13 ldr r3, [pc, #76] @ (8001620 ) 80015d2: 681b ldr r3, [r3, #0] 80015d4: 69db ldr r3, [r3, #28] 80015d6: f403 3380 and.w r3, r3, #65536 @ 0x10000 80015da: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80015de: d0f7 beq.n 80015d0 /* Make sure that UART is ready to receive) */ while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_REACK) == RESET); 80015e0: bf00 nop 80015e2: 4b0f ldr r3, [pc, #60] @ (8001620 ) 80015e4: 681b ldr r3, [r3, #0] 80015e6: 69db ldr r3, [r3, #28] 80015e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80015ec: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80015f0: d1f7 bne.n 80015e2 /* Enable USART interrupt */ __HAL_UART_ENABLE_IT(&huart2, UART_IT_WUF); 80015f2: 4b0b ldr r3, [pc, #44] @ (8001620 ) 80015f4: 681b ldr r3, [r3, #0] 80015f6: 689a ldr r2, [r3, #8] 80015f8: 4b09 ldr r3, [pc, #36] @ (8001620 ) 80015fa: 681b ldr r3, [r3, #0] 80015fc: f442 0280 orr.w r2, r2, #4194304 @ 0x400000 8001600: 609a str r2, [r3, #8] /*Enable wakeup from stop mode*/ HAL_UARTEx_EnableStopMode(&huart2); 8001602: 4807 ldr r0, [pc, #28] @ (8001620 ) 8001604: f005 ffe8 bl 80075d8 /*Start LPUART receive on IT*/ HAL_UART_Receive_IT(&huart2, &charRx, 1); 8001608: 2201 movs r2, #1 800160a: 4906 ldr r1, [pc, #24] @ (8001624 ) 800160c: 4804 ldr r0, [pc, #16] @ (8001620 ) 800160e: f003 feb5 bl 800537c return UTIL_ADV_TRACE_OK; 8001612: 2300 movs r3, #0 /* USER CODE BEGIN vcom_ReceiveInit_2 */ /* USER CODE END vcom_ReceiveInit_2 */ } 8001614: 4618 mov r0, r3 8001616: 3710 adds r7, #16 8001618: 46bd mov sp, r7 800161a: bd80 pop {r7, pc} 800161c: 200001f8 .word 0x200001f8 8001620: 200000fc .word 0x200000fc 8001624: 200001f0 .word 0x200001f0 08001628 : void vcom_Resume(void) { 8001628: b580 push {r7, lr} 800162a: af00 add r7, sp, #0 /* USER CODE BEGIN vcom_Resume_1 */ /* USER CODE END vcom_Resume_1 */ /*to re-enable lost UART settings*/ if (HAL_UART_Init(&huart2) != HAL_OK) 800162c: 4808 ldr r0, [pc, #32] @ (8001650 ) 800162e: f003 fdbc bl 80051aa 8001632: 4603 mov r3, r0 8001634: 2b00 cmp r3, #0 8001636: d001 beq.n 800163c { Error_Handler(); 8001638: f7ff f8ca bl 80007d0 } /*to re-enable lost DMA settings*/ if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 800163c: 4805 ldr r0, [pc, #20] @ (8001654 ) 800163e: f000 fad5 bl 8001bec 8001642: 4603 mov r3, r0 8001644: 2b00 cmp r3, #0 8001646: d001 beq.n 800164c { Error_Handler(); 8001648: f7ff f8c2 bl 80007d0 } /* USER CODE BEGIN vcom_Resume_2 */ /* USER CODE END vcom_Resume_2 */ } 800164c: bf00 nop 800164e: bd80 pop {r7, pc} 8001650: 200000fc .word 0x200000fc 8001654: 20000190 .word 0x20000190 08001658 : void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8001658: b580 push {r7, lr} 800165a: b082 sub sp, #8 800165c: af00 add r7, sp, #0 800165e: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */ /* USER CODE END HAL_UART_TxCpltCallback_1 */ /* buffer transmission complete*/ if (huart->Instance == USART2) 8001660: 687b ldr r3, [r7, #4] 8001662: 681b ldr r3, [r3, #0] 8001664: 4a05 ldr r2, [pc, #20] @ (800167c ) 8001666: 4293 cmp r3, r2 8001668: d103 bne.n 8001672 { TxCpltCallback(NULL); 800166a: 4b05 ldr r3, [pc, #20] @ (8001680 ) 800166c: 681b ldr r3, [r3, #0] 800166e: 2000 movs r0, #0 8001670: 4798 blx r3 } /* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */ /* USER CODE END HAL_UART_TxCpltCallback_2 */ } 8001672: bf00 nop 8001674: 3708 adds r7, #8 8001676: 46bd mov sp, r7 8001678: bd80 pop {r7, pc} 800167a: bf00 nop 800167c: 40004400 .word 0x40004400 8001680: 200001f4 .word 0x200001f4 08001684 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8001684: b580 push {r7, lr} 8001686: b082 sub sp, #8 8001688: af00 add r7, sp, #0 800168a: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */ /* USER CODE END HAL_UART_RxCpltCallback_1 */ if (huart->Instance == USART2) 800168c: 687b ldr r3, [r7, #4] 800168e: 681b ldr r3, [r3, #0] 8001690: 4a0d ldr r2, [pc, #52] @ (80016c8 ) 8001692: 4293 cmp r3, r2 8001694: d113 bne.n 80016be { if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode)) 8001696: 4b0d ldr r3, [pc, #52] @ (80016cc ) 8001698: 681b ldr r3, [r3, #0] 800169a: 2b00 cmp r3, #0 800169c: d00a beq.n 80016b4 800169e: 687b ldr r3, [r7, #4] 80016a0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80016a4: 2b00 cmp r3, #0 80016a6: d105 bne.n 80016b4 { RxCpltCallback(&charRx, 1, 0); 80016a8: 4b08 ldr r3, [pc, #32] @ (80016cc ) 80016aa: 681b ldr r3, [r3, #0] 80016ac: 2200 movs r2, #0 80016ae: 2101 movs r1, #1 80016b0: 4807 ldr r0, [pc, #28] @ (80016d0 ) 80016b2: 4798 blx r3 } HAL_UART_Receive_IT(huart, &charRx, 1); 80016b4: 2201 movs r2, #1 80016b6: 4906 ldr r1, [pc, #24] @ (80016d0 ) 80016b8: 6878 ldr r0, [r7, #4] 80016ba: f003 fe5f bl 800537c } /* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */ /* USER CODE END HAL_UART_RxCpltCallback_2 */ } 80016be: bf00 nop 80016c0: 3708 adds r7, #8 80016c2: 46bd mov sp, r7 80016c4: bd80 pop {r7, pc} 80016c6: bf00 nop 80016c8: 40004400 .word 0x40004400 80016cc: 200001f8 .word 0x200001f8 80016d0: 200001f0 .word 0x200001f0 080016d4 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80016d4: 480d ldr r0, [pc, #52] @ (800170c ) mov sp, r0 /* set stack pointer */ 80016d6: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80016d8: f7ff fb7a bl 8000dd0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80016dc: 480c ldr r0, [pc, #48] @ (8001710 ) ldr r1, =_edata 80016de: 490d ldr r1, [pc, #52] @ (8001714 ) ldr r2, =_sidata 80016e0: 4a0d ldr r2, [pc, #52] @ (8001718 ) movs r3, #0 80016e2: 2300 movs r3, #0 b LoopCopyDataInit 80016e4: e002 b.n 80016ec 080016e6 : CopyDataInit: ldr r4, [r2, r3] 80016e6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80016e8: 50c4 str r4, [r0, r3] adds r3, r3, #4 80016ea: 3304 adds r3, #4 080016ec : LoopCopyDataInit: adds r4, r0, r3 80016ec: 18c4 adds r4, r0, r3 cmp r4, r1 80016ee: 428c cmp r4, r1 bcc CopyDataInit 80016f0: d3f9 bcc.n 80016e6 /* Zero fill the bss segment. */ ldr r2, =_sbss 80016f2: 4a0a ldr r2, [pc, #40] @ (800171c ) ldr r4, =_ebss 80016f4: 4c0a ldr r4, [pc, #40] @ (8001720 ) movs r3, #0 80016f6: 2300 movs r3, #0 b LoopFillZerobss 80016f8: e001 b.n 80016fe 080016fa : FillZerobss: str r3, [r2] 80016fa: 6013 str r3, [r2, #0] adds r2, r2, #4 80016fc: 3204 adds r2, #4 080016fe : LoopFillZerobss: cmp r2, r4 80016fe: 42a2 cmp r2, r4 bcc FillZerobss 8001700: d3fb bcc.n 80016fa /* Call static constructors */ bl __libc_init_array 8001702: f00d f861 bl 800e7c8 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001706: f7fe fffe bl 8000706
0800170a : LoopForever: b LoopForever 800170a: e7fe b.n 800170a ldr r0, =_estack 800170c: 20010000 .word 0x20010000 ldr r0, =_sdata 8001710: 20000000 .word 0x20000000 ldr r1, =_edata 8001714: 2000008c .word 0x2000008c ldr r2, =_sidata 8001718: 0800fe10 .word 0x0800fe10 ldr r2, =_sbss 800171c: 2000008c .word 0x2000008c ldr r4, =_ebss 8001720: 20001068 .word 0x20001068 08001724 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001724: e7fe b.n 8001724 08001726 : { 8001726: b480 push {r7} 8001728: b085 sub sp, #20 800172a: af00 add r7, sp, #0 800172c: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 800172e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001732: 6cda ldr r2, [r3, #76] @ 0x4c 8001734: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8001738: 687b ldr r3, [r7, #4] 800173a: 4313 orrs r3, r2 800173c: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 800173e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8001742: 6cda ldr r2, [r3, #76] @ 0x4c 8001744: 687b ldr r3, [r7, #4] 8001746: 4013 ands r3, r2 8001748: 60fb str r3, [r7, #12] (void)tmpreg; 800174a: 68fb ldr r3, [r7, #12] } 800174c: bf00 nop 800174e: 3714 adds r7, #20 8001750: 46bd mov sp, r7 8001752: bc80 pop {r7} 8001754: 4770 bx lr ... 08001758 : /** * @brief Init Radio Switch * @retval BSP status */ int32_t BSP_RADIO_Init(void) { 8001758: b580 push {r7, lr} 800175a: b086 sub sp, #24 800175c: af00 add r7, sp, #0 GPIO_InitTypeDef gpio_init_structure = {0}; 800175e: 1d3b adds r3, r7, #4 8001760: 2200 movs r2, #0 8001762: 601a str r2, [r3, #0] 8001764: 605a str r2, [r3, #4] 8001766: 609a str r2, [r3, #8] 8001768: 60da str r2, [r3, #12] 800176a: 611a str r2, [r3, #16] /* Enable the Radio Switch Clock */ RF_SW_CTRL3_GPIO_CLK_ENABLE(); 800176c: 2004 movs r0, #4 800176e: f7ff ffda bl 8001726 /* Configure the Radio Switch pin */ gpio_init_structure.Pin = RF_SW_CTRL1_PIN; 8001772: 2310 movs r3, #16 8001774: 607b str r3, [r7, #4] gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; 8001776: 2301 movs r3, #1 8001778: 60bb str r3, [r7, #8] gpio_init_structure.Pull = GPIO_NOPULL; 800177a: 2300 movs r3, #0 800177c: 60fb str r3, [r7, #12] gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800177e: 2303 movs r3, #3 8001780: 613b str r3, [r7, #16] HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure); 8001782: 1d3b adds r3, r7, #4 8001784: 4619 mov r1, r3 8001786: 4812 ldr r0, [pc, #72] @ (80017d0 ) 8001788: f000 fe54 bl 8002434 gpio_init_structure.Pin = RF_SW_CTRL2_PIN; 800178c: 2320 movs r3, #32 800178e: 607b str r3, [r7, #4] HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure); 8001790: 1d3b adds r3, r7, #4 8001792: 4619 mov r1, r3 8001794: 480e ldr r0, [pc, #56] @ (80017d0 ) 8001796: f000 fe4d bl 8002434 gpio_init_structure.Pin = RF_SW_CTRL3_PIN; 800179a: 2308 movs r3, #8 800179c: 607b str r3, [r7, #4] HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure); 800179e: 1d3b adds r3, r7, #4 80017a0: 4619 mov r1, r3 80017a2: 480b ldr r0, [pc, #44] @ (80017d0 ) 80017a4: f000 fe46 bl 8002434 HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); 80017a8: 2200 movs r2, #0 80017aa: 2120 movs r1, #32 80017ac: 4808 ldr r0, [pc, #32] @ (80017d0 ) 80017ae: f001 f86f bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); 80017b2: 2200 movs r2, #0 80017b4: 2110 movs r1, #16 80017b6: 4806 ldr r0, [pc, #24] @ (80017d0 ) 80017b8: f001 f86a bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); 80017bc: 2200 movs r2, #0 80017be: 2108 movs r1, #8 80017c0: 4803 ldr r0, [pc, #12] @ (80017d0 ) 80017c2: f001 f865 bl 8002890 return BSP_ERROR_NONE; 80017c6: 2300 movs r3, #0 } 80017c8: 4618 mov r0, r3 80017ca: 3718 adds r7, #24 80017cc: 46bd mov sp, r7 80017ce: bd80 pop {r7, pc} 80017d0: 48000800 .word 0x48000800 080017d4 : * @arg RADIO_SWITCH_RFO_LP * @arg RADIO_SWITCH_RFO_HP * @retval BSP status */ int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config) { 80017d4: b580 push {r7, lr} 80017d6: b082 sub sp, #8 80017d8: af00 add r7, sp, #0 80017da: 4603 mov r3, r0 80017dc: 71fb strb r3, [r7, #7] switch (Config) 80017de: 79fb ldrb r3, [r7, #7] 80017e0: 2b03 cmp r3, #3 80017e2: d84b bhi.n 800187c 80017e4: a201 add r2, pc, #4 @ (adr r2, 80017ec ) 80017e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80017ea: bf00 nop 80017ec: 080017fd .word 0x080017fd 80017f0: 0800181d .word 0x0800181d 80017f4: 0800183d .word 0x0800183d 80017f8: 0800185d .word 0x0800185d { case RADIO_SWITCH_OFF: { /* Turn off switch */ HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); 80017fc: 2200 movs r2, #0 80017fe: 2108 movs r1, #8 8001800: 4821 ldr r0, [pc, #132] @ (8001888 ) 8001802: f001 f845 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); 8001806: 2200 movs r2, #0 8001808: 2110 movs r1, #16 800180a: 481f ldr r0, [pc, #124] @ (8001888 ) 800180c: f001 f840 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); 8001810: 2200 movs r2, #0 8001812: 2120 movs r1, #32 8001814: 481c ldr r0, [pc, #112] @ (8001888 ) 8001816: f001 f83b bl 8002890 break; 800181a: e030 b.n 800187e } case RADIO_SWITCH_RX: { /*Turns On in Rx Mode the RF Switch */ HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); 800181c: 2201 movs r2, #1 800181e: 2108 movs r1, #8 8001820: 4819 ldr r0, [pc, #100] @ (8001888 ) 8001822: f001 f835 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); 8001826: 2201 movs r2, #1 8001828: 2110 movs r1, #16 800182a: 4817 ldr r0, [pc, #92] @ (8001888 ) 800182c: f001 f830 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); 8001830: 2200 movs r2, #0 8001832: 2120 movs r1, #32 8001834: 4814 ldr r0, [pc, #80] @ (8001888 ) 8001836: f001 f82b bl 8002890 break; 800183a: e020 b.n 800187e } case RADIO_SWITCH_RFO_LP: { /*Turns On in Tx Low Power the RF Switch */ HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); 800183c: 2201 movs r2, #1 800183e: 2108 movs r1, #8 8001840: 4811 ldr r0, [pc, #68] @ (8001888 ) 8001842: f001 f825 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); 8001846: 2201 movs r2, #1 8001848: 2110 movs r1, #16 800184a: 480f ldr r0, [pc, #60] @ (8001888 ) 800184c: f001 f820 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); 8001850: 2201 movs r2, #1 8001852: 2120 movs r1, #32 8001854: 480c ldr r0, [pc, #48] @ (8001888 ) 8001856: f001 f81b bl 8002890 break; 800185a: e010 b.n 800187e } case RADIO_SWITCH_RFO_HP: { /*Turns On in Tx High Power the RF Switch */ HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); 800185c: 2201 movs r2, #1 800185e: 2108 movs r1, #8 8001860: 4809 ldr r0, [pc, #36] @ (8001888 ) 8001862: f001 f815 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); 8001866: 2200 movs r2, #0 8001868: 2110 movs r1, #16 800186a: 4807 ldr r0, [pc, #28] @ (8001888 ) 800186c: f001 f810 bl 8002890 HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); 8001870: 2201 movs r2, #1 8001872: 2120 movs r1, #32 8001874: 4804 ldr r0, [pc, #16] @ (8001888 ) 8001876: f001 f80b bl 8002890 break; 800187a: e000 b.n 800187e } default: break; 800187c: bf00 nop } return BSP_ERROR_NONE; 800187e: 2300 movs r3, #0 } 8001880: 4618 mov r0, r3 8001882: 3708 adds r7, #8 8001884: 46bd mov sp, r7 8001886: bd80 pop {r7, pc} 8001888: 48000800 .word 0x48000800 0800188c : * RADIO_CONF_RFO_LP_HP * RADIO_CONF_RFO_LP * RADIO_CONF_RFO_HP */ int32_t BSP_RADIO_GetTxConfig(void) { 800188c: b480 push {r7} 800188e: af00 add r7, sp, #0 return RADIO_CONF_RFO_LP_HP; 8001890: 2300 movs r3, #0 } 8001892: 4618 mov r0, r3 8001894: 46bd mov sp, r7 8001896: bc80 pop {r7} 8001898: 4770 bx lr 0800189a : * @retval * RADIO_CONF_TCXO_NOT_SUPPORTED * RADIO_CONF_TCXO_SUPPORTED */ int32_t BSP_RADIO_IsTCXO(void) { 800189a: b480 push {r7} 800189c: af00 add r7, sp, #0 return RADIO_CONF_TCXO_SUPPORTED; 800189e: 2301 movs r3, #1 } 80018a0: 4618 mov r0, r3 80018a2: 46bd mov sp, r7 80018a4: bc80 pop {r7} 80018a6: 4770 bx lr 080018a8 : * @retval * RADIO_CONF_DCDC_NOT_SUPPORTED * RADIO_CONF_DCDC_SUPPORTED */ int32_t BSP_RADIO_IsDCDC(void) { 80018a8: b480 push {r7} 80018aa: af00 add r7, sp, #0 return RADIO_CONF_DCDC_SUPPORTED; 80018ac: 2301 movs r3, #1 } 80018ae: 4618 mov r0, r3 80018b0: 46bd mov sp, r7 80018b2: bc80 pop {r7} 80018b4: 4770 bx lr 080018b6 : * @retval * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode */ int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config) { 80018b6: b480 push {r7} 80018b8: b085 sub sp, #20 80018ba: af00 add r7, sp, #0 80018bc: 4603 mov r3, r0 80018be: 71fb strb r3, [r7, #7] int32_t ret; if(Config == RADIO_RFO_LP_MAXPOWER) 80018c0: 79fb ldrb r3, [r7, #7] 80018c2: 2b00 cmp r3, #0 80018c4: d102 bne.n 80018cc { ret = RADIO_CONF_RFO_LP_MAX_15_dBm; 80018c6: 230f movs r3, #15 80018c8: 60fb str r3, [r7, #12] 80018ca: e001 b.n 80018d0 } else { ret = RADIO_CONF_RFO_HP_MAX_22_dBm; 80018cc: 2316 movs r3, #22 80018ce: 60fb str r3, [r7, #12] } return ret; 80018d0: 68fb ldr r3, [r7, #12] } 80018d2: 4618 mov r0, r3 80018d4: 3714 adds r7, #20 80018d6: 46bd mov sp, r7 80018d8: bc80 pop {r7} 80018da: 4770 bx lr 080018dc : * @brief Enable the CPU1 Debug Module during SLEEP mode * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) { 80018dc: b480 push {r7} 80018de: af00 add r7, sp, #0 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 80018e0: 4b04 ldr r3, [pc, #16] @ (80018f4 ) 80018e2: 685b ldr r3, [r3, #4] 80018e4: 4a03 ldr r2, [pc, #12] @ (80018f4 ) 80018e6: f043 0301 orr.w r3, r3, #1 80018ea: 6053 str r3, [r2, #4] } 80018ec: bf00 nop 80018ee: 46bd mov sp, r7 80018f0: bc80 pop {r7} 80018f2: 4770 bx lr 80018f4: e0042000 .word 0xe0042000 080018f8 : * in Stop mode even when this bit is enabled * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) { 80018f8: b480 push {r7} 80018fa: af00 add r7, sp, #0 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 80018fc: 4b04 ldr r3, [pc, #16] @ (8001910 ) 80018fe: 685b ldr r3, [r3, #4] 8001900: 4a03 ldr r2, [pc, #12] @ (8001910 ) 8001902: f043 0302 orr.w r3, r3, #2 8001906: 6053 str r3, [r2, #4] } 8001908: bf00 nop 800190a: 46bd mov sp, r7 800190c: bc80 pop {r7} 800190e: 4770 bx lr 8001910: e0042000 .word 0xe0042000 08001914 : * in Standby mode even when this bit is enabled * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) { 8001914: b480 push {r7} 8001916: af00 add r7, sp, #0 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 8001918: 4b04 ldr r3, [pc, #16] @ (800192c ) 800191a: 685b ldr r3, [r3, #4] 800191c: 4a03 ldr r2, [pc, #12] @ (800192c ) 800191e: f043 0304 orr.w r3, r3, #4 8001922: 6053 str r3, [r2, #4] } 8001924: bf00 nop 8001926: 46bd mov sp, r7 8001928: bc80 pop {r7} 800192a: 4770 bx lr 800192c: e0042000 .word 0xe0042000 08001930 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001930: b580 push {r7, lr} 8001932: b082 sub sp, #8 8001934: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8001936: 2300 movs r3, #0 8001938: 71fb strb r3, [r7, #7] #endif /* PREFETCH_ENABLE */ #ifdef CORE_CM0PLUS #else /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800193a: 2003 movs r0, #3 800193c: f000 f914 bl 8001b68 /* Update the SystemCoreClock global variable */ #if defined(DUAL_CORE) && defined(CORE_CM0PLUS) SystemCoreClock = HAL_RCC_GetHCLK2Freq(); #else SystemCoreClock = HAL_RCC_GetHCLKFreq(); 8001940: f002 f8b8 bl 8003ab4 8001944: 4603 mov r3, r0 8001946: 4a09 ldr r2, [pc, #36] @ (800196c ) 8001948: 6013 str r3, [r2, #0] #endif /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 800194a: 200f movs r0, #15 800194c: f7ff f972 bl 8000c34 8001950: 4603 mov r3, r0 8001952: 2b00 cmp r3, #0 8001954: d002 beq.n 800195c { status = HAL_ERROR; 8001956: 2301 movs r3, #1 8001958: 71fb strb r3, [r7, #7] 800195a: e001 b.n 8001960 } else { /* Init the low level hardware */ HAL_MspInit(); 800195c: f7ff f82f bl 80009be } /* Return function status */ return status; 8001960: 79fb ldrb r3, [r7, #7] } 8001962: 4618 mov r0, r3 8001964: 3708 adds r7, #8 8001966: 46bd mov sp, r7 8001968: bd80 pop {r7, pc} 800196a: bf00 nop 800196c: 20000000 .word 0x20000000 08001970 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { 8001970: b480 push {r7} 8001972: af00 add r7, sp, #0 /* Disable SysTick Interrupt */ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 8001974: 4b04 ldr r3, [pc, #16] @ (8001988 ) 8001976: 681b ldr r3, [r3, #0] 8001978: 4a03 ldr r2, [pc, #12] @ (8001988 ) 800197a: f023 0302 bic.w r3, r3, #2 800197e: 6013 str r3, [r2, #0] } 8001980: bf00 nop 8001982: 46bd mov sp, r7 8001984: bc80 pop {r7} 8001986: 4770 bx lr 8001988: e000e010 .word 0xe000e010 0800198c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { 800198c: b480 push {r7} 800198e: af00 add r7, sp, #0 /* Enable SysTick Interrupt */ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 8001990: 4b04 ldr r3, [pc, #16] @ (80019a4 ) 8001992: 681b ldr r3, [r3, #0] 8001994: 4a03 ldr r2, [pc, #12] @ (80019a4 ) 8001996: f043 0302 orr.w r3, r3, #2 800199a: 6013 str r3, [r2, #0] } 800199c: bf00 nop 800199e: 46bd mov sp, r7 80019a0: bc80 pop {r7} 80019a2: 4770 bx lr 80019a4: e000e010 .word 0xe000e010 080019a8 : /** * @brief Enable the CPU1 Debug Module during SLEEP mode * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { 80019a8: b580 push {r7, lr} 80019aa: af00 add r7, sp, #0 LL_DBGMCU_EnableDBGSleepMode(); 80019ac: f7ff ff96 bl 80018dc } 80019b0: bf00 nop 80019b2: bd80 pop {r7, pc} 080019b4 : * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged * in Stop mode even when this bit is enabled * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { 80019b4: b580 push {r7, lr} 80019b6: af00 add r7, sp, #0 LL_DBGMCU_EnableDBGStopMode(); 80019b8: f7ff ff9e bl 80018f8 } 80019bc: bf00 nop 80019be: bd80 pop {r7, pc} 080019c0 : * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged * in Standby mode even when this bit is enabled * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { 80019c0: b580 push {r7, lr} 80019c2: af00 add r7, sp, #0 LL_DBGMCU_EnableDBGStandbyMode(); 80019c4: f7ff ffa6 bl 8001914 } 80019c8: bf00 nop 80019ca: bd80 pop {r7, pc} 080019cc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80019cc: b480 push {r7} 80019ce: b085 sub sp, #20 80019d0: af00 add r7, sp, #0 80019d2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80019d4: 687b ldr r3, [r7, #4] 80019d6: f003 0307 and.w r3, r3, #7 80019da: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80019dc: 4b0c ldr r3, [pc, #48] @ (8001a10 <__NVIC_SetPriorityGrouping+0x44>) 80019de: 68db ldr r3, [r3, #12] 80019e0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80019e2: 68ba ldr r2, [r7, #8] 80019e4: f64f 03ff movw r3, #63743 @ 0xf8ff 80019e8: 4013 ands r3, r2 80019ea: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80019ec: 68fb ldr r3, [r7, #12] 80019ee: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80019f0: 68bb ldr r3, [r7, #8] 80019f2: 4313 orrs r3, r2 reg_value = (reg_value | 80019f4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80019f8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80019fc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80019fe: 4a04 ldr r2, [pc, #16] @ (8001a10 <__NVIC_SetPriorityGrouping+0x44>) 8001a00: 68bb ldr r3, [r7, #8] 8001a02: 60d3 str r3, [r2, #12] } 8001a04: bf00 nop 8001a06: 3714 adds r7, #20 8001a08: 46bd mov sp, r7 8001a0a: bc80 pop {r7} 8001a0c: 4770 bx lr 8001a0e: bf00 nop 8001a10: e000ed00 .word 0xe000ed00 08001a14 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001a14: b480 push {r7} 8001a16: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001a18: 4b04 ldr r3, [pc, #16] @ (8001a2c <__NVIC_GetPriorityGrouping+0x18>) 8001a1a: 68db ldr r3, [r3, #12] 8001a1c: 0a1b lsrs r3, r3, #8 8001a1e: f003 0307 and.w r3, r3, #7 } 8001a22: 4618 mov r0, r3 8001a24: 46bd mov sp, r7 8001a26: bc80 pop {r7} 8001a28: 4770 bx lr 8001a2a: bf00 nop 8001a2c: e000ed00 .word 0xe000ed00 08001a30 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001a30: b480 push {r7} 8001a32: b083 sub sp, #12 8001a34: af00 add r7, sp, #0 8001a36: 4603 mov r3, r0 8001a38: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001a3a: f997 3007 ldrsb.w r3, [r7, #7] 8001a3e: 2b00 cmp r3, #0 8001a40: db0b blt.n 8001a5a <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001a42: 79fb ldrb r3, [r7, #7] 8001a44: f003 021f and.w r2, r3, #31 8001a48: 4906 ldr r1, [pc, #24] @ (8001a64 <__NVIC_EnableIRQ+0x34>) 8001a4a: f997 3007 ldrsb.w r3, [r7, #7] 8001a4e: 095b lsrs r3, r3, #5 8001a50: 2001 movs r0, #1 8001a52: fa00 f202 lsl.w r2, r0, r2 8001a56: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001a5a: bf00 nop 8001a5c: 370c adds r7, #12 8001a5e: 46bd mov sp, r7 8001a60: bc80 pop {r7} 8001a62: 4770 bx lr 8001a64: e000e100 .word 0xe000e100 08001a68 <__NVIC_DisableIRQ>: \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { 8001a68: b480 push {r7} 8001a6a: b083 sub sp, #12 8001a6c: af00 add r7, sp, #0 8001a6e: 4603 mov r3, r0 8001a70: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001a72: f997 3007 ldrsb.w r3, [r7, #7] 8001a76: 2b00 cmp r3, #0 8001a78: db12 blt.n 8001aa0 <__NVIC_DisableIRQ+0x38> { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001a7a: 79fb ldrb r3, [r7, #7] 8001a7c: f003 021f and.w r2, r3, #31 8001a80: 490a ldr r1, [pc, #40] @ (8001aac <__NVIC_DisableIRQ+0x44>) 8001a82: f997 3007 ldrsb.w r3, [r7, #7] 8001a86: 095b lsrs r3, r3, #5 8001a88: 2001 movs r0, #1 8001a8a: fa00 f202 lsl.w r2, r0, r2 8001a8e: 3320 adds r3, #32 8001a90: f841 2023 str.w r2, [r1, r3, lsl #2] \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8001a94: f3bf 8f4f dsb sy } 8001a98: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001a9a: f3bf 8f6f isb sy } 8001a9e: bf00 nop __DSB(); __ISB(); } } 8001aa0: bf00 nop 8001aa2: 370c adds r7, #12 8001aa4: 46bd mov sp, r7 8001aa6: bc80 pop {r7} 8001aa8: 4770 bx lr 8001aaa: bf00 nop 8001aac: e000e100 .word 0xe000e100 08001ab0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001ab0: b480 push {r7} 8001ab2: b083 sub sp, #12 8001ab4: af00 add r7, sp, #0 8001ab6: 4603 mov r3, r0 8001ab8: 6039 str r1, [r7, #0] 8001aba: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001abc: f997 3007 ldrsb.w r3, [r7, #7] 8001ac0: 2b00 cmp r3, #0 8001ac2: db0a blt.n 8001ada <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ac4: 683b ldr r3, [r7, #0] 8001ac6: b2da uxtb r2, r3 8001ac8: 490c ldr r1, [pc, #48] @ (8001afc <__NVIC_SetPriority+0x4c>) 8001aca: f997 3007 ldrsb.w r3, [r7, #7] 8001ace: 0112 lsls r2, r2, #4 8001ad0: b2d2 uxtb r2, r2 8001ad2: 440b add r3, r1 8001ad4: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001ad8: e00a b.n 8001af0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ada: 683b ldr r3, [r7, #0] 8001adc: b2da uxtb r2, r3 8001ade: 4908 ldr r1, [pc, #32] @ (8001b00 <__NVIC_SetPriority+0x50>) 8001ae0: 79fb ldrb r3, [r7, #7] 8001ae2: f003 030f and.w r3, r3, #15 8001ae6: 3b04 subs r3, #4 8001ae8: 0112 lsls r2, r2, #4 8001aea: b2d2 uxtb r2, r2 8001aec: 440b add r3, r1 8001aee: 761a strb r2, [r3, #24] } 8001af0: bf00 nop 8001af2: 370c adds r7, #12 8001af4: 46bd mov sp, r7 8001af6: bc80 pop {r7} 8001af8: 4770 bx lr 8001afa: bf00 nop 8001afc: e000e100 .word 0xe000e100 8001b00: e000ed00 .word 0xe000ed00 08001b04 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b04: b480 push {r7} 8001b06: b089 sub sp, #36 @ 0x24 8001b08: af00 add r7, sp, #0 8001b0a: 60f8 str r0, [r7, #12] 8001b0c: 60b9 str r1, [r7, #8] 8001b0e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001b10: 68fb ldr r3, [r7, #12] 8001b12: f003 0307 and.w r3, r3, #7 8001b16: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001b18: 69fb ldr r3, [r7, #28] 8001b1a: f1c3 0307 rsb r3, r3, #7 8001b1e: 2b04 cmp r3, #4 8001b20: bf28 it cs 8001b22: 2304 movcs r3, #4 8001b24: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001b26: 69fb ldr r3, [r7, #28] 8001b28: 3304 adds r3, #4 8001b2a: 2b06 cmp r3, #6 8001b2c: d902 bls.n 8001b34 8001b2e: 69fb ldr r3, [r7, #28] 8001b30: 3b03 subs r3, #3 8001b32: e000 b.n 8001b36 8001b34: 2300 movs r3, #0 8001b36: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b38: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001b3c: 69bb ldr r3, [r7, #24] 8001b3e: fa02 f303 lsl.w r3, r2, r3 8001b42: 43da mvns r2, r3 8001b44: 68bb ldr r3, [r7, #8] 8001b46: 401a ands r2, r3 8001b48: 697b ldr r3, [r7, #20] 8001b4a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001b4c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001b50: 697b ldr r3, [r7, #20] 8001b52: fa01 f303 lsl.w r3, r1, r3 8001b56: 43d9 mvns r1, r3 8001b58: 687b ldr r3, [r7, #4] 8001b5a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b5c: 4313 orrs r3, r2 ); } 8001b5e: 4618 mov r0, r3 8001b60: 3724 adds r7, #36 @ 0x24 8001b62: 46bd mov sp, r7 8001b64: bc80 pop {r7} 8001b66: 4770 bx lr 08001b68 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001b68: b580 push {r7, lr} 8001b6a: b082 sub sp, #8 8001b6c: af00 add r7, sp, #0 8001b6e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001b70: 6878 ldr r0, [r7, #4] 8001b72: f7ff ff2b bl 80019cc <__NVIC_SetPriorityGrouping> } 8001b76: bf00 nop 8001b78: 3708 adds r7, #8 8001b7a: 46bd mov sp, r7 8001b7c: bd80 pop {r7, pc} 08001b7e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b7e: b580 push {r7, lr} 8001b80: b086 sub sp, #24 8001b82: af00 add r7, sp, #0 8001b84: 4603 mov r3, r0 8001b86: 60b9 str r1, [r7, #8] 8001b88: 607a str r2, [r7, #4] 8001b8a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001b8c: f7ff ff42 bl 8001a14 <__NVIC_GetPriorityGrouping> 8001b90: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001b92: 687a ldr r2, [r7, #4] 8001b94: 68b9 ldr r1, [r7, #8] 8001b96: 6978 ldr r0, [r7, #20] 8001b98: f7ff ffb4 bl 8001b04 8001b9c: 4602 mov r2, r0 8001b9e: f997 300f ldrsb.w r3, [r7, #15] 8001ba2: 4611 mov r1, r2 8001ba4: 4618 mov r0, r3 8001ba6: f7ff ff83 bl 8001ab0 <__NVIC_SetPriority> } 8001baa: bf00 nop 8001bac: 3718 adds r7, #24 8001bae: 46bd mov sp, r7 8001bb0: bd80 pop {r7, pc} 08001bb2 : * (For the complete STM32 Devices IRQ Channels list, please refer * to the appropriate CMSIS device file (stm32wlxxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001bb2: b580 push {r7, lr} 8001bb4: b082 sub sp, #8 8001bb6: af00 add r7, sp, #0 8001bb8: 4603 mov r3, r0 8001bba: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001bbc: f997 3007 ldrsb.w r3, [r7, #7] 8001bc0: 4618 mov r0, r3 8001bc2: f7ff ff35 bl 8001a30 <__NVIC_EnableIRQ> } 8001bc6: bf00 nop 8001bc8: 3708 adds r7, #8 8001bca: 46bd mov sp, r7 8001bcc: bd80 pop {r7, pc} 08001bce : * (For the complete STM32 Devices IRQ Channels list, please refer * to the appropriate CMSIS device file (stm32wlxxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 8001bce: b580 push {r7, lr} 8001bd0: b082 sub sp, #8 8001bd2: af00 add r7, sp, #0 8001bd4: 4603 mov r3, r0 8001bd6: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 8001bd8: f997 3007 ldrsb.w r3, [r7, #7] 8001bdc: 4618 mov r0, r3 8001bde: f7ff ff43 bl 8001a68 <__NVIC_DisableIRQ> } 8001be2: bf00 nop 8001be4: 3708 adds r7, #8 8001be6: 46bd mov sp, r7 8001be8: bd80 pop {r7, pc} ... 08001bec : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001bec: b580 push {r7, lr} 8001bee: b082 sub sp, #8 8001bf0: af00 add r7, sp, #0 8001bf2: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (hdma == NULL) 8001bf4: 687b ldr r3, [r7, #4] 8001bf6: 2b00 cmp r3, #0 8001bf8: d101 bne.n 8001bfe { return HAL_ERROR; 8001bfa: 2301 movs r3, #1 8001bfc: e08e b.n 8001d1c assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8001bfe: 687b ldr r3, [r7, #4] 8001c00: 681b ldr r3, [r3, #0] 8001c02: 461a mov r2, r3 8001c04: 4b47 ldr r3, [pc, #284] @ (8001d24 ) 8001c06: 429a cmp r2, r3 8001c08: d80f bhi.n 8001c2a { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001c0a: 687b ldr r3, [r7, #4] 8001c0c: 681b ldr r3, [r3, #0] 8001c0e: 461a mov r2, r3 8001c10: 4b45 ldr r3, [pc, #276] @ (8001d28 ) 8001c12: 4413 add r3, r2 8001c14: 4a45 ldr r2, [pc, #276] @ (8001d2c ) 8001c16: fba2 2303 umull r2, r3, r2, r3 8001c1a: 091b lsrs r3, r3, #4 8001c1c: 009a lsls r2, r3, #2 8001c1e: 687b ldr r3, [r7, #4] 8001c20: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA1; 8001c22: 687b ldr r3, [r7, #4] 8001c24: 4a42 ldr r2, [pc, #264] @ (8001d30 ) 8001c26: 641a str r2, [r3, #64] @ 0x40 8001c28: e00e b.n 8001c48 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; 8001c2a: 687b ldr r3, [r7, #4] 8001c2c: 681b ldr r3, [r3, #0] 8001c2e: 461a mov r2, r3 8001c30: 4b40 ldr r3, [pc, #256] @ (8001d34 ) 8001c32: 4413 add r3, r2 8001c34: 4a3d ldr r2, [pc, #244] @ (8001d2c ) 8001c36: fba2 2303 umull r2, r3, r2, r3 8001c3a: 091b lsrs r3, r3, #4 8001c3c: 009a lsls r2, r3, #2 8001c3e: 687b ldr r3, [r7, #4] 8001c40: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA2; 8001c42: 687b ldr r3, [r7, #4] 8001c44: 4a3c ldr r2, [pc, #240] @ (8001d38 ) 8001c46: 641a str r2, [r3, #64] @ 0x40 } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001c48: 687b ldr r3, [r7, #4] 8001c4a: 2202 movs r2, #2 8001c4c: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8001c50: 687b ldr r3, [r7, #4] 8001c52: 681b ldr r3, [r3, #0] 8001c54: 681b ldr r3, [r3, #0] 8001c56: 687a ldr r2, [r7, #4] 8001c58: 6812 ldr r2, [r2, #0] 8001c5a: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 8001c5e: f023 0370 bic.w r3, r3, #112 @ 0x70 8001c62: 6013 str r3, [r2, #0] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Set the DMA Channel configuration */ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ 8001c64: 687b ldr r3, [r7, #4] 8001c66: 681b ldr r3, [r3, #0] 8001c68: 6819 ldr r1, [r3, #0] 8001c6a: 687b ldr r3, [r7, #4] 8001c6c: 689a ldr r2, [r3, #8] 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 68db ldr r3, [r3, #12] 8001c72: 431a orrs r2, r3 8001c74: 687b ldr r3, [r7, #4] 8001c76: 691b ldr r3, [r3, #16] 8001c78: 431a orrs r2, r3 8001c7a: 687b ldr r3, [r7, #4] 8001c7c: 695b ldr r3, [r3, #20] 8001c7e: 431a orrs r2, r3 8001c80: 687b ldr r3, [r7, #4] 8001c82: 699b ldr r3, [r3, #24] 8001c84: 431a orrs r2, r3 8001c86: 687b ldr r3, [r7, #4] 8001c88: 69db ldr r3, [r3, #28] 8001c8a: 431a orrs r2, r3 8001c8c: 687b ldr r3, [r7, #4] 8001c8e: 6a1b ldr r3, [r3, #32] 8001c90: 431a orrs r2, r3 8001c92: 687b ldr r3, [r7, #4] 8001c94: 681b ldr r3, [r3, #0] 8001c96: 430a orrs r2, r1 8001c98: 601a str r2, [r3, #0] hdma->Init.Mode | hdma->Init.Priority)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8001c9a: 6878 ldr r0, [r7, #4] 8001c9c: f000 fb5e bl 800235c if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8001ca0: 687b ldr r3, [r7, #4] 8001ca2: 689b ldr r3, [r3, #8] 8001ca4: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8001ca8: d102 bne.n 8001cb0 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8001caa: 687b ldr r3, [r7, #4] 8001cac: 2200 movs r2, #0 8001cae: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8001cb0: 687b ldr r3, [r7, #4] 8001cb2: 685a ldr r2, [r3, #4] 8001cb4: 687b ldr r3, [r7, #4] 8001cb6: 6c9b ldr r3, [r3, #72] @ 0x48 8001cb8: f002 027f and.w r2, r2, #127 @ 0x7f 8001cbc: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 6cdb ldr r3, [r3, #76] @ 0x4c 8001cc2: 687a ldr r2, [r7, #4] 8001cc4: 6d12 ldr r2, [r2, #80] @ 0x50 8001cc6: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8001cc8: 687b ldr r3, [r7, #4] 8001cca: 685b ldr r3, [r3, #4] 8001ccc: 2b00 cmp r3, #0 8001cce: d010 beq.n 8001cf2 8001cd0: 687b ldr r3, [r7, #4] 8001cd2: 685b ldr r3, [r3, #4] 8001cd4: 2b04 cmp r3, #4 8001cd6: d80c bhi.n 8001cf2 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8001cd8: 6878 ldr r0, [r7, #4] 8001cda: f000 fb87 bl 80023ec /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8001cde: 687b ldr r3, [r7, #4] 8001ce0: 6d5b ldr r3, [r3, #84] @ 0x54 8001ce2: 2200 movs r2, #0 8001ce4: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 6d9b ldr r3, [r3, #88] @ 0x58 8001cea: 687a ldr r2, [r7, #4] 8001cec: 6dd2 ldr r2, [r2, #92] @ 0x5c 8001cee: 605a str r2, [r3, #4] 8001cf0: e008 b.n 8001d04 } else { hdma->DMAmuxRequestGen = NULL; 8001cf2: 687b ldr r3, [r7, #4] 8001cf4: 2200 movs r2, #0 8001cf6: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = NULL; 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 2200 movs r2, #0 8001cfc: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 0U; 8001cfe: 687b ldr r3, [r7, #4] 8001d00: 2200 movs r2, #0 8001d02: 65da str r2, [r3, #92] @ 0x5c } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001d04: 687b ldr r3, [r7, #4] 8001d06: 2200 movs r2, #0 8001d08: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001d0a: 687b ldr r3, [r7, #4] 8001d0c: 2201 movs r2, #1 8001d0e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Release Lock */ __HAL_UNLOCK(hdma); 8001d12: 687b ldr r3, [r7, #4] 8001d14: 2200 movs r2, #0 8001d16: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_OK; 8001d1a: 2300 movs r3, #0 } 8001d1c: 4618 mov r0, r3 8001d1e: 3708 adds r7, #8 8001d20: 46bd mov sp, r7 8001d22: bd80 pop {r7, pc} 8001d24: 40020407 .word 0x40020407 8001d28: bffdfff8 .word 0xbffdfff8 8001d2c: cccccccd .word 0xcccccccd 8001d30: 40020000 .word 0x40020000 8001d34: bffdfbf8 .word 0xbffdfbf8 8001d38: 40020400 .word 0x40020400 08001d3c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { 8001d3c: b580 push {r7, lr} 8001d3e: b082 sub sp, #8 8001d40: af00 add r7, sp, #0 8001d42: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (NULL == hdma) 8001d44: 687b ldr r3, [r7, #4] 8001d46: 2b00 cmp r3, #0 8001d48: d101 bne.n 8001d4e { return HAL_ERROR; 8001d4a: 2301 movs r3, #1 8001d4c: e07b b.n 8001e46 /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); 8001d4e: 687b ldr r3, [r7, #4] 8001d50: 681b ldr r3, [r3, #0] 8001d52: 681a ldr r2, [r3, #0] 8001d54: 687b ldr r3, [r7, #4] 8001d56: 681b ldr r3, [r3, #0] 8001d58: f022 0201 bic.w r2, r2, #1 8001d5c: 601a str r2, [r3, #0] /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8001d5e: 687b ldr r3, [r7, #4] 8001d60: 681b ldr r3, [r3, #0] 8001d62: 461a mov r2, r3 8001d64: 4b3a ldr r3, [pc, #232] @ (8001e50 ) 8001d66: 429a cmp r2, r3 8001d68: d80f bhi.n 8001d8a { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001d6a: 687b ldr r3, [r7, #4] 8001d6c: 681b ldr r3, [r3, #0] 8001d6e: 461a mov r2, r3 8001d70: 4b38 ldr r3, [pc, #224] @ (8001e54 ) 8001d72: 4413 add r3, r2 8001d74: 4a38 ldr r2, [pc, #224] @ (8001e58 ) 8001d76: fba2 2303 umull r2, r3, r2, r3 8001d7a: 091b lsrs r3, r3, #4 8001d7c: 009a lsls r2, r3, #2 8001d7e: 687b ldr r3, [r7, #4] 8001d80: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA1; 8001d82: 687b ldr r3, [r7, #4] 8001d84: 4a35 ldr r2, [pc, #212] @ (8001e5c ) 8001d86: 641a str r2, [r3, #64] @ 0x40 8001d88: e00e b.n 8001da8 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; 8001d8a: 687b ldr r3, [r7, #4] 8001d8c: 681b ldr r3, [r3, #0] 8001d8e: 461a mov r2, r3 8001d90: 4b33 ldr r3, [pc, #204] @ (8001e60 ) 8001d92: 4413 add r3, r2 8001d94: 4a30 ldr r2, [pc, #192] @ (8001e58 ) 8001d96: fba2 2303 umull r2, r3, r2, r3 8001d9a: 091b lsrs r3, r3, #4 8001d9c: 009a lsls r2, r3, #2 8001d9e: 687b ldr r3, [r7, #4] 8001da0: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA2; 8001da2: 687b ldr r3, [r7, #4] 8001da4: 4a2f ldr r2, [pc, #188] @ (8001e64 ) 8001da6: 641a str r2, [r3, #64] @ 0x40 } /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; 8001da8: 687b ldr r3, [r7, #4] 8001daa: 681b ldr r3, [r3, #0] 8001dac: 2200 movs r2, #0 8001dae: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); 8001db0: 687b ldr r3, [r7, #4] 8001db2: 6c5b ldr r3, [r3, #68] @ 0x44 8001db4: f003 021c and.w r2, r3, #28 8001db8: 687b ldr r3, [r7, #4] 8001dba: 6c1b ldr r3, [r3, #64] @ 0x40 8001dbc: 2101 movs r1, #1 8001dbe: fa01 f202 lsl.w r2, r1, r2 8001dc2: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8001dc4: 6878 ldr r0, [r7, #4] 8001dc6: f000 fac9 bl 800235c /* Reset the DMAMUX channel that corresponds to the DMA channel */ hdma->DMAmuxChannel->CCR = 0U; 8001dca: 687b ldr r3, [r7, #4] 8001dcc: 6c9b ldr r3, [r3, #72] @ 0x48 8001dce: 2200 movs r2, #0 8001dd0: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001dd2: 687b ldr r3, [r7, #4] 8001dd4: 6cdb ldr r3, [r3, #76] @ 0x4c 8001dd6: 687a ldr r2, [r7, #4] 8001dd8: 6d12 ldr r2, [r2, #80] @ 0x50 8001dda: 605a str r2, [r3, #4] /* Reset Request generator parameters if any */ if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8001ddc: 687b ldr r3, [r7, #4] 8001dde: 685b ldr r3, [r3, #4] 8001de0: 2b00 cmp r3, #0 8001de2: d00f beq.n 8001e04 8001de4: 687b ldr r3, [r7, #4] 8001de6: 685b ldr r3, [r3, #4] 8001de8: 2b04 cmp r3, #4 8001dea: d80b bhi.n 8001e04 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8001dec: 6878 ldr r0, [r7, #4] 8001dee: f000 fafd bl 80023ec /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8001df2: 687b ldr r3, [r7, #4] 8001df4: 6d5b ldr r3, [r3, #84] @ 0x54 8001df6: 2200 movs r2, #0 8001df8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001dfa: 687b ldr r3, [r7, #4] 8001dfc: 6d9b ldr r3, [r3, #88] @ 0x58 8001dfe: 687a ldr r2, [r7, #4] 8001e00: 6dd2 ldr r2, [r2, #92] @ 0x5c 8001e02: 605a str r2, [r3, #4] } hdma->DMAmuxRequestGen = NULL; 8001e04: 687b ldr r3, [r7, #4] 8001e06: 2200 movs r2, #0 8001e08: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = NULL; 8001e0a: 687b ldr r3, [r7, #4] 8001e0c: 2200 movs r2, #0 8001e0e: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 0U; 8001e10: 687b ldr r3, [r7, #4] 8001e12: 2200 movs r2, #0 8001e14: 65da str r2, [r3, #92] @ 0x5c /* Clean callbacks */ hdma->XferCpltCallback = NULL; 8001e16: 687b ldr r3, [r7, #4] 8001e18: 2200 movs r2, #0 8001e1a: 62da str r2, [r3, #44] @ 0x2c hdma->XferHalfCpltCallback = NULL; 8001e1c: 687b ldr r3, [r7, #4] 8001e1e: 2200 movs r2, #0 8001e20: 631a str r2, [r3, #48] @ 0x30 hdma->XferErrorCallback = NULL; 8001e22: 687b ldr r3, [r7, #4] 8001e24: 2200 movs r2, #0 8001e26: 635a str r2, [r3, #52] @ 0x34 hdma->XferAbortCallback = NULL; 8001e28: 687b ldr r3, [r7, #4] 8001e2a: 2200 movs r2, #0 8001e2c: 639a str r2, [r3, #56] @ 0x38 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001e2e: 687b ldr r3, [r7, #4] 8001e30: 2200 movs r2, #0 8001e32: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; 8001e34: 687b ldr r3, [r7, #4] 8001e36: 2200 movs r2, #0 8001e38: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Release Lock */ __HAL_UNLOCK(hdma); 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 2200 movs r2, #0 8001e40: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_OK; 8001e44: 2300 movs r3, #0 } 8001e46: 4618 mov r0, r3 8001e48: 3708 adds r7, #8 8001e4a: 46bd mov sp, r7 8001e4c: bd80 pop {r7, pc} 8001e4e: bf00 nop 8001e50: 40020407 .word 0x40020407 8001e54: bffdfff8 .word 0xbffdfff8 8001e58: cccccccd .word 0xcccccccd 8001e5c: 40020000 .word 0x40020000 8001e60: bffdfbf8 .word 0xbffdfbf8 8001e64: 40020400 .word 0x40020400 08001e68 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001e68: b580 push {r7, lr} 8001e6a: b086 sub sp, #24 8001e6c: af00 add r7, sp, #0 8001e6e: 60f8 str r0, [r7, #12] 8001e70: 60b9 str r1, [r7, #8] 8001e72: 607a str r2, [r7, #4] 8001e74: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001e76: 2300 movs r3, #0 8001e78: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001e7a: 68fb ldr r3, [r7, #12] 8001e7c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8001e80: 2b01 cmp r3, #1 8001e82: d101 bne.n 8001e88 8001e84: 2302 movs r3, #2 8001e86: e069 b.n 8001f5c 8001e88: 68fb ldr r3, [r7, #12] 8001e8a: 2201 movs r2, #1 8001e8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->State == HAL_DMA_STATE_READY) 8001e90: 68fb ldr r3, [r7, #12] 8001e92: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8001e96: b2db uxtb r3, r3 8001e98: 2b01 cmp r3, #1 8001e9a: d155 bne.n 8001f48 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001e9c: 68fb ldr r3, [r7, #12] 8001e9e: 2202 movs r2, #2 8001ea0: f883 2025 strb.w r2, [r3, #37] @ 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001ea4: 68fb ldr r3, [r7, #12] 8001ea6: 2200 movs r2, #0 8001ea8: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001eaa: 68fb ldr r3, [r7, #12] 8001eac: 681b ldr r3, [r3, #0] 8001eae: 681a ldr r2, [r3, #0] 8001eb0: 68fb ldr r3, [r7, #12] 8001eb2: 681b ldr r3, [r3, #0] 8001eb4: f022 0201 bic.w r2, r2, #1 8001eb8: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001eba: 683b ldr r3, [r7, #0] 8001ebc: 687a ldr r2, [r7, #4] 8001ebe: 68b9 ldr r1, [r7, #8] 8001ec0: 68f8 ldr r0, [r7, #12] 8001ec2: f000 fa0d bl 80022e0 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) 8001ec6: 68fb ldr r3, [r7, #12] 8001ec8: 6b1b ldr r3, [r3, #48] @ 0x30 8001eca: 2b00 cmp r3, #0 8001ecc: d008 beq.n 8001ee0 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8001ece: 68fb ldr r3, [r7, #12] 8001ed0: 681b ldr r3, [r3, #0] 8001ed2: 681a ldr r2, [r3, #0] 8001ed4: 68fb ldr r3, [r7, #12] 8001ed6: 681b ldr r3, [r3, #0] 8001ed8: f042 020e orr.w r2, r2, #14 8001edc: 601a str r2, [r3, #0] 8001ede: e00f b.n 8001f00 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8001ee0: 68fb ldr r3, [r7, #12] 8001ee2: 681b ldr r3, [r3, #0] 8001ee4: 681a ldr r2, [r3, #0] 8001ee6: 68fb ldr r3, [r7, #12] 8001ee8: 681b ldr r3, [r3, #0] 8001eea: f022 0204 bic.w r2, r2, #4 8001eee: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8001ef0: 68fb ldr r3, [r7, #12] 8001ef2: 681b ldr r3, [r3, #0] 8001ef4: 681a ldr r2, [r3, #0] 8001ef6: 68fb ldr r3, [r7, #12] 8001ef8: 681b ldr r3, [r3, #0] 8001efa: f042 020a orr.w r2, r2, #10 8001efe: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8001f00: 68fb ldr r3, [r7, #12] 8001f02: 6c9b ldr r3, [r3, #72] @ 0x48 8001f04: 681b ldr r3, [r3, #0] 8001f06: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001f0a: 2b00 cmp r3, #0 8001f0c: d007 beq.n 8001f1e { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8001f0e: 68fb ldr r3, [r7, #12] 8001f10: 6c9b ldr r3, [r3, #72] @ 0x48 8001f12: 681a ldr r2, [r3, #0] 8001f14: 68fb ldr r3, [r7, #12] 8001f16: 6c9b ldr r3, [r3, #72] @ 0x48 8001f18: f442 7280 orr.w r2, r2, #256 @ 0x100 8001f1c: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != NULL) 8001f1e: 68fb ldr r3, [r7, #12] 8001f20: 6d5b ldr r3, [r3, #84] @ 0x54 8001f22: 2b00 cmp r3, #0 8001f24: d007 beq.n 8001f36 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8001f26: 68fb ldr r3, [r7, #12] 8001f28: 6d5b ldr r3, [r3, #84] @ 0x54 8001f2a: 681a ldr r2, [r3, #0] 8001f2c: 68fb ldr r3, [r7, #12] 8001f2e: 6d5b ldr r3, [r3, #84] @ 0x54 8001f30: f442 7280 orr.w r2, r2, #256 @ 0x100 8001f34: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001f36: 68fb ldr r3, [r7, #12] 8001f38: 681b ldr r3, [r3, #0] 8001f3a: 681a ldr r2, [r3, #0] 8001f3c: 68fb ldr r3, [r7, #12] 8001f3e: 681b ldr r3, [r3, #0] 8001f40: f042 0201 orr.w r2, r2, #1 8001f44: 601a str r2, [r3, #0] 8001f46: e008 b.n 8001f5a } else { /* Change the error code */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8001f48: 68fb ldr r3, [r7, #12] 8001f4a: 2280 movs r2, #128 @ 0x80 8001f4c: 63da str r2, [r3, #60] @ 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f4e: 68fb ldr r3, [r7, #12] 8001f50: 2200 movs r2, #0 8001f52: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return error status */ status = HAL_ERROR; 8001f56: 2301 movs r3, #1 8001f58: 75fb strb r3, [r7, #23] } return status; 8001f5a: 7dfb ldrb r3, [r7, #23] } 8001f5c: 4618 mov r0, r3 8001f5e: 3718 adds r7, #24 8001f60: 46bd mov sp, r7 8001f62: bd80 pop {r7, pc} 08001f64 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001f64: b480 push {r7} 8001f66: b083 sub sp, #12 8001f68: af00 add r7, sp, #0 8001f6a: 6078 str r0, [r7, #4] /* Check the DMA peripheral handle */ if (NULL == hdma) 8001f6c: 687b ldr r3, [r7, #4] 8001f6e: 2b00 cmp r3, #0 8001f70: d101 bne.n 8001f76 { return HAL_ERROR; 8001f72: 2301 movs r3, #1 8001f74: e04f b.n 8002016 } /* Check the DMA peripheral state */ if (hdma->State != HAL_DMA_STATE_BUSY) 8001f76: 687b ldr r3, [r7, #4] 8001f78: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8001f7c: b2db uxtb r3, r3 8001f7e: 2b02 cmp r3, #2 8001f80: d008 beq.n 8001f94 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001f82: 687b ldr r3, [r7, #4] 8001f84: 2204 movs r2, #4 8001f86: 63da str r2, [r3, #60] @ 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f88: 687b ldr r3, [r7, #4] 8001f8a: 2200 movs r2, #0 8001f8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 8001f90: 2301 movs r3, #1 8001f92: e040 b.n 8002016 } else { /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8001f94: 687b ldr r3, [r7, #4] 8001f96: 681b ldr r3, [r3, #0] 8001f98: 681a ldr r2, [r3, #0] 8001f9a: 687b ldr r3, [r7, #4] 8001f9c: 681b ldr r3, [r3, #0] 8001f9e: f022 0201 bic.w r2, r2, #1 8001fa2: 601a str r2, [r3, #0] /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8001fa4: 687b ldr r3, [r7, #4] 8001fa6: 681b ldr r3, [r3, #0] 8001fa8: 681a ldr r2, [r3, #0] 8001faa: 687b ldr r3, [r7, #4] 8001fac: 681b ldr r3, [r3, #0] 8001fae: f022 020e bic.w r2, r2, #14 8001fb2: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8001fb4: 687b ldr r3, [r7, #4] 8001fb6: 6c9b ldr r3, [r3, #72] @ 0x48 8001fb8: 681a ldr r2, [r3, #0] 8001fba: 687b ldr r3, [r7, #4] 8001fbc: 6c9b ldr r3, [r3, #72] @ 0x48 8001fbe: f422 7280 bic.w r2, r2, #256 @ 0x100 8001fc2: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: 6c5b ldr r3, [r3, #68] @ 0x44 8001fc8: f003 021c and.w r2, r3, #28 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 6c1b ldr r3, [r3, #64] @ 0x40 8001fd0: 2101 movs r1, #1 8001fd2: fa01 f202 lsl.w r2, r1, r2 8001fd6: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001fd8: 687b ldr r3, [r7, #4] 8001fda: 6cdb ldr r3, [r3, #76] @ 0x4c 8001fdc: 687a ldr r2, [r7, #4] 8001fde: 6d12 ldr r2, [r2, #80] @ 0x50 8001fe0: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != NULL) 8001fe2: 687b ldr r3, [r7, #4] 8001fe4: 6d5b ldr r3, [r3, #84] @ 0x54 8001fe6: 2b00 cmp r3, #0 8001fe8: d00c beq.n 8002004 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001fea: 687b ldr r3, [r7, #4] 8001fec: 6d5b ldr r3, [r3, #84] @ 0x54 8001fee: 681a ldr r2, [r3, #0] 8001ff0: 687b ldr r3, [r7, #4] 8001ff2: 6d5b ldr r3, [r3, #84] @ 0x54 8001ff4: f422 7280 bic.w r2, r2, #256 @ 0x100 8001ff8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001ffa: 687b ldr r3, [r7, #4] 8001ffc: 6d9b ldr r3, [r3, #88] @ 0x58 8001ffe: 687a ldr r2, [r7, #4] 8002000: 6dd2 ldr r2, [r2, #92] @ 0x5c 8002002: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002004: 687b ldr r3, [r7, #4] 8002006: 2201 movs r2, #1 8002008: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800200c: 687b ldr r3, [r7, #4] 800200e: 2200 movs r2, #0 8002010: f883 2024 strb.w r2, [r3, #36] @ 0x24 } return HAL_OK; 8002014: 2300 movs r3, #0 } 8002016: 4618 mov r0, r3 8002018: 370c adds r7, #12 800201a: 46bd mov sp, r7 800201c: bc80 pop {r7} 800201e: 4770 bx lr 08002020 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002020: b580 push {r7, lr} 8002022: b084 sub sp, #16 8002024: af00 add r7, sp, #0 8002026: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002028: 2300 movs r3, #0 800202a: 73fb strb r3, [r7, #15] if (hdma->State != HAL_DMA_STATE_BUSY) 800202c: 687b ldr r3, [r7, #4] 800202e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8002032: b2db uxtb r3, r3 8002034: 2b02 cmp r3, #2 8002036: d005 beq.n 8002044 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002038: 687b ldr r3, [r7, #4] 800203a: 2204 movs r2, #4 800203c: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 800203e: 2301 movs r3, #1 8002040: 73fb strb r3, [r7, #15] 8002042: e047 b.n 80020d4 } else { /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002044: 687b ldr r3, [r7, #4] 8002046: 681b ldr r3, [r3, #0] 8002048: 681a ldr r2, [r3, #0] 800204a: 687b ldr r3, [r7, #4] 800204c: 681b ldr r3, [r3, #0] 800204e: f022 0201 bic.w r2, r2, #1 8002052: 601a str r2, [r3, #0] /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002054: 687b ldr r3, [r7, #4] 8002056: 681b ldr r3, [r3, #0] 8002058: 681a ldr r2, [r3, #0] 800205a: 687b ldr r3, [r7, #4] 800205c: 681b ldr r3, [r3, #0] 800205e: f022 020e bic.w r2, r2, #14 8002062: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8002064: 687b ldr r3, [r7, #4] 8002066: 6c9b ldr r3, [r3, #72] @ 0x48 8002068: 681a ldr r2, [r3, #0] 800206a: 687b ldr r3, [r7, #4] 800206c: 6c9b ldr r3, [r3, #72] @ 0x48 800206e: f422 7280 bic.w r2, r2, #256 @ 0x100 8002072: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); 8002074: 687b ldr r3, [r7, #4] 8002076: 6c5b ldr r3, [r3, #68] @ 0x44 8002078: f003 021c and.w r2, r3, #28 800207c: 687b ldr r3, [r7, #4] 800207e: 6c1b ldr r3, [r3, #64] @ 0x40 8002080: 2101 movs r1, #1 8002082: fa01 f202 lsl.w r2, r1, r2 8002086: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002088: 687b ldr r3, [r7, #4] 800208a: 6cdb ldr r3, [r3, #76] @ 0x4c 800208c: 687a ldr r2, [r7, #4] 800208e: 6d12 ldr r2, [r2, #80] @ 0x50 8002090: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != NULL) 8002092: 687b ldr r3, [r7, #4] 8002094: 6d5b ldr r3, [r3, #84] @ 0x54 8002096: 2b00 cmp r3, #0 8002098: d00c beq.n 80020b4 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 800209a: 687b ldr r3, [r7, #4] 800209c: 6d5b ldr r3, [r3, #84] @ 0x54 800209e: 681a ldr r2, [r3, #0] 80020a0: 687b ldr r3, [r7, #4] 80020a2: 6d5b ldr r3, [r3, #84] @ 0x54 80020a4: f422 7280 bic.w r2, r2, #256 @ 0x100 80020a8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80020aa: 687b ldr r3, [r7, #4] 80020ac: 6d9b ldr r3, [r3, #88] @ 0x58 80020ae: 687a ldr r2, [r7, #4] 80020b0: 6dd2 ldr r2, [r2, #92] @ 0x5c 80020b2: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80020b4: 687b ldr r3, [r7, #4] 80020b6: 2201 movs r2, #1 80020b8: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80020bc: 687b ldr r3, [r7, #4] 80020be: 2200 movs r2, #0 80020c0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 80020c4: 687b ldr r3, [r7, #4] 80020c6: 6b9b ldr r3, [r3, #56] @ 0x38 80020c8: 2b00 cmp r3, #0 80020ca: d003 beq.n 80020d4 { hdma->XferAbortCallback(hdma); 80020cc: 687b ldr r3, [r7, #4] 80020ce: 6b9b ldr r3, [r3, #56] @ 0x38 80020d0: 6878 ldr r0, [r7, #4] 80020d2: 4798 blx r3 } } return status; 80020d4: 7bfb ldrb r3, [r7, #15] } 80020d6: 4618 mov r0, r3 80020d8: 3710 adds r7, #16 80020da: 46bd mov sp, r7 80020dc: bd80 pop {r7, pc} ... 080020e0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80020e0: b580 push {r7, lr} 80020e2: b084 sub sp, #16 80020e4: af00 add r7, sp, #0 80020e6: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80020e8: 687b ldr r3, [r7, #4] 80020ea: 6c1b ldr r3, [r3, #64] @ 0x40 80020ec: 681b ldr r3, [r3, #0] 80020ee: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 80020f0: 687b ldr r3, [r7, #4] 80020f2: 681b ldr r3, [r3, #0] 80020f4: 681b ldr r3, [r3, #0] 80020f6: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) 80020f8: 687b ldr r3, [r7, #4] 80020fa: 6c5b ldr r3, [r3, #68] @ 0x44 80020fc: f003 031c and.w r3, r3, #28 8002100: 2204 movs r2, #4 8002102: 409a lsls r2, r3 8002104: 68fb ldr r3, [r7, #12] 8002106: 4013 ands r3, r2 8002108: 2b00 cmp r3, #0 800210a: d027 beq.n 800215c 800210c: 68bb ldr r3, [r7, #8] 800210e: f003 0304 and.w r3, r3, #4 8002112: 2b00 cmp r3, #0 8002114: d022 beq.n 800215c { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002116: 687b ldr r3, [r7, #4] 8002118: 681b ldr r3, [r3, #0] 800211a: 681b ldr r3, [r3, #0] 800211c: f003 0320 and.w r3, r3, #32 8002120: 2b00 cmp r3, #0 8002122: d107 bne.n 8002134 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002124: 687b ldr r3, [r7, #4] 8002126: 681b ldr r3, [r3, #0] 8002128: 681a ldr r2, [r3, #0] 800212a: 687b ldr r3, [r7, #4] 800212c: 681b ldr r3, [r3, #0] 800212e: f022 0204 bic.w r2, r2, #4 8002132: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); 8002134: 687b ldr r3, [r7, #4] 8002136: 6c5b ldr r3, [r3, #68] @ 0x44 8002138: f003 021c and.w r2, r3, #28 800213c: 687b ldr r3, [r7, #4] 800213e: 6c1b ldr r3, [r3, #64] @ 0x40 8002140: 2104 movs r1, #4 8002142: fa01 f202 lsl.w r2, r1, r2 8002146: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 8002148: 687b ldr r3, [r7, #4] 800214a: 6b1b ldr r3, [r3, #48] @ 0x30 800214c: 2b00 cmp r3, #0 800214e: f000 8081 beq.w 8002254 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002152: 687b ldr r3, [r7, #4] 8002154: 6b1b ldr r3, [r3, #48] @ 0x30 8002156: 6878 ldr r0, [r7, #4] 8002158: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 800215a: e07b b.n 8002254 } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) 800215c: 687b ldr r3, [r7, #4] 800215e: 6c5b ldr r3, [r3, #68] @ 0x44 8002160: f003 031c and.w r3, r3, #28 8002164: 2202 movs r2, #2 8002166: 409a lsls r2, r3 8002168: 68fb ldr r3, [r7, #12] 800216a: 4013 ands r3, r2 800216c: 2b00 cmp r3, #0 800216e: d03d beq.n 80021ec 8002170: 68bb ldr r3, [r7, #8] 8002172: f003 0302 and.w r3, r3, #2 8002176: 2b00 cmp r3, #0 8002178: d038 beq.n 80021ec { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800217a: 687b ldr r3, [r7, #4] 800217c: 681b ldr r3, [r3, #0] 800217e: 681b ldr r3, [r3, #0] 8002180: f003 0320 and.w r3, r3, #32 8002184: 2b00 cmp r3, #0 8002186: d10b bne.n 80021a0 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8002188: 687b ldr r3, [r7, #4] 800218a: 681b ldr r3, [r3, #0] 800218c: 681a ldr r2, [r3, #0] 800218e: 687b ldr r3, [r7, #4] 8002190: 681b ldr r3, [r3, #0] 8002192: f022 020a bic.w r2, r2, #10 8002196: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002198: 687b ldr r3, [r7, #4] 800219a: 2201 movs r2, #1 800219c: f883 2025 strb.w r2, [r3, #37] @ 0x25 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); 80021a0: 687b ldr r3, [r7, #4] 80021a2: 681b ldr r3, [r3, #0] 80021a4: 461a mov r2, r3 80021a6: 4b2e ldr r3, [pc, #184] @ (8002260 ) 80021a8: 429a cmp r2, r3 80021aa: d909 bls.n 80021c0 80021ac: 687b ldr r3, [r7, #4] 80021ae: 6c5b ldr r3, [r3, #68] @ 0x44 80021b0: f003 031c and.w r3, r3, #28 80021b4: 4a2b ldr r2, [pc, #172] @ (8002264 ) 80021b6: 2102 movs r1, #2 80021b8: fa01 f303 lsl.w r3, r1, r3 80021bc: 6053 str r3, [r2, #4] 80021be: e008 b.n 80021d2 80021c0: 687b ldr r3, [r7, #4] 80021c2: 6c5b ldr r3, [r3, #68] @ 0x44 80021c4: f003 031c and.w r3, r3, #28 80021c8: 4a27 ldr r2, [pc, #156] @ (8002268 ) 80021ca: 2102 movs r1, #2 80021cc: fa01 f303 lsl.w r3, r1, r3 80021d0: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80021d2: 687b ldr r3, [r7, #4] 80021d4: 2200 movs r2, #0 80021d6: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferCpltCallback != NULL) 80021da: 687b ldr r3, [r7, #4] 80021dc: 6adb ldr r3, [r3, #44] @ 0x2c 80021de: 2b00 cmp r3, #0 80021e0: d038 beq.n 8002254 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80021e2: 687b ldr r3, [r7, #4] 80021e4: 6adb ldr r3, [r3, #44] @ 0x2c 80021e6: 6878 ldr r0, [r7, #4] 80021e8: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 80021ea: e033 b.n 8002254 } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) 80021ec: 687b ldr r3, [r7, #4] 80021ee: 6c5b ldr r3, [r3, #68] @ 0x44 80021f0: f003 031c and.w r3, r3, #28 80021f4: 2208 movs r2, #8 80021f6: 409a lsls r2, r3 80021f8: 68fb ldr r3, [r7, #12] 80021fa: 4013 ands r3, r2 80021fc: 2b00 cmp r3, #0 80021fe: d02a beq.n 8002256 8002200: 68bb ldr r3, [r7, #8] 8002202: f003 0308 and.w r3, r3, #8 8002206: 2b00 cmp r3, #0 8002208: d025 beq.n 8002256 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800220a: 687b ldr r3, [r7, #4] 800220c: 681b ldr r3, [r3, #0] 800220e: 681a ldr r2, [r3, #0] 8002210: 687b ldr r3, [r7, #4] 8002212: 681b ldr r3, [r3, #0] 8002214: f022 020e bic.w r2, r2, #14 8002218: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); 800221a: 687b ldr r3, [r7, #4] 800221c: 6c5b ldr r3, [r3, #68] @ 0x44 800221e: f003 021c and.w r2, r3, #28 8002222: 687b ldr r3, [r7, #4] 8002224: 6c1b ldr r3, [r3, #64] @ 0x40 8002226: 2101 movs r1, #1 8002228: fa01 f202 lsl.w r2, r1, r2 800222c: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800222e: 687b ldr r3, [r7, #4] 8002230: 2201 movs r2, #1 8002232: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002234: 687b ldr r3, [r7, #4] 8002236: 2201 movs r2, #1 8002238: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800223c: 687b ldr r3, [r7, #4] 800223e: 2200 movs r2, #0 8002240: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferErrorCallback != NULL) 8002244: 687b ldr r3, [r7, #4] 8002246: 6b5b ldr r3, [r3, #52] @ 0x34 8002248: 2b00 cmp r3, #0 800224a: d004 beq.n 8002256 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800224c: 687b ldr r3, [r7, #4] 800224e: 6b5b ldr r3, [r3, #52] @ 0x34 8002250: 6878 ldr r0, [r7, #4] 8002252: 4798 blx r3 } else { /* Nothing To Do */ } return; 8002254: bf00 nop 8002256: bf00 nop } 8002258: 3710 adds r7, #16 800225a: 46bd mov sp, r7 800225c: bd80 pop {r7, pc} 800225e: bf00 nop 8002260: 40020080 .word 0x40020080 8002264: 40020400 .word 0x40020400 8002268: 40020000 .word 0x40020000 0800226c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 800226c: b480 push {r7} 800226e: b083 sub sp, #12 8002270: af00 add r7, sp, #0 8002272: 6078 str r0, [r7, #4] /* Return the DMA error code */ return hdma->ErrorCode; 8002274: 687b ldr r3, [r7, #4] 8002276: 6bdb ldr r3, [r3, #60] @ 0x3c } 8002278: 4618 mov r0, r3 800227a: 370c adds r7, #12 800227c: 46bd mov sp, r7 800227e: bc80 pop {r7} 8002280: 4770 bx lr 08002282 : * @param ChannelAttributes specifies the DMA channel secure/privilege attributes. * This parameter can be a one or a combination of @ref DMA_Channel_Attributes * @retval HAL Status */ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes) { 8002282: b480 push {r7} 8002284: b085 sub sp, #20 8002286: af00 add r7, sp, #0 8002288: 6078 str r0, [r7, #4] 800228a: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800228c: 2300 movs r3, #0 800228e: 72fb strb r3, [r7, #11] #if defined (CORE_CM0PLUS) uint32_t ccr_SECM; #endif /* CORE_CM0PLUS */ /* Check the DMA peripheral handle */ if (hdma == NULL) 8002290: 687b ldr r3, [r7, #4] 8002292: 2b00 cmp r3, #0 8002294: d103 bne.n 800229e { status = HAL_ERROR; 8002296: 2301 movs r3, #1 8002298: 72fb strb r3, [r7, #11] return status; 800229a: 7afb ldrb r3, [r7, #11] 800229c: e01b b.n 80022d6 /* Check the parameters */ assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); /* Read CCR register */ ccr = READ_REG(hdma->Instance->CCR); 800229e: 687b ldr r3, [r7, #4] 80022a0: 681b ldr r3, [r3, #0] 80022a2: 681b ldr r3, [r3, #0] 80022a4: 60fb str r3, [r7, #12] /* Apply any requested privilege/non-privilege attributes */ if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) != 0U) 80022a6: 683b ldr r3, [r7, #0] 80022a8: f003 0310 and.w r3, r3, #16 80022ac: 2b00 cmp r3, #0 80022ae: d00d beq.n 80022cc { if ((ChannelAttributes & DMA_CCR_PRIV) != 0U) 80022b0: 683b ldr r3, [r7, #0] 80022b2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80022b6: 2b00 cmp r3, #0 80022b8: d004 beq.n 80022c4 { SET_BIT(ccr, DMA_CCR_PRIV); 80022ba: 68fb ldr r3, [r7, #12] 80022bc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80022c0: 60fb str r3, [r7, #12] 80022c2: e003 b.n 80022cc } else { CLEAR_BIT(ccr, DMA_CCR_PRIV); 80022c4: 68fb ldr r3, [r7, #12] 80022c6: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 80022ca: 60fb str r3, [r7, #12] } #endif /* CORE_CM0PLUS */ /* Update CCR Register: PRIV, SECM, SCEC, DSEC bits */ WRITE_REG(hdma->Instance->CCR, ccr); 80022cc: 687b ldr r3, [r7, #4] 80022ce: 681b ldr r3, [r3, #0] 80022d0: 68fa ldr r2, [r7, #12] 80022d2: 601a str r2, [r3, #0] return status; 80022d4: 7afb ldrb r3, [r7, #11] } 80022d6: 4618 mov r0, r3 80022d8: 3714 adds r7, #20 80022da: 46bd mov sp, r7 80022dc: bc80 pop {r7} 80022de: 4770 bx lr 080022e0 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80022e0: b480 push {r7} 80022e2: b085 sub sp, #20 80022e4: af00 add r7, sp, #0 80022e6: 60f8 str r0, [r7, #12] 80022e8: 60b9 str r1, [r7, #8] 80022ea: 607a str r2, [r7, #4] 80022ec: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80022ee: 68fb ldr r3, [r7, #12] 80022f0: 6cdb ldr r3, [r3, #76] @ 0x4c 80022f2: 68fa ldr r2, [r7, #12] 80022f4: 6d12 ldr r2, [r2, #80] @ 0x50 80022f6: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != NULL) 80022f8: 68fb ldr r3, [r7, #12] 80022fa: 6d5b ldr r3, [r3, #84] @ 0x54 80022fc: 2b00 cmp r3, #0 80022fe: d004 beq.n 800230a { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002300: 68fb ldr r3, [r7, #12] 8002302: 6d9b ldr r3, [r3, #88] @ 0x58 8002304: 68fa ldr r2, [r7, #12] 8002306: 6dd2 ldr r2, [r2, #92] @ 0x5c 8002308: 605a str r2, [r3, #4] } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); 800230a: 68fb ldr r3, [r7, #12] 800230c: 6c5b ldr r3, [r3, #68] @ 0x44 800230e: f003 021c and.w r2, r3, #28 8002312: 68fb ldr r3, [r7, #12] 8002314: 6c1b ldr r3, [r3, #64] @ 0x40 8002316: 2101 movs r1, #1 8002318: fa01 f202 lsl.w r2, r1, r2 800231c: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 800231e: 68fb ldr r3, [r7, #12] 8002320: 681b ldr r3, [r3, #0] 8002322: 683a ldr r2, [r7, #0] 8002324: 605a str r2, [r3, #4] /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002326: 68fb ldr r3, [r7, #12] 8002328: 689b ldr r3, [r3, #8] 800232a: 2b10 cmp r3, #16 800232c: d108 bne.n 8002340 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 800232e: 68fb ldr r3, [r7, #12] 8002330: 681b ldr r3, [r3, #0] 8002332: 687a ldr r2, [r7, #4] 8002334: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8002336: 68fb ldr r3, [r7, #12] 8002338: 681b ldr r3, [r3, #0] 800233a: 68ba ldr r2, [r7, #8] 800233c: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 800233e: e007 b.n 8002350 hdma->Instance->CPAR = SrcAddress; 8002340: 68fb ldr r3, [r7, #12] 8002342: 681b ldr r3, [r3, #0] 8002344: 68ba ldr r2, [r7, #8] 8002346: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8002348: 68fb ldr r3, [r7, #12] 800234a: 681b ldr r3, [r3, #0] 800234c: 687a ldr r2, [r7, #4] 800234e: 60da str r2, [r3, #12] } 8002350: bf00 nop 8002352: 3714 adds r7, #20 8002354: 46bd mov sp, r7 8002356: bc80 pop {r7} 8002358: 4770 bx lr ... 0800235c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800235c: b480 push {r7} 800235e: b085 sub sp, #20 8002360: af00 add r7, sp, #0 8002362: 6078 str r0, [r7, #4] uint32_t channel_number; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8002364: 687b ldr r3, [r7, #4] 8002366: 681b ldr r3, [r3, #0] 8002368: 461a mov r2, r3 800236a: 4b1c ldr r3, [pc, #112] @ (80023dc ) 800236c: 429a cmp r2, r3 800236e: d813 bhi.n 8002398 { /* DMA1 */ /* Associate a DMA Channel to a DMAMUX channel */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); 8002370: 687b ldr r3, [r7, #4] 8002372: 6c5b ldr r3, [r3, #68] @ 0x44 8002374: 089b lsrs r3, r3, #2 8002376: 009b lsls r3, r3, #2 8002378: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 800237c: f503 3302 add.w r3, r3, #133120 @ 0x20800 8002380: 687a ldr r2, [r7, #4] 8002382: 6493 str r3, [r2, #72] @ 0x48 /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8002384: 687b ldr r3, [r7, #4] 8002386: 681b ldr r3, [r3, #0] 8002388: b2db uxtb r3, r3 800238a: 3b08 subs r3, #8 800238c: 4a14 ldr r2, [pc, #80] @ (80023e0 ) 800238e: fba2 2303 umull r2, r3, r2, r3 8002392: 091b lsrs r3, r3, #4 8002394: 60fb str r3, [r7, #12] 8002396: e011 b.n 80023bc } else { /* DMA2 */ /* Associate a DMA Channel to a DMAMUX channel */ hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); 8002398: 687b ldr r3, [r7, #4] 800239a: 6c5b ldr r3, [r3, #68] @ 0x44 800239c: 089b lsrs r3, r3, #2 800239e: 009a lsls r2, r3, #2 80023a0: 4b10 ldr r3, [pc, #64] @ (80023e4 ) 80023a2: 4413 add r3, r2 80023a4: 687a ldr r2, [r7, #4] 80023a6: 6493 str r3, [r2, #72] @ 0x48 /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); 80023a8: 687b ldr r3, [r7, #4] 80023aa: 681b ldr r3, [r3, #0] 80023ac: b2db uxtb r3, r3 80023ae: 3b08 subs r3, #8 80023b0: 4a0b ldr r2, [pc, #44] @ (80023e0 ) 80023b2: fba2 2303 umull r2, r3, r2, r3 80023b6: 091b lsrs r3, r3, #4 80023b8: 3307 adds r3, #7 80023ba: 60fb str r3, [r7, #12] } /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 80023bc: 687b ldr r3, [r7, #4] 80023be: 4a0a ldr r2, [pc, #40] @ (80023e8 ) 80023c0: 64da str r2, [r3, #76] @ 0x4c /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 80023c2: 68fb ldr r3, [r7, #12] 80023c4: f003 031f and.w r3, r3, #31 80023c8: 2201 movs r2, #1 80023ca: 409a lsls r2, r3 80023cc: 687b ldr r3, [r7, #4] 80023ce: 651a str r2, [r3, #80] @ 0x50 } 80023d0: bf00 nop 80023d2: 3714 adds r7, #20 80023d4: 46bd mov sp, r7 80023d6: bc80 pop {r7} 80023d8: 4770 bx lr 80023da: bf00 nop 80023dc: 40020407 .word 0x40020407 80023e0: cccccccd .word 0xcccccccd 80023e4: 4002081c .word 0x4002081c 80023e8: 40020880 .word 0x40020880 080023ec : * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 80023ec: b480 push {r7} 80023ee: b085 sub sp, #20 80023f0: af00 add r7, sp, #0 80023f2: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 80023f4: 687b ldr r3, [r7, #4] 80023f6: 685b ldr r3, [r3, #4] 80023f8: f003 037f and.w r3, r3, #127 @ 0x7f 80023fc: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 80023fe: 68fa ldr r2, [r7, #12] 8002400: 4b0a ldr r3, [pc, #40] @ (800242c ) 8002402: 4413 add r3, r2 8002404: 009b lsls r3, r3, #2 8002406: 461a mov r2, r3 8002408: 687b ldr r3, [r7, #4] 800240a: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800240c: 687b ldr r3, [r7, #4] 800240e: 4a08 ldr r2, [pc, #32] @ (8002430 ) 8002410: 659a str r2, [r3, #88] @ 0x58 /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 8002412: 68fb ldr r3, [r7, #12] 8002414: 3b01 subs r3, #1 8002416: f003 0303 and.w r3, r3, #3 800241a: 2201 movs r2, #1 800241c: 409a lsls r2, r3 800241e: 687b ldr r3, [r7, #4] 8002420: 65da str r2, [r3, #92] @ 0x5c } 8002422: bf00 nop 8002424: 3714 adds r7, #20 8002426: 46bd mov sp, r7 8002428: bc80 pop {r7} 800242a: 4770 bx lr 800242c: 1000823f .word 0x1000823f 8002430: 40020940 .word 0x40020940 08002434 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 8002434: b480 push {r7} 8002436: b087 sub sp, #28 8002438: af00 add r7, sp, #0 800243a: 6078 str r0, [r7, #4] 800243c: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800243e: 2300 movs r3, #0 8002440: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8002442: e140 b.n 80026c6 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8002444: 683b ldr r3, [r7, #0] 8002446: 681a ldr r2, [r3, #0] 8002448: 2101 movs r1, #1 800244a: 697b ldr r3, [r7, #20] 800244c: fa01 f303 lsl.w r3, r1, r3 8002450: 4013 ands r3, r2 8002452: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8002454: 68fb ldr r3, [r7, #12] 8002456: 2b00 cmp r3, #0 8002458: f000 8132 beq.w 80026c0 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800245c: 683b ldr r3, [r7, #0] 800245e: 685b ldr r3, [r3, #4] 8002460: f003 0303 and.w r3, r3, #3 8002464: 2b01 cmp r3, #1 8002466: d005 beq.n 8002474 8002468: 683b ldr r3, [r7, #0] 800246a: 685b ldr r3, [r3, #4] 800246c: f003 0303 and.w r3, r3, #3 8002470: 2b02 cmp r3, #2 8002472: d130 bne.n 80024d6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002474: 687b ldr r3, [r7, #4] 8002476: 689b ldr r3, [r3, #8] 8002478: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800247a: 697b ldr r3, [r7, #20] 800247c: 005b lsls r3, r3, #1 800247e: 2203 movs r2, #3 8002480: fa02 f303 lsl.w r3, r2, r3 8002484: 43db mvns r3, r3 8002486: 693a ldr r2, [r7, #16] 8002488: 4013 ands r3, r2 800248a: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); 800248c: 683b ldr r3, [r7, #0] 800248e: 68da ldr r2, [r3, #12] 8002490: 697b ldr r3, [r7, #20] 8002492: 005b lsls r3, r3, #1 8002494: fa02 f303 lsl.w r3, r2, r3 8002498: 693a ldr r2, [r7, #16] 800249a: 4313 orrs r3, r2 800249c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 800249e: 687b ldr r3, [r7, #4] 80024a0: 693a ldr r2, [r7, #16] 80024a2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80024a4: 687b ldr r3, [r7, #4] 80024a6: 685b ldr r3, [r3, #4] 80024a8: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 80024aa: 2201 movs r2, #1 80024ac: 697b ldr r3, [r7, #20] 80024ae: fa02 f303 lsl.w r3, r2, r3 80024b2: 43db mvns r3, r3 80024b4: 693a ldr r2, [r7, #16] 80024b6: 4013 ands r3, r2 80024b8: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80024ba: 683b ldr r3, [r7, #0] 80024bc: 685b ldr r3, [r3, #4] 80024be: 091b lsrs r3, r3, #4 80024c0: f003 0201 and.w r2, r3, #1 80024c4: 697b ldr r3, [r7, #20] 80024c6: fa02 f303 lsl.w r3, r2, r3 80024ca: 693a ldr r2, [r7, #16] 80024cc: 4313 orrs r3, r2 80024ce: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80024d0: 687b ldr r3, [r7, #4] 80024d2: 693a ldr r2, [r7, #16] 80024d4: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80024d6: 683b ldr r3, [r7, #0] 80024d8: 685b ldr r3, [r3, #4] 80024da: f003 0303 and.w r3, r3, #3 80024de: 2b03 cmp r3, #3 80024e0: d017 beq.n 8002512 { temp = GPIOx->PUPDR; 80024e2: 687b ldr r3, [r7, #4] 80024e4: 68db ldr r3, [r3, #12] 80024e6: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 80024e8: 697b ldr r3, [r7, #20] 80024ea: 005b lsls r3, r3, #1 80024ec: 2203 movs r2, #3 80024ee: fa02 f303 lsl.w r3, r2, r3 80024f2: 43db mvns r3, r3 80024f4: 693a ldr r2, [r7, #16] 80024f6: 4013 ands r3, r2 80024f8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80024fa: 683b ldr r3, [r7, #0] 80024fc: 689a ldr r2, [r3, #8] 80024fe: 697b ldr r3, [r7, #20] 8002500: 005b lsls r3, r3, #1 8002502: fa02 f303 lsl.w r3, r2, r3 8002506: 693a ldr r2, [r7, #16] 8002508: 4313 orrs r3, r2 800250a: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 800250c: 687b ldr r3, [r7, #4] 800250e: 693a ldr r2, [r7, #16] 8002510: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002512: 683b ldr r3, [r7, #0] 8002514: 685b ldr r3, [r3, #4] 8002516: f003 0303 and.w r3, r3, #3 800251a: 2b02 cmp r3, #2 800251c: d123 bne.n 8002566 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800251e: 697b ldr r3, [r7, #20] 8002520: 08da lsrs r2, r3, #3 8002522: 687b ldr r3, [r7, #4] 8002524: 3208 adds r2, #8 8002526: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800252a: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800252c: 697b ldr r3, [r7, #20] 800252e: f003 0307 and.w r3, r3, #7 8002532: 009b lsls r3, r3, #2 8002534: 220f movs r2, #15 8002536: fa02 f303 lsl.w r3, r2, r3 800253a: 43db mvns r3, r3 800253c: 693a ldr r2, [r7, #16] 800253e: 4013 ands r3, r2 8002540: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002542: 683b ldr r3, [r7, #0] 8002544: 691a ldr r2, [r3, #16] 8002546: 697b ldr r3, [r7, #20] 8002548: f003 0307 and.w r3, r3, #7 800254c: 009b lsls r3, r3, #2 800254e: fa02 f303 lsl.w r3, r2, r3 8002552: 693a ldr r2, [r7, #16] 8002554: 4313 orrs r3, r2 8002556: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8002558: 697b ldr r3, [r7, #20] 800255a: 08da lsrs r2, r3, #3 800255c: 687b ldr r3, [r7, #4] 800255e: 3208 adds r2, #8 8002560: 6939 ldr r1, [r7, #16] 8002562: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002566: 687b ldr r3, [r7, #4] 8002568: 681b ldr r3, [r3, #0] 800256a: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800256c: 697b ldr r3, [r7, #20] 800256e: 005b lsls r3, r3, #1 8002570: 2203 movs r2, #3 8002572: fa02 f303 lsl.w r3, r2, r3 8002576: 43db mvns r3, r3 8002578: 693a ldr r2, [r7, #16] 800257a: 4013 ands r3, r2 800257c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800257e: 683b ldr r3, [r7, #0] 8002580: 685b ldr r3, [r3, #4] 8002582: f003 0203 and.w r2, r3, #3 8002586: 697b ldr r3, [r7, #20] 8002588: 005b lsls r3, r3, #1 800258a: fa02 f303 lsl.w r3, r2, r3 800258e: 693a ldr r2, [r7, #16] 8002590: 4313 orrs r3, r2 8002592: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8002594: 687b ldr r3, [r7, #4] 8002596: 693a ldr r2, [r7, #16] 8002598: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 800259a: 683b ldr r3, [r7, #0] 800259c: 685b ldr r3, [r3, #4] 800259e: f403 3340 and.w r3, r3, #196608 @ 0x30000 80025a2: 2b00 cmp r3, #0 80025a4: f000 808c beq.w 80026c0 { temp = SYSCFG->EXTICR[position >> 2u]; 80025a8: 4a4e ldr r2, [pc, #312] @ (80026e4 ) 80025aa: 697b ldr r3, [r7, #20] 80025ac: 089b lsrs r3, r3, #2 80025ae: 3302 adds r3, #2 80025b0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80025b4: 613b str r3, [r7, #16] temp &= ~(0x07uL << (4U * (position & 0x03U))); 80025b6: 697b ldr r3, [r7, #20] 80025b8: f003 0303 and.w r3, r3, #3 80025bc: 009b lsls r3, r3, #2 80025be: 2207 movs r2, #7 80025c0: fa02 f303 lsl.w r3, r2, r3 80025c4: 43db mvns r3, r3 80025c6: 693a ldr r2, [r7, #16] 80025c8: 4013 ands r3, r2 80025ca: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 80025cc: 687b ldr r3, [r7, #4] 80025ce: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 80025d2: d00d beq.n 80025f0 80025d4: 687b ldr r3, [r7, #4] 80025d6: 4a44 ldr r2, [pc, #272] @ (80026e8 ) 80025d8: 4293 cmp r3, r2 80025da: d007 beq.n 80025ec 80025dc: 687b ldr r3, [r7, #4] 80025de: 4a43 ldr r2, [pc, #268] @ (80026ec ) 80025e0: 4293 cmp r3, r2 80025e2: d101 bne.n 80025e8 80025e4: 2302 movs r3, #2 80025e6: e004 b.n 80025f2 80025e8: 2307 movs r3, #7 80025ea: e002 b.n 80025f2 80025ec: 2301 movs r3, #1 80025ee: e000 b.n 80025f2 80025f0: 2300 movs r3, #0 80025f2: 697a ldr r2, [r7, #20] 80025f4: f002 0203 and.w r2, r2, #3 80025f8: 0092 lsls r2, r2, #2 80025fa: 4093 lsls r3, r2 80025fc: 693a ldr r2, [r7, #16] 80025fe: 4313 orrs r3, r2 8002600: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8002602: 4938 ldr r1, [pc, #224] @ (80026e4 ) 8002604: 697b ldr r3, [r7, #20] 8002606: 089b lsrs r3, r3, #2 8002608: 3302 adds r3, #2 800260a: 693a ldr r2, [r7, #16] 800260c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8002610: 4b37 ldr r3, [pc, #220] @ (80026f0 ) 8002612: 681b ldr r3, [r3, #0] 8002614: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8002616: 68fb ldr r3, [r7, #12] 8002618: 43db mvns r3, r3 800261a: 693a ldr r2, [r7, #16] 800261c: 4013 ands r3, r2 800261e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8002620: 683b ldr r3, [r7, #0] 8002622: 685b ldr r3, [r3, #4] 8002624: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002628: 2b00 cmp r3, #0 800262a: d003 beq.n 8002634 { temp |= iocurrent; 800262c: 693a ldr r2, [r7, #16] 800262e: 68fb ldr r3, [r7, #12] 8002630: 4313 orrs r3, r2 8002632: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8002634: 4a2e ldr r2, [pc, #184] @ (80026f0 ) 8002636: 693b ldr r3, [r7, #16] 8002638: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800263a: 4b2d ldr r3, [pc, #180] @ (80026f0 ) 800263c: 685b ldr r3, [r3, #4] 800263e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8002640: 68fb ldr r3, [r7, #12] 8002642: 43db mvns r3, r3 8002644: 693a ldr r2, [r7, #16] 8002646: 4013 ands r3, r2 8002648: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 800264a: 683b ldr r3, [r7, #0] 800264c: 685b ldr r3, [r3, #4] 800264e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002652: 2b00 cmp r3, #0 8002654: d003 beq.n 800265e { temp |= iocurrent; 8002656: 693a ldr r2, [r7, #16] 8002658: 68fb ldr r3, [r7, #12] 800265a: 4313 orrs r3, r2 800265c: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 800265e: 4a24 ldr r2, [pc, #144] @ (80026f0 ) 8002660: 693b ldr r3, [r7, #16] 8002662: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ #ifdef CORE_CM0PLUS temp = EXTI->C2IMR1; #else temp = EXTI->IMR1; 8002664: 4b22 ldr r3, [pc, #136] @ (80026f0 ) 8002666: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800266a: 613b str r3, [r7, #16] #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); 800266c: 68fb ldr r3, [r7, #12] 800266e: 43db mvns r3, r3 8002670: 693a ldr r2, [r7, #16] 8002672: 4013 ands r3, r2 8002674: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8002676: 683b ldr r3, [r7, #0] 8002678: 685b ldr r3, [r3, #4] 800267a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800267e: 2b00 cmp r3, #0 8002680: d003 beq.n 800268a { temp |= iocurrent; 8002682: 693a ldr r2, [r7, #16] 8002684: 68fb ldr r3, [r7, #12] 8002686: 4313 orrs r3, r2 8002688: 613b str r3, [r7, #16] } #ifdef CORE_CM0PLUS EXTI->C2IMR1 = temp; #else EXTI->IMR1 = temp; 800268a: 4a19 ldr r2, [pc, #100] @ (80026f0 ) 800268c: 693b ldr r3, [r7, #16] 800268e: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* CORE_CM0PLUS */ #ifdef CORE_CM0PLUS temp = EXTI->C2EMR1; #else temp = EXTI->EMR1; 8002692: 4b17 ldr r3, [pc, #92] @ (80026f0 ) 8002694: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8002698: 613b str r3, [r7, #16] #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); 800269a: 68fb ldr r3, [r7, #12] 800269c: 43db mvns r3, r3 800269e: 693a ldr r2, [r7, #16] 80026a0: 4013 ands r3, r2 80026a2: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 80026a4: 683b ldr r3, [r7, #0] 80026a6: 685b ldr r3, [r3, #4] 80026a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80026ac: 2b00 cmp r3, #0 80026ae: d003 beq.n 80026b8 { temp |= iocurrent; 80026b0: 693a ldr r2, [r7, #16] 80026b2: 68fb ldr r3, [r7, #12] 80026b4: 4313 orrs r3, r2 80026b6: 613b str r3, [r7, #16] } #ifdef CORE_CM0PLUS EXTI->C2EMR1 = temp; #else EXTI->EMR1 = temp; 80026b8: 4a0d ldr r2, [pc, #52] @ (80026f0 ) 80026ba: 693b ldr r3, [r7, #16] 80026bc: f8c2 3084 str.w r3, [r2, #132] @ 0x84 #endif /* CORE_CM0PLUS */ } } position++; 80026c0: 697b ldr r3, [r7, #20] 80026c2: 3301 adds r3, #1 80026c4: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80026c6: 683b ldr r3, [r7, #0] 80026c8: 681a ldr r2, [r3, #0] 80026ca: 697b ldr r3, [r7, #20] 80026cc: fa22 f303 lsr.w r3, r2, r3 80026d0: 2b00 cmp r3, #0 80026d2: f47f aeb7 bne.w 8002444 } } 80026d6: bf00 nop 80026d8: bf00 nop 80026da: 371c adds r7, #28 80026dc: 46bd mov sp, r7 80026de: bc80 pop {r7} 80026e0: 4770 bx lr 80026e2: bf00 nop 80026e4: 40010000 .word 0x40010000 80026e8: 48000400 .word 0x48000400 80026ec: 48000800 .word 0x48000800 80026f0: 58000800 .word 0x58000800 080026f4 : * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { 80026f4: b480 push {r7} 80026f6: b087 sub sp, #28 80026f8: af00 add r7, sp, #0 80026fa: 6078 str r0, [r7, #4] 80026fc: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80026fe: 2300 movs r3, #0 8002700: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0x00u) 8002702: e0af b.n 8002864 { /* Get current io position */ iocurrent = (GPIO_Pin) & (1uL << position); 8002704: 2201 movs r2, #1 8002706: 697b ldr r3, [r7, #20] 8002708: fa02 f303 lsl.w r3, r2, r3 800270c: 683a ldr r2, [r7, #0] 800270e: 4013 ands r3, r2 8002710: 613b str r3, [r7, #16] if (iocurrent != 0x00u) 8002712: 693b ldr r3, [r7, #16] 8002714: 2b00 cmp r3, #0 8002716: f000 80a2 beq.w 800285e { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2u]; 800271a: 4a59 ldr r2, [pc, #356] @ (8002880 ) 800271c: 697b ldr r3, [r7, #20] 800271e: 089b lsrs r3, r3, #2 8002720: 3302 adds r3, #2 8002722: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002726: 60fb str r3, [r7, #12] tmp &= (0x07uL << (4U * (position & 0x03U))); 8002728: 697b ldr r3, [r7, #20] 800272a: f003 0303 and.w r3, r3, #3 800272e: 009b lsls r3, r3, #2 8002730: 2207 movs r2, #7 8002732: fa02 f303 lsl.w r3, r2, r3 8002736: 68fa ldr r2, [r7, #12] 8002738: 4013 ands r3, r2 800273a: 60fb str r3, [r7, #12] if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) 800273c: 687b ldr r3, [r7, #4] 800273e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8002742: d00d beq.n 8002760 8002744: 687b ldr r3, [r7, #4] 8002746: 4a4f ldr r2, [pc, #316] @ (8002884 ) 8002748: 4293 cmp r3, r2 800274a: d007 beq.n 800275c 800274c: 687b ldr r3, [r7, #4] 800274e: 4a4e ldr r2, [pc, #312] @ (8002888 ) 8002750: 4293 cmp r3, r2 8002752: d101 bne.n 8002758 8002754: 2302 movs r3, #2 8002756: e004 b.n 8002762 8002758: 2307 movs r3, #7 800275a: e002 b.n 8002762 800275c: 2301 movs r3, #1 800275e: e000 b.n 8002762 8002760: 2300 movs r3, #0 8002762: 697a ldr r2, [r7, #20] 8002764: f002 0203 and.w r2, r2, #3 8002768: 0092 lsls r2, r2, #2 800276a: 4093 lsls r3, r2 800276c: 68fa ldr r2, [r7, #12] 800276e: 429a cmp r2, r3 8002770: d136 bne.n 80027e0 /* Clear EXTI line configuration */ #ifdef CORE_CM0PLUS EXTI->C2IMR1 &= ~(iocurrent); EXTI->C2EMR1 &= ~(iocurrent); #else EXTI->IMR1 &= ~(iocurrent); 8002772: 4b46 ldr r3, [pc, #280] @ (800288c ) 8002774: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8002778: 693b ldr r3, [r7, #16] 800277a: 43db mvns r3, r3 800277c: 4943 ldr r1, [pc, #268] @ (800288c ) 800277e: 4013 ands r3, r2 8002780: f8c1 3080 str.w r3, [r1, #128] @ 0x80 EXTI->EMR1 &= ~(iocurrent); 8002784: 4b41 ldr r3, [pc, #260] @ (800288c ) 8002786: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800278a: 693b ldr r3, [r7, #16] 800278c: 43db mvns r3, r3 800278e: 493f ldr r1, [pc, #252] @ (800288c ) 8002790: 4013 ands r3, r2 8002792: f8c1 3084 str.w r3, [r1, #132] @ 0x84 #endif /* CORE_CM0PLUS */ /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); 8002796: 4b3d ldr r3, [pc, #244] @ (800288c ) 8002798: 681a ldr r2, [r3, #0] 800279a: 693b ldr r3, [r7, #16] 800279c: 43db mvns r3, r3 800279e: 493b ldr r1, [pc, #236] @ (800288c ) 80027a0: 4013 ands r3, r2 80027a2: 600b str r3, [r1, #0] EXTI->FTSR1 &= ~(iocurrent); 80027a4: 4b39 ldr r3, [pc, #228] @ (800288c ) 80027a6: 685a ldr r2, [r3, #4] 80027a8: 693b ldr r3, [r7, #16] 80027aa: 43db mvns r3, r3 80027ac: 4937 ldr r1, [pc, #220] @ (800288c ) 80027ae: 4013 ands r3, r2 80027b0: 604b str r3, [r1, #4] /* Clear EXTICR configuration */ tmp = 0x07uL << (4u * (position & 0x03U)); 80027b2: 697b ldr r3, [r7, #20] 80027b4: f003 0303 and.w r3, r3, #3 80027b8: 009b lsls r3, r3, #2 80027ba: 2207 movs r2, #7 80027bc: fa02 f303 lsl.w r3, r2, r3 80027c0: 60fb str r3, [r7, #12] SYSCFG->EXTICR[position >> 2u] &= ~tmp; 80027c2: 4a2f ldr r2, [pc, #188] @ (8002880 ) 80027c4: 697b ldr r3, [r7, #20] 80027c6: 089b lsrs r3, r3, #2 80027c8: 3302 adds r3, #2 80027ca: f852 1023 ldr.w r1, [r2, r3, lsl #2] 80027ce: 68fb ldr r3, [r7, #12] 80027d0: 43da mvns r2, r3 80027d2: 482b ldr r0, [pc, #172] @ (8002880 ) 80027d4: 697b ldr r3, [r7, #20] 80027d6: 089b lsrs r3, r3, #2 80027d8: 400a ands r2, r1 80027da: 3302 adds r3, #2 80027dc: f840 2023 str.w r2, [r0, r3, lsl #2] } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); 80027e0: 687b ldr r3, [r7, #4] 80027e2: 681a ldr r2, [r3, #0] 80027e4: 697b ldr r3, [r7, #20] 80027e6: 005b lsls r3, r3, #1 80027e8: 2103 movs r1, #3 80027ea: fa01 f303 lsl.w r3, r1, r3 80027ee: 431a orrs r2, r3 80027f0: 687b ldr r3, [r7, #4] 80027f2: 601a str r2, [r3, #0] /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; 80027f4: 697b ldr r3, [r7, #20] 80027f6: 08da lsrs r2, r3, #3 80027f8: 687b ldr r3, [r7, #4] 80027fa: 3208 adds r2, #8 80027fc: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8002800: 697b ldr r3, [r7, #20] 8002802: f003 0307 and.w r3, r3, #7 8002806: 009b lsls r3, r3, #2 8002808: 220f movs r2, #15 800280a: fa02 f303 lsl.w r3, r2, r3 800280e: 43db mvns r3, r3 8002810: 697a ldr r2, [r7, #20] 8002812: 08d2 lsrs r2, r2, #3 8002814: 4019 ands r1, r3 8002816: 687b ldr r3, [r7, #4] 8002818: 3208 adds r2, #8 800281a: f843 1022 str.w r1, [r3, r2, lsl #2] /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800281e: 687b ldr r3, [r7, #4] 8002820: 689a ldr r2, [r3, #8] 8002822: 697b ldr r3, [r7, #20] 8002824: 005b lsls r3, r3, #1 8002826: 2103 movs r1, #3 8002828: fa01 f303 lsl.w r3, r1, r3 800282c: 43db mvns r3, r3 800282e: 401a ands r2, r3 8002830: 687b ldr r3, [r7, #4] 8002832: 609a str r2, [r3, #8] /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; 8002834: 687b ldr r3, [r7, #4] 8002836: 685a ldr r2, [r3, #4] 8002838: 2101 movs r1, #1 800283a: 697b ldr r3, [r7, #20] 800283c: fa01 f303 lsl.w r3, r1, r3 8002840: 43db mvns r3, r3 8002842: 401a ands r2, r3 8002844: 687b ldr r3, [r7, #4] 8002846: 605a str r2, [r3, #4] /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8002848: 687b ldr r3, [r7, #4] 800284a: 68da ldr r2, [r3, #12] 800284c: 697b ldr r3, [r7, #20] 800284e: 005b lsls r3, r3, #1 8002850: 2103 movs r1, #3 8002852: fa01 f303 lsl.w r3, r1, r3 8002856: 43db mvns r3, r3 8002858: 401a ands r2, r3 800285a: 687b ldr r3, [r7, #4] 800285c: 60da str r2, [r3, #12] } position++; 800285e: 697b ldr r3, [r7, #20] 8002860: 3301 adds r3, #1 8002862: 617b str r3, [r7, #20] while ((GPIO_Pin >> position) != 0x00u) 8002864: 683a ldr r2, [r7, #0] 8002866: 697b ldr r3, [r7, #20] 8002868: fa22 f303 lsr.w r3, r2, r3 800286c: 2b00 cmp r3, #0 800286e: f47f af49 bne.w 8002704 } } 8002872: bf00 nop 8002874: bf00 nop 8002876: 371c adds r7, #28 8002878: 46bd mov sp, r7 800287a: bc80 pop {r7} 800287c: 4770 bx lr 800287e: bf00 nop 8002880: 40010000 .word 0x40010000 8002884: 48000400 .word 0x48000400 8002888: 48000800 .word 0x48000800 800288c: 58000800 .word 0x58000800 08002890 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002890: b480 push {r7} 8002892: b083 sub sp, #12 8002894: af00 add r7, sp, #0 8002896: 6078 str r0, [r7, #4] 8002898: 460b mov r3, r1 800289a: 807b strh r3, [r7, #2] 800289c: 4613 mov r3, r2 800289e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80028a0: 787b ldrb r3, [r7, #1] 80028a2: 2b00 cmp r3, #0 80028a4: d003 beq.n 80028ae { GPIOx->BSRR = (uint32_t)GPIO_Pin; 80028a6: 887a ldrh r2, [r7, #2] 80028a8: 687b ldr r3, [r7, #4] 80028aa: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 80028ac: e002 b.n 80028b4 GPIOx->BRR = (uint32_t)GPIO_Pin; 80028ae: 887a ldrh r2, [r7, #2] 80028b0: 687b ldr r3, [r7, #4] 80028b2: 629a str r2, [r3, #40] @ 0x28 } 80028b4: bf00 nop 80028b6: 370c adds r7, #12 80028b8: 46bd mov sp, r7 80028ba: bc80 pop {r7} 80028bc: 4770 bx lr ... 080028c0 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 80028c0: b580 push {r7, lr} 80028c2: b082 sub sp, #8 80028c4: af00 add r7, sp, #0 80028c6: 4603 mov r3, r0 80028c8: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 80028ca: 4b08 ldr r3, [pc, #32] @ (80028ec ) 80028cc: 68da ldr r2, [r3, #12] 80028ce: 88fb ldrh r3, [r7, #6] 80028d0: 4013 ands r3, r2 80028d2: 2b00 cmp r3, #0 80028d4: d006 beq.n 80028e4 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80028d6: 4a05 ldr r2, [pc, #20] @ (80028ec ) 80028d8: 88fb ldrh r3, [r7, #6] 80028da: 60d3 str r3, [r2, #12] HAL_GPIO_EXTI_Callback(GPIO_Pin); 80028dc: 88fb ldrh r3, [r7, #6] 80028de: 4618 mov r0, r3 80028e0: f000 f806 bl 80028f0 } } 80028e4: bf00 nop 80028e6: 3708 adds r7, #8 80028e8: 46bd mov sp, r7 80028ea: bd80 pop {r7, pc} 80028ec: 58000800 .word 0x58000800 080028f0 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 80028f0: b480 push {r7} 80028f2: b083 sub sp, #12 80028f4: af00 add r7, sp, #0 80028f6: 4603 mov r3, r0 80028f8: 80fb strh r3, [r7, #6] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } 80028fa: bf00 nop 80028fc: 370c adds r7, #12 80028fe: 46bd mov sp, r7 8002900: bc80 pop {r7} 8002902: 4770 bx lr 08002904 : * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * backup domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8002904: b480 push {r7} 8002906: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); 8002908: 4b04 ldr r3, [pc, #16] @ (800291c ) 800290a: 681b ldr r3, [r3, #0] 800290c: 4a03 ldr r2, [pc, #12] @ (800291c ) 800290e: f443 7380 orr.w r3, r3, #256 @ 0x100 8002912: 6013 str r3, [r2, #0] } 8002914: bf00 nop 8002916: 46bd mov sp, r7 8002918: bc80 pop {r7} 800291a: 4770 bx lr 800291c: 58000400 .word 0x58000400 08002920 : * @note When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { 8002920: b580 push {r7, lr} 8002922: b082 sub sp, #8 8002924: af00 add r7, sp, #0 8002926: 6078 str r0, [r7, #4] 8002928: 460b mov r3, r1 800292a: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Set Regulator parameter */ if (Regulator == PWR_MAINREGULATOR_ON) 800292c: 687b ldr r3, [r7, #4] 800292e: 2b00 cmp r3, #0 8002930: d10c bne.n 800294c { /* If in low-power run mode at this point, exit it */ if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) 8002932: 4b13 ldr r3, [pc, #76] @ (8002980 ) 8002934: 695b ldr r3, [r3, #20] 8002936: f403 7300 and.w r3, r3, #512 @ 0x200 800293a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800293e: d10d bne.n 800295c { if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) 8002940: f000 f83c bl 80029bc 8002944: 4603 mov r3, r0 8002946: 2b00 cmp r3, #0 8002948: d008 beq.n 800295c { return ; 800294a: e015 b.n 8002978 } else { /* If in run mode, first move to low-power run mode. The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF))) 800294c: 4b0c ldr r3, [pc, #48] @ (8002980 ) 800294e: 695b ldr r3, [r3, #20] 8002950: f403 7300 and.w r3, r3, #512 @ 0x200 8002954: 2b00 cmp r3, #0 8002956: d101 bne.n 800295c { HAL_PWREx_EnableLowPowerRunMode(); 8002958: f000 f822 bl 80029a0 } } /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 800295c: 4b09 ldr r3, [pc, #36] @ (8002984 ) 800295e: 691b ldr r3, [r3, #16] 8002960: 4a08 ldr r2, [pc, #32] @ (8002984 ) 8002962: f023 0304 bic.w r3, r3, #4 8002966: 6113 str r3, [r2, #16] /* Select SLEEP mode entry -------------------------------------------------*/ if (SLEEPEntry == PWR_SLEEPENTRY_WFI) 8002968: 78fb ldrb r3, [r7, #3] 800296a: 2b01 cmp r3, #1 800296c: d101 bne.n 8002972 { /* Request Wait For Interrupt */ __WFI(); 800296e: bf30 wfi 8002970: e002 b.n 8002978 } else { /* Request Wait For Event */ __SEV(); 8002972: bf40 sev __WFE(); 8002974: bf20 wfe __WFE(); 8002976: bf20 wfe } } 8002978: 3708 adds r7, #8 800297a: 46bd mov sp, r7 800297c: bd80 pop {r7, pc} 800297e: bf00 nop 8002980: 58000400 .word 0x58000400 8002984: e000ed00 .word 0xe000ed00 08002988 : /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) */ uint32_t HAL_PWREx_GetVoltageRange(void) { 8002988: b480 push {r7} 800298a: af00 add r7, sp, #0 return (PWR->CR1 & PWR_CR1_VOS); 800298c: 4b03 ldr r3, [pc, #12] @ (800299c ) 800298e: 681b ldr r3, [r3, #0] 8002990: f403 63c0 and.w r3, r3, #1536 @ 0x600 } 8002994: 4618 mov r0, r3 8002996: 46bd mov sp, r7 8002998: bc80 pop {r7} 800299a: 4770 bx lr 800299c: 58000400 .word 0x58000400 080029a0 : * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. * @note Clock frequency must be reduced below 2 MHz. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { 80029a0: b480 push {r7} 80029a2: af00 add r7, sp, #0 /* Set Regulator parameter */ SET_BIT(PWR->CR1, PWR_CR1_LPR); 80029a4: 4b04 ldr r3, [pc, #16] @ (80029b8 ) 80029a6: 681b ldr r3, [r3, #0] 80029a8: 4a03 ldr r2, [pc, #12] @ (80029b8 ) 80029aa: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80029ae: 6013 str r3, [r2, #0] } 80029b0: bf00 nop 80029b2: 46bd mov sp, r7 80029b4: bc80 pop {r7} 80029b6: 4770 bx lr 80029b8: 58000400 .word 0x58000400 080029bc : * returns HAL_TIMEOUT status). The system clock frequency can then be * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { 80029bc: b480 push {r7} 80029be: b083 sub sp, #12 80029c0: af00 add r7, sp, #0 uint32_t wait_loop_index; /* Clear LPR bit */ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 80029c2: 4b16 ldr r3, [pc, #88] @ (8002a1c ) 80029c4: 681b ldr r3, [r3, #0] 80029c6: 4a15 ldr r2, [pc, #84] @ (8002a1c ) 80029c8: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80029cc: 6013 str r3, [r2, #0] /* Wait until REGLPF is reset */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); 80029ce: 4b14 ldr r3, [pc, #80] @ (8002a20 ) 80029d0: 681b ldr r3, [r3, #0] 80029d2: 2232 movs r2, #50 @ 0x32 80029d4: fb02 f303 mul.w r3, r2, r3 80029d8: 4a12 ldr r2, [pc, #72] @ (8002a24 ) 80029da: fba2 2303 umull r2, r3, r2, r3 80029de: 0c9b lsrs r3, r3, #18 80029e0: 607b str r3, [r7, #4] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) 80029e2: e002 b.n 80029ea { wait_loop_index--; 80029e4: 687b ldr r3, [r7, #4] 80029e6: 3b01 subs r3, #1 80029e8: 607b str r3, [r7, #4] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) 80029ea: 4b0c ldr r3, [pc, #48] @ (8002a1c ) 80029ec: 695b ldr r3, [r3, #20] 80029ee: f403 7300 and.w r3, r3, #512 @ 0x200 80029f2: f5b3 7f00 cmp.w r3, #512 @ 0x200 80029f6: d102 bne.n 80029fe 80029f8: 687b ldr r3, [r7, #4] 80029fa: 2b00 cmp r3, #0 80029fc: d1f2 bne.n 80029e4 } if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) 80029fe: 4b07 ldr r3, [pc, #28] @ (8002a1c ) 8002a00: 695b ldr r3, [r3, #20] 8002a02: f403 7300 and.w r3, r3, #512 @ 0x200 8002a06: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002a0a: d101 bne.n 8002a10 { return HAL_TIMEOUT; 8002a0c: 2303 movs r3, #3 8002a0e: e000 b.n 8002a12 } return HAL_OK; 8002a10: 2300 movs r3, #0 } 8002a12: 4618 mov r0, r3 8002a14: 370c adds r7, #12 8002a16: 46bd mov sp, r7 8002a18: bc80 pop {r7} 8002a1a: 4770 bx lr 8002a1c: 58000400 .word 0x58000400 8002a20: 20000000 .word 0x20000000 8002a24: 431bde83 .word 0x431bde83 08002a28 : * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction * @retval None */ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) { 8002a28: b480 push {r7} 8002a2a: b083 sub sp, #12 8002a2c: af00 add r7, sp, #0 8002a2e: 4603 mov r3, r0 8002a30: 71fb strb r3, [r7, #7] #ifdef CORE_CM0PLUS /* Set Stop mode 2 */ MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2); #else /* Set Stop mode 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); 8002a32: 4b10 ldr r3, [pc, #64] @ (8002a74 ) 8002a34: 681b ldr r3, [r3, #0] 8002a36: f023 0307 bic.w r3, r3, #7 8002a3a: 4a0e ldr r2, [pc, #56] @ (8002a74 ) 8002a3c: f043 0302 orr.w r3, r3, #2 8002a40: 6013 str r3, [r2, #0] #endif /* CORE_CM0PLUS */ /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 8002a42: 4b0d ldr r3, [pc, #52] @ (8002a78 ) 8002a44: 691b ldr r3, [r3, #16] 8002a46: 4a0c ldr r2, [pc, #48] @ (8002a78 ) 8002a48: f043 0304 orr.w r3, r3, #4 8002a4c: 6113 str r3, [r2, #16] /* Select Stop mode entry --------------------------------------------------*/ if (STOPEntry == PWR_STOPENTRY_WFI) 8002a4e: 79fb ldrb r3, [r7, #7] 8002a50: 2b01 cmp r3, #1 8002a52: d101 bne.n 8002a58 { /* Request Wait For Interrupt */ __WFI(); 8002a54: bf30 wfi 8002a56: e002 b.n 8002a5e } else { /* Request Wait For Event */ __SEV(); 8002a58: bf40 sev __WFE(); 8002a5a: bf20 wfe __WFE(); 8002a5c: bf20 wfe } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 8002a5e: 4b06 ldr r3, [pc, #24] @ (8002a78 ) 8002a60: 691b ldr r3, [r3, #16] 8002a62: 4a05 ldr r2, [pc, #20] @ (8002a78 ) 8002a64: f023 0304 bic.w r3, r3, #4 8002a68: 6113 str r3, [r2, #16] } 8002a6a: bf00 nop 8002a6c: 370c adds r7, #12 8002a6e: 46bd mov sp, r7 8002a70: bc80 pop {r7} 8002a72: 4770 bx lr 8002a74: 58000400 .word 0x58000400 8002a78: e000ed00 .word 0xe000ed00 08002a7c : { 8002a7c: b480 push {r7} 8002a7e: af00 add r7, sp, #0 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); 8002a80: 4b06 ldr r3, [pc, #24] @ (8002a9c ) 8002a82: 681b ldr r3, [r3, #0] 8002a84: f403 7380 and.w r3, r3, #256 @ 0x100 8002a88: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002a8c: d101 bne.n 8002a92 8002a8e: 2301 movs r3, #1 8002a90: e000 b.n 8002a94 8002a92: 2300 movs r3, #0 } 8002a94: 4618 mov r0, r3 8002a96: 46bd mov sp, r7 8002a98: bc80 pop {r7} 8002a9a: 4770 bx lr 8002a9c: 58000400 .word 0x58000400 08002aa0 : { 8002aa0: b480 push {r7} 8002aa2: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); 8002aa4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002aa8: 681b ldr r3, [r3, #0] 8002aaa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002aae: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8002ab2: 6013 str r3, [r2, #0] } 8002ab4: bf00 nop 8002ab6: 46bd mov sp, r7 8002ab8: bc80 pop {r7} 8002aba: 4770 bx lr 08002abc : { 8002abc: b480 push {r7} 8002abe: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); 8002ac0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002ac4: 681b ldr r3, [r3, #0] 8002ac6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002aca: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8002ace: 6013 str r3, [r2, #0] } 8002ad0: bf00 nop 8002ad2: 46bd mov sp, r7 8002ad4: bc80 pop {r7} 8002ad6: 4770 bx lr 08002ad8 : { 8002ad8: b480 push {r7} 8002ada: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); 8002adc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002ae0: 681b ldr r3, [r3, #0] 8002ae2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002ae6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8002aea: d101 bne.n 8002af0 8002aec: 2301 movs r3, #1 8002aee: e000 b.n 8002af2 8002af0: 2300 movs r3, #0 } 8002af2: 4618 mov r0, r3 8002af4: 46bd mov sp, r7 8002af6: bc80 pop {r7} 8002af8: 4770 bx lr 08002afa : { 8002afa: b480 push {r7} 8002afc: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEON); 8002afe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b02: 681b ldr r3, [r3, #0] 8002b04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002b08: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8002b0c: 6013 str r3, [r2, #0] } 8002b0e: bf00 nop 8002b10: 46bd mov sp, r7 8002b12: bc80 pop {r7} 8002b14: 4770 bx lr 08002b16 : { 8002b16: b480 push {r7} 8002b18: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 8002b1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b1e: 681b ldr r3, [r3, #0] 8002b20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002b24: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002b28: 6013 str r3, [r2, #0] } 8002b2a: bf00 nop 8002b2c: 46bd mov sp, r7 8002b2e: bc80 pop {r7} 8002b30: 4770 bx lr 08002b32 : { 8002b32: b480 push {r7} 8002b34: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); 8002b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b3a: 681b ldr r3, [r3, #0] 8002b3c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002b40: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8002b44: d101 bne.n 8002b4a 8002b46: 2301 movs r3, #1 8002b48: e000 b.n 8002b4c 8002b4a: 2300 movs r3, #0 } 8002b4c: 4618 mov r0, r3 8002b4e: 46bd mov sp, r7 8002b50: bc80 pop {r7} 8002b52: 4770 bx lr 08002b54 : { 8002b54: b480 push {r7} 8002b56: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSION); 8002b58: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b5c: 681b ldr r3, [r3, #0] 8002b5e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002b62: f443 7380 orr.w r3, r3, #256 @ 0x100 8002b66: 6013 str r3, [r2, #0] } 8002b68: bf00 nop 8002b6a: 46bd mov sp, r7 8002b6c: bc80 pop {r7} 8002b6e: 4770 bx lr 08002b70 : { 8002b70: b480 push {r7} 8002b72: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 8002b74: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b78: 681b ldr r3, [r3, #0] 8002b7a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002b7e: f423 7380 bic.w r3, r3, #256 @ 0x100 8002b82: 6013 str r3, [r2, #0] } 8002b84: bf00 nop 8002b86: 46bd mov sp, r7 8002b88: bc80 pop {r7} 8002b8a: 4770 bx lr 08002b8c : { 8002b8c: b480 push {r7} 8002b8e: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); 8002b90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002b94: 681b ldr r3, [r3, #0] 8002b96: f403 6380 and.w r3, r3, #1024 @ 0x400 8002b9a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b9e: d101 bne.n 8002ba4 8002ba0: 2301 movs r3, #1 8002ba2: e000 b.n 8002ba6 8002ba4: 2300 movs r3, #0 } 8002ba6: 4618 mov r0, r3 8002ba8: 46bd mov sp, r7 8002baa: bc80 pop {r7} 8002bac: 4770 bx lr 08002bae : { 8002bae: b480 push {r7} 8002bb0: b083 sub sp, #12 8002bb2: af00 add r7, sp, #0 8002bb4: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); 8002bb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002bba: 685b ldr r3, [r3, #4] 8002bbc: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8002bc0: 687b ldr r3, [r7, #4] 8002bc2: 061b lsls r3, r3, #24 8002bc4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002bc8: 4313 orrs r3, r2 8002bca: 604b str r3, [r1, #4] } 8002bcc: bf00 nop 8002bce: 370c adds r7, #12 8002bd0: 46bd mov sp, r7 8002bd2: bc80 pop {r7} 8002bd4: 4770 bx lr 08002bd6 : { 8002bd6: b480 push {r7} 8002bd8: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 8002bda: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002bde: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002be2: f003 0302 and.w r3, r3, #2 8002be6: 2b02 cmp r3, #2 8002be8: d101 bne.n 8002bee 8002bea: 2301 movs r3, #1 8002bec: e000 b.n 8002bf0 8002bee: 2300 movs r3, #0 } 8002bf0: 4618 mov r0, r3 8002bf2: 46bd mov sp, r7 8002bf4: bc80 pop {r7} 8002bf6: 4770 bx lr 08002bf8 : { 8002bf8: b480 push {r7} 8002bfa: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSION); 8002bfc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c00: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002c04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002c08: f043 0301 orr.w r3, r3, #1 8002c0c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 8002c10: bf00 nop 8002c12: 46bd mov sp, r7 8002c14: bc80 pop {r7} 8002c16: 4770 bx lr 08002c18 : { 8002c18: b480 push {r7} 8002c1a: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 8002c1c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c20: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002c24: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002c28: f023 0301 bic.w r3, r3, #1 8002c2c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 8002c30: bf00 nop 8002c32: 46bd mov sp, r7 8002c34: bc80 pop {r7} 8002c36: 4770 bx lr 08002c38 : { 8002c38: b480 push {r7} 8002c3a: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); 8002c3c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c40: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002c44: f003 0302 and.w r3, r3, #2 8002c48: 2b02 cmp r3, #2 8002c4a: d101 bne.n 8002c50 8002c4c: 2301 movs r3, #1 8002c4e: e000 b.n 8002c52 8002c50: 2300 movs r3, #0 } 8002c52: 4618 mov r0, r3 8002c54: 46bd mov sp, r7 8002c56: bc80 pop {r7} 8002c58: 4770 bx lr 08002c5a : { 8002c5a: b480 push {r7} 8002c5c: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); 8002c5e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c62: 681b ldr r3, [r3, #0] 8002c64: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002c68: f043 0301 orr.w r3, r3, #1 8002c6c: 6013 str r3, [r2, #0] } 8002c6e: bf00 nop 8002c70: 46bd mov sp, r7 8002c72: bc80 pop {r7} 8002c74: 4770 bx lr 08002c76 : { 8002c76: b480 push {r7} 8002c78: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 8002c7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c7e: 681b ldr r3, [r3, #0] 8002c80: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002c84: f023 0301 bic.w r3, r3, #1 8002c88: 6013 str r3, [r2, #0] } 8002c8a: bf00 nop 8002c8c: 46bd mov sp, r7 8002c8e: bc80 pop {r7} 8002c90: 4770 bx lr 08002c92 : { 8002c92: b480 push {r7} 8002c94: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); 8002c96: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002c9a: 681b ldr r3, [r3, #0] 8002c9c: f003 0302 and.w r3, r3, #2 8002ca0: 2b02 cmp r3, #2 8002ca2: d101 bne.n 8002ca8 8002ca4: 2301 movs r3, #1 8002ca6: e000 b.n 8002caa 8002ca8: 2300 movs r3, #0 } 8002caa: 4618 mov r0, r3 8002cac: 46bd mov sp, r7 8002cae: bc80 pop {r7} 8002cb0: 4770 bx lr 08002cb2 : { 8002cb2: b480 push {r7} 8002cb4: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); 8002cb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002cba: 681b ldr r3, [r3, #0] 8002cbc: f003 0308 and.w r3, r3, #8 8002cc0: 2b08 cmp r3, #8 8002cc2: d101 bne.n 8002cc8 8002cc4: 2301 movs r3, #1 8002cc6: e000 b.n 8002cca 8002cc8: 2300 movs r3, #0 } 8002cca: 4618 mov r0, r3 8002ccc: 46bd mov sp, r7 8002cce: bc80 pop {r7} 8002cd0: 4770 bx lr 08002cd2 : { 8002cd2: b480 push {r7} 8002cd4: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); 8002cd6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002cda: 681b ldr r3, [r3, #0] 8002cdc: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 8002ce0: 4618 mov r0, r3 8002ce2: 46bd mov sp, r7 8002ce4: bc80 pop {r7} 8002ce6: 4770 bx lr 08002ce8 : { 8002ce8: b480 push {r7} 8002cea: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); 8002cec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002cf0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002cf4: f403 6370 and.w r3, r3, #3840 @ 0xf00 } 8002cf8: 4618 mov r0, r3 8002cfa: 46bd mov sp, r7 8002cfc: bc80 pop {r7} 8002cfe: 4770 bx lr 08002d00 : { 8002d00: b480 push {r7} 8002d02: b083 sub sp, #12 8002d04: af00 add r7, sp, #0 8002d06: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); 8002d08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002d0c: 685b ldr r3, [r3, #4] 8002d0e: f423 427f bic.w r2, r3, #65280 @ 0xff00 8002d12: 687b ldr r3, [r7, #4] 8002d14: 021b lsls r3, r3, #8 8002d16: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002d1a: 4313 orrs r3, r2 8002d1c: 604b str r3, [r1, #4] } 8002d1e: bf00 nop 8002d20: 370c adds r7, #12 8002d22: 46bd mov sp, r7 8002d24: bc80 pop {r7} 8002d26: 4770 bx lr 08002d28 : { 8002d28: b480 push {r7} 8002d2a: b083 sub sp, #12 8002d2c: af00 add r7, sp, #0 8002d2e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 8002d30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002d34: 689b ldr r3, [r3, #8] 8002d36: f023 0203 bic.w r2, r3, #3 8002d3a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002d3e: 687b ldr r3, [r7, #4] 8002d40: 4313 orrs r3, r2 8002d42: 608b str r3, [r1, #8] } 8002d44: bf00 nop 8002d46: 370c adds r7, #12 8002d48: 46bd mov sp, r7 8002d4a: bc80 pop {r7} 8002d4c: 4770 bx lr 08002d4e : { 8002d4e: b480 push {r7} 8002d50: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 8002d52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002d56: 689b ldr r3, [r3, #8] 8002d58: f003 030c and.w r3, r3, #12 } 8002d5c: 4618 mov r0, r3 8002d5e: 46bd mov sp, r7 8002d60: bc80 pop {r7} 8002d62: 4770 bx lr 08002d64 : { 8002d64: b480 push {r7} 8002d66: b083 sub sp, #12 8002d68: af00 add r7, sp, #0 8002d6a: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 8002d6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002d70: 689b ldr r3, [r3, #8] 8002d72: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8002d76: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: 4313 orrs r3, r2 8002d7e: 608b str r3, [r1, #8] } 8002d80: bf00 nop 8002d82: 370c adds r7, #12 8002d84: 46bd mov sp, r7 8002d86: bc80 pop {r7} 8002d88: 4770 bx lr 08002d8a : { 8002d8a: b480 push {r7} 8002d8c: b083 sub sp, #12 8002d8e: af00 add r7, sp, #0 8002d90: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); 8002d92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002d96: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 8002d9a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8002d9e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002da2: 687b ldr r3, [r7, #4] 8002da4: 4313 orrs r3, r2 8002da6: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 8002daa: bf00 nop 8002dac: 370c adds r7, #12 8002dae: 46bd mov sp, r7 8002db0: bc80 pop {r7} 8002db2: 4770 bx lr 08002db4 : { 8002db4: b480 push {r7} 8002db6: b083 sub sp, #12 8002db8: af00 add r7, sp, #0 8002dba: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); 8002dbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002dc0: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 8002dc4: f023 020f bic.w r2, r3, #15 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 091b lsrs r3, r3, #4 8002dcc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002dd0: 4313 orrs r3, r2 8002dd2: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 8002dd6: bf00 nop 8002dd8: 370c adds r7, #12 8002dda: 46bd mov sp, r7 8002ddc: bc80 pop {r7} 8002dde: 4770 bx lr 08002de0 : { 8002de0: b480 push {r7} 8002de2: b083 sub sp, #12 8002de4: af00 add r7, sp, #0 8002de6: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 8002de8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002dec: 689b ldr r3, [r3, #8] 8002dee: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8002df2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002df6: 687b ldr r3, [r7, #4] 8002df8: 4313 orrs r3, r2 8002dfa: 608b str r3, [r1, #8] } 8002dfc: bf00 nop 8002dfe: 370c adds r7, #12 8002e00: 46bd mov sp, r7 8002e02: bc80 pop {r7} 8002e04: 4770 bx lr 08002e06 : { 8002e06: b480 push {r7} 8002e08: b083 sub sp, #12 8002e0a: af00 add r7, sp, #0 8002e0c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 8002e0e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e12: 689b ldr r3, [r3, #8] 8002e14: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8002e18: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002e1c: 687b ldr r3, [r7, #4] 8002e1e: 4313 orrs r3, r2 8002e20: 608b str r3, [r1, #8] } 8002e22: bf00 nop 8002e24: 370c adds r7, #12 8002e26: 46bd mov sp, r7 8002e28: bc80 pop {r7} 8002e2a: 4770 bx lr 08002e2c : { 8002e2c: b480 push {r7} 8002e2e: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 8002e30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e34: 689b ldr r3, [r3, #8] 8002e36: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 8002e3a: 4618 mov r0, r3 8002e3c: 46bd mov sp, r7 8002e3e: bc80 pop {r7} 8002e40: 4770 bx lr 08002e42 : { 8002e42: b480 push {r7} 8002e44: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); 8002e46: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e4a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 8002e4e: 011b lsls r3, r3, #4 8002e50: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 8002e54: 4618 mov r0, r3 8002e56: 46bd mov sp, r7 8002e58: bc80 pop {r7} 8002e5a: 4770 bx lr 08002e5c : { 8002e5c: b480 push {r7} 8002e5e: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 8002e60: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e64: 689b ldr r3, [r3, #8] 8002e66: f403 63e0 and.w r3, r3, #1792 @ 0x700 } 8002e6a: 4618 mov r0, r3 8002e6c: 46bd mov sp, r7 8002e6e: bc80 pop {r7} 8002e70: 4770 bx lr 08002e72 : { 8002e72: b480 push {r7} 8002e74: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 8002e76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e7a: 689b ldr r3, [r3, #8] 8002e7c: f403 5360 and.w r3, r3, #14336 @ 0x3800 } 8002e80: 4618 mov r0, r3 8002e82: 46bd mov sp, r7 8002e84: bc80 pop {r7} 8002e86: 4770 bx lr 08002e88 : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { 8002e88: b480 push {r7} 8002e8a: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); 8002e8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002e90: 681b ldr r3, [r3, #0] 8002e92: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002e96: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002e9a: 6013 str r3, [r2, #0] } 8002e9c: bf00 nop 8002e9e: 46bd mov sp, r7 8002ea0: bc80 pop {r7} 8002ea2: 4770 bx lr 08002ea4 : * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { 8002ea4: b480 push {r7} 8002ea6: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 8002ea8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002eac: 681b ldr r3, [r3, #0] 8002eae: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002eb2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8002eb6: 6013 str r3, [r2, #0] } 8002eb8: bf00 nop 8002eba: 46bd mov sp, r7 8002ebc: bc80 pop {r7} 8002ebe: 4770 bx lr 08002ec0 : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { 8002ec0: b480 push {r7} 8002ec2: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); 8002ec4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002ec8: 681b ldr r3, [r3, #0] 8002eca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002ece: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8002ed2: d101 bne.n 8002ed8 8002ed4: 2301 movs r3, #1 8002ed6: e000 b.n 8002eda 8002ed8: 2300 movs r3, #0 } 8002eda: 4618 mov r0, r3 8002edc: 46bd mov sp, r7 8002ede: bc80 pop {r7} 8002ee0: 4770 bx lr 08002ee2 : * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @retval Between 6 and 127 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) { 8002ee2: b480 push {r7} 8002ee4: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002ee6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002eea: 68db ldr r3, [r3, #12] 8002eec: 0a1b lsrs r3, r3, #8 8002eee: f003 037f and.w r3, r3, #127 @ 0x7f } 8002ef2: 4618 mov r0, r3 8002ef4: 46bd mov sp, r7 8002ef6: bc80 pop {r7} 8002ef8: 4770 bx lr 08002efa : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @arg @ref LL_RCC_PLLR_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) { 8002efa: b480 push {r7} 8002efc: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 8002efe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f02: 68db ldr r3, [r3, #12] 8002f04: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 } 8002f08: 4618 mov r0, r3 8002f0a: 46bd mov sp, r7 8002f0c: bc80 pop {r7} 8002f0e: 4770 bx lr 08002f10 : * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { 8002f10: b480 push {r7} 8002f12: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 8002f14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f18: 68db ldr r3, [r3, #12] 8002f1a: f003 0370 and.w r3, r3, #112 @ 0x70 } 8002f1e: 4618 mov r0, r3 8002f20: 46bd mov sp, r7 8002f22: bc80 pop {r7} 8002f24: 4770 bx lr 08002f26 : * @arg @ref LL_RCC_PLLSOURCE_MSI * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { 8002f26: b480 push {r7} 8002f28: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 8002f2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f2e: 68db ldr r3, [r3, #12] 8002f30: f003 0303 and.w r3, r3, #3 } 8002f34: 4618 mov r0, r3 8002f36: 46bd mov sp, r7 8002f38: bc80 pop {r7} 8002f3a: 4770 bx lr 08002f3c : * @brief Check if HCLK1 prescaler flag value has been applied or not * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) { 8002f3c: b480 push {r7} 8002f3e: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); 8002f40: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f44: 689b ldr r3, [r3, #8] 8002f46: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002f4a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8002f4e: d101 bne.n 8002f54 8002f50: 2301 movs r3, #1 8002f52: e000 b.n 8002f56 8002f54: 2300 movs r3, #0 } 8002f56: 4618 mov r0, r3 8002f58: 46bd mov sp, r7 8002f5a: bc80 pop {r7} 8002f5c: 4770 bx lr 08002f5e : * @brief Check if HCLK2 prescaler flag value has been applied or not * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) { 8002f5e: b480 push {r7} 8002f60: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); 8002f62: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f66: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 8002f6a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002f6e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8002f72: d101 bne.n 8002f78 8002f74: 2301 movs r3, #1 8002f76: e000 b.n 8002f7a 8002f78: 2300 movs r3, #0 } 8002f7a: 4618 mov r0, r3 8002f7c: 46bd mov sp, r7 8002f7e: bc80 pop {r7} 8002f80: 4770 bx lr 08002f82 : * @brief Check if HCLK3 prescaler flag value has been applied or not * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) { 8002f82: b480 push {r7} 8002f84: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); 8002f86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002f8a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 8002f8e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002f92: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8002f96: d101 bne.n 8002f9c 8002f98: 2301 movs r3, #1 8002f9a: e000 b.n 8002f9e 8002f9c: 2300 movs r3, #0 } 8002f9e: 4618 mov r0, r3 8002fa0: 46bd mov sp, r7 8002fa2: bc80 pop {r7} 8002fa4: 4770 bx lr 08002fa6 : * @brief Check if PLCK1 prescaler flag value has been applied or not * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) { 8002fa6: b480 push {r7} 8002fa8: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); 8002faa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002fae: 689b ldr r3, [r3, #8] 8002fb0: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002fb4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8002fb8: d101 bne.n 8002fbe 8002fba: 2301 movs r3, #1 8002fbc: e000 b.n 8002fc0 8002fbe: 2300 movs r3, #0 } 8002fc0: 4618 mov r0, r3 8002fc2: 46bd mov sp, r7 8002fc4: bc80 pop {r7} 8002fc6: 4770 bx lr 08002fc8 : * @brief Check if PLCK2 prescaler flag value has been applied or not * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) { 8002fc8: b480 push {r7} 8002fca: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); 8002fcc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002fd0: 689b ldr r3, [r3, #8] 8002fd2: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002fd6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002fda: d101 bne.n 8002fe0 8002fdc: 2301 movs r3, #1 8002fde: e000 b.n 8002fe2 8002fe0: 2300 movs r3, #0 } 8002fe2: 4618 mov r0, r3 8002fe4: 46bd mov sp, r7 8002fe6: bc80 pop {r7} 8002fe8: 4770 bx lr ... 08002fec : * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8002fec: b580 push {r7, lr} 8002fee: b088 sub sp, #32 8002ff0: af00 add r7, sp, #0 8002ff2: 6078 str r0, [r7, #4] uint32_t sysclk_source; uint32_t pll_config; HAL_StatusTypeDef status; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8002ff4: 687b ldr r3, [r7, #4] 8002ff6: 2b00 cmp r3, #0 8002ff8: d101 bne.n 8002ffe { return HAL_ERROR; 8002ffa: 2301 movs r3, #1 8002ffc: e36f b.n 80036de } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002ffe: f7ff fea6 bl 8002d4e 8003002: 61f8 str r0, [r7, #28] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003004: f7ff ff8f bl 8002f26 8003008: 61b8 str r0, [r7, #24] /*----------------------------- MSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 800300a: 687b ldr r3, [r7, #4] 800300c: 681b ldr r3, [r3, #0] 800300e: f003 0320 and.w r3, r3, #32 8003012: 2b00 cmp r3, #0 8003014: f000 80c4 beq.w 80031a0 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* When the MSI is used as system clock it will not be disabled */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || 8003018: 69fb ldr r3, [r7, #28] 800301a: 2b00 cmp r3, #0 800301c: d005 beq.n 800302a 800301e: 69fb ldr r3, [r7, #28] 8003020: 2b0c cmp r3, #12 8003022: d176 bne.n 8003112 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) 8003024: 69bb ldr r3, [r7, #24] 8003026: 2b01 cmp r3, #1 8003028: d173 bne.n 8003112 { if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800302a: 687b ldr r3, [r7, #4] 800302c: 6a1b ldr r3, [r3, #32] 800302e: 2b00 cmp r3, #0 8003030: d101 bne.n 8003036 { return HAL_ERROR; 8003032: 2301 movs r3, #1 8003034: e353 b.n 80036de else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the AHB3 clock and the supply voltage of the device. */ if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 8003036: 687b ldr r3, [r7, #4] 8003038: 6a9a ldr r2, [r3, #40] @ 0x28 800303a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800303e: 681b ldr r3, [r3, #0] 8003040: f003 0308 and.w r3, r3, #8 8003044: 2b00 cmp r3, #0 8003046: d005 beq.n 8003054 8003048: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800304c: 681b ldr r3, [r3, #0] 800304e: f003 03f0 and.w r3, r3, #240 @ 0xf0 8003052: e006 b.n 8003062 8003054: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003058: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800305c: 091b lsrs r3, r3, #4 800305e: f003 03f0 and.w r3, r3, #240 @ 0xf0 8003062: 4293 cmp r3, r2 8003064: d222 bcs.n 80030ac { /* First increase number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8003066: 687b ldr r3, [r7, #4] 8003068: 6a9b ldr r3, [r3, #40] @ 0x28 800306a: 4618 mov r0, r3 800306c: f000 fd5a bl 8003b24 8003070: 4603 mov r3, r0 8003072: 2b00 cmp r3, #0 8003074: d001 beq.n 800307a { return HAL_ERROR; 8003076: 2301 movs r3, #1 8003078: e331 b.n 80036de } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800307a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800307e: 681b ldr r3, [r3, #0] 8003080: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003084: f043 0308 orr.w r3, r3, #8 8003088: 6013 str r3, [r2, #0] 800308a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800308e: 681b ldr r3, [r3, #0] 8003090: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8003094: 687b ldr r3, [r7, #4] 8003096: 6a9b ldr r3, [r3, #40] @ 0x28 8003098: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800309c: 4313 orrs r3, r2 800309e: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 80030a0: 687b ldr r3, [r7, #4] 80030a2: 6a5b ldr r3, [r3, #36] @ 0x24 80030a4: 4618 mov r0, r3 80030a6: f7ff fe2b bl 8002d00 80030aa: e021 b.n 80030f0 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 80030ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80030b0: 681b ldr r3, [r3, #0] 80030b2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80030b6: f043 0308 orr.w r3, r3, #8 80030ba: 6013 str r3, [r2, #0] 80030bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80030c0: 681b ldr r3, [r3, #0] 80030c2: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80030c6: 687b ldr r3, [r7, #4] 80030c8: 6a9b ldr r3, [r3, #40] @ 0x28 80030ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80030ce: 4313 orrs r3, r2 80030d0: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 80030d2: 687b ldr r3, [r7, #4] 80030d4: 6a5b ldr r3, [r3, #36] @ 0x24 80030d6: 4618 mov r0, r3 80030d8: f7ff fe12 bl 8002d00 /* Decrease number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 80030dc: 687b ldr r3, [r7, #4] 80030de: 6a9b ldr r3, [r3, #40] @ 0x28 80030e0: 4618 mov r0, r3 80030e2: f000 fd1f bl 8003b24 80030e6: 4603 mov r3, r0 80030e8: 2b00 cmp r3, #0 80030ea: d001 beq.n 80030f0 { return HAL_ERROR; 80030ec: 2301 movs r3, #1 80030ee: e2f6 b.n 80036de } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 80030f0: f000 fce0 bl 8003ab4 80030f4: 4603 mov r3, r0 80030f6: 4aa7 ldr r2, [pc, #668] @ (8003394 ) 80030f8: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ status = HAL_InitTick(uwTickPrio); 80030fa: 4ba7 ldr r3, [pc, #668] @ (8003398 ) 80030fc: 681b ldr r3, [r3, #0] 80030fe: 4618 mov r0, r3 8003100: f7fd fd98 bl 8000c34 8003104: 4603 mov r3, r0 8003106: 74fb strb r3, [r7, #19] if (status != HAL_OK) 8003108: 7cfb ldrb r3, [r7, #19] 800310a: 2b00 cmp r3, #0 800310c: d047 beq.n 800319e { return status; 800310e: 7cfb ldrb r3, [r7, #19] 8003110: e2e5 b.n 80036de } } else { /* Check the MSI State */ if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 8003112: 687b ldr r3, [r7, #4] 8003114: 6a1b ldr r3, [r3, #32] 8003116: 2b00 cmp r3, #0 8003118: d02c beq.n 8003174 { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 800311a: f7ff fd9e bl 8002c5a /* Get timeout */ tickstart = HAL_GetTick(); 800311e: f7fd fd93 bl 8000c48 8003122: 6178 str r0, [r7, #20] /* Wait till MSI is ready */ while (LL_RCC_MSI_IsReady() == 0U) 8003124: e008 b.n 8003138 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8003126: f7fd fd8f bl 8000c48 800312a: 4602 mov r2, r0 800312c: 697b ldr r3, [r7, #20] 800312e: 1ad3 subs r3, r2, r3 8003130: 2b02 cmp r3, #2 8003132: d901 bls.n 8003138 { return HAL_TIMEOUT; 8003134: 2303 movs r3, #3 8003136: e2d2 b.n 80036de while (LL_RCC_MSI_IsReady() == 0U) 8003138: f7ff fdab bl 8002c92 800313c: 4603 mov r3, r0 800313e: 2b00 cmp r3, #0 8003140: d0f1 beq.n 8003126 } } /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8003142: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003146: 681b ldr r3, [r3, #0] 8003148: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800314c: f043 0308 orr.w r3, r3, #8 8003150: 6013 str r3, [r2, #0] 8003152: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003156: 681b ldr r3, [r3, #0] 8003158: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800315c: 687b ldr r3, [r7, #4] 800315e: 6a9b ldr r3, [r3, #40] @ 0x28 8003160: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003164: 4313 orrs r3, r2 8003166: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8003168: 687b ldr r3, [r7, #4] 800316a: 6a5b ldr r3, [r3, #36] @ 0x24 800316c: 4618 mov r0, r3 800316e: f7ff fdc7 bl 8002d00 8003172: e015 b.n 80031a0 } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 8003174: f7ff fd7f bl 8002c76 /* Get timeout */ tickstart = HAL_GetTick(); 8003178: f7fd fd66 bl 8000c48 800317c: 6178 str r0, [r7, #20] /* Wait till MSI is disabled */ while (LL_RCC_MSI_IsReady() != 0U) 800317e: e008 b.n 8003192 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8003180: f7fd fd62 bl 8000c48 8003184: 4602 mov r2, r0 8003186: 697b ldr r3, [r7, #20] 8003188: 1ad3 subs r3, r2, r3 800318a: 2b02 cmp r3, #2 800318c: d901 bls.n 8003192 { return HAL_TIMEOUT; 800318e: 2303 movs r3, #3 8003190: e2a5 b.n 80036de while (LL_RCC_MSI_IsReady() != 0U) 8003192: f7ff fd7e bl 8002c92 8003196: 4603 mov r3, r0 8003198: 2b00 cmp r3, #0 800319a: d1f1 bne.n 8003180 800319c: e000 b.n 80031a0 if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800319e: bf00 nop } } } /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80031a0: 687b ldr r3, [r7, #4] 80031a2: 681b ldr r3, [r3, #0] 80031a4: f003 0301 and.w r3, r3, #1 80031a8: 2b00 cmp r3, #0 80031aa: d058 beq.n 800325e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || 80031ac: 69fb ldr r3, [r7, #28] 80031ae: 2b08 cmp r3, #8 80031b0: d005 beq.n 80031be 80031b2: 69fb ldr r3, [r7, #28] 80031b4: 2b0c cmp r3, #12 80031b6: d108 bne.n 80031ca ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) 80031b8: 69bb ldr r3, [r7, #24] 80031ba: 2b03 cmp r3, #3 80031bc: d105 bne.n 80031ca { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) 80031be: 687b ldr r3, [r7, #4] 80031c0: 685b ldr r3, [r3, #4] 80031c2: 2b00 cmp r3, #0 80031c4: d14b bne.n 800325e { return HAL_ERROR; 80031c6: 2301 movs r3, #1 80031c8: e289 b.n 80036de /* Set the new HSE configuration ---------------------------------------*/ /* Check HSE division factor */ assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); /* Set HSE division factor */ MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); 80031ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80031ce: 681b ldr r3, [r3, #0] 80031d0: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80031d4: 687b ldr r3, [r7, #4] 80031d6: 689b ldr r3, [r3, #8] 80031d8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80031dc: 4313 orrs r3, r2 80031de: 600b str r3, [r1, #0] __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80031e0: 687b ldr r3, [r7, #4] 80031e2: 685b ldr r3, [r3, #4] 80031e4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80031e8: d102 bne.n 80031f0 80031ea: f7ff fc86 bl 8002afa 80031ee: e00d b.n 800320c 80031f0: 687b ldr r3, [r7, #4] 80031f2: 685b ldr r3, [r3, #4] 80031f4: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 80031f8: d104 bne.n 8003204 80031fa: f7ff fc51 bl 8002aa0 80031fe: f7ff fc7c bl 8002afa 8003202: e003 b.n 800320c 8003204: f7ff fc87 bl 8002b16 8003208: f7ff fc58 bl 8002abc /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800320c: 687b ldr r3, [r7, #4] 800320e: 685b ldr r3, [r3, #4] 8003210: 2b00 cmp r3, #0 8003212: d012 beq.n 800323a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003214: f7fd fd18 bl 8000c48 8003218: 6178 str r0, [r7, #20] /* Wait till HSE is ready */ while (LL_RCC_HSE_IsReady() == 0U) 800321a: e008 b.n 800322e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800321c: f7fd fd14 bl 8000c48 8003220: 4602 mov r2, r0 8003222: 697b ldr r3, [r7, #20] 8003224: 1ad3 subs r3, r2, r3 8003226: 2b64 cmp r3, #100 @ 0x64 8003228: d901 bls.n 800322e { return HAL_TIMEOUT; 800322a: 2303 movs r3, #3 800322c: e257 b.n 80036de while (LL_RCC_HSE_IsReady() == 0U) 800322e: f7ff fc80 bl 8002b32 8003232: 4603 mov r3, r0 8003234: 2b00 cmp r3, #0 8003236: d0f1 beq.n 800321c 8003238: e011 b.n 800325e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800323a: f7fd fd05 bl 8000c48 800323e: 6178 str r0, [r7, #20] /* Wait till HSE is disabled */ while (LL_RCC_HSE_IsReady() != 0U) 8003240: e008 b.n 8003254 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003242: f7fd fd01 bl 8000c48 8003246: 4602 mov r2, r0 8003248: 697b ldr r3, [r7, #20] 800324a: 1ad3 subs r3, r2, r3 800324c: 2b64 cmp r3, #100 @ 0x64 800324e: d901 bls.n 8003254 { return HAL_TIMEOUT; 8003250: 2303 movs r3, #3 8003252: e244 b.n 80036de while (LL_RCC_HSE_IsReady() != 0U) 8003254: f7ff fc6d bl 8002b32 8003258: 4603 mov r3, r0 800325a: 2b00 cmp r3, #0 800325c: d1f1 bne.n 8003242 } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800325e: 687b ldr r3, [r7, #4] 8003260: 681b ldr r3, [r3, #0] 8003262: f003 0302 and.w r3, r3, #2 8003266: 2b00 cmp r3, #0 8003268: d046 beq.n 80032f8 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || 800326a: 69fb ldr r3, [r7, #28] 800326c: 2b04 cmp r3, #4 800326e: d005 beq.n 800327c 8003270: 69fb ldr r3, [r7, #28] 8003272: 2b0c cmp r3, #12 8003274: d10e bne.n 8003294 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) 8003276: 69bb ldr r3, [r7, #24] 8003278: 2b02 cmp r3, #2 800327a: d10b bne.n 8003294 { /* When HSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 800327c: 687b ldr r3, [r7, #4] 800327e: 691b ldr r3, [r3, #16] 8003280: 2b00 cmp r3, #0 8003282: d101 bne.n 8003288 { return HAL_ERROR; 8003284: 2301 movs r3, #1 8003286: e22a b.n 80036de } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003288: 687b ldr r3, [r7, #4] 800328a: 695b ldr r3, [r3, #20] 800328c: 4618 mov r0, r3 800328e: f7ff fc8e bl 8002bae if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 8003292: e031 b.n 80032f8 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003294: 687b ldr r3, [r7, #4] 8003296: 691b ldr r3, [r3, #16] 8003298: 2b00 cmp r3, #0 800329a: d019 beq.n 80032d0 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800329c: f7ff fc5a bl 8002b54 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80032a0: f7fd fcd2 bl 8000c48 80032a4: 6178 str r0, [r7, #20] /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() == 0U) 80032a6: e008 b.n 80032ba { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80032a8: f7fd fcce bl 8000c48 80032ac: 4602 mov r2, r0 80032ae: 697b ldr r3, [r7, #20] 80032b0: 1ad3 subs r3, r2, r3 80032b2: 2b02 cmp r3, #2 80032b4: d901 bls.n 80032ba { return HAL_TIMEOUT; 80032b6: 2303 movs r3, #3 80032b8: e211 b.n 80036de while (LL_RCC_HSI_IsReady() == 0U) 80032ba: f7ff fc67 bl 8002b8c 80032be: 4603 mov r3, r0 80032c0: 2b00 cmp r3, #0 80032c2: d0f1 beq.n 80032a8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80032c4: 687b ldr r3, [r7, #4] 80032c6: 695b ldr r3, [r3, #20] 80032c8: 4618 mov r0, r3 80032ca: f7ff fc70 bl 8002bae 80032ce: e013 b.n 80032f8 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80032d0: f7ff fc4e bl 8002b70 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80032d4: f7fd fcb8 bl 8000c48 80032d8: 6178 str r0, [r7, #20] /* Wait till HSI is disabled */ while (LL_RCC_HSI_IsReady() != 0U) 80032da: e008 b.n 80032ee { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80032dc: f7fd fcb4 bl 8000c48 80032e0: 4602 mov r2, r0 80032e2: 697b ldr r3, [r7, #20] 80032e4: 1ad3 subs r3, r2, r3 80032e6: 2b02 cmp r3, #2 80032e8: d901 bls.n 80032ee { return HAL_TIMEOUT; 80032ea: 2303 movs r3, #3 80032ec: e1f7 b.n 80036de while (LL_RCC_HSI_IsReady() != 0U) 80032ee: f7ff fc4d bl 8002b8c 80032f2: 4603 mov r3, r0 80032f4: 2b00 cmp r3, #0 80032f6: d1f1 bne.n 80032dc } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80032f8: 687b ldr r3, [r7, #4] 80032fa: 681b ldr r3, [r3, #0] 80032fc: f003 0308 and.w r3, r3, #8 8003300: 2b00 cmp r3, #0 8003302: d06e beq.n 80033e2 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8003304: 687b ldr r3, [r7, #4] 8003306: 699b ldr r3, [r3, #24] 8003308: 2b00 cmp r3, #0 800330a: d056 beq.n 80033ba { uint32_t csr_temp = RCC->CSR; 800330c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003310: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8003314: 60fb str r3, [r7, #12] /* Check LSI division factor */ assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) 8003316: 687b ldr r3, [r7, #4] 8003318: 69da ldr r2, [r3, #28] 800331a: 68fb ldr r3, [r7, #12] 800331c: f003 0310 and.w r3, r3, #16 8003320: 429a cmp r2, r3 8003322: d031 beq.n 8003388 { if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ 8003324: 68fb ldr r3, [r7, #12] 8003326: f003 0302 and.w r3, r3, #2 800332a: 2b00 cmp r3, #0 800332c: d006 beq.n 800333c ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) 800332e: 68fb ldr r3, [r7, #12] 8003330: f003 0301 and.w r3, r3, #1 if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ 8003334: 2b00 cmp r3, #0 8003336: d101 bne.n 800333c { /* If LSIRDY is set while LSION is not enabled, LSIPRE can't be updated */ return HAL_ERROR; 8003338: 2301 movs r3, #1 800333a: e1d0 b.n 80036de } /* Turn off LSI before changing RCC_CSR_LSIPRE */ if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) 800333c: 68fb ldr r3, [r7, #12] 800333e: f003 0301 and.w r3, r3, #1 8003342: 2b00 cmp r3, #0 8003344: d013 beq.n 800336e { __HAL_RCC_LSI_DISABLE(); 8003346: f7ff fc67 bl 8002c18 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800334a: f7fd fc7d bl 8000c48 800334e: 6178 str r0, [r7, #20] /* Wait till LSI is disabled */ while (LL_RCC_LSI_IsReady() != 0U) 8003350: e008 b.n 8003364 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003352: f7fd fc79 bl 8000c48 8003356: 4602 mov r2, r0 8003358: 697b ldr r3, [r7, #20] 800335a: 1ad3 subs r3, r2, r3 800335c: 2b11 cmp r3, #17 800335e: d901 bls.n 8003364 { return HAL_TIMEOUT; 8003360: 2303 movs r3, #3 8003362: e1bc b.n 80036de while (LL_RCC_LSI_IsReady() != 0U) 8003364: f7ff fc68 bl 8002c38 8003368: 4603 mov r3, r0 800336a: 2b00 cmp r3, #0 800336c: d1f1 bne.n 8003352 } } } /* Set LSI division factor */ MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); 800336e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003372: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8003376: f023 0210 bic.w r2, r3, #16 800337a: 687b ldr r3, [r7, #4] 800337c: 69db ldr r3, [r3, #28] 800337e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003382: 4313 orrs r3, r2 8003384: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003388: f7ff fc36 bl 8002bf8 /* Get Start Tick */ tickstart = HAL_GetTick(); 800338c: f7fd fc5c bl 8000c48 8003390: 6178 str r0, [r7, #20] /* Wait till LSI is ready */ while (LL_RCC_LSI_IsReady() == 0U) 8003392: e00c b.n 80033ae 8003394: 20000000 .word 0x20000000 8003398: 20000004 .word 0x20000004 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800339c: f7fd fc54 bl 8000c48 80033a0: 4602 mov r2, r0 80033a2: 697b ldr r3, [r7, #20] 80033a4: 1ad3 subs r3, r2, r3 80033a6: 2b11 cmp r3, #17 80033a8: d901 bls.n 80033ae { return HAL_TIMEOUT; 80033aa: 2303 movs r3, #3 80033ac: e197 b.n 80036de while (LL_RCC_LSI_IsReady() == 0U) 80033ae: f7ff fc43 bl 8002c38 80033b2: 4603 mov r3, r0 80033b4: 2b00 cmp r3, #0 80033b6: d0f1 beq.n 800339c 80033b8: e013 b.n 80033e2 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80033ba: f7ff fc2d bl 8002c18 /* Get Start Tick */ tickstart = HAL_GetTick(); 80033be: f7fd fc43 bl 8000c48 80033c2: 6178 str r0, [r7, #20] /* Wait till LSI is disabled */ while (LL_RCC_LSI_IsReady() != 0U) 80033c4: e008 b.n 80033d8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80033c6: f7fd fc3f bl 8000c48 80033ca: 4602 mov r2, r0 80033cc: 697b ldr r3, [r7, #20] 80033ce: 1ad3 subs r3, r2, r3 80033d0: 2b11 cmp r3, #17 80033d2: d901 bls.n 80033d8 { return HAL_TIMEOUT; 80033d4: 2303 movs r3, #3 80033d6: e182 b.n 80036de while (LL_RCC_LSI_IsReady() != 0U) 80033d8: f7ff fc2e bl 8002c38 80033dc: 4603 mov r3, r0 80033de: 2b00 cmp r3, #0 80033e0: d1f1 bne.n 80033c6 } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80033e2: 687b ldr r3, [r7, #4] 80033e4: 681b ldr r3, [r3, #0] 80033e6: f003 0304 and.w r3, r3, #4 80033ea: 2b00 cmp r3, #0 80033ec: f000 80d8 beq.w 80035a0 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (LL_PWR_IsEnabledBkUpAccess() == 0U) 80033f0: f7ff fb44 bl 8002a7c 80033f4: 4603 mov r3, r0 80033f6: 2b00 cmp r3, #0 80033f8: d113 bne.n 8003422 { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 80033fa: f7ff fa83 bl 8002904 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80033fe: f7fd fc23 bl 8000c48 8003402: 6178 str r0, [r7, #20] while (LL_PWR_IsEnabledBkUpAccess() == 0U) 8003404: e008 b.n 8003418 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003406: f7fd fc1f bl 8000c48 800340a: 4602 mov r2, r0 800340c: 697b ldr r3, [r7, #20] 800340e: 1ad3 subs r3, r2, r3 8003410: 2b02 cmp r3, #2 8003412: d901 bls.n 8003418 { return HAL_TIMEOUT; 8003414: 2303 movs r3, #3 8003416: e162 b.n 80036de while (LL_PWR_IsEnabledBkUpAccess() == 0U) 8003418: f7ff fb30 bl 8002a7c 800341c: 4603 mov r3, r0 800341e: 2b00 cmp r3, #0 8003420: d0f1 beq.n 8003406 } } } /* Set the new LSE configuration -----------------------------------------*/ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003422: 687b ldr r3, [r7, #4] 8003424: 68db ldr r3, [r3, #12] 8003426: 2b00 cmp r3, #0 8003428: d07b beq.n 8003522 { /* Enable LSE bypasss (if requested) */ if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) 800342a: 687b ldr r3, [r7, #4] 800342c: 68db ldr r3, [r3, #12] 800342e: 2b85 cmp r3, #133 @ 0x85 8003430: d003 beq.n 800343a || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) 8003432: 687b ldr r3, [r7, #4] 8003434: 68db ldr r3, [r3, #12] 8003436: 2b05 cmp r3, #5 8003438: d109 bne.n 800344e { /* LSE oscillator bypass enable */ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 800343a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800343e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003442: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003446: f043 0304 orr.w r3, r3, #4 800344a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Get Start Tick */ tickstart = HAL_GetTick(); 800344e: f7fd fbfb bl 8000c48 8003452: 6178 str r0, [r7, #20] /* LSE oscillator enable */ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 8003454: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003458: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800345c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003460: f043 0301 orr.w r3, r3, #1 8003464: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() == 0U) 8003468: e00a b.n 8003480 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800346a: f7fd fbed bl 8000c48 800346e: 4602 mov r2, r0 8003470: 697b ldr r3, [r7, #20] 8003472: 1ad3 subs r3, r2, r3 8003474: f241 3288 movw r2, #5000 @ 0x1388 8003478: 4293 cmp r3, r2 800347a: d901 bls.n 8003480 { return HAL_TIMEOUT; 800347c: 2303 movs r3, #3 800347e: e12e b.n 80036de while (LL_RCC_LSE_IsReady() == 0U) 8003480: f7ff fba9 bl 8002bd6 8003484: 4603 mov r3, r0 8003486: 2b00 cmp r3, #0 8003488: d0ef beq.n 800346a } } /* Enable LSE system clock (if requested) */ if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) 800348a: 687b ldr r3, [r7, #4] 800348c: 68db ldr r3, [r3, #12] 800348e: 2b81 cmp r3, #129 @ 0x81 8003490: d003 beq.n 800349a || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) 8003492: 687b ldr r3, [r7, #4] 8003494: 68db ldr r3, [r3, #12] 8003496: 2b85 cmp r3, #133 @ 0x85 8003498: d121 bne.n 80034de { /* Get Start Tick */ tickstart = HAL_GetTick(); 800349a: f7fd fbd5 bl 8000c48 800349e: 6178 str r0, [r7, #20] SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); 80034a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80034a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80034a8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80034ac: f043 0380 orr.w r3, r3, #128 @ 0x80 80034b0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait till LSESYS is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) 80034b4: e00a b.n 80034cc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80034b6: f7fd fbc7 bl 8000c48 80034ba: 4602 mov r2, r0 80034bc: 697b ldr r3, [r7, #20] 80034be: 1ad3 subs r3, r2, r3 80034c0: f241 3288 movw r2, #5000 @ 0x1388 80034c4: 4293 cmp r3, r2 80034c6: d901 bls.n 80034cc { return HAL_TIMEOUT; 80034c8: 2303 movs r3, #3 80034ca: e108 b.n 80036de while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) 80034cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80034d0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80034d4: f403 6300 and.w r3, r3, #2048 @ 0x800 80034d8: 2b00 cmp r3, #0 80034da: d0ec beq.n 80034b6 if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) 80034dc: e060 b.n 80035a0 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80034de: f7fd fbb3 bl 8000c48 80034e2: 6178 str r0, [r7, #20] CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); 80034e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80034e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80034ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80034f0: f023 0380 bic.w r3, r3, #128 @ 0x80 80034f4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait till LSESYSRDY is cleared */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) 80034f8: e00a b.n 8003510 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80034fa: f7fd fba5 bl 8000c48 80034fe: 4602 mov r2, r0 8003500: 697b ldr r3, [r7, #20] 8003502: 1ad3 subs r3, r2, r3 8003504: f241 3288 movw r2, #5000 @ 0x1388 8003508: 4293 cmp r3, r2 800350a: d901 bls.n 8003510 { return HAL_TIMEOUT; 800350c: 2303 movs r3, #3 800350e: e0e6 b.n 80036de while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) 8003510: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003514: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003518: f403 6300 and.w r3, r3, #2048 @ 0x800 800351c: 2b00 cmp r3, #0 800351e: d1ec bne.n 80034fa 8003520: e03e b.n 80035a0 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003522: f7fd fb91 bl 8000c48 8003526: 6178 str r0, [r7, #20] CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); 8003528: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800352c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003530: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003534: f023 0380 bic.w r3, r3, #128 @ 0x80 8003538: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait till LSESYSRDY is cleared */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) 800353c: e00a b.n 8003554 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800353e: f7fd fb83 bl 8000c48 8003542: 4602 mov r2, r0 8003544: 697b ldr r3, [r7, #20] 8003546: 1ad3 subs r3, r2, r3 8003548: f241 3288 movw r2, #5000 @ 0x1388 800354c: 4293 cmp r3, r2 800354e: d901 bls.n 8003554 { return HAL_TIMEOUT; 8003550: 2303 movs r3, #3 8003552: e0c4 b.n 80036de while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) 8003554: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003558: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800355c: f403 6300 and.w r3, r3, #2048 @ 0x800 8003560: 2b00 cmp r3, #0 8003562: d1ec bne.n 800353e } } /* Get Start Tick */ tickstart = HAL_GetTick(); 8003564: f7fd fb70 bl 8000c48 8003568: 6178 str r0, [r7, #20] /* LSE oscillator disable */ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 800356a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800356e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003572: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003576: f023 0301 bic.w r3, r3, #1 800357a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait till LSE is disabled */ while (LL_RCC_LSE_IsReady() != 0U) 800357e: e00a b.n 8003596 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003580: f7fd fb62 bl 8000c48 8003584: 4602 mov r2, r0 8003586: 697b ldr r3, [r7, #20] 8003588: 1ad3 subs r3, r2, r3 800358a: f241 3288 movw r2, #5000 @ 0x1388 800358e: 4293 cmp r3, r2 8003590: d901 bls.n 8003596 { return HAL_TIMEOUT; 8003592: 2303 movs r3, #3 8003594: e0a3 b.n 80036de while (LL_RCC_LSE_IsReady() != 0U) 8003596: f7ff fb1e bl 8002bd6 800359a: 4603 mov r3, r0 800359c: 2b00 cmp r3, #0 800359e: d1ef bne.n 8003580 /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 80035a0: 687b ldr r3, [r7, #4] 80035a2: 6adb ldr r3, [r3, #44] @ 0x2c 80035a4: 2b00 cmp r3, #0 80035a6: f000 8099 beq.w 80036dc { /* Check if the PLL is used as system clock or not */ if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80035aa: 69fb ldr r3, [r7, #28] 80035ac: 2b0c cmp r3, #12 80035ae: d06c beq.n 800368a { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 80035b0: 687b ldr r3, [r7, #4] 80035b2: 6adb ldr r3, [r3, #44] @ 0x2c 80035b4: 2b02 cmp r3, #2 80035b6: d14b bne.n 8003650 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80035b8: f7ff fc74 bl 8002ea4 /* Get Start Tick */ tickstart = HAL_GetTick(); 80035bc: f7fd fb44 bl 8000c48 80035c0: 6178 str r0, [r7, #20] /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() != 0U) 80035c2: e008 b.n 80035d6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80035c4: f7fd fb40 bl 8000c48 80035c8: 4602 mov r2, r0 80035ca: 697b ldr r3, [r7, #20] 80035cc: 1ad3 subs r3, r2, r3 80035ce: 2b0a cmp r3, #10 80035d0: d901 bls.n 80035d6 { return HAL_TIMEOUT; 80035d2: 2303 movs r3, #3 80035d4: e083 b.n 80036de while (LL_RCC_PLL_IsReady() != 0U) 80035d6: f7ff fc73 bl 8002ec0 80035da: 4603 mov r3, r0 80035dc: 2b00 cmp r3, #0 80035de: d1f1 bne.n 80035c4 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80035e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80035e4: 68da ldr r2, [r3, #12] 80035e6: 4b40 ldr r3, [pc, #256] @ (80036e8 ) 80035e8: 4013 ands r3, r2 80035ea: 687a ldr r2, [r7, #4] 80035ec: 6b11 ldr r1, [r2, #48] @ 0x30 80035ee: 687a ldr r2, [r7, #4] 80035f0: 6b52 ldr r2, [r2, #52] @ 0x34 80035f2: 4311 orrs r1, r2 80035f4: 687a ldr r2, [r7, #4] 80035f6: 6b92 ldr r2, [r2, #56] @ 0x38 80035f8: 0212 lsls r2, r2, #8 80035fa: 4311 orrs r1, r2 80035fc: 687a ldr r2, [r7, #4] 80035fe: 6bd2 ldr r2, [r2, #60] @ 0x3c 8003600: 4311 orrs r1, r2 8003602: 687a ldr r2, [r7, #4] 8003604: 6c12 ldr r2, [r2, #64] @ 0x40 8003606: 4311 orrs r1, r2 8003608: 687a ldr r2, [r7, #4] 800360a: 6c52 ldr r2, [r2, #68] @ 0x44 800360c: 430a orrs r2, r1 800360e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003612: 4313 orrs r3, r2 8003614: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003616: f7ff fc37 bl 8002e88 /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800361a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800361e: 68db ldr r3, [r3, #12] 8003620: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003624: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003628: 60d3 str r3, [r2, #12] /* Get Start Tick */ tickstart = HAL_GetTick(); 800362a: f7fd fb0d bl 8000c48 800362e: 6178 str r0, [r7, #20] /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() == 0U) 8003630: e008 b.n 8003644 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003632: f7fd fb09 bl 8000c48 8003636: 4602 mov r2, r0 8003638: 697b ldr r3, [r7, #20] 800363a: 1ad3 subs r3, r2, r3 800363c: 2b0a cmp r3, #10 800363e: d901 bls.n 8003644 { return HAL_TIMEOUT; 8003640: 2303 movs r3, #3 8003642: e04c b.n 80036de while (LL_RCC_PLL_IsReady() == 0U) 8003644: f7ff fc3c bl 8002ec0 8003648: 4603 mov r3, r0 800364a: 2b00 cmp r3, #0 800364c: d0f1 beq.n 8003632 800364e: e045 b.n 80036dc } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003650: f7ff fc28 bl 8002ea4 /* Get Start Tick */ tickstart = HAL_GetTick(); 8003654: f7fd faf8 bl 8000c48 8003658: 6178 str r0, [r7, #20] /* Wait till PLL is disabled */ while (LL_RCC_PLL_IsReady() != 0U) 800365a: e008 b.n 800366e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800365c: f7fd faf4 bl 8000c48 8003660: 4602 mov r2, r0 8003662: 697b ldr r3, [r7, #20] 8003664: 1ad3 subs r3, r2, r3 8003666: 2b0a cmp r3, #10 8003668: d901 bls.n 800366e { return HAL_TIMEOUT; 800366a: 2303 movs r3, #3 800366c: e037 b.n 80036de while (LL_RCC_PLL_IsReady() != 0U) 800366e: f7ff fc27 bl 8002ec0 8003672: 4603 mov r3, r0 8003674: 2b00 cmp r3, #0 8003676: d1f1 bne.n 800365c } } /* Disable the PLL source and outputs to save power when PLL is off */ CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); 8003678: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800367c: 68da ldr r2, [r3, #12] 800367e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003682: 4b1a ldr r3, [pc, #104] @ (80036ec ) 8003684: 4013 ands r3, r2 8003686: 60cb str r3, [r1, #12] 8003688: e028 b.n 80036dc } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 800368a: 687b ldr r3, [r7, #4] 800368c: 6adb ldr r3, [r3, #44] @ 0x2c 800368e: 2b01 cmp r3, #1 8003690: d101 bne.n 8003696 { return HAL_ERROR; 8003692: 2301 movs r3, #1 8003694: e023 b.n 80036de } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8003696: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800369a: 68db ldr r3, [r3, #12] 800369c: 61bb str r3, [r7, #24] if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) 800369e: 69bb ldr r3, [r7, #24] 80036a0: f003 0203 and.w r2, r3, #3 80036a4: 687b ldr r3, [r7, #4] 80036a6: 6b1b ldr r3, [r3, #48] @ 0x30 80036a8: 429a cmp r2, r3 80036aa: d115 bne.n 80036d8 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) 80036ac: 69bb ldr r3, [r7, #24] 80036ae: f003 0270 and.w r2, r3, #112 @ 0x70 80036b2: 687b ldr r3, [r7, #4] 80036b4: 6b5b ldr r3, [r3, #52] @ 0x34 80036b6: 429a cmp r2, r3 80036b8: d10e bne.n 80036d8 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) 80036ba: 69bb ldr r3, [r7, #24] 80036bc: f403 42fe and.w r2, r3, #32512 @ 0x7f00 80036c0: 687b ldr r3, [r7, #4] 80036c2: 6b9b ldr r3, [r3, #56] @ 0x38 80036c4: 021b lsls r3, r3, #8 80036c6: 429a cmp r2, r3 80036c8: d106 bne.n 80036d8 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 80036ca: 69bb ldr r3, [r7, #24] 80036cc: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 80036d0: 687b ldr r3, [r7, #4] 80036d2: 6c5b ldr r3, [r3, #68] @ 0x44 80036d4: 429a cmp r2, r3 80036d6: d001 beq.n 80036dc { return HAL_ERROR; 80036d8: 2301 movs r3, #1 80036da: e000 b.n 80036de } } } } return HAL_OK; 80036dc: 2300 movs r3, #0 } 80036de: 4618 mov r0, r3 80036e0: 3720 adds r7, #32 80036e2: 46bd mov sp, r7 80036e4: bd80 pop {r7, pc} 80036e6: bf00 nop 80036e8: 11c1808c .word 0x11c1808c 80036ec: eefefffc .word 0xeefefffc 080036f0 : * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80036f0: b580 push {r7, lr} 80036f2: b084 sub sp, #16 80036f4: af00 add r7, sp, #0 80036f6: 6078 str r0, [r7, #4] 80036f8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80036fa: 687b ldr r3, [r7, #4] 80036fc: 2b00 cmp r3, #0 80036fe: d101 bne.n 8003704 { return HAL_ERROR; 8003700: 2301 movs r3, #1 8003702: e12c b.n 800395e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK3) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003704: 4b98 ldr r3, [pc, #608] @ (8003968 ) 8003706: 681b ldr r3, [r3, #0] 8003708: f003 0307 and.w r3, r3, #7 800370c: 683a ldr r2, [r7, #0] 800370e: 429a cmp r2, r3 8003710: d91b bls.n 800374a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003712: 4b95 ldr r3, [pc, #596] @ (8003968 ) 8003714: 681b ldr r3, [r3, #0] 8003716: f023 0207 bic.w r2, r3, #7 800371a: 4993 ldr r1, [pc, #588] @ (8003968 ) 800371c: 683b ldr r3, [r7, #0] 800371e: 4313 orrs r3, r2 8003720: 600b str r3, [r1, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003722: f7fd fa91 bl 8000c48 8003726: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 8003728: e008 b.n 800373c { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800372a: f7fd fa8d bl 8000c48 800372e: 4602 mov r2, r0 8003730: 68fb ldr r3, [r7, #12] 8003732: 1ad3 subs r3, r2, r3 8003734: 2b02 cmp r3, #2 8003736: d901 bls.n 800373c { return HAL_TIMEOUT; 8003738: 2303 movs r3, #3 800373a: e110 b.n 800395e while (__HAL_FLASH_GET_LATENCY() != FLatency) 800373c: 4b8a ldr r3, [pc, #552] @ (8003968 ) 800373e: 681b ldr r3, [r3, #0] 8003740: f003 0307 and.w r3, r3, #7 8003744: 683a ldr r2, [r7, #0] 8003746: 429a cmp r2, r3 8003748: d1ef bne.n 800372a } } } /*-------------------------- HCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800374a: 687b ldr r3, [r7, #4] 800374c: 681b ldr r3, [r3, #0] 800374e: f003 0302 and.w r3, r3, #2 8003752: 2b00 cmp r3, #0 8003754: d016 beq.n 8003784 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); 8003756: 687b ldr r3, [r7, #4] 8003758: 689b ldr r3, [r3, #8] 800375a: 4618 mov r0, r3 800375c: f7ff fb02 bl 8002d64 /* HCLK1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 8003760: f7fd fa72 bl 8000c48 8003764: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_HPRE() == 0U) 8003766: e008 b.n 800377a { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 8003768: f7fd fa6e bl 8000c48 800376c: 4602 mov r2, r0 800376e: 68fb ldr r3, [r7, #12] 8003770: 1ad3 subs r3, r2, r3 8003772: 2b02 cmp r3, #2 8003774: d901 bls.n 800377a { return HAL_TIMEOUT; 8003776: 2303 movs r3, #3 8003778: e0f1 b.n 800395e while (LL_RCC_IsActiveFlag_HPRE() == 0U) 800377a: f7ff fbdf bl 8002f3c 800377e: 4603 mov r3, r0 8003780: 2b00 cmp r3, #0 8003782: d0f1 beq.n 8003768 } } #if defined(DUAL_CORE) /*-------------------------- HCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) 8003784: 687b ldr r3, [r7, #4] 8003786: 681b ldr r3, [r3, #0] 8003788: f003 0320 and.w r3, r3, #32 800378c: 2b00 cmp r3, #0 800378e: d016 beq.n 80037be { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); 8003790: 687b ldr r3, [r7, #4] 8003792: 695b ldr r3, [r3, #20] 8003794: 4618 mov r0, r3 8003796: f7ff faf8 bl 8002d8a /* HCLK2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800379a: f7fd fa55 bl 8000c48 800379e: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 80037a0: e008 b.n 80037b4 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 80037a2: f7fd fa51 bl 8000c48 80037a6: 4602 mov r2, r0 80037a8: 68fb ldr r3, [r7, #12] 80037aa: 1ad3 subs r3, r2, r3 80037ac: 2b02 cmp r3, #2 80037ae: d901 bls.n 80037b4 { return HAL_TIMEOUT; 80037b0: 2303 movs r3, #3 80037b2: e0d4 b.n 800395e while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 80037b4: f7ff fbd3 bl 8002f5e 80037b8: 4603 mov r3, r0 80037ba: 2b00 cmp r3, #0 80037bc: d0f1 beq.n 80037a2 } } #endif /* DUAL_CORE */ /*-------------------------- HCLK3 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) 80037be: 687b ldr r3, [r7, #4] 80037c0: 681b ldr r3, [r3, #0] 80037c2: f003 0340 and.w r3, r3, #64 @ 0x40 80037c6: 2b00 cmp r3, #0 80037c8: d016 beq.n 80037f8 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); 80037ca: 687b ldr r3, [r7, #4] 80037cc: 699b ldr r3, [r3, #24] 80037ce: 4618 mov r0, r3 80037d0: f7ff faf0 bl 8002db4 /* AHB shared prescaler flag when value applied */ tickstart = HAL_GetTick(); 80037d4: f7fd fa38 bl 8000c48 80037d8: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 80037da: e008 b.n 80037ee { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 80037dc: f7fd fa34 bl 8000c48 80037e0: 4602 mov r2, r0 80037e2: 68fb ldr r3, [r7, #12] 80037e4: 1ad3 subs r3, r2, r3 80037e6: 2b02 cmp r3, #2 80037e8: d901 bls.n 80037ee { return HAL_TIMEOUT; 80037ea: 2303 movs r3, #3 80037ec: e0b7 b.n 800395e while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 80037ee: f7ff fbc8 bl 8002f82 80037f2: 4603 mov r3, r0 80037f4: 2b00 cmp r3, #0 80037f6: d0f1 beq.n 80037dc } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80037f8: 687b ldr r3, [r7, #4] 80037fa: 681b ldr r3, [r3, #0] 80037fc: f003 0304 and.w r3, r3, #4 8003800: 2b00 cmp r3, #0 8003802: d016 beq.n 8003832 { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); 8003804: 687b ldr r3, [r7, #4] 8003806: 68db ldr r3, [r3, #12] 8003808: 4618 mov r0, r3 800380a: f7ff fae9 bl 8002de0 /* APB1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800380e: f7fd fa1b bl 8000c48 8003812: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 8003814: e008 b.n 8003828 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 8003816: f7fd fa17 bl 8000c48 800381a: 4602 mov r2, r0 800381c: 68fb ldr r3, [r7, #12] 800381e: 1ad3 subs r3, r2, r3 8003820: 2b02 cmp r3, #2 8003822: d901 bls.n 8003828 { return HAL_TIMEOUT; 8003824: 2303 movs r3, #3 8003826: e09a b.n 800395e while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 8003828: f7ff fbbd bl 8002fa6 800382c: 4603 mov r3, r0 800382e: 2b00 cmp r3, #0 8003830: d0f1 beq.n 8003816 } } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003832: 687b ldr r3, [r7, #4] 8003834: 681b ldr r3, [r3, #0] 8003836: f003 0308 and.w r3, r3, #8 800383a: 2b00 cmp r3, #0 800383c: d017 beq.n 800386e { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); 800383e: 687b ldr r3, [r7, #4] 8003840: 691b ldr r3, [r3, #16] 8003842: 00db lsls r3, r3, #3 8003844: 4618 mov r0, r3 8003846: f7ff fade bl 8002e06 /* APB2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800384a: f7fd f9fd bl 8000c48 800384e: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 8003850: e008 b.n 8003864 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 8003852: f7fd f9f9 bl 8000c48 8003856: 4602 mov r2, r0 8003858: 68fb ldr r3, [r7, #12] 800385a: 1ad3 subs r3, r2, r3 800385c: 2b02 cmp r3, #2 800385e: d901 bls.n 8003864 { return HAL_TIMEOUT; 8003860: 2303 movs r3, #3 8003862: e07c b.n 800395e while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 8003864: f7ff fbb0 bl 8002fc8 8003868: 4603 mov r3, r0 800386a: 2b00 cmp r3, #0 800386c: d0f1 beq.n 8003852 } } } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800386e: 687b ldr r3, [r7, #4] 8003870: 681b ldr r3, [r3, #0] 8003872: f003 0301 and.w r3, r3, #1 8003876: 2b00 cmp r3, #0 8003878: d043 beq.n 8003902 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800387a: 687b ldr r3, [r7, #4] 800387c: 685b ldr r3, [r3, #4] 800387e: 2b02 cmp r3, #2 8003880: d106 bne.n 8003890 { /* Check the HSE ready flag */ if (LL_RCC_HSE_IsReady() == 0U) 8003882: f7ff f956 bl 8002b32 8003886: 4603 mov r3, r0 8003888: 2b00 cmp r3, #0 800388a: d11e bne.n 80038ca { return HAL_ERROR; 800388c: 2301 movs r3, #1 800388e: e066 b.n 800395e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003890: 687b ldr r3, [r7, #4] 8003892: 685b ldr r3, [r3, #4] 8003894: 2b03 cmp r3, #3 8003896: d106 bne.n 80038a6 { /* Check the PLL ready flag */ if (LL_RCC_PLL_IsReady() == 0U) 8003898: f7ff fb12 bl 8002ec0 800389c: 4603 mov r3, r0 800389e: 2b00 cmp r3, #0 80038a0: d113 bne.n 80038ca { return HAL_ERROR; 80038a2: 2301 movs r3, #1 80038a4: e05b b.n 800395e } } /* MSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 80038a6: 687b ldr r3, [r7, #4] 80038a8: 685b ldr r3, [r3, #4] 80038aa: 2b00 cmp r3, #0 80038ac: d106 bne.n 80038bc { /* Check the MSI ready flag */ if (LL_RCC_MSI_IsReady() == 0U) 80038ae: f7ff f9f0 bl 8002c92 80038b2: 4603 mov r3, r0 80038b4: 2b00 cmp r3, #0 80038b6: d108 bne.n 80038ca { return HAL_ERROR; 80038b8: 2301 movs r3, #1 80038ba: e050 b.n 800395e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (LL_RCC_HSI_IsReady() == 0U) 80038bc: f7ff f966 bl 8002b8c 80038c0: 4603 mov r3, r0 80038c2: 2b00 cmp r3, #0 80038c4: d101 bne.n 80038ca { return HAL_ERROR; 80038c6: 2301 movs r3, #1 80038c8: e049 b.n 800395e } } /* apply system clock switch */ LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); 80038ca: 687b ldr r3, [r7, #4] 80038cc: 685b ldr r3, [r3, #4] 80038ce: 4618 mov r0, r3 80038d0: f7ff fa2a bl 8002d28 /* Get Start Tick */ tickstart = HAL_GetTick(); 80038d4: f7fd f9b8 bl 8000c48 80038d8: 60f8 str r0, [r7, #12] /* check system clock source switch status */ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80038da: e00a b.n 80038f2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80038dc: f7fd f9b4 bl 8000c48 80038e0: 4602 mov r2, r0 80038e2: 68fb ldr r3, [r7, #12] 80038e4: 1ad3 subs r3, r2, r3 80038e6: f241 3288 movw r2, #5000 @ 0x1388 80038ea: 4293 cmp r3, r2 80038ec: d901 bls.n 80038f2 { return HAL_TIMEOUT; 80038ee: 2303 movs r3, #3 80038f0: e035 b.n 800395e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80038f2: f7ff fa2c bl 8002d4e 80038f6: 4602 mov r2, r0 80038f8: 687b ldr r3, [r7, #4] 80038fa: 685b ldr r3, [r3, #4] 80038fc: 009b lsls r3, r3, #2 80038fe: 429a cmp r2, r3 8003900: d1ec bne.n 80038dc } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003902: 4b19 ldr r3, [pc, #100] @ (8003968 ) 8003904: 681b ldr r3, [r3, #0] 8003906: f003 0307 and.w r3, r3, #7 800390a: 683a ldr r2, [r7, #0] 800390c: 429a cmp r2, r3 800390e: d21b bcs.n 8003948 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003910: 4b15 ldr r3, [pc, #84] @ (8003968 ) 8003912: 681b ldr r3, [r3, #0] 8003914: f023 0207 bic.w r2, r3, #7 8003918: 4913 ldr r1, [pc, #76] @ (8003968 ) 800391a: 683b ldr r3, [r7, #0] 800391c: 4313 orrs r3, r2 800391e: 600b str r3, [r1, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003920: f7fd f992 bl 8000c48 8003924: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 8003926: e008 b.n 800393a { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 8003928: f7fd f98e bl 8000c48 800392c: 4602 mov r2, r0 800392e: 68fb ldr r3, [r7, #12] 8003930: 1ad3 subs r3, r2, r3 8003932: 2b02 cmp r3, #2 8003934: d901 bls.n 800393a { return HAL_TIMEOUT; 8003936: 2303 movs r3, #3 8003938: e011 b.n 800395e while (__HAL_FLASH_GET_LATENCY() != FLatency) 800393a: 4b0b ldr r3, [pc, #44] @ (8003968 ) 800393c: 681b ldr r3, [r3, #0] 800393e: f003 0307 and.w r3, r3, #7 8003942: 683a ldr r2, [r7, #0] 8003944: 429a cmp r2, r3 8003946: d1ef bne.n 8003928 } /*--------------------------------------------------------------------------*/ /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 8003948: f000 f8b4 bl 8003ab4 800394c: 4603 mov r3, r0 800394e: 4a07 ldr r2, [pc, #28] @ (800396c ) 8003950: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ return HAL_InitTick(uwTickPrio); 8003952: 4b07 ldr r3, [pc, #28] @ (8003970 ) 8003954: 681b ldr r3, [r3, #0] 8003956: 4618 mov r0, r3 8003958: f7fd f96c bl 8000c34 800395c: 4603 mov r3, r0 } 800395e: 4618 mov r0, r3 8003960: 3710 adds r7, #16 8003962: 46bd mov sp, r7 8003964: bd80 pop {r7, pc} 8003966: bf00 nop 8003968: 58004000 .word 0x58004000 800396c: 20000000 .word 0x20000000 8003970: 20000004 .word 0x20000004 08003974 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003974: b590 push {r4, r7, lr} 8003976: b087 sub sp, #28 8003978: af00 add r7, sp, #0 uint32_t sysclk_source; uint32_t pllsource; uint32_t sysclockfreq = 0U; 800397a: 2300 movs r3, #0 800397c: 617b str r3, [r7, #20] uint32_t msifreq = 0U; 800397e: 2300 movs r3, #0 8003980: 613b str r3, [r7, #16] uint32_t pllinputfreq; sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003982: f7ff f9e4 bl 8002d4e 8003986: 60b8 str r0, [r7, #8] pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003988: f7ff facd bl 8002f26 800398c: 6078 str r0, [r7, #4] if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || 800398e: 68bb ldr r3, [r7, #8] 8003990: 2b00 cmp r3, #0 8003992: d005 beq.n 80039a0 8003994: 68bb ldr r3, [r7, #8] 8003996: 2b0c cmp r3, #12 8003998: d139 bne.n 8003a0e ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) 800399a: 687b ldr r3, [r7, #4] 800399c: 2b01 cmp r3, #1 800399e: d136 bne.n 8003a0e { /* MSI or PLL with MSI source used as system clock source */ /* Retrieve MSI frequency range in Hz */ msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 80039a0: f7ff f987 bl 8002cb2 80039a4: 4603 mov r3, r0 80039a6: 2b00 cmp r3, #0 80039a8: d115 bne.n 80039d6 80039aa: f7ff f982 bl 8002cb2 80039ae: 4603 mov r3, r0 80039b0: 2b01 cmp r3, #1 80039b2: d106 bne.n 80039c2 80039b4: f7ff f98d bl 8002cd2 80039b8: 4603 mov r3, r0 80039ba: 0a1b lsrs r3, r3, #8 80039bc: f003 030f and.w r3, r3, #15 80039c0: e005 b.n 80039ce 80039c2: f7ff f991 bl 8002ce8 80039c6: 4603 mov r3, r0 80039c8: 0a1b lsrs r3, r3, #8 80039ca: f003 030f and.w r3, r3, #15 80039ce: 4a36 ldr r2, [pc, #216] @ (8003aa8 ) 80039d0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80039d4: e014 b.n 8003a00 80039d6: f7ff f96c bl 8002cb2 80039da: 4603 mov r3, r0 80039dc: 2b01 cmp r3, #1 80039de: d106 bne.n 80039ee 80039e0: f7ff f977 bl 8002cd2 80039e4: 4603 mov r3, r0 80039e6: 091b lsrs r3, r3, #4 80039e8: f003 030f and.w r3, r3, #15 80039ec: e005 b.n 80039fa 80039ee: f7ff f97b bl 8002ce8 80039f2: 4603 mov r3, r0 80039f4: 091b lsrs r3, r3, #4 80039f6: f003 030f and.w r3, r3, #15 80039fa: 4a2b ldr r2, [pc, #172] @ (8003aa8 ) 80039fc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003a00: 613b str r3, [r7, #16] ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); /* Get SYSCLK source */ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) 8003a02: 68bb ldr r3, [r7, #8] 8003a04: 2b00 cmp r3, #0 8003a06: d115 bne.n 8003a34 { /* MSI used as system clock source */ sysclockfreq = msifreq; 8003a08: 693b ldr r3, [r7, #16] 8003a0a: 617b str r3, [r7, #20] if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) 8003a0c: e012 b.n 8003a34 } } else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) 8003a0e: 68bb ldr r3, [r7, #8] 8003a10: 2b04 cmp r3, #4 8003a12: d102 bne.n 8003a1a { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 8003a14: 4b25 ldr r3, [pc, #148] @ (8003aac ) 8003a16: 617b str r3, [r7, #20] 8003a18: e00c b.n 8003a34 } else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) 8003a1a: 68bb ldr r3, [r7, #8] 8003a1c: 2b08 cmp r3, #8 8003a1e: d109 bne.n 8003a34 { /* HSE used as system clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 8003a20: f7ff f85a bl 8002ad8 8003a24: 4603 mov r3, r0 8003a26: 2b01 cmp r3, #1 8003a28: d102 bne.n 8003a30 { sysclockfreq = HSE_VALUE / 2U; 8003a2a: 4b20 ldr r3, [pc, #128] @ (8003aac ) 8003a2c: 617b str r3, [r7, #20] 8003a2e: e001 b.n 8003a34 } else { sysclockfreq = HSE_VALUE; 8003a30: 4b1f ldr r3, [pc, #124] @ (8003ab0 ) 8003a32: 617b str r3, [r7, #20] else { /* Nothing to do */ } if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003a34: f7ff f98b bl 8002d4e 8003a38: 4603 mov r3, r0 8003a3a: 2b0c cmp r3, #12 8003a3c: d12f bne.n 8003a9e { /* PLL used as system clock source */ pllsource = LL_RCC_PLL_GetMainSource(); 8003a3e: f7ff fa72 bl 8002f26 8003a42: 6078 str r0, [r7, #4] switch (pllsource) 8003a44: 687b ldr r3, [r7, #4] 8003a46: 2b02 cmp r3, #2 8003a48: d003 beq.n 8003a52 8003a4a: 687b ldr r3, [r7, #4] 8003a4c: 2b03 cmp r3, #3 8003a4e: d003 beq.n 8003a58 8003a50: e00d b.n 8003a6e { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; 8003a52: 4b16 ldr r3, [pc, #88] @ (8003aac ) 8003a54: 60fb str r3, [r7, #12] break; 8003a56: e00d b.n 8003a74 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 8003a58: f7ff f83e bl 8002ad8 8003a5c: 4603 mov r3, r0 8003a5e: 2b01 cmp r3, #1 8003a60: d102 bne.n 8003a68 { pllinputfreq = HSE_VALUE / 2U; 8003a62: 4b12 ldr r3, [pc, #72] @ (8003aac ) 8003a64: 60fb str r3, [r7, #12] } else { pllinputfreq = HSE_VALUE; } break; 8003a66: e005 b.n 8003a74 pllinputfreq = HSE_VALUE; 8003a68: 4b11 ldr r3, [pc, #68] @ (8003ab0 ) 8003a6a: 60fb str r3, [r7, #12] break; 8003a6c: e002 b.n 8003a74 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllinputfreq = msifreq; 8003a6e: 693b ldr r3, [r7, #16] 8003a70: 60fb str r3, [r7, #12] break; 8003a72: bf00 nop } sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 8003a74: f7ff fa35 bl 8002ee2 8003a78: 4602 mov r2, r0 8003a7a: 68fb ldr r3, [r7, #12] 8003a7c: fb03 f402 mul.w r4, r3, r2 8003a80: f7ff fa46 bl 8002f10 8003a84: 4603 mov r3, r0 8003a86: 091b lsrs r3, r3, #4 8003a88: 3301 adds r3, #1 8003a8a: fbb4 f4f3 udiv r4, r4, r3 8003a8e: f7ff fa34 bl 8002efa 8003a92: 4603 mov r3, r0 8003a94: 0f5b lsrs r3, r3, #29 8003a96: 3301 adds r3, #1 8003a98: fbb4 f3f3 udiv r3, r4, r3 8003a9c: 617b str r3, [r7, #20] LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); } return sysclockfreq; 8003a9e: 697b ldr r3, [r7, #20] } 8003aa0: 4618 mov r0, r3 8003aa2: 371c adds r7, #28 8003aa4: 46bd mov sp, r7 8003aa6: bd90 pop {r4, r7, pc} 8003aa8: 0800fac4 .word 0x0800fac4 8003aac: 00f42400 .word 0x00f42400 8003ab0: 01e84800 .word 0x01e84800 08003ab4 : /** * @brief Return the HCLK frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003ab4: b598 push {r3, r4, r7, lr} 8003ab6: af00 add r7, sp, #0 /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); 8003ab8: f7ff ff5c bl 8003974 8003abc: 4604 mov r4, r0 8003abe: f7ff f9b5 bl 8002e2c 8003ac2: 4603 mov r3, r0 8003ac4: 091b lsrs r3, r3, #4 8003ac6: f003 030f and.w r3, r3, #15 8003aca: 4a03 ldr r2, [pc, #12] @ (8003ad8 ) 8003acc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003ad0: fbb4 f3f3 udiv r3, r4, r3 } 8003ad4: 4618 mov r0, r3 8003ad6: bd98 pop {r3, r4, r7, pc} 8003ad8: 0800fa64 .word 0x0800fa64 08003adc : /** * @brief Return the PCLK1 frequency. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003adc: b598 push {r3, r4, r7, lr} 8003ade: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); 8003ae0: f7ff ffe8 bl 8003ab4 8003ae4: 4604 mov r4, r0 8003ae6: f7ff f9b9 bl 8002e5c 8003aea: 4603 mov r3, r0 8003aec: 0a1b lsrs r3, r3, #8 8003aee: 4a03 ldr r2, [pc, #12] @ (8003afc ) 8003af0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003af4: fa24 f303 lsr.w r3, r4, r3 } 8003af8: 4618 mov r0, r3 8003afa: bd98 pop {r3, r4, r7, pc} 8003afc: 0800faa4 .word 0x0800faa4 08003b00 : /** * @brief Return the PCLK2 frequency. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003b00: b598 push {r3, r4, r7, lr} 8003b02: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); 8003b04: f7ff ffd6 bl 8003ab4 8003b08: 4604 mov r4, r0 8003b0a: f7ff f9b2 bl 8002e72 8003b0e: 4603 mov r3, r0 8003b10: 0adb lsrs r3, r3, #11 8003b12: 4a03 ldr r2, [pc, #12] @ (8003b20 ) 8003b14: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003b18: fa24 f303 lsr.w r3, r4, r3 } 8003b1c: 4618 mov r0, r3 8003b1e: bd98 pop {r3, r4, r7, pc} 8003b20: 0800faa4 .word 0x0800faa4 08003b24 : voltage range. * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) { 8003b24: b590 push {r4, r7, lr} 8003b26: b085 sub sp, #20 8003b28: af00 add r7, sp, #0 8003b2a: 6078 str r0, [r7, #4] uint32_t flash_clksrcfreq; uint32_t msifreq; /* MSI frequency range in Hz */ msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 091b lsrs r3, r3, #4 8003b30: f003 030f and.w r3, r3, #15 8003b34: 4a10 ldr r2, [pc, #64] @ (8003b78 ) 8003b36: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003b3a: 60fb str r3, [r7, #12] flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); 8003b3c: f7ff f981 bl 8002e42 8003b40: 4603 mov r3, r0 8003b42: 091b lsrs r3, r3, #4 8003b44: f003 030f and.w r3, r3, #15 8003b48: 4a0c ldr r2, [pc, #48] @ (8003b7c ) 8003b4a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003b4e: 68fa ldr r2, [r7, #12] 8003b50: fbb2 f3f3 udiv r3, r2, r3 8003b54: 60bb str r3, [r7, #8] return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); 8003b56: 68bb ldr r3, [r7, #8] 8003b58: 4a09 ldr r2, [pc, #36] @ (8003b80 ) 8003b5a: fba2 2303 umull r2, r3, r2, r3 8003b5e: 0c9c lsrs r4, r3, #18 8003b60: f7fe ff12 bl 8002988 8003b64: 4603 mov r3, r0 8003b66: 4619 mov r1, r3 8003b68: 4620 mov r0, r4 8003b6a: f000 f80b bl 8003b84 8003b6e: 4603 mov r3, r0 } 8003b70: 4618 mov r0, r3 8003b72: 3714 adds r7, #20 8003b74: 46bd mov sp, r7 8003b76: bd90 pop {r4, r7, pc} 8003b78: 0800fac4 .word 0x0800fac4 8003b7c: 0800fa64 .word 0x0800fa64 8003b80: 431bde83 .word 0x431bde83 08003b84 : * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) { 8003b84: b580 push {r7, lr} 8003b86: b08e sub sp, #56 @ 0x38 8003b88: af00 add r7, sp, #0 8003b8a: 6078 str r0, [r7, #4] 8003b8c: 6039 str r1, [r7, #0] /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; 8003b8e: 4a3a ldr r2, [pc, #232] @ (8003c78 ) 8003b90: f107 0320 add.w r3, r7, #32 8003b94: e892 0003 ldmia.w r2, {r0, r1} 8003b98: 6018 str r0, [r3, #0] 8003b9a: 3304 adds r3, #4 8003b9c: 8019 strh r1, [r3, #0] /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; 8003b9e: 4a37 ldr r2, [pc, #220] @ (8003c7c ) 8003ba0: f107 0318 add.w r3, r7, #24 8003ba4: e892 0003 ldmia.w r2, {r0, r1} 8003ba8: 6018 str r0, [r3, #0] 8003baa: 3304 adds r3, #4 8003bac: 8019 strh r1, [r3, #0] /* Flash Latency range */ const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; 8003bae: 4a34 ldr r2, [pc, #208] @ (8003c80 ) 8003bb0: f107 030c add.w r3, r7, #12 8003bb4: ca07 ldmia r2, {r0, r1, r2} 8003bb6: e883 0007 stmia.w r3, {r0, r1, r2} uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 8003bba: 2300 movs r3, #0 8003bbc: 637b str r3, [r7, #52] @ 0x34 uint32_t tickstart; if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) 8003bbe: 683b ldr r3, [r7, #0] 8003bc0: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003bc4: d11b bne.n 8003bfe { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 8003bc6: 2300 movs r3, #0 8003bc8: 633b str r3, [r7, #48] @ 0x30 8003bca: e014 b.n 8003bf6 { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) 8003bcc: 6b3b ldr r3, [r7, #48] @ 0x30 8003bce: 005b lsls r3, r3, #1 8003bd0: 3338 adds r3, #56 @ 0x38 8003bd2: 443b add r3, r7 8003bd4: f833 3c18 ldrh.w r3, [r3, #-24] 8003bd8: 461a mov r2, r3 8003bda: 687b ldr r3, [r7, #4] 8003bdc: 4293 cmp r3, r2 8003bde: d807 bhi.n 8003bf0 { latency = FLASH_LATENCY_RANGE[index]; 8003be0: 6b3b ldr r3, [r7, #48] @ 0x30 8003be2: 009b lsls r3, r3, #2 8003be4: 3338 adds r3, #56 @ 0x38 8003be6: 443b add r3, r7 8003be8: f853 3c2c ldr.w r3, [r3, #-44] 8003bec: 637b str r3, [r7, #52] @ 0x34 break; 8003bee: e021 b.n 8003c34 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 8003bf0: 6b3b ldr r3, [r7, #48] @ 0x30 8003bf2: 3301 adds r3, #1 8003bf4: 633b str r3, [r7, #48] @ 0x30 8003bf6: 6b3b ldr r3, [r7, #48] @ 0x30 8003bf8: 2b02 cmp r3, #2 8003bfa: d9e7 bls.n 8003bcc 8003bfc: e01a b.n 8003c34 } } } else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 8003bfe: 2300 movs r3, #0 8003c00: 62fb str r3, [r7, #44] @ 0x2c 8003c02: e014 b.n 8003c2e { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) 8003c04: 6afb ldr r3, [r7, #44] @ 0x2c 8003c06: 005b lsls r3, r3, #1 8003c08: 3338 adds r3, #56 @ 0x38 8003c0a: 443b add r3, r7 8003c0c: f833 3c20 ldrh.w r3, [r3, #-32] 8003c10: 461a mov r2, r3 8003c12: 687b ldr r3, [r7, #4] 8003c14: 4293 cmp r3, r2 8003c16: d807 bhi.n 8003c28 { latency = FLASH_LATENCY_RANGE[index]; 8003c18: 6afb ldr r3, [r7, #44] @ 0x2c 8003c1a: 009b lsls r3, r3, #2 8003c1c: 3338 adds r3, #56 @ 0x38 8003c1e: 443b add r3, r7 8003c20: f853 3c2c ldr.w r3, [r3, #-44] 8003c24: 637b str r3, [r7, #52] @ 0x34 break; 8003c26: e005 b.n 8003c34 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 8003c28: 6afb ldr r3, [r7, #44] @ 0x2c 8003c2a: 3301 adds r3, #1 8003c2c: 62fb str r3, [r7, #44] @ 0x2c 8003c2e: 6afb ldr r3, [r7, #44] @ 0x2c 8003c30: 2b02 cmp r3, #2 8003c32: d9e7 bls.n 8003c04 } } } __HAL_FLASH_SET_LATENCY(latency); 8003c34: 4b13 ldr r3, [pc, #76] @ (8003c84 ) 8003c36: 681b ldr r3, [r3, #0] 8003c38: f023 0207 bic.w r2, r3, #7 8003c3c: 4911 ldr r1, [pc, #68] @ (8003c84 ) 8003c3e: 6b7b ldr r3, [r7, #52] @ 0x34 8003c40: 4313 orrs r3, r2 8003c42: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003c44: f7fd f800 bl 8000c48 8003c48: 62b8 str r0, [r7, #40] @ 0x28 /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != latency) 8003c4a: e008 b.n 8003c5e { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 8003c4c: f7fc fffc bl 8000c48 8003c50: 4602 mov r2, r0 8003c52: 6abb ldr r3, [r7, #40] @ 0x28 8003c54: 1ad3 subs r3, r2, r3 8003c56: 2b02 cmp r3, #2 8003c58: d901 bls.n 8003c5e { return HAL_TIMEOUT; 8003c5a: 2303 movs r3, #3 8003c5c: e007 b.n 8003c6e while (__HAL_FLASH_GET_LATENCY() != latency) 8003c5e: 4b09 ldr r3, [pc, #36] @ (8003c84 ) 8003c60: 681b ldr r3, [r3, #0] 8003c62: f003 0307 and.w r3, r3, #7 8003c66: 6b7a ldr r2, [r7, #52] @ 0x34 8003c68: 429a cmp r2, r3 8003c6a: d1ef bne.n 8003c4c } } return HAL_OK; 8003c6c: 2300 movs r3, #0 } 8003c6e: 4618 mov r0, r3 8003c70: 3738 adds r7, #56 @ 0x38 8003c72: 46bd mov sp, r7 8003c74: bd80 pop {r7, pc} 8003c76: bf00 nop 8003c78: 0800f0cc .word 0x0800f0cc 8003c7c: 0800f0d4 .word 0x0800f0d4 8003c80: 0800f0dc .word 0x0800f0dc 8003c84: 58004000 .word 0x58004000 08003c88 : { 8003c88: b480 push {r7} 8003c8a: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 8003c8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003c90: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003c94: f003 0302 and.w r3, r3, #2 8003c98: 2b02 cmp r3, #2 8003c9a: d101 bne.n 8003ca0 8003c9c: 2301 movs r3, #1 8003c9e: e000 b.n 8003ca2 8003ca0: 2300 movs r3, #0 } 8003ca2: 4618 mov r0, r3 8003ca4: 46bd mov sp, r7 8003ca6: bc80 pop {r7} 8003ca8: 4770 bx lr 08003caa : { 8003caa: b480 push {r7} 8003cac: b083 sub sp, #12 8003cae: af00 add r7, sp, #0 8003cb0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); 8003cb2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003cb6: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8003cba: 687b ldr r3, [r7, #4] 8003cbc: 0c1b lsrs r3, r3, #16 8003cbe: 43db mvns r3, r3 8003cc0: 401a ands r2, r3 8003cc2: 687b ldr r3, [r7, #4] 8003cc4: b29b uxth r3, r3 8003cc6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003cca: 4313 orrs r3, r2 8003ccc: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003cd0: bf00 nop 8003cd2: 370c adds r7, #12 8003cd4: 46bd mov sp, r7 8003cd6: bc80 pop {r7} 8003cd8: 4770 bx lr 08003cda : { 8003cda: b480 push {r7} 8003cdc: b083 sub sp, #12 8003cde: af00 add r7, sp, #0 8003ce0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); 8003ce2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003ce6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003cea: f423 7240 bic.w r2, r3, #768 @ 0x300 8003cee: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003cf2: 687b ldr r3, [r7, #4] 8003cf4: 4313 orrs r3, r2 8003cf6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003cfa: bf00 nop 8003cfc: 370c adds r7, #12 8003cfe: 46bd mov sp, r7 8003d00: bc80 pop {r7} 8003d02: 4770 bx lr 08003d04 : { 8003d04: b480 push {r7} 8003d06: b083 sub sp, #12 8003d08: af00 add r7, sp, #0 8003d0a: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 8003d0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003d10: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003d14: f423 6240 bic.w r2, r3, #3072 @ 0xc00 8003d18: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003d1c: 687b ldr r3, [r7, #4] 8003d1e: 4313 orrs r3, r2 8003d20: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003d24: bf00 nop 8003d26: 370c adds r7, #12 8003d28: 46bd mov sp, r7 8003d2a: bc80 pop {r7} 8003d2c: 4770 bx lr 08003d2e : { 8003d2e: b480 push {r7} 8003d30: b083 sub sp, #12 8003d32: af00 add r7, sp, #0 8003d34: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); 8003d36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003d3a: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8003d3e: 687b ldr r3, [r7, #4] 8003d40: 091b lsrs r3, r3, #4 8003d42: f403 237f and.w r3, r3, #1044480 @ 0xff000 8003d46: 43db mvns r3, r3 8003d48: 401a ands r2, r3 8003d4a: 687b ldr r3, [r7, #4] 8003d4c: 011b lsls r3, r3, #4 8003d4e: f403 237f and.w r3, r3, #1044480 @ 0xff000 8003d52: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003d56: 4313 orrs r3, r2 8003d58: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003d5c: bf00 nop 8003d5e: 370c adds r7, #12 8003d60: 46bd mov sp, r7 8003d62: bc80 pop {r7} 8003d64: 4770 bx lr 08003d66 : { 8003d66: b480 push {r7} 8003d68: b083 sub sp, #12 8003d6a: af00 add r7, sp, #0 8003d6c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); 8003d6e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003d72: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8003d76: 687b ldr r3, [r7, #4] 8003d78: 0c1b lsrs r3, r3, #16 8003d7a: 041b lsls r3, r3, #16 8003d7c: 43db mvns r3, r3 8003d7e: 401a ands r2, r3 8003d80: 687b ldr r3, [r7, #4] 8003d82: 041b lsls r3, r3, #16 8003d84: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003d88: 4313 orrs r3, r2 8003d8a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003d8e: bf00 nop 8003d90: 370c adds r7, #12 8003d92: 46bd mov sp, r7 8003d94: bc80 pop {r7} 8003d96: 4770 bx lr 08003d98 : { 8003d98: b480 push {r7} 8003d9a: b083 sub sp, #12 8003d9c: af00 add r7, sp, #0 8003d9e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); 8003da0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003da4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003da8: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 8003dac: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003db0: 687b ldr r3, [r7, #4] 8003db2: 4313 orrs r3, r2 8003db4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003db8: bf00 nop 8003dba: 370c adds r7, #12 8003dbc: 46bd mov sp, r7 8003dbe: bc80 pop {r7} 8003dc0: 4770 bx lr 08003dc2 : { 8003dc2: b480 push {r7} 8003dc4: b083 sub sp, #12 8003dc6: af00 add r7, sp, #0 8003dc8: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 8003dca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003dce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003dd2: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8003dd6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003dda: 687b ldr r3, [r7, #4] 8003ddc: 4313 orrs r3, r2 8003dde: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 8003de2: bf00 nop 8003de4: 370c adds r7, #12 8003de6: 46bd mov sp, r7 8003de8: bc80 pop {r7} 8003dea: 4770 bx lr 08003dec : { 8003dec: b480 push {r7} 8003dee: b083 sub sp, #12 8003df0: af00 add r7, sp, #0 8003df2: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 8003df4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003df8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003dfc: f423 7240 bic.w r2, r3, #768 @ 0x300 8003e00: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8003e04: 687b ldr r3, [r7, #4] 8003e06: 4313 orrs r3, r2 8003e08: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 8003e0c: bf00 nop 8003e0e: 370c adds r7, #12 8003e10: 46bd mov sp, r7 8003e12: bc80 pop {r7} 8003e14: 4770 bx lr 08003e16 : { 8003e16: b480 push {r7} 8003e18: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 8003e1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003e1e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003e22: f403 7340 and.w r3, r3, #768 @ 0x300 } 8003e26: 4618 mov r0, r3 8003e28: 46bd mov sp, r7 8003e2a: bc80 pop {r7} 8003e2c: 4770 bx lr 08003e2e : { 8003e2e: b480 push {r7} 8003e30: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 8003e32: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003e36: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003e3a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003e3e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003e42: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 8003e46: bf00 nop 8003e48: 46bd mov sp, r7 8003e4a: bc80 pop {r7} 8003e4c: 4770 bx lr 08003e4e : { 8003e4e: b480 push {r7} 8003e50: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 8003e52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003e56: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003e5a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003e5e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003e62: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 8003e66: bf00 nop 8003e68: 46bd mov sp, r7 8003e6a: bc80 pop {r7} 8003e6c: 4770 bx lr ... 08003e70 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003e70: b580 push {r7, lr} 8003e72: b086 sub sp, #24 8003e74: af00 add r7, sp, #0 8003e76: 6078 str r0, [r7, #4] uint32_t tmpregister = 0; 8003e78: 2300 movs r3, #0 8003e7a: 617b str r3, [r7, #20] uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003e7c: 2300 movs r3, #0 8003e7e: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003e80: 2300 movs r3, #0 8003e82: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8003e84: 687b ldr r3, [r7, #4] 8003e86: 681b ldr r3, [r3, #0] 8003e88: f403 3380 and.w r3, r3, #65536 @ 0x10000 8003e8c: 2b00 cmp r3, #0 8003e8e: d058 beq.n 8003f42 /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 8003e90: f7fe fd38 bl 8002904 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003e94: f7fc fed8 bl 8000c48 8003e98: 60f8 str r0, [r7, #12] while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) 8003e9a: e009 b.n 8003eb0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003e9c: f7fc fed4 bl 8000c48 8003ea0: 4602 mov r2, r0 8003ea2: 68fb ldr r3, [r7, #12] 8003ea4: 1ad3 subs r3, r2, r3 8003ea6: 2b02 cmp r3, #2 8003ea8: d902 bls.n 8003eb0 { ret = HAL_TIMEOUT; 8003eaa: 2303 movs r3, #3 8003eac: 74fb strb r3, [r7, #19] break; 8003eae: e006 b.n 8003ebe while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) 8003eb0: 4b7b ldr r3, [pc, #492] @ (80040a0 ) 8003eb2: 681b ldr r3, [r3, #0] 8003eb4: f403 7380 and.w r3, r3, #256 @ 0x100 8003eb8: f5b3 7f80 cmp.w r3, #256 @ 0x100 8003ebc: d1ee bne.n 8003e9c } } if (ret == HAL_OK) 8003ebe: 7cfb ldrb r3, [r7, #19] 8003ec0: 2b00 cmp r3, #0 8003ec2: d13c bne.n 8003f3e { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) 8003ec4: f7ff ffa7 bl 8003e16 8003ec8: 4602 mov r2, r0 8003eca: 687b ldr r3, [r7, #4] 8003ecc: 6b5b ldr r3, [r3, #52] @ 0x34 8003ece: 429a cmp r2, r3 8003ed0: d00f beq.n 8003ef2 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8003ed2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8003ed6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003eda: f423 7340 bic.w r3, r3, #768 @ 0x300 8003ede: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003ee0: f7ff ffa5 bl 8003e2e __HAL_RCC_BACKUPRESET_RELEASE(); 8003ee4: f7ff ffb3 bl 8003e4e /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8003ee8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8003eec: 697b ldr r3, [r7, #20] 8003eee: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) 8003ef2: 697b ldr r3, [r7, #20] 8003ef4: f003 0302 and.w r3, r3, #2 8003ef8: 2b00 cmp r3, #0 8003efa: d014 beq.n 8003f26 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003efc: f7fc fea4 bl 8000c48 8003f00: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() != 1U) 8003f02: e00b b.n 8003f1c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003f04: f7fc fea0 bl 8000c48 8003f08: 4602 mov r2, r0 8003f0a: 68fb ldr r3, [r7, #12] 8003f0c: 1ad3 subs r3, r2, r3 8003f0e: f241 3288 movw r2, #5000 @ 0x1388 8003f12: 4293 cmp r3, r2 8003f14: d902 bls.n 8003f1c { ret = HAL_TIMEOUT; 8003f16: 2303 movs r3, #3 8003f18: 74fb strb r3, [r7, #19] break; 8003f1a: e004 b.n 8003f26 while (LL_RCC_LSE_IsReady() != 1U) 8003f1c: f7ff feb4 bl 8003c88 8003f20: 4603 mov r3, r0 8003f22: 2b01 cmp r3, #1 8003f24: d1ee bne.n 8003f04 } } } if (ret == HAL_OK) 8003f26: 7cfb ldrb r3, [r7, #19] 8003f28: 2b00 cmp r3, #0 8003f2a: d105 bne.n 8003f38 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003f2c: 687b ldr r3, [r7, #4] 8003f2e: 6b5b ldr r3, [r3, #52] @ 0x34 8003f30: 4618 mov r0, r3 8003f32: f7ff ff5b bl 8003dec 8003f36: e004 b.n 8003f42 } else { /* set overall return value */ status = ret; 8003f38: 7cfb ldrb r3, [r7, #19] 8003f3a: 74bb strb r3, [r7, #18] 8003f3c: e001 b.n 8003f42 } } else { /* set overall return value */ status = ret; 8003f3e: 7cfb ldrb r3, [r7, #19] 8003f40: 74bb strb r3, [r7, #18] } } /*-------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8003f42: 687b ldr r3, [r7, #4] 8003f44: 681b ldr r3, [r3, #0] 8003f46: f003 0301 and.w r3, r3, #1 8003f4a: 2b00 cmp r3, #0 8003f4c: d004 beq.n 8003f58 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003f4e: 687b ldr r3, [r7, #4] 8003f50: 685b ldr r3, [r3, #4] 8003f52: 4618 mov r0, r3 8003f54: f7ff fea9 bl 8003caa } /*-------------------- USART2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8003f58: 687b ldr r3, [r7, #4] 8003f5a: 681b ldr r3, [r3, #0] 8003f5c: f003 0302 and.w r3, r3, #2 8003f60: 2b00 cmp r3, #0 8003f62: d004 beq.n 8003f6e { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8003f64: 687b ldr r3, [r7, #4] 8003f66: 689b ldr r3, [r3, #8] 8003f68: 4618 mov r0, r3 8003f6a: f7ff fe9e bl 8003caa } /*-------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8003f6e: 687b ldr r3, [r7, #4] 8003f70: 681b ldr r3, [r3, #0] 8003f72: f003 0320 and.w r3, r3, #32 8003f76: 2b00 cmp r3, #0 8003f78: d004 beq.n 8003f84 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003f7a: 687b ldr r3, [r7, #4] 8003f7c: 691b ldr r3, [r3, #16] 8003f7e: 4618 mov r0, r3 8003f80: f7ff fec0 bl 8003d04 } /*-------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 8003f84: 687b ldr r3, [r7, #4] 8003f86: 681b ldr r3, [r3, #0] 8003f88: f403 7300 and.w r3, r3, #512 @ 0x200 8003f8c: 2b00 cmp r3, #0 8003f8e: d004 beq.n 8003f9a { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8003f90: 687b ldr r3, [r7, #4] 8003f92: 6a1b ldr r3, [r3, #32] 8003f94: 4618 mov r0, r3 8003f96: f7ff fee6 bl 8003d66 } /*-------------------- LPTIM2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 681b ldr r3, [r3, #0] 8003f9e: f403 6380 and.w r3, r3, #1024 @ 0x400 8003fa2: 2b00 cmp r3, #0 8003fa4: d004 beq.n 8003fb0 { /* Check the parameters */ assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); /* Configure the LPTIM2 clock source */ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 6a5b ldr r3, [r3, #36] @ 0x24 8003faa: 4618 mov r0, r3 8003fac: f7ff fedb bl 8003d66 } /*-------------------- LPTIM3 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) 8003fb0: 687b ldr r3, [r7, #4] 8003fb2: 681b ldr r3, [r3, #0] 8003fb4: f403 6300 and.w r3, r3, #2048 @ 0x800 8003fb8: 2b00 cmp r3, #0 8003fba: d004 beq.n 8003fc6 { /* Check the parameters */ assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); /* Configure the LPTIM3 clock source */ __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); 8003fbc: 687b ldr r3, [r7, #4] 8003fbe: 6a9b ldr r3, [r3, #40] @ 0x28 8003fc0: 4618 mov r0, r3 8003fc2: f7ff fed0 bl 8003d66 } /*-------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8003fc6: 687b ldr r3, [r7, #4] 8003fc8: 681b ldr r3, [r3, #0] 8003fca: f003 0340 and.w r3, r3, #64 @ 0x40 8003fce: 2b00 cmp r3, #0 8003fd0: d004 beq.n 8003fdc { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003fd2: 687b ldr r3, [r7, #4] 8003fd4: 695b ldr r3, [r3, #20] 8003fd6: 4618 mov r0, r3 8003fd8: f7ff fea9 bl 8003d2e } /*-------------------- I2C2 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8003fdc: 687b ldr r3, [r7, #4] 8003fde: 681b ldr r3, [r3, #0] 8003fe0: f003 0380 and.w r3, r3, #128 @ 0x80 8003fe4: 2b00 cmp r3, #0 8003fe6: d004 beq.n 8003ff2 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8003fe8: 687b ldr r3, [r7, #4] 8003fea: 699b ldr r3, [r3, #24] 8003fec: 4618 mov r0, r3 8003fee: f7ff fe9e bl 8003d2e } /*-------------------- I2C3 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 681b ldr r3, [r3, #0] 8003ff6: f403 7380 and.w r3, r3, #256 @ 0x100 8003ffa: 2b00 cmp r3, #0 8003ffc: d004 beq.n 8004008 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 8003ffe: 687b ldr r3, [r7, #4] 8004000: 69db ldr r3, [r3, #28] 8004002: 4618 mov r0, r3 8004004: f7ff fe93 bl 8003d2e } /*-------------------- I2S2 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) 8004008: 687b ldr r3, [r7, #4] 800400a: 681b ldr r3, [r3, #0] 800400c: f003 0310 and.w r3, r3, #16 8004010: 2b00 cmp r3, #0 8004012: d011 beq.n 8004038 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8004014: 687b ldr r3, [r7, #4] 8004016: 68db ldr r3, [r3, #12] 8004018: 4618 mov r0, r3 800401a: f7ff fe5e bl 8003cda if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) 800401e: 687b ldr r3, [r7, #4] 8004020: 68db ldr r3, [r3, #12] 8004022: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004026: d107 bne.n 8004038 { /* Enable RCC_PLL_I2S2CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); 8004028: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800402c: 68db ldr r3, [r3, #12] 800402e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004032: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8004036: 60d3 str r3, [r2, #12] } } /*-------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8004038: 687b ldr r3, [r7, #4] 800403a: 681b ldr r3, [r3, #0] 800403c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004040: 2b00 cmp r3, #0 8004042: d010 beq.n 8004066 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8004044: 687b ldr r3, [r7, #4] 8004046: 6b1b ldr r3, [r3, #48] @ 0x30 8004048: 4618 mov r0, r3 800404a: f7ff fea5 bl 8003d98 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 800404e: 687b ldr r3, [r7, #4] 8004050: 6b1b ldr r3, [r3, #48] @ 0x30 8004052: 2b00 cmp r3, #0 8004054: d107 bne.n 8004066 { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); 8004056: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800405a: 68db ldr r3, [r3, #12] 800405c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004060: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8004064: 60d3 str r3, [r2, #12] } } /*-------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8004066: 687b ldr r3, [r7, #4] 8004068: 681b ldr r3, [r3, #0] 800406a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800406e: 2b00 cmp r3, #0 8004070: d011 beq.n 8004096 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8004072: 687b ldr r3, [r7, #4] 8004074: 6adb ldr r3, [r3, #44] @ 0x2c 8004076: 4618 mov r0, r3 8004078: f7ff fea3 bl 8003dc2 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) 800407c: 687b ldr r3, [r7, #4] 800407e: 6adb ldr r3, [r3, #44] @ 0x2c 8004080: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004084: d107 bne.n 8004096 { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 8004086: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800408a: 68db ldr r3, [r3, #12] 800408c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004090: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004094: 60d3 str r3, [r2, #12] } } return status; 8004096: 7cbb ldrb r3, [r7, #18] } 8004098: 4618 mov r0, r3 800409a: 3718 adds r7, #24 800409c: 46bd mov sp, r7 800409e: bd80 pop {r7, pc} 80040a0: 58000400 .word 0x58000400 080040a4 : * @brief Initialize the RTC peripheral * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 80040a4: b580 push {r7, lr} 80040a6: b084 sub sp, #16 80040a8: af00 add r7, sp, #0 80040aa: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_ERROR; 80040ac: 2301 movs r3, #1 80040ae: 73fb strb r3, [r7, #15] /* Check the RTC peripheral state */ if (hrtc != NULL) 80040b0: 687b ldr r3, [r7, #4] 80040b2: 2b00 cmp r3, #0 80040b4: d07b beq.n 80041ae { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 80040b6: 687b ldr r3, [r7, #4] 80040b8: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 80040bc: b2db uxtb r3, r3 80040be: 2b00 cmp r3, #0 80040c0: d106 bne.n 80040d0 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 80040c2: 687b ldr r3, [r7, #4] 80040c4: 2200 movs r2, #0 80040c6: f883 202c strb.w r2, [r3, #44] @ 0x2c /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 80040ca: 6878 ldr r0, [r7, #4] 80040cc: f7fc fc00 bl 80008d0 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 80040d0: 687b ldr r3, [r7, #4] 80040d2: 2202 movs r2, #2 80040d4: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) 80040d8: 4b37 ldr r3, [pc, #220] @ (80041b8 ) 80040da: 68db ldr r3, [r3, #12] 80040dc: f003 0310 and.w r3, r3, #16 80040e0: 2b10 cmp r3, #16 80040e2: d05b beq.n 800419c { /* Check that the RTC mode is not 'binary only' */ if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) 80040e4: 4b34 ldr r3, [pc, #208] @ (80041b8 ) 80040e6: 68db ldr r3, [r3, #12] 80040e8: f403 7340 and.w r3, r3, #768 @ 0x300 80040ec: f5b3 7f80 cmp.w r3, #256 @ 0x100 80040f0: d051 beq.n 8004196 { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80040f2: 4b31 ldr r3, [pc, #196] @ (80041b8 ) 80040f4: 22ca movs r2, #202 @ 0xca 80040f6: 625a str r2, [r3, #36] @ 0x24 80040f8: 4b2f ldr r3, [pc, #188] @ (80041b8 ) 80040fa: 2253 movs r2, #83 @ 0x53 80040fc: 625a str r2, [r3, #36] @ 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 80040fe: 6878 ldr r0, [r7, #4] 8004100: f000 fa14 bl 800452c 8004104: 4603 mov r3, r0 8004106: 73fb strb r3, [r7, #15] if (status == HAL_OK) 8004108: 7bfb ldrb r3, [r7, #15] 800410a: 2b00 cmp r3, #0 800410c: d13f bne.n 800418e { /* Clear RTC_CR FMT, OSEL and POL Bits */ CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); 800410e: 4b2a ldr r3, [pc, #168] @ (80041b8 ) 8004110: 699b ldr r3, [r3, #24] 8004112: 4a29 ldr r2, [pc, #164] @ (80041b8 ) 8004114: f023 638e bic.w r3, r3, #74448896 @ 0x4700000 8004118: f023 0340 bic.w r3, r3, #64 @ 0x40 800411c: 6193 str r3, [r2, #24] /* Set RTC_CR register */ SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); 800411e: 4b26 ldr r3, [pc, #152] @ (80041b8 ) 8004120: 699a ldr r2, [r3, #24] 8004122: 687b ldr r3, [r7, #4] 8004124: 6859 ldr r1, [r3, #4] 8004126: 687b ldr r3, [r7, #4] 8004128: 691b ldr r3, [r3, #16] 800412a: 4319 orrs r1, r3 800412c: 687b ldr r3, [r7, #4] 800412e: 699b ldr r3, [r3, #24] 8004130: 430b orrs r3, r1 8004132: 4921 ldr r1, [pc, #132] @ (80041b8 ) 8004134: 4313 orrs r3, r2 8004136: 618b str r3, [r1, #24] /* Configure the RTC PRER */ WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); 8004138: 687b ldr r3, [r7, #4] 800413a: 68da ldr r2, [r3, #12] 800413c: 687b ldr r3, [r7, #4] 800413e: 689b ldr r3, [r3, #8] 8004140: 041b lsls r3, r3, #16 8004142: 491d ldr r1, [pc, #116] @ (80041b8 ) 8004144: 4313 orrs r3, r2 8004146: 610b str r3, [r1, #16] /* Configure the Binary mode */ MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); 8004148: 4b1b ldr r3, [pc, #108] @ (80041b8 ) 800414a: 68db ldr r3, [r3, #12] 800414c: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8004150: 687b ldr r3, [r7, #4] 8004152: 6a59 ldr r1, [r3, #36] @ 0x24 8004154: 687b ldr r3, [r7, #4] 8004156: 6a9b ldr r3, [r3, #40] @ 0x28 8004158: 430b orrs r3, r1 800415a: 4917 ldr r1, [pc, #92] @ (80041b8 ) 800415c: 4313 orrs r3, r2 800415e: 60cb str r3, [r1, #12] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 8004160: 6878 ldr r0, [r7, #4] 8004162: f000 fa17 bl 8004594 8004166: 4603 mov r3, r0 8004168: 73fb strb r3, [r7, #15] if (status == HAL_OK) 800416a: 7bfb ldrb r3, [r7, #15] 800416c: 2b00 cmp r3, #0 800416e: d10e bne.n 800418e { MODIFY_REG(RTC->CR, \ 8004170: 4b11 ldr r3, [pc, #68] @ (80041b8 ) 8004172: 699b ldr r3, [r3, #24] 8004174: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 8004178: 687b ldr r3, [r7, #4] 800417a: 6a19 ldr r1, [r3, #32] 800417c: 687b ldr r3, [r7, #4] 800417e: 69db ldr r3, [r3, #28] 8004180: 4319 orrs r1, r3 8004182: 687b ldr r3, [r7, #4] 8004184: 695b ldr r3, [r3, #20] 8004186: 430b orrs r3, r1 8004188: 490b ldr r1, [pc, #44] @ (80041b8 ) 800418a: 4313 orrs r3, r2 800418c: 618b str r3, [r1, #24] hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800418e: 4b0a ldr r3, [pc, #40] @ (80041b8 ) 8004190: 22ff movs r2, #255 @ 0xff 8004192: 625a str r2, [r3, #36] @ 0x24 8004194: e004 b.n 80041a0 } else { /* The calendar does not need to be initialized as the 'binary only' mode is selected */ status = HAL_OK; 8004196: 2300 movs r3, #0 8004198: 73fb strb r3, [r7, #15] 800419a: e001 b.n 80041a0 } } else { /* The calendar is already initialized */ status = HAL_OK; 800419c: 2300 movs r3, #0 800419e: 73fb strb r3, [r7, #15] } if (status == HAL_OK) 80041a0: 7bfb ldrb r3, [r7, #15] 80041a2: 2b00 cmp r3, #0 80041a4: d103 bne.n 80041ae { hrtc->State = HAL_RTC_STATE_READY; 80041a6: 687b ldr r3, [r7, #4] 80041a8: 2201 movs r2, #1 80041aa: f883 202d strb.w r2, [r3, #45] @ 0x2d } } return status; 80041ae: 7bfb ldrb r3, [r7, #15] } 80041b0: 4618 mov r0, r3 80041b2: 3710 adds r7, #16 80041b4: 46bd mov sp, r7 80041b6: bd80 pop {r7, pc} 80041b8: 40002800 .word 0x40002800 080041bc : * @arg RTC_FORMAT_BIN: Binary format * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { 80041bc: b590 push {r4, r7, lr} 80041be: b087 sub sp, #28 80041c0: af00 add r7, sp, #0 80041c2: 60f8 str r0, [r7, #12] 80041c4: 60b9 str r1, [r7, #8] 80041c6: 607a str r2, [r7, #4] uint32_t tmpreg = 0; 80041c8: 2300 movs r3, #0 80041ca: 617b str r3, [r7, #20] uint32_t binaryMode; /* Process Locked */ __HAL_LOCK(hrtc); 80041cc: 68fb ldr r3, [r7, #12] 80041ce: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80041d2: 2b01 cmp r3, #1 80041d4: d101 bne.n 80041da 80041d6: 2302 movs r3, #2 80041d8: e0f3 b.n 80043c2 80041da: 68fb ldr r3, [r7, #12] 80041dc: 2201 movs r2, #1 80041de: f883 202c strb.w r2, [r3, #44] @ 0x2c hrtc->State = HAL_RTC_STATE_BUSY; 80041e2: 68fb ldr r3, [r7, #12] 80041e4: 2202 movs r2, #2 80041e6: f883 202d strb.w r2, [r3, #45] @ 0x2d RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); } #endif /* USE_FULL_ASSERT */ /* Get Binary mode (32-bit free-running counter configuration) */ binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); 80041ea: 4b78 ldr r3, [pc, #480] @ (80043cc ) 80041ec: 68db ldr r3, [r3, #12] 80041ee: f403 7340 and.w r3, r3, #768 @ 0x300 80041f2: 613b str r3, [r7, #16] if (binaryMode != RTC_BINARY_ONLY) 80041f4: 693b ldr r3, [r7, #16] 80041f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80041fa: d06a beq.n 80042d2 { if (Format == RTC_FORMAT_BIN) 80041fc: 687b ldr r3, [r7, #4] 80041fe: 2b00 cmp r3, #0 8004200: d13a bne.n 8004278 { if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) 8004202: 4b72 ldr r3, [pc, #456] @ (80043cc ) 8004204: 699b ldr r3, [r3, #24] 8004206: f003 0340 and.w r3, r3, #64 @ 0x40 800420a: 2b00 cmp r3, #0 800420c: d102 bne.n 8004214 assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { sAlarm->AlarmTime.TimeFormat = 0x00U; 800420e: 68bb ldr r3, [r7, #8] 8004210: 2200 movs r2, #0 8004212: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY) 8004214: 68bb ldr r3, [r7, #8] 8004216: 695b ldr r3, [r3, #20] 8004218: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } } tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 800421c: 68bb ldr r3, [r7, #8] 800421e: 781b ldrb r3, [r3, #0] 8004220: 4618 mov r0, r3 8004222: f000 f9f5 bl 8004610 8004226: 4603 mov r3, r0 8004228: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ 800422a: 68bb ldr r3, [r7, #8] 800422c: 785b ldrb r3, [r3, #1] 800422e: 4618 mov r0, r3 8004230: f000 f9ee bl 8004610 8004234: 4603 mov r3, r0 8004236: 021b lsls r3, r3, #8 tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 8004238: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ 800423a: 68bb ldr r3, [r7, #8] 800423c: 789b ldrb r3, [r3, #2] 800423e: 4618 mov r0, r3 8004240: f000 f9e6 bl 8004610 8004244: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ 8004246: ea44 0203 orr.w r2, r4, r3 ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ 800424a: 68bb ldr r3, [r7, #8] 800424c: 78db ldrb r3, [r3, #3] 800424e: 059b lsls r3, r3, #22 ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ 8004250: ea42 0403 orr.w r4, r2, r3 ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ 8004254: 68bb ldr r3, [r7, #8] 8004256: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800425a: 4618 mov r0, r3 800425c: f000 f9d8 bl 8004610 8004260: 4603 mov r3, r0 8004262: 061b lsls r3, r3, #24 ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ 8004264: ea44 0203 orr.w r2, r4, r3 ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ 8004268: 68bb ldr r3, [r7, #8] 800426a: 6a1b ldr r3, [r3, #32] ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ 800426c: 431a orrs r2, r3 ((uint32_t)sAlarm->AlarmMask)); 800426e: 68bb ldr r3, [r7, #8] 8004270: 695b ldr r3, [r3, #20] tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 8004272: 4313 orrs r3, r2 8004274: 617b str r3, [r7, #20] 8004276: e02c b.n 80042d2 } else /* Format BCD */ { if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL) 8004278: 68bb ldr r3, [r7, #8] 800427a: 695b ldr r3, [r3, #20] 800427c: f1b3 3f80 cmp.w r3, #2155905152 @ 0x80808080 8004280: d00d beq.n 800429e { if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS) 8004282: 68bb ldr r3, [r7, #8] 8004284: 695b ldr r3, [r3, #20] 8004286: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800428a: d008 beq.n 800429e { if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) 800428c: 4b4f ldr r3, [pc, #316] @ (80043cc ) 800428e: 699b ldr r3, [r3, #24] 8004290: f003 0340 and.w r3, r3, #64 @ 0x40 8004294: 2b00 cmp r3, #0 8004296: d102 bne.n 800429e assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { sAlarm->AlarmTime.TimeFormat = 0x00U; 8004298: 68bb ldr r3, [r7, #8] 800429a: 2200 movs r2, #0 800429c: 70da strb r2, [r3, #3] { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } } #endif /* USE_FULL_ASSERT */ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 800429e: 68bb ldr r3, [r7, #8] 80042a0: 781b ldrb r3, [r3, #0] 80042a2: 041a lsls r2, r3, #16 ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ 80042a4: 68bb ldr r3, [r7, #8] 80042a6: 785b ldrb r3, [r3, #1] 80042a8: 021b lsls r3, r3, #8 tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 80042aa: 4313 orrs r3, r2 ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ 80042ac: 68ba ldr r2, [r7, #8] 80042ae: 7892 ldrb r2, [r2, #2] ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ 80042b0: 431a orrs r2, r3 ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ 80042b2: 68bb ldr r3, [r7, #8] 80042b4: 78db ldrb r3, [r3, #3] 80042b6: 059b lsls r3, r3, #22 ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ 80042b8: 431a orrs r2, r3 ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ 80042ba: 68bb ldr r3, [r7, #8] 80042bc: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80042c0: 061b lsls r3, r3, #24 ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ 80042c2: 431a orrs r2, r3 ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ 80042c4: 68bb ldr r3, [r7, #8] 80042c6: 6a1b ldr r3, [r3, #32] ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ 80042c8: 431a orrs r2, r3 ((uint32_t)sAlarm->AlarmMask)); 80042ca: 68bb ldr r3, [r7, #8] 80042cc: 695b ldr r3, [r3, #20] tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ 80042ce: 4313 orrs r3, r2 80042d0: 617b str r3, [r7, #20] } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80042d2: 4b3e ldr r3, [pc, #248] @ (80043cc ) 80042d4: 22ca movs r2, #202 @ 0xca 80042d6: 625a str r2, [r3, #36] @ 0x24 80042d8: 4b3c ldr r3, [pc, #240] @ (80043cc ) 80042da: 2253 movs r2, #83 @ 0x53 80042dc: 625a str r2, [r3, #36] @ 0x24 /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) 80042de: 68bb ldr r3, [r7, #8] 80042e0: 6a9b ldr r3, [r3, #40] @ 0x28 80042e2: f5b3 7f80 cmp.w r3, #256 @ 0x100 80042e6: d12c bne.n 8004342 { /* Disable the Alarm A interrupt */ CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); 80042e8: 4b38 ldr r3, [pc, #224] @ (80043cc ) 80042ea: 699b ldr r3, [r3, #24] 80042ec: 4a37 ldr r2, [pc, #220] @ (80043cc ) 80042ee: f423 5388 bic.w r3, r3, #4352 @ 0x1100 80042f2: 6193 str r3, [r2, #24] /* Clear flag alarm A */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); 80042f4: 4b35 ldr r3, [pc, #212] @ (80043cc ) 80042f6: 2201 movs r2, #1 80042f8: 65da str r2, [r3, #92] @ 0x5c if (binaryMode == RTC_BINARY_ONLY) 80042fa: 693b ldr r3, [r7, #16] 80042fc: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004300: d107 bne.n 8004312 { RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; 8004302: 68bb ldr r3, [r7, #8] 8004304: 699a ldr r2, [r3, #24] 8004306: 68bb ldr r3, [r7, #8] 8004308: 69db ldr r3, [r3, #28] 800430a: 4930 ldr r1, [pc, #192] @ (80043cc ) 800430c: 4313 orrs r3, r2 800430e: 644b str r3, [r1, #68] @ 0x44 8004310: e006 b.n 8004320 } else { WRITE_REG(RTC->ALRMAR, tmpreg); 8004312: 4a2e ldr r2, [pc, #184] @ (80043cc ) 8004314: 697b ldr r3, [r7, #20] 8004316: 6413 str r3, [r2, #64] @ 0x40 WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); 8004318: 4a2c ldr r2, [pc, #176] @ (80043cc ) 800431a: 68bb ldr r3, [r7, #8] 800431c: 699b ldr r3, [r3, #24] 800431e: 6453 str r3, [r2, #68] @ 0x44 } WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); 8004320: 4a2a ldr r2, [pc, #168] @ (80043cc ) 8004322: 68bb ldr r3, [r7, #8] 8004324: 685b ldr r3, [r3, #4] 8004326: 6713 str r3, [r2, #112] @ 0x70 /* Store in the handle the Alarm A enabled */ SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); 8004328: 68fb ldr r3, [r7, #12] 800432a: 6b1b ldr r3, [r3, #48] @ 0x30 800432c: f043 0201 orr.w r2, r3, #1 8004330: 68fb ldr r3, [r7, #12] 8004332: 631a str r2, [r3, #48] @ 0x30 /* Configure the Alarm interrupt */ SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); 8004334: 4b25 ldr r3, [pc, #148] @ (80043cc ) 8004336: 699b ldr r3, [r3, #24] 8004338: 4a24 ldr r2, [pc, #144] @ (80043cc ) 800433a: f443 5388 orr.w r3, r3, #4352 @ 0x1100 800433e: 6193 str r3, [r2, #24] 8004340: e02b b.n 800439a } else { /* Disable the Alarm B interrupt */ CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); 8004342: 4b22 ldr r3, [pc, #136] @ (80043cc ) 8004344: 699b ldr r3, [r3, #24] 8004346: 4a21 ldr r2, [pc, #132] @ (80043cc ) 8004348: f423 5308 bic.w r3, r3, #8704 @ 0x2200 800434c: 6193 str r3, [r2, #24] /* Clear flag alarm B */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); 800434e: 4b1f ldr r3, [pc, #124] @ (80043cc ) 8004350: 2202 movs r2, #2 8004352: 65da str r2, [r3, #92] @ 0x5c if (binaryMode == RTC_BINARY_ONLY) 8004354: 693b ldr r3, [r7, #16] 8004356: f5b3 7f80 cmp.w r3, #256 @ 0x100 800435a: d107 bne.n 800436c { WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); 800435c: 68bb ldr r3, [r7, #8] 800435e: 699a ldr r2, [r3, #24] 8004360: 68bb ldr r3, [r7, #8] 8004362: 69db ldr r3, [r3, #28] 8004364: 4919 ldr r1, [pc, #100] @ (80043cc ) 8004366: 4313 orrs r3, r2 8004368: 64cb str r3, [r1, #76] @ 0x4c 800436a: e006 b.n 800437a } else { WRITE_REG(RTC->ALRMBR, tmpreg); 800436c: 4a17 ldr r2, [pc, #92] @ (80043cc ) 800436e: 697b ldr r3, [r7, #20] 8004370: 6493 str r3, [r2, #72] @ 0x48 WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); 8004372: 4a16 ldr r2, [pc, #88] @ (80043cc ) 8004374: 68bb ldr r3, [r7, #8] 8004376: 699b ldr r3, [r3, #24] 8004378: 64d3 str r3, [r2, #76] @ 0x4c } WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); 800437a: 4a14 ldr r2, [pc, #80] @ (80043cc ) 800437c: 68bb ldr r3, [r7, #8] 800437e: 685b ldr r3, [r3, #4] 8004380: 6753 str r3, [r2, #116] @ 0x74 /* Store in the handle the Alarm B enabled */ SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); 8004382: 68fb ldr r3, [r7, #12] 8004384: 6b1b ldr r3, [r3, #48] @ 0x30 8004386: f043 0202 orr.w r2, r3, #2 800438a: 68fb ldr r3, [r7, #12] 800438c: 631a str r2, [r3, #48] @ 0x30 /* Configure the Alarm interrupt */ SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); 800438e: 4b0f ldr r3, [pc, #60] @ (80043cc ) 8004390: 699b ldr r3, [r3, #24] 8004392: 4a0e ldr r2, [pc, #56] @ (80043cc ) 8004394: f443 5308 orr.w r3, r3, #8704 @ 0x2200 8004398: 6193 str r3, [r2, #24] } /* RTC Alarm Interrupt Configuration: EXTI configuration */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); 800439a: 4b0d ldr r3, [pc, #52] @ (80043d0 ) 800439c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80043a0: 4a0b ldr r2, [pc, #44] @ (80043d0 ) 80043a2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80043a6: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80043aa: 4b08 ldr r3, [pc, #32] @ (80043cc ) 80043ac: 22ff movs r2, #255 @ 0xff 80043ae: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_READY; 80043b0: 68fb ldr r3, [r7, #12] 80043b2: 2201 movs r2, #1 80043b4: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Process Unlocked */ __HAL_UNLOCK(hrtc); 80043b8: 68fb ldr r3, [r7, #12] 80043ba: 2200 movs r2, #0 80043bc: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 80043c0: 2300 movs r3, #0 } 80043c2: 4618 mov r0, r3 80043c4: 371c adds r7, #28 80043c6: 46bd mov sp, r7 80043c8: bd90 pop {r4, r7, pc} 80043ca: bf00 nop 80043cc: 40002800 .word 0x40002800 80043d0: 58000800 .word 0x58000800 080043d4 : * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { 80043d4: b480 push {r7} 80043d6: b083 sub sp, #12 80043d8: af00 add r7, sp, #0 80043da: 6078 str r0, [r7, #4] 80043dc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); /* Process Locked */ __HAL_LOCK(hrtc); 80043de: 687b ldr r3, [r7, #4] 80043e0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80043e4: 2b01 cmp r3, #1 80043e6: d101 bne.n 80043ec 80043e8: 2302 movs r3, #2 80043ea: e048 b.n 800447e 80043ec: 687b ldr r3, [r7, #4] 80043ee: 2201 movs r2, #1 80043f0: f883 202c strb.w r2, [r3, #44] @ 0x2c hrtc->State = HAL_RTC_STATE_BUSY; 80043f4: 687b ldr r3, [r7, #4] 80043f6: 2202 movs r2, #2 80043f8: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80043fc: 4b22 ldr r3, [pc, #136] @ (8004488 ) 80043fe: 22ca movs r2, #202 @ 0xca 8004400: 625a str r2, [r3, #36] @ 0x24 8004402: 4b21 ldr r3, [pc, #132] @ (8004488 ) 8004404: 2253 movs r2, #83 @ 0x53 8004406: 625a str r2, [r3, #36] @ 0x24 if (Alarm == RTC_ALARM_A) 8004408: 683b ldr r3, [r7, #0] 800440a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800440e: d115 bne.n 800443c { /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); 8004410: 4b1d ldr r3, [pc, #116] @ (8004488 ) 8004412: 699b ldr r3, [r3, #24] 8004414: 4a1c ldr r2, [pc, #112] @ (8004488 ) 8004416: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800441a: 6193 str r3, [r2, #24] /* AlarmA, Clear SSCLR */ CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); 800441c: 4b1a ldr r3, [pc, #104] @ (8004488 ) 800441e: 6c5b ldr r3, [r3, #68] @ 0x44 8004420: 4a19 ldr r2, [pc, #100] @ (8004488 ) 8004422: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8004426: 6453 str r3, [r2, #68] @ 0x44 /* Store in the handle the Alarm A disabled */ CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); 8004428: 687b ldr r3, [r7, #4] 800442a: 6b1b ldr r3, [r3, #48] @ 0x30 800442c: f023 0201 bic.w r2, r3, #1 8004430: 687b ldr r3, [r7, #4] 8004432: 631a str r2, [r3, #48] @ 0x30 /* Clear AlarmA flag */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); 8004434: 4b14 ldr r3, [pc, #80] @ (8004488 ) 8004436: 2201 movs r2, #1 8004438: 65da str r2, [r3, #92] @ 0x5c 800443a: e014 b.n 8004466 } else { /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); 800443c: 4b12 ldr r3, [pc, #72] @ (8004488 ) 800443e: 699b ldr r3, [r3, #24] 8004440: 4a11 ldr r2, [pc, #68] @ (8004488 ) 8004442: f423 5308 bic.w r3, r3, #8704 @ 0x2200 8004446: 6193 str r3, [r2, #24] /* AlarmB, Clear SSCLR */ CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); 8004448: 4b0f ldr r3, [pc, #60] @ (8004488 ) 800444a: 6cdb ldr r3, [r3, #76] @ 0x4c 800444c: 4a0e ldr r2, [pc, #56] @ (8004488 ) 800444e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8004452: 64d3 str r3, [r2, #76] @ 0x4c /* Store in the handle the Alarm B disabled */ CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); 8004454: 687b ldr r3, [r7, #4] 8004456: 6b1b ldr r3, [r3, #48] @ 0x30 8004458: f023 0202 bic.w r2, r3, #2 800445c: 687b ldr r3, [r7, #4] 800445e: 631a str r2, [r3, #48] @ 0x30 /* Clear AlarmB flag */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); 8004460: 4b09 ldr r3, [pc, #36] @ (8004488 ) 8004462: 2202 movs r2, #2 8004464: 65da str r2, [r3, #92] @ 0x5c } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8004466: 4b08 ldr r3, [pc, #32] @ (8004488 ) 8004468: 22ff movs r2, #255 @ 0xff 800446a: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_READY; 800446c: 687b ldr r3, [r7, #4] 800446e: 2201 movs r2, #1 8004470: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8004474: 687b ldr r3, [r7, #4] 8004476: 2200 movs r2, #0 8004478: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 800447c: 2300 movs r3, #0 } 800447e: 4618 mov r0, r3 8004480: 370c adds r7, #12 8004482: 46bd mov sp, r7 8004484: bc80 pop {r7} 8004486: 4770 bx lr 8004488: 40002800 .word 0x40002800 0800448c : * @brief Handle Alarm interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { 800448c: b580 push {r7, lr} 800448e: b084 sub sp, #16 8004490: af00 add r7, sp, #0 8004492: 6078 str r0, [r7, #4] uint32_t tmp = READ_REG(RTC->MISR) & READ_REG(hrtc->IsEnabled.RtcFeatures); 8004494: 4b11 ldr r3, [pc, #68] @ (80044dc ) 8004496: 6d5a ldr r2, [r3, #84] @ 0x54 8004498: 687b ldr r3, [r7, #4] 800449a: 6b1b ldr r3, [r3, #48] @ 0x30 800449c: 4013 ands r3, r2 800449e: 60fb str r3, [r7, #12] if ((tmp & RTC_MISR_ALRAMF) != 0U) 80044a0: 68fb ldr r3, [r7, #12] 80044a2: f003 0301 and.w r3, r3, #1 80044a6: 2b00 cmp r3, #0 80044a8: d005 beq.n 80044b6 { /* Clear the AlarmA interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); 80044aa: 4b0c ldr r3, [pc, #48] @ (80044dc ) 80044ac: 2201 movs r2, #1 80044ae: 65da str r2, [r3, #92] @ 0x5c #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call Compare Match registered Callback */ hrtc->AlarmAEventCallback(hrtc); #else HAL_RTC_AlarmAEventCallback(hrtc); 80044b0: 6878 ldr r0, [r7, #4] 80044b2: f7fc fdf0 bl 8001096 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } if ((tmp & RTC_MISR_ALRBMF) != 0U) 80044b6: 68fb ldr r3, [r7, #12] 80044b8: f003 0302 and.w r3, r3, #2 80044bc: 2b00 cmp r3, #0 80044be: d005 beq.n 80044cc { /* Clear the AlarmB interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); 80044c0: 4b06 ldr r3, [pc, #24] @ (80044dc ) 80044c2: 2202 movs r2, #2 80044c4: 65da str r2, [r3, #92] @ 0x5c #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call Compare Match registered Callback */ hrtc->AlarmBEventCallback(hrtc); #else HAL_RTCEx_AlarmBEventCallback(hrtc); 80044c6: 6878 ldr r0, [r7, #4] 80044c8: f000 f94a bl 8004760 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; 80044cc: 687b ldr r3, [r7, #4] 80044ce: 2201 movs r2, #1 80044d0: f883 202d strb.w r2, [r3, #45] @ 0x2d } 80044d4: bf00 nop 80044d6: 3710 adds r7, #16 80044d8: 46bd mov sp, r7 80044da: bd80 pop {r7, pc} 80044dc: 40002800 .word 0x40002800 080044e0 : * correctly copied into the RTC_TR and RTC_DR shadow registers. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc) { 80044e0: b580 push {r7, lr} 80044e2: b084 sub sp, #16 80044e4: af00 add r7, sp, #0 80044e6: 6078 str r0, [r7, #4] uint32_t tickstart; UNUSED(hrtc); /* Clear RSF flag */ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); 80044e8: 4b0f ldr r3, [pc, #60] @ (8004528 ) 80044ea: 68db ldr r3, [r3, #12] 80044ec: 4a0e ldr r2, [pc, #56] @ (8004528 ) 80044ee: f023 0320 bic.w r3, r3, #32 80044f2: 60d3 str r3, [r2, #12] tickstart = HAL_GetTick(); 80044f4: f7fc fba8 bl 8000c48 80044f8: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) 80044fa: e009 b.n 8004510 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80044fc: f7fc fba4 bl 8000c48 8004500: 4602 mov r2, r0 8004502: 68fb ldr r3, [r7, #12] 8004504: 1ad3 subs r3, r2, r3 8004506: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800450a: d901 bls.n 8004510 { return HAL_TIMEOUT; 800450c: 2303 movs r3, #3 800450e: e006 b.n 800451e while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) 8004510: 4b05 ldr r3, [pc, #20] @ (8004528 ) 8004512: 68db ldr r3, [r3, #12] 8004514: f003 0320 and.w r3, r3, #32 8004518: 2b00 cmp r3, #0 800451a: d0ef beq.n 80044fc } } return HAL_OK; 800451c: 2300 movs r3, #0 } 800451e: 4618 mov r0, r3 8004520: 3710 adds r7, #16 8004522: 46bd mov sp, r7 8004524: bd80 pop {r7, pc} 8004526: bf00 nop 8004528: 40002800 .word 0x40002800 0800452c : * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 800452c: b580 push {r7, lr} 800452e: b084 sub sp, #16 8004530: af00 add r7, sp, #0 8004532: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004534: 2300 movs r3, #0 8004536: 73fb strb r3, [r7, #15] UNUSED(hrtc); /* Check if the Initialization mode is set */ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) 8004538: 4b15 ldr r3, [pc, #84] @ (8004590 ) 800453a: 68db ldr r3, [r3, #12] 800453c: f003 0340 and.w r3, r3, #64 @ 0x40 8004540: 2b00 cmp r3, #0 8004542: d120 bne.n 8004586 { /* Set the Initialization mode */ SET_BIT(RTC->ICSR, RTC_ICSR_INIT); 8004544: 4b12 ldr r3, [pc, #72] @ (8004590 ) 8004546: 68db ldr r3, [r3, #12] 8004548: 4a11 ldr r2, [pc, #68] @ (8004590 ) 800454a: f043 0380 orr.w r3, r3, #128 @ 0x80 800454e: 60d3 str r3, [r2, #12] tickstart = HAL_GetTick(); 8004550: f7fc fb7a bl 8000c48 8004554: 60b8 str r0, [r7, #8] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) 8004556: e00d b.n 8004574 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8004558: f7fc fb76 bl 8000c48 800455c: 4602 mov r2, r0 800455e: 68bb ldr r3, [r7, #8] 8004560: 1ad3 subs r3, r2, r3 8004562: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8004566: d905 bls.n 8004574 { status = HAL_TIMEOUT; 8004568: 2303 movs r3, #3 800456a: 73fb strb r3, [r7, #15] hrtc->State = HAL_RTC_STATE_TIMEOUT; 800456c: 687b ldr r3, [r7, #4] 800456e: 2203 movs r2, #3 8004570: f883 202d strb.w r2, [r3, #45] @ 0x2d while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) 8004574: 4b06 ldr r3, [pc, #24] @ (8004590 ) 8004576: 68db ldr r3, [r3, #12] 8004578: f003 0340 and.w r3, r3, #64 @ 0x40 800457c: 2b00 cmp r3, #0 800457e: d102 bne.n 8004586 8004580: 7bfb ldrb r3, [r7, #15] 8004582: 2b03 cmp r3, #3 8004584: d1e8 bne.n 8004558 } } } return status; 8004586: 7bfb ldrb r3, [r7, #15] } 8004588: 4618 mov r0, r3 800458a: 3710 adds r7, #16 800458c: 46bd mov sp, r7 800458e: bd80 pop {r7, pc} 8004590: 40002800 .word 0x40002800 08004594 : * @brief Exit the RTC Initialization mode. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8004594: b580 push {r7, lr} 8004596: b084 sub sp, #16 8004598: af00 add r7, sp, #0 800459a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800459c: 2300 movs r3, #0 800459e: 73fb strb r3, [r7, #15] /* Exit Initialization mode */ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); 80045a0: 4b1a ldr r3, [pc, #104] @ (800460c ) 80045a2: 68db ldr r3, [r3, #12] 80045a4: 4a19 ldr r2, [pc, #100] @ (800460c ) 80045a6: f023 0380 bic.w r3, r3, #128 @ 0x80 80045aa: 60d3 str r3, [r2, #12] /* If CR_BYPSHAD bit = 0, wait for synchro */ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) 80045ac: 4b17 ldr r3, [pc, #92] @ (800460c ) 80045ae: 699b ldr r3, [r3, #24] 80045b0: f003 0320 and.w r3, r3, #32 80045b4: 2b00 cmp r3, #0 80045b6: d10c bne.n 80045d2 { if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 80045b8: 6878 ldr r0, [r7, #4] 80045ba: f7ff ff91 bl 80044e0 80045be: 4603 mov r3, r0 80045c0: 2b00 cmp r3, #0 80045c2: d01e beq.n 8004602 { hrtc->State = HAL_RTC_STATE_TIMEOUT; 80045c4: 687b ldr r3, [r7, #4] 80045c6: 2203 movs r2, #3 80045c8: f883 202d strb.w r2, [r3, #45] @ 0x2d status = HAL_TIMEOUT; 80045cc: 2303 movs r3, #3 80045ce: 73fb strb r3, [r7, #15] 80045d0: e017 b.n 8004602 } } else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ { /* Clear BYPSHAD bit */ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); 80045d2: 4b0e ldr r3, [pc, #56] @ (800460c ) 80045d4: 699b ldr r3, [r3, #24] 80045d6: 4a0d ldr r2, [pc, #52] @ (800460c ) 80045d8: f023 0320 bic.w r3, r3, #32 80045dc: 6193 str r3, [r2, #24] if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 80045de: 6878 ldr r0, [r7, #4] 80045e0: f7ff ff7e bl 80044e0 80045e4: 4603 mov r3, r0 80045e6: 2b00 cmp r3, #0 80045e8: d005 beq.n 80045f6 { hrtc->State = HAL_RTC_STATE_TIMEOUT; 80045ea: 687b ldr r3, [r7, #4] 80045ec: 2203 movs r2, #3 80045ee: f883 202d strb.w r2, [r3, #45] @ 0x2d status = HAL_TIMEOUT; 80045f2: 2303 movs r3, #3 80045f4: 73fb strb r3, [r7, #15] } /* Restore BYPSHAD bit */ SET_BIT(RTC->CR, RTC_CR_BYPSHAD); 80045f6: 4b05 ldr r3, [pc, #20] @ (800460c ) 80045f8: 699b ldr r3, [r3, #24] 80045fa: 4a04 ldr r2, [pc, #16] @ (800460c ) 80045fc: f043 0320 orr.w r3, r3, #32 8004600: 6193 str r3, [r2, #24] } return status; 8004602: 7bfb ldrb r3, [r7, #15] } 8004604: 4618 mov r0, r3 8004606: 3710 adds r7, #16 8004608: 46bd mov sp, r7 800460a: bd80 pop {r7, pc} 800460c: 40002800 .word 0x40002800 08004610 : * @brief Convert a 2 digit decimal to BCD format. * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { 8004610: b480 push {r7} 8004612: b085 sub sp, #20 8004614: af00 add r7, sp, #0 8004616: 4603 mov r3, r0 8004618: 71fb strb r3, [r7, #7] uint32_t bcdhigh = 0U; 800461a: 2300 movs r3, #0 800461c: 60fb str r3, [r7, #12] uint8_t tmp_Value = Value; 800461e: 79fb ldrb r3, [r7, #7] 8004620: 72fb strb r3, [r7, #11] while (tmp_Value >= 10U) 8004622: e005 b.n 8004630 { bcdhigh++; 8004624: 68fb ldr r3, [r7, #12] 8004626: 3301 adds r3, #1 8004628: 60fb str r3, [r7, #12] tmp_Value -= 10U; 800462a: 7afb ldrb r3, [r7, #11] 800462c: 3b0a subs r3, #10 800462e: 72fb strb r3, [r7, #11] while (tmp_Value >= 10U) 8004630: 7afb ldrb r3, [r7, #11] 8004632: 2b09 cmp r3, #9 8004634: d8f6 bhi.n 8004624 } return ((uint8_t)(bcdhigh << 4U) | tmp_Value); 8004636: 68fb ldr r3, [r7, #12] 8004638: b2db uxtb r3, r3 800463a: 011b lsls r3, r3, #4 800463c: b2da uxtb r2, r3 800463e: 7afb ldrb r3, [r7, #11] 8004640: 4313 orrs r3, r2 8004642: b2db uxtb r3, r3 } 8004644: 4618 mov r0, r3 8004646: 3714 adds r7, #20 8004648: 46bd mov sp, r7 800464a: bc80 pop {r7} 800464c: 4770 bx lr ... 08004650 : * directly from the Calendar counter. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) { 8004650: b480 push {r7} 8004652: b083 sub sp, #12 8004654: af00 add r7, sp, #0 8004656: 6078 str r0, [r7, #4] /* Process Locked */ __HAL_LOCK(hrtc); 8004658: 687b ldr r3, [r7, #4] 800465a: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 800465e: 2b01 cmp r3, #1 8004660: d101 bne.n 8004666 8004662: 2302 movs r3, #2 8004664: e01f b.n 80046a6 8004666: 687b ldr r3, [r7, #4] 8004668: 2201 movs r2, #1 800466a: f883 202c strb.w r2, [r3, #44] @ 0x2c hrtc->State = HAL_RTC_STATE_BUSY; 800466e: 687b ldr r3, [r7, #4] 8004670: 2202 movs r2, #2 8004672: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8004676: 4b0e ldr r3, [pc, #56] @ (80046b0 ) 8004678: 22ca movs r2, #202 @ 0xca 800467a: 625a str r2, [r3, #36] @ 0x24 800467c: 4b0c ldr r3, [pc, #48] @ (80046b0 ) 800467e: 2253 movs r2, #83 @ 0x53 8004680: 625a str r2, [r3, #36] @ 0x24 /* Set the BYPSHAD bit */ SET_BIT(RTC->CR, RTC_CR_BYPSHAD); 8004682: 4b0b ldr r3, [pc, #44] @ (80046b0 ) 8004684: 699b ldr r3, [r3, #24] 8004686: 4a0a ldr r2, [pc, #40] @ (80046b0 ) 8004688: f043 0320 orr.w r3, r3, #32 800468c: 6193 str r3, [r2, #24] /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800468e: 4b08 ldr r3, [pc, #32] @ (80046b0 ) 8004690: 22ff movs r2, #255 @ 0xff 8004692: 625a str r2, [r3, #36] @ 0x24 /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8004694: 687b ldr r3, [r7, #4] 8004696: 2201 movs r2, #1 8004698: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800469c: 687b ldr r3, [r7, #4] 800469e: 2200 movs r2, #0 80046a0: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 80046a4: 2300 movs r3, #0 } 80046a6: 4618 mov r0, r3 80046a8: 370c adds r7, #12 80046aa: 46bd mov sp, r7 80046ac: bc80 pop {r7} 80046ae: 4770 bx lr 80046b0: 40002800 .word 0x40002800 080046b4 : * @brief Set SSR Underflow detection with Interrupt. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) { 80046b4: b480 push {r7} 80046b6: b083 sub sp, #12 80046b8: af00 add r7, sp, #0 80046ba: 6078 str r0, [r7, #4] /* Process Locked */ __HAL_LOCK(hrtc); 80046bc: 687b ldr r3, [r7, #4] 80046be: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80046c2: 2b01 cmp r3, #1 80046c4: d101 bne.n 80046ca 80046c6: 2302 movs r3, #2 80046c8: e027 b.n 800471a 80046ca: 687b ldr r3, [r7, #4] 80046cc: 2201 movs r2, #1 80046ce: f883 202c strb.w r2, [r3, #44] @ 0x2c hrtc->State = HAL_RTC_STATE_BUSY; 80046d2: 687b ldr r3, [r7, #4] 80046d4: 2202 movs r2, #2 80046d6: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80046da: 4b12 ldr r3, [pc, #72] @ (8004724 ) 80046dc: 22ca movs r2, #202 @ 0xca 80046de: 625a str r2, [r3, #36] @ 0x24 80046e0: 4b10 ldr r3, [pc, #64] @ (8004724 ) 80046e2: 2253 movs r2, #83 @ 0x53 80046e4: 625a str r2, [r3, #36] @ 0x24 /* Enable IT SSRU */ __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); 80046e6: 4b0f ldr r3, [pc, #60] @ (8004724 ) 80046e8: 699b ldr r3, [r3, #24] 80046ea: 4a0e ldr r2, [pc, #56] @ (8004724 ) 80046ec: f043 0380 orr.w r3, r3, #128 @ 0x80 80046f0: 6193 str r3, [r2, #24] /* RTC SSRU Interrupt Configuration: EXTI configuration */ __HAL_RTC_SSRU_EXTI_ENABLE_IT(); 80046f2: 4b0d ldr r3, [pc, #52] @ (8004728 ) 80046f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80046f8: 4a0b ldr r2, [pc, #44] @ (8004728 ) 80046fa: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80046fe: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8004702: 4b08 ldr r3, [pc, #32] @ (8004724 ) 8004704: 22ff movs r2, #255 @ 0xff 8004706: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_READY; 8004708: 687b ldr r3, [r7, #4] 800470a: 2201 movs r2, #1 800470c: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8004710: 687b ldr r3, [r7, #4] 8004712: 2200 movs r2, #0 8004714: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 8004718: 2300 movs r3, #0 } 800471a: 4618 mov r0, r3 800471c: 370c adds r7, #12 800471e: 46bd mov sp, r7 8004720: bc80 pop {r7} 8004722: 4770 bx lr 8004724: 40002800 .word 0x40002800 8004728: 58000800 .word 0x58000800 0800472c : * @brief Handle SSR underflow interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) { 800472c: b580 push {r7, lr} 800472e: b082 sub sp, #8 8004730: af00 add r7, sp, #0 8004732: 6078 str r0, [r7, #4] if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) 8004734: 4b09 ldr r3, [pc, #36] @ (800475c ) 8004736: 6d5b ldr r3, [r3, #84] @ 0x54 8004738: f003 0340 and.w r3, r3, #64 @ 0x40 800473c: 2b00 cmp r3, #0 800473e: d005 beq.n 800474c { /* Immediately clear flags */ RTC->SCR = RTC_SCR_CSSRUF; 8004740: 4b06 ldr r3, [pc, #24] @ (800475c ) 8004742: 2240 movs r2, #64 @ 0x40 8004744: 65da str r2, [r3, #92] @ 0x5c /* SSRU callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call SSRUEvent registered Callback */ hrtc->SSRUEventCallback(hrtc); #else HAL_RTCEx_SSRUEventCallback(hrtc); 8004746: 6878 ldr r0, [r7, #4] 8004748: f7fc fcaf bl 80010aa #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; 800474c: 687b ldr r3, [r7, #4] 800474e: 2201 movs r2, #1 8004750: f883 202d strb.w r2, [r3, #45] @ 0x2d } 8004754: bf00 nop 8004756: 3708 adds r7, #8 8004758: 46bd mov sp, r7 800475a: bd80 pop {r7, pc} 800475c: 40002800 .word 0x40002800 08004760 : * @brief Alarm B callback. * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { 8004760: b480 push {r7} 8004762: b083 sub sp, #12 8004764: af00 add r7, sp, #0 8004766: 6078 str r0, [r7, #4] UNUSED(hrtc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file */ } 8004768: bf00 nop 800476a: 370c adds r7, #12 800476c: 46bd mov sp, r7 800476e: bc80 pop {r7} 8004770: 4770 bx lr ... 08004774 : * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB * @param Data Data to be written in the specified Backup data register. * @retval None */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) { 8004774: b480 push {r7} 8004776: b087 sub sp, #28 8004778: af00 add r7, sp, #0 800477a: 60f8 str r0, [r7, #12] 800477c: 60b9 str r1, [r7, #8] 800477e: 607a str r2, [r7, #4] UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t) &(TAMP->BKP0R); 8004780: 4b07 ldr r3, [pc, #28] @ (80047a0 ) 8004782: 617b str r3, [r7, #20] tmp += (BackupRegister * 4U); 8004784: 68bb ldr r3, [r7, #8] 8004786: 009b lsls r3, r3, #2 8004788: 697a ldr r2, [r7, #20] 800478a: 4413 add r3, r2 800478c: 617b str r3, [r7, #20] /* Write the specified register */ *(__IO uint32_t *)tmp = (uint32_t)Data; 800478e: 697b ldr r3, [r7, #20] 8004790: 687a ldr r2, [r7, #4] 8004792: 601a str r2, [r3, #0] } 8004794: bf00 nop 8004796: 371c adds r7, #28 8004798: 46bd mov sp, r7 800479a: bc80 pop {r7} 800479c: 4770 bx lr 800479e: bf00 nop 80047a0: 4000b100 .word 0x4000b100 080047a4 : * @param BackupRegister RTC Backup data Register number. * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB * @retval Read value */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { 80047a4: b480 push {r7} 80047a6: b085 sub sp, #20 80047a8: af00 add r7, sp, #0 80047aa: 6078 str r0, [r7, #4] 80047ac: 6039 str r1, [r7, #0] UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t) &(TAMP->BKP0R); 80047ae: 4b07 ldr r3, [pc, #28] @ (80047cc ) 80047b0: 60fb str r3, [r7, #12] tmp += (BackupRegister * 4U); 80047b2: 683b ldr r3, [r7, #0] 80047b4: 009b lsls r3, r3, #2 80047b6: 68fa ldr r2, [r7, #12] 80047b8: 4413 add r3, r2 80047ba: 60fb str r3, [r7, #12] /* Read the specified register */ return (*(__IO uint32_t *)tmp); 80047bc: 68fb ldr r3, [r7, #12] 80047be: 681b ldr r3, [r3, #0] } 80047c0: 4618 mov r0, r3 80047c2: 3714 adds r7, #20 80047c4: 46bd mov sp, r7 80047c6: bc80 pop {r7} 80047c8: 4770 bx lr 80047ca: bf00 nop 80047cc: 4000b100 .word 0x4000b100 080047d0 : { 80047d0: b480 push {r7} 80047d2: b083 sub sp, #12 80047d4: af00 add r7, sp, #0 80047d6: 6078 str r0, [r7, #4] MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); 80047d8: 4b06 ldr r3, [pc, #24] @ (80047f4 ) 80047da: 689b ldr r3, [r3, #8] 80047dc: f423 6200 bic.w r2, r3, #2048 @ 0x800 80047e0: 4904 ldr r1, [pc, #16] @ (80047f4 ) 80047e2: 687b ldr r3, [r7, #4] 80047e4: 4313 orrs r3, r2 80047e6: 608b str r3, [r1, #8] } 80047e8: bf00 nop 80047ea: 370c adds r7, #12 80047ec: 46bd mov sp, r7 80047ee: bc80 pop {r7} 80047f0: 4770 bx lr 80047f2: bf00 nop 80047f4: 58000400 .word 0x58000400 080047f8 : { 80047f8: b480 push {r7} 80047fa: af00 add r7, sp, #0 SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); 80047fc: 4b05 ldr r3, [pc, #20] @ (8004814 ) 80047fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004802: 4a04 ldr r2, [pc, #16] @ (8004814 ) 8004804: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8004808: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800480c: bf00 nop 800480e: 46bd mov sp, r7 8004810: bc80 pop {r7} 8004812: 4770 bx lr 8004814: 58000400 .word 0x58000400 08004818 : { 8004818: b480 push {r7} 800481a: af00 add r7, sp, #0 CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); 800481c: 4b05 ldr r3, [pc, #20] @ (8004834 ) 800481e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004822: 4a04 ldr r2, [pc, #16] @ (8004834 ) 8004824: f423 4300 bic.w r3, r3, #32768 @ 0x8000 8004828: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800482c: bf00 nop 800482e: 46bd mov sp, r7 8004830: bc80 pop {r7} 8004832: 4770 bx lr 8004834: 58000400 .word 0x58000400 08004838 : { 8004838: b480 push {r7} 800483a: af00 add r7, sp, #0 WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); 800483c: 4b03 ldr r3, [pc, #12] @ (800484c ) 800483e: f44f 6200 mov.w r2, #2048 @ 0x800 8004842: 619a str r2, [r3, #24] } 8004844: bf00 nop 8004846: 46bd mov sp, r7 8004848: bc80 pop {r7} 800484a: 4770 bx lr 800484c: 58000400 .word 0x58000400 08004850 : { 8004850: b480 push {r7} 8004852: af00 add r7, sp, #0 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); 8004854: 4b06 ldr r3, [pc, #24] @ (8004870 ) 8004856: 695b ldr r3, [r3, #20] 8004858: f003 0302 and.w r3, r3, #2 800485c: 2b02 cmp r3, #2 800485e: d101 bne.n 8004864 8004860: 2301 movs r3, #1 8004862: e000 b.n 8004866 8004864: 2300 movs r3, #0 } 8004866: 4618 mov r0, r3 8004868: 46bd mov sp, r7 800486a: bc80 pop {r7} 800486c: 4770 bx lr 800486e: bf00 nop 8004870: 58000400 .word 0x58000400 08004874 : { 8004874: b480 push {r7} 8004876: af00 add r7, sp, #0 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); 8004878: 4b06 ldr r3, [pc, #24] @ (8004894 ) 800487a: 695b ldr r3, [r3, #20] 800487c: f003 0304 and.w r3, r3, #4 8004880: 2b04 cmp r3, #4 8004882: d101 bne.n 8004888 8004884: 2301 movs r3, #1 8004886: e000 b.n 800488a 8004888: 2300 movs r3, #0 } 800488a: 4618 mov r0, r3 800488c: 46bd mov sp, r7 800488e: bc80 pop {r7} 8004890: 4770 bx lr 8004892: bf00 nop 8004894: 58000400 .word 0x58000400 08004898 : { 8004898: b480 push {r7} 800489a: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); 800489c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80048a0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80048a4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80048a8: f423 4300 bic.w r3, r3, #32768 @ 0x8000 80048ac: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 80048b0: bf00 nop 80048b2: 46bd mov sp, r7 80048b4: bc80 pop {r7} 80048b6: 4770 bx lr 080048b8 : { 80048b8: b480 push {r7} 80048ba: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); 80048bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80048c0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80048c4: f403 4380 and.w r3, r3, #16384 @ 0x4000 80048c8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80048cc: d101 bne.n 80048d2 80048ce: 2301 movs r3, #1 80048d0: e000 b.n 80048d4 80048d2: 2300 movs r3, #0 } 80048d4: 4618 mov r0, r3 80048d6: 46bd mov sp, r7 80048d8: bc80 pop {r7} 80048da: 4770 bx lr 080048dc : { 80048dc: b480 push {r7} 80048de: b083 sub sp, #12 80048e0: af00 add r7, sp, #0 80048e2: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); 80048e4: 4b06 ldr r3, [pc, #24] @ (8004900 ) 80048e6: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 80048ea: 4905 ldr r1, [pc, #20] @ (8004900 ) 80048ec: 687b ldr r3, [r7, #4] 80048ee: 4313 orrs r3, r2 80048f0: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 80048f4: bf00 nop 80048f6: 370c adds r7, #12 80048f8: 46bd mov sp, r7 80048fa: bc80 pop {r7} 80048fc: 4770 bx lr 80048fe: bf00 nop 8004900: 58000800 .word 0x58000800 08004904 : * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY * to avoid the reset of Radio peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) { 8004904: b580 push {r7, lr} 8004906: b084 sub sp, #16 8004908: af00 add r7, sp, #0 800490a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; __IO uint32_t count; HAL_SUBGHZ_StateTypeDef subghz_state; /* Check the hsubghz handle allocation */ if (hsubghz == NULL) 800490c: 687b ldr r3, [r7, #4] 800490e: 2b00 cmp r3, #0 8004910: d103 bne.n 800491a { status = HAL_ERROR; 8004912: 2301 movs r3, #1 8004914: 73fb strb r3, [r7, #15] return status; 8004916: 7bfb ldrb r3, [r7, #15] 8004918: e052 b.n 80049c0 } else { status = HAL_OK; 800491a: 2300 movs r3, #0 800491c: 73fb strb r3, [r7, #15] } assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); subghz_state = hsubghz->State; 800491e: 687b ldr r3, [r7, #4] 8004920: 799b ldrb r3, [r3, #6] 8004922: 73bb strb r3, [r7, #14] if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || 8004924: 7bbb ldrb r3, [r7, #14] 8004926: 2b00 cmp r3, #0 8004928: d002 beq.n 8004930 800492a: 7bbb ldrb r3, [r7, #14] 800492c: 2b03 cmp r3, #3 800492e: d109 bne.n 8004944 (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) { /* Allocate lock resource and initialize it */ hsubghz->Lock = HAL_UNLOCKED; 8004930: 687b ldr r3, [r7, #4] 8004932: 2200 movs r2, #0 8004934: 715a strb r2, [r3, #5] /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hsubghz->MspInitCallback(hsubghz); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SUBGHZ_MspInit(hsubghz); 8004936: 6878 ldr r0, [r7, #4] 8004938: f7fc f8e6 bl 8000b08 #if defined(CORE_CM0PLUS) /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); #else /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); 800493c: f44f 5080 mov.w r0, #4096 @ 0x1000 8004940: f7ff ffcc bl 80048dc #endif /* CORE_CM0PLUS */ } if (subghz_state == HAL_SUBGHZ_STATE_RESET) 8004944: 7bbb ldrb r3, [r7, #14] 8004946: 2b00 cmp r3, #0 8004948: d126 bne.n 8004998 { /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ hsubghz->State = HAL_SUBGHZ_STATE_BUSY; 800494a: 687b ldr r3, [r7, #4] 800494c: 2202 movs r2, #2 800494e: 719a strb r2, [r3, #6] /* De-asserts the reset signal of the Radio peripheral */ LL_RCC_RF_DisableReset(); 8004950: f7ff ffa2 bl 8004898 /* Verify that Radio in reset status flag is set */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; 8004954: 4b1c ldr r3, [pc, #112] @ (80049c8 ) 8004956: 681a ldr r2, [r3, #0] 8004958: 4613 mov r3, r2 800495a: 00db lsls r3, r3, #3 800495c: 1a9b subs r3, r3, r2 800495e: 009b lsls r3, r3, #2 8004960: 0cdb lsrs r3, r3, #19 8004962: 2264 movs r2, #100 @ 0x64 8004964: fb02 f303 mul.w r3, r2, r3 8004968: 60bb str r3, [r7, #8] do { if (count == 0U) 800496a: 68bb ldr r3, [r7, #8] 800496c: 2b00 cmp r3, #0 800496e: d105 bne.n 800497c { status = HAL_ERROR; 8004970: 2301 movs r3, #1 8004972: 73fb strb r3, [r7, #15] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; 8004974: 687b ldr r3, [r7, #4] 8004976: 2201 movs r2, #1 8004978: 609a str r2, [r3, #8] break; 800497a: e007 b.n 800498c } count--; 800497c: 68bb ldr r3, [r7, #8] 800497e: 3b01 subs r3, #1 8004980: 60bb str r3, [r7, #8] } while (LL_RCC_IsRFUnderReset() != 0UL); 8004982: f7ff ff99 bl 80048b8 8004986: 4603 mov r3, r0 8004988: 2b00 cmp r3, #0 800498a: d1ee bne.n 800496a /* Asserts the reset signal of the Radio peripheral */ LL_PWR_UnselectSUBGHZSPI_NSS(); 800498c: f7ff ff34 bl 80047f8 #if defined(CORE_CM0PLUS) /* Enable wakeup signal of the Radio peripheral */ LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); #else /* Enable wakeup signal of the Radio peripheral */ LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); 8004990: f44f 6000 mov.w r0, #2048 @ 0x800 8004994: f7ff ff1c bl 80047d0 #endif /* CORE_CM0PLUS */ } /* Clear Pending Flag */ LL_PWR_ClearFlag_RFBUSY(); 8004998: f7ff ff4e bl 8004838 if (status == HAL_OK) 800499c: 7bfb ldrb r3, [r7, #15] 800499e: 2b00 cmp r3, #0 80049a0: d10a bne.n 80049b8 { /* Initialize SUBGHZSPI Peripheral */ SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); 80049a2: 687b ldr r3, [r7, #4] 80049a4: 681b ldr r3, [r3, #0] 80049a6: 4618 mov r0, r3 80049a8: f000 fac2 bl 8004f30 hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; 80049ac: 687b ldr r3, [r7, #4] 80049ae: 2201 movs r2, #1 80049b0: 711a strb r2, [r3, #4] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; 80049b2: 687b ldr r3, [r7, #4] 80049b4: 2200 movs r2, #0 80049b6: 609a str r2, [r3, #8] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 80049b8: 687b ldr r3, [r7, #4] 80049ba: 2201 movs r2, #1 80049bc: 719a strb r2, [r3, #6] return status; 80049be: 7bfb ldrb r3, [r7, #15] } 80049c0: 4618 mov r0, r3 80049c2: 3710 adds r7, #16 80049c4: 46bd mov sp, r7 80049c6: bd80 pop {r7, pc} 80049c8: 20000000 .word 0x20000000 080049cc : */ HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer, uint16_t Size) { 80049cc: b580 push {r7, lr} 80049ce: b086 sub sp, #24 80049d0: af00 add r7, sp, #0 80049d2: 60f8 str r0, [r7, #12] 80049d4: 607a str r2, [r7, #4] 80049d6: 461a mov r2, r3 80049d8: 460b mov r3, r1 80049da: 817b strh r3, [r7, #10] 80049dc: 4613 mov r3, r2 80049de: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 80049e0: 68fb ldr r3, [r7, #12] 80049e2: 799b ldrb r3, [r3, #6] 80049e4: b2db uxtb r3, r3 80049e6: 2b01 cmp r3, #1 80049e8: d14a bne.n 8004a80 { /* Process Locked */ __HAL_LOCK(hsubghz); 80049ea: 68fb ldr r3, [r7, #12] 80049ec: 795b ldrb r3, [r3, #5] 80049ee: 2b01 cmp r3, #1 80049f0: d101 bne.n 80049f6 80049f2: 2302 movs r3, #2 80049f4: e045 b.n 8004a82 80049f6: 68fb ldr r3, [r7, #12] 80049f8: 2201 movs r2, #1 80049fa: 715a strb r2, [r3, #5] hsubghz->State = HAL_SUBGHZ_STATE_BUSY; 80049fc: 68fb ldr r3, [r7, #12] 80049fe: 2202 movs r2, #2 8004a00: 719a strb r2, [r3, #6] (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004a02: 68f8 ldr r0, [r7, #12] 8004a04: f000 fb62 bl 80050cc /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004a08: f7ff ff06 bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER); 8004a0c: 210d movs r1, #13 8004a0e: 68f8 ldr r0, [r7, #12] 8004a10: f000 faae bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); 8004a14: 897b ldrh r3, [r7, #10] 8004a16: 0a1b lsrs r3, r3, #8 8004a18: b29b uxth r3, r3 8004a1a: b2db uxtb r3, r3 8004a1c: 4619 mov r1, r3 8004a1e: 68f8 ldr r0, [r7, #12] 8004a20: f000 faa6 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); 8004a24: 897b ldrh r3, [r7, #10] 8004a26: b2db uxtb r3, r3 8004a28: 4619 mov r1, r3 8004a2a: 68f8 ldr r0, [r7, #12] 8004a2c: f000 faa0 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004a30: 2300 movs r3, #0 8004a32: 82bb strh r3, [r7, #20] 8004a34: e00a b.n 8004a4c { (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); 8004a36: 8abb ldrh r3, [r7, #20] 8004a38: 687a ldr r2, [r7, #4] 8004a3a: 4413 add r3, r2 8004a3c: 781b ldrb r3, [r3, #0] 8004a3e: 4619 mov r1, r3 8004a40: 68f8 ldr r0, [r7, #12] 8004a42: f000 fa95 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004a46: 8abb ldrh r3, [r7, #20] 8004a48: 3301 adds r3, #1 8004a4a: 82bb strh r3, [r7, #20] 8004a4c: 8aba ldrh r2, [r7, #20] 8004a4e: 893b ldrh r3, [r7, #8] 8004a50: 429a cmp r2, r3 8004a52: d3f0 bcc.n 8004a36 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004a54: f7ff fed0 bl 80047f8 (void)SUBGHZ_WaitOnBusy(hsubghz); 8004a58: 68f8 ldr r0, [r7, #12] 8004a5a: f000 fb57 bl 800510c if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004a5e: 68fb ldr r3, [r7, #12] 8004a60: 689b ldr r3, [r3, #8] 8004a62: 2b00 cmp r3, #0 8004a64: d002 beq.n 8004a6c { status = HAL_ERROR; 8004a66: 2301 movs r3, #1 8004a68: 75fb strb r3, [r7, #23] 8004a6a: e001 b.n 8004a70 } else { status = HAL_OK; 8004a6c: 2300 movs r3, #0 8004a6e: 75fb strb r3, [r7, #23] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004a70: 68fb ldr r3, [r7, #12] 8004a72: 2201 movs r2, #1 8004a74: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004a76: 68fb ldr r3, [r7, #12] 8004a78: 2200 movs r2, #0 8004a7a: 715a strb r2, [r3, #5] return status; 8004a7c: 7dfb ldrb r3, [r7, #23] 8004a7e: e000 b.n 8004a82 } else { return HAL_BUSY; 8004a80: 2302 movs r3, #2 } } 8004a82: 4618 mov r0, r3 8004a84: 3718 adds r7, #24 8004a86: 46bd mov sp, r7 8004a88: bd80 pop {r7, pc} 08004a8a : */ HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer, uint16_t Size) { 8004a8a: b580 push {r7, lr} 8004a8c: b088 sub sp, #32 8004a8e: af00 add r7, sp, #0 8004a90: 60f8 str r0, [r7, #12] 8004a92: 607a str r2, [r7, #4] 8004a94: 461a mov r2, r3 8004a96: 460b mov r3, r1 8004a98: 817b strh r3, [r7, #10] 8004a9a: 4613 mov r3, r2 8004a9c: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; uint8_t *pData = pBuffer; 8004a9e: 687b ldr r3, [r7, #4] 8004aa0: 61bb str r3, [r7, #24] if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 8004aa2: 68fb ldr r3, [r7, #12] 8004aa4: 799b ldrb r3, [r3, #6] 8004aa6: b2db uxtb r3, r3 8004aa8: 2b01 cmp r3, #1 8004aaa: d14a bne.n 8004b42 { /* Process Locked */ __HAL_LOCK(hsubghz); 8004aac: 68fb ldr r3, [r7, #12] 8004aae: 795b ldrb r3, [r3, #5] 8004ab0: 2b01 cmp r3, #1 8004ab2: d101 bne.n 8004ab8 8004ab4: 2302 movs r3, #2 8004ab6: e045 b.n 8004b44 8004ab8: 68fb ldr r3, [r7, #12] 8004aba: 2201 movs r2, #1 8004abc: 715a strb r2, [r3, #5] (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004abe: 68f8 ldr r0, [r7, #12] 8004ac0: f000 fb04 bl 80050cc /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004ac4: f7ff fea8 bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER); 8004ac8: 211d movs r1, #29 8004aca: 68f8 ldr r0, [r7, #12] 8004acc: f000 fa50 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); 8004ad0: 897b ldrh r3, [r7, #10] 8004ad2: 0a1b lsrs r3, r3, #8 8004ad4: b29b uxth r3, r3 8004ad6: b2db uxtb r3, r3 8004ad8: 4619 mov r1, r3 8004ada: 68f8 ldr r0, [r7, #12] 8004adc: f000 fa48 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); 8004ae0: 897b ldrh r3, [r7, #10] 8004ae2: b2db uxtb r3, r3 8004ae4: 4619 mov r1, r3 8004ae6: 68f8 ldr r0, [r7, #12] 8004ae8: f000 fa42 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, 0U); 8004aec: 2100 movs r1, #0 8004aee: 68f8 ldr r0, [r7, #12] 8004af0: f000 fa3e bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004af4: 2300 movs r3, #0 8004af6: 82fb strh r3, [r7, #22] 8004af8: e009 b.n 8004b0e { (void)SUBGHZSPI_Receive(hsubghz, (pData)); 8004afa: 69b9 ldr r1, [r7, #24] 8004afc: 68f8 ldr r0, [r7, #12] 8004afe: f000 fa8d bl 800501c pData++; 8004b02: 69bb ldr r3, [r7, #24] 8004b04: 3301 adds r3, #1 8004b06: 61bb str r3, [r7, #24] for (uint16_t i = 0U; i < Size; i++) 8004b08: 8afb ldrh r3, [r7, #22] 8004b0a: 3301 adds r3, #1 8004b0c: 82fb strh r3, [r7, #22] 8004b0e: 8afa ldrh r2, [r7, #22] 8004b10: 893b ldrh r3, [r7, #8] 8004b12: 429a cmp r2, r3 8004b14: d3f1 bcc.n 8004afa } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004b16: f7ff fe6f bl 80047f8 (void)SUBGHZ_WaitOnBusy(hsubghz); 8004b1a: 68f8 ldr r0, [r7, #12] 8004b1c: f000 faf6 bl 800510c if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004b20: 68fb ldr r3, [r7, #12] 8004b22: 689b ldr r3, [r3, #8] 8004b24: 2b00 cmp r3, #0 8004b26: d002 beq.n 8004b2e { status = HAL_ERROR; 8004b28: 2301 movs r3, #1 8004b2a: 77fb strb r3, [r7, #31] 8004b2c: e001 b.n 8004b32 } else { status = HAL_OK; 8004b2e: 2300 movs r3, #0 8004b30: 77fb strb r3, [r7, #31] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004b32: 68fb ldr r3, [r7, #12] 8004b34: 2201 movs r2, #1 8004b36: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004b38: 68fb ldr r3, [r7, #12] 8004b3a: 2200 movs r2, #0 8004b3c: 715a strb r2, [r3, #5] return status; 8004b3e: 7ffb ldrb r3, [r7, #31] 8004b40: e000 b.n 8004b44 } else { return HAL_BUSY; 8004b42: 2302 movs r3, #2 } } 8004b44: 4618 mov r0, r3 8004b46: 3720 adds r7, #32 8004b48: 46bd mov sp, r7 8004b4a: bd80 pop {r7, pc} 08004b4c : */ HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, uint16_t Size) { 8004b4c: b580 push {r7, lr} 8004b4e: b086 sub sp, #24 8004b50: af00 add r7, sp, #0 8004b52: 60f8 str r0, [r7, #12] 8004b54: 607a str r2, [r7, #4] 8004b56: 461a mov r2, r3 8004b58: 460b mov r3, r1 8004b5a: 72fb strb r3, [r7, #11] 8004b5c: 4613 mov r3, r2 8004b5e: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; /* LORA Modulation not available on STM32WLx4xx devices */ assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 8004b60: 68fb ldr r3, [r7, #12] 8004b62: 799b ldrb r3, [r3, #6] 8004b64: b2db uxtb r3, r3 8004b66: 2b01 cmp r3, #1 8004b68: d14a bne.n 8004c00 { /* Process Locked */ __HAL_LOCK(hsubghz); 8004b6a: 68fb ldr r3, [r7, #12] 8004b6c: 795b ldrb r3, [r3, #5] 8004b6e: 2b01 cmp r3, #1 8004b70: d101 bne.n 8004b76 8004b72: 2302 movs r3, #2 8004b74: e045 b.n 8004c02 8004b76: 68fb ldr r3, [r7, #12] 8004b78: 2201 movs r2, #1 8004b7a: 715a strb r2, [r3, #5] /* Need to wakeup Radio if already in Sleep at startup */ (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004b7c: 68f8 ldr r0, [r7, #12] 8004b7e: f000 faa5 bl 80050cc if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) 8004b82: 7afb ldrb r3, [r7, #11] 8004b84: 2b84 cmp r3, #132 @ 0x84 8004b86: d002 beq.n 8004b8e 8004b88: 7afb ldrb r3, [r7, #11] 8004b8a: 2b94 cmp r3, #148 @ 0x94 8004b8c: d103 bne.n 8004b96 { hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; 8004b8e: 68fb ldr r3, [r7, #12] 8004b90: 2201 movs r2, #1 8004b92: 711a strb r2, [r3, #4] 8004b94: e002 b.n 8004b9c } else { hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; 8004b96: 68fb ldr r3, [r7, #12] 8004b98: 2200 movs r2, #0 8004b9a: 711a strb r2, [r3, #4] } /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004b9c: f7ff fe3c bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); 8004ba0: 7afb ldrb r3, [r7, #11] 8004ba2: 4619 mov r1, r3 8004ba4: 68f8 ldr r0, [r7, #12] 8004ba6: f000 f9e3 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004baa: 2300 movs r3, #0 8004bac: 82bb strh r3, [r7, #20] 8004bae: e00a b.n 8004bc6 { (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); 8004bb0: 8abb ldrh r3, [r7, #20] 8004bb2: 687a ldr r2, [r7, #4] 8004bb4: 4413 add r3, r2 8004bb6: 781b ldrb r3, [r3, #0] 8004bb8: 4619 mov r1, r3 8004bba: 68f8 ldr r0, [r7, #12] 8004bbc: f000 f9d8 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004bc0: 8abb ldrh r3, [r7, #20] 8004bc2: 3301 adds r3, #1 8004bc4: 82bb strh r3, [r7, #20] 8004bc6: 8aba ldrh r2, [r7, #20] 8004bc8: 893b ldrh r3, [r7, #8] 8004bca: 429a cmp r2, r3 8004bcc: d3f0 bcc.n 8004bb0 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004bce: f7ff fe13 bl 80047f8 if (Command != RADIO_SET_SLEEP) 8004bd2: 7afb ldrb r3, [r7, #11] 8004bd4: 2b84 cmp r3, #132 @ 0x84 8004bd6: d002 beq.n 8004bde { (void)SUBGHZ_WaitOnBusy(hsubghz); 8004bd8: 68f8 ldr r0, [r7, #12] 8004bda: f000 fa97 bl 800510c } if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004bde: 68fb ldr r3, [r7, #12] 8004be0: 689b ldr r3, [r3, #8] 8004be2: 2b00 cmp r3, #0 8004be4: d002 beq.n 8004bec { status = HAL_ERROR; 8004be6: 2301 movs r3, #1 8004be8: 75fb strb r3, [r7, #23] 8004bea: e001 b.n 8004bf0 } else { status = HAL_OK; 8004bec: 2300 movs r3, #0 8004bee: 75fb strb r3, [r7, #23] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004bf0: 68fb ldr r3, [r7, #12] 8004bf2: 2201 movs r2, #1 8004bf4: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004bf6: 68fb ldr r3, [r7, #12] 8004bf8: 2200 movs r2, #0 8004bfa: 715a strb r2, [r3, #5] return status; 8004bfc: 7dfb ldrb r3, [r7, #23] 8004bfe: e000 b.n 8004c02 } else { return HAL_BUSY; 8004c00: 2302 movs r3, #2 } } 8004c02: 4618 mov r0, r3 8004c04: 3718 adds r7, #24 8004c06: 46bd mov sp, r7 8004c08: bd80 pop {r7, pc} 08004c0a : */ HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, uint16_t Size) { 8004c0a: b580 push {r7, lr} 8004c0c: b088 sub sp, #32 8004c0e: af00 add r7, sp, #0 8004c10: 60f8 str r0, [r7, #12] 8004c12: 607a str r2, [r7, #4] 8004c14: 461a mov r2, r3 8004c16: 460b mov r3, r1 8004c18: 72fb strb r3, [r7, #11] 8004c1a: 4613 mov r3, r2 8004c1c: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; uint8_t *pData = pBuffer; 8004c1e: 687b ldr r3, [r7, #4] 8004c20: 61bb str r3, [r7, #24] if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 8004c22: 68fb ldr r3, [r7, #12] 8004c24: 799b ldrb r3, [r3, #6] 8004c26: b2db uxtb r3, r3 8004c28: 2b01 cmp r3, #1 8004c2a: d13d bne.n 8004ca8 { /* Process Locked */ __HAL_LOCK(hsubghz); 8004c2c: 68fb ldr r3, [r7, #12] 8004c2e: 795b ldrb r3, [r3, #5] 8004c30: 2b01 cmp r3, #1 8004c32: d101 bne.n 8004c38 8004c34: 2302 movs r3, #2 8004c36: e038 b.n 8004caa 8004c38: 68fb ldr r3, [r7, #12] 8004c3a: 2201 movs r2, #1 8004c3c: 715a strb r2, [r3, #5] (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004c3e: 68f8 ldr r0, [r7, #12] 8004c40: f000 fa44 bl 80050cc /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004c44: f7ff fde8 bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); 8004c48: 7afb ldrb r3, [r7, #11] 8004c4a: 4619 mov r1, r3 8004c4c: 68f8 ldr r0, [r7, #12] 8004c4e: f000 f98f bl 8004f70 /* Use to flush the Status (First byte) receive from SUBGHZ as not use */ (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); 8004c52: 2100 movs r1, #0 8004c54: 68f8 ldr r0, [r7, #12] 8004c56: f000 f98b bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004c5a: 2300 movs r3, #0 8004c5c: 82fb strh r3, [r7, #22] 8004c5e: e009 b.n 8004c74 { (void)SUBGHZSPI_Receive(hsubghz, (pData)); 8004c60: 69b9 ldr r1, [r7, #24] 8004c62: 68f8 ldr r0, [r7, #12] 8004c64: f000 f9da bl 800501c pData++; 8004c68: 69bb ldr r3, [r7, #24] 8004c6a: 3301 adds r3, #1 8004c6c: 61bb str r3, [r7, #24] for (uint16_t i = 0U; i < Size; i++) 8004c6e: 8afb ldrh r3, [r7, #22] 8004c70: 3301 adds r3, #1 8004c72: 82fb strh r3, [r7, #22] 8004c74: 8afa ldrh r2, [r7, #22] 8004c76: 893b ldrh r3, [r7, #8] 8004c78: 429a cmp r2, r3 8004c7a: d3f1 bcc.n 8004c60 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004c7c: f7ff fdbc bl 80047f8 (void)SUBGHZ_WaitOnBusy(hsubghz); 8004c80: 68f8 ldr r0, [r7, #12] 8004c82: f000 fa43 bl 800510c if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004c86: 68fb ldr r3, [r7, #12] 8004c88: 689b ldr r3, [r3, #8] 8004c8a: 2b00 cmp r3, #0 8004c8c: d002 beq.n 8004c94 { status = HAL_ERROR; 8004c8e: 2301 movs r3, #1 8004c90: 77fb strb r3, [r7, #31] 8004c92: e001 b.n 8004c98 } else { status = HAL_OK; 8004c94: 2300 movs r3, #0 8004c96: 77fb strb r3, [r7, #31] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004c98: 68fb ldr r3, [r7, #12] 8004c9a: 2201 movs r2, #1 8004c9c: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004c9e: 68fb ldr r3, [r7, #12] 8004ca0: 2200 movs r2, #0 8004ca2: 715a strb r2, [r3, #5] return status; 8004ca4: 7ffb ldrb r3, [r7, #31] 8004ca6: e000 b.n 8004caa } else { return HAL_BUSY; 8004ca8: 2302 movs r3, #2 } } 8004caa: 4618 mov r0, r3 8004cac: 3720 adds r7, #32 8004cae: 46bd mov sp, r7 8004cb0: bd80 pop {r7, pc} 08004cb2 : */ HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer, uint16_t Size) { 8004cb2: b580 push {r7, lr} 8004cb4: b086 sub sp, #24 8004cb6: af00 add r7, sp, #0 8004cb8: 60f8 str r0, [r7, #12] 8004cba: 607a str r2, [r7, #4] 8004cbc: 461a mov r2, r3 8004cbe: 460b mov r3, r1 8004cc0: 72fb strb r3, [r7, #11] 8004cc2: 4613 mov r3, r2 8004cc4: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 8004cc6: 68fb ldr r3, [r7, #12] 8004cc8: 799b ldrb r3, [r3, #6] 8004cca: b2db uxtb r3, r3 8004ccc: 2b01 cmp r3, #1 8004cce: d13e bne.n 8004d4e { /* Process Locked */ __HAL_LOCK(hsubghz); 8004cd0: 68fb ldr r3, [r7, #12] 8004cd2: 795b ldrb r3, [r3, #5] 8004cd4: 2b01 cmp r3, #1 8004cd6: d101 bne.n 8004cdc 8004cd8: 2302 movs r3, #2 8004cda: e039 b.n 8004d50 8004cdc: 68fb ldr r3, [r7, #12] 8004cde: 2201 movs r2, #1 8004ce0: 715a strb r2, [r3, #5] (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004ce2: 68f8 ldr r0, [r7, #12] 8004ce4: f000 f9f2 bl 80050cc /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004ce8: f7ff fd96 bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER); 8004cec: 210e movs r1, #14 8004cee: 68f8 ldr r0, [r7, #12] 8004cf0: f000 f93e bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, Offset); 8004cf4: 7afb ldrb r3, [r7, #11] 8004cf6: 4619 mov r1, r3 8004cf8: 68f8 ldr r0, [r7, #12] 8004cfa: f000 f939 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004cfe: 2300 movs r3, #0 8004d00: 82bb strh r3, [r7, #20] 8004d02: e00a b.n 8004d1a { (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); 8004d04: 8abb ldrh r3, [r7, #20] 8004d06: 687a ldr r2, [r7, #4] 8004d08: 4413 add r3, r2 8004d0a: 781b ldrb r3, [r3, #0] 8004d0c: 4619 mov r1, r3 8004d0e: 68f8 ldr r0, [r7, #12] 8004d10: f000 f92e bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004d14: 8abb ldrh r3, [r7, #20] 8004d16: 3301 adds r3, #1 8004d18: 82bb strh r3, [r7, #20] 8004d1a: 8aba ldrh r2, [r7, #20] 8004d1c: 893b ldrh r3, [r7, #8] 8004d1e: 429a cmp r2, r3 8004d20: d3f0 bcc.n 8004d04 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004d22: f7ff fd69 bl 80047f8 (void)SUBGHZ_WaitOnBusy(hsubghz); 8004d26: 68f8 ldr r0, [r7, #12] 8004d28: f000 f9f0 bl 800510c if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004d2c: 68fb ldr r3, [r7, #12] 8004d2e: 689b ldr r3, [r3, #8] 8004d30: 2b00 cmp r3, #0 8004d32: d002 beq.n 8004d3a { status = HAL_ERROR; 8004d34: 2301 movs r3, #1 8004d36: 75fb strb r3, [r7, #23] 8004d38: e001 b.n 8004d3e } else { status = HAL_OK; 8004d3a: 2300 movs r3, #0 8004d3c: 75fb strb r3, [r7, #23] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004d3e: 68fb ldr r3, [r7, #12] 8004d40: 2201 movs r2, #1 8004d42: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004d44: 68fb ldr r3, [r7, #12] 8004d46: 2200 movs r2, #0 8004d48: 715a strb r2, [r3, #5] return status; 8004d4a: 7dfb ldrb r3, [r7, #23] 8004d4c: e000 b.n 8004d50 } else { return HAL_BUSY; 8004d4e: 2302 movs r3, #2 } } 8004d50: 4618 mov r0, r3 8004d52: 3718 adds r7, #24 8004d54: 46bd mov sp, r7 8004d56: bd80 pop {r7, pc} 08004d58 : */ HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer, uint16_t Size) { 8004d58: b580 push {r7, lr} 8004d5a: b088 sub sp, #32 8004d5c: af00 add r7, sp, #0 8004d5e: 60f8 str r0, [r7, #12] 8004d60: 607a str r2, [r7, #4] 8004d62: 461a mov r2, r3 8004d64: 460b mov r3, r1 8004d66: 72fb strb r3, [r7, #11] 8004d68: 4613 mov r3, r2 8004d6a: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; uint8_t *pData = pBuffer; 8004d6c: 687b ldr r3, [r7, #4] 8004d6e: 61bb str r3, [r7, #24] if (hsubghz->State == HAL_SUBGHZ_STATE_READY) 8004d70: 68fb ldr r3, [r7, #12] 8004d72: 799b ldrb r3, [r3, #6] 8004d74: b2db uxtb r3, r3 8004d76: 2b01 cmp r3, #1 8004d78: d141 bne.n 8004dfe { /* Process Locked */ __HAL_LOCK(hsubghz); 8004d7a: 68fb ldr r3, [r7, #12] 8004d7c: 795b ldrb r3, [r3, #5] 8004d7e: 2b01 cmp r3, #1 8004d80: d101 bne.n 8004d86 8004d82: 2302 movs r3, #2 8004d84: e03c b.n 8004e00 8004d86: 68fb ldr r3, [r7, #12] 8004d88: 2201 movs r2, #1 8004d8a: 715a strb r2, [r3, #5] (void)SUBGHZ_CheckDeviceReady(hsubghz); 8004d8c: 68f8 ldr r0, [r7, #12] 8004d8e: f000 f99d bl 80050cc /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); 8004d92: f7ff fd41 bl 8004818 (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER); 8004d96: 211e movs r1, #30 8004d98: 68f8 ldr r0, [r7, #12] 8004d9a: f000 f8e9 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, Offset); 8004d9e: 7afb ldrb r3, [r7, #11] 8004da0: 4619 mov r1, r3 8004da2: 68f8 ldr r0, [r7, #12] 8004da4: f000 f8e4 bl 8004f70 (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); 8004da8: 2100 movs r1, #0 8004daa: 68f8 ldr r0, [r7, #12] 8004dac: f000 f8e0 bl 8004f70 for (uint16_t i = 0U; i < Size; i++) 8004db0: 2300 movs r3, #0 8004db2: 82fb strh r3, [r7, #22] 8004db4: e009 b.n 8004dca { (void)SUBGHZSPI_Receive(hsubghz, (pData)); 8004db6: 69b9 ldr r1, [r7, #24] 8004db8: 68f8 ldr r0, [r7, #12] 8004dba: f000 f92f bl 800501c pData++; 8004dbe: 69bb ldr r3, [r7, #24] 8004dc0: 3301 adds r3, #1 8004dc2: 61bb str r3, [r7, #24] for (uint16_t i = 0U; i < Size; i++) 8004dc4: 8afb ldrh r3, [r7, #22] 8004dc6: 3301 adds r3, #1 8004dc8: 82fb strh r3, [r7, #22] 8004dca: 8afa ldrh r2, [r7, #22] 8004dcc: 893b ldrh r3, [r7, #8] 8004dce: 429a cmp r2, r3 8004dd0: d3f1 bcc.n 8004db6 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 8004dd2: f7ff fd11 bl 80047f8 (void)SUBGHZ_WaitOnBusy(hsubghz); 8004dd6: 68f8 ldr r0, [r7, #12] 8004dd8: f000 f998 bl 800510c if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) 8004ddc: 68fb ldr r3, [r7, #12] 8004dde: 689b ldr r3, [r3, #8] 8004de0: 2b00 cmp r3, #0 8004de2: d002 beq.n 8004dea { status = HAL_ERROR; 8004de4: 2301 movs r3, #1 8004de6: 77fb strb r3, [r7, #31] 8004de8: e001 b.n 8004dee } else { status = HAL_OK; 8004dea: 2300 movs r3, #0 8004dec: 77fb strb r3, [r7, #31] } hsubghz->State = HAL_SUBGHZ_STATE_READY; 8004dee: 68fb ldr r3, [r7, #12] 8004df0: 2201 movs r2, #1 8004df2: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); 8004df4: 68fb ldr r3, [r7, #12] 8004df6: 2200 movs r2, #0 8004df8: 715a strb r2, [r3, #5] return status; 8004dfa: 7ffb ldrb r3, [r7, #31] 8004dfc: e000 b.n 8004e00 } else { return HAL_BUSY; 8004dfe: 2302 movs r3, #2 } } 8004e00: 4618 mov r0, r3 8004e02: 3720 adds r7, #32 8004e04: 46bd mov sp, r7 8004e06: bd80 pop {r7, pc} 08004e08 : * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the configuration information for the specified SUBGHZ module. * @retval None */ void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) { 8004e08: b580 push {r7, lr} 8004e0a: b084 sub sp, #16 8004e0c: af00 add r7, sp, #0 8004e0e: 6078 str r0, [r7, #4] uint8_t tmpisr[2U] = {0U}; 8004e10: 2300 movs r3, #0 8004e12: 81bb strh r3, [r7, #12] uint16_t itsource; /* Retrieve Interrupts from SUBGHZ Irq Register */ (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); 8004e14: f107 020c add.w r2, r7, #12 8004e18: 2302 movs r3, #2 8004e1a: 2112 movs r1, #18 8004e1c: 6878 ldr r0, [r7, #4] 8004e1e: f7ff fef4 bl 8004c0a itsource = tmpisr[0U]; 8004e22: 7b3b ldrb r3, [r7, #12] 8004e24: 81fb strh r3, [r7, #14] itsource = (itsource << 8U) | tmpisr[1U]; 8004e26: f9b7 300e ldrsh.w r3, [r7, #14] 8004e2a: 021b lsls r3, r3, #8 8004e2c: b21a sxth r2, r3 8004e2e: 7b7b ldrb r3, [r7, #13] 8004e30: b21b sxth r3, r3 8004e32: 4313 orrs r3, r2 8004e34: b21b sxth r3, r3 8004e36: 81fb strh r3, [r7, #14] /* Clear SUBGHZ Irq Register */ (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); 8004e38: f107 020c add.w r2, r7, #12 8004e3c: 2302 movs r3, #2 8004e3e: 2102 movs r1, #2 8004e40: 6878 ldr r0, [r7, #4] 8004e42: f7ff fe83 bl 8004b4c /* Packet transmission completed Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) 8004e46: 89fb ldrh r3, [r7, #14] 8004e48: f003 0301 and.w r3, r3, #1 8004e4c: 2b00 cmp r3, #0 8004e4e: d002 beq.n 8004e56 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->TxCpltCallback(hsubghz); #else HAL_SUBGHZ_TxCpltCallback(hsubghz); 8004e50: 6878 ldr r0, [r7, #4] 8004e52: f005 fdcd bl 800a9f0 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Packet received Interrupt */ if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET)) 8004e56: 89fb ldrh r3, [r7, #14] 8004e58: 085b lsrs r3, r3, #1 8004e5a: f003 0301 and.w r3, r3, #1 8004e5e: 2b00 cmp r3, #0 8004e60: d00e beq.n 8004e80 { if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) 8004e62: 89fb ldrh r3, [r7, #14] 8004e64: 099b lsrs r3, r3, #6 8004e66: f003 0301 and.w r3, r3, #1 8004e6a: 2b00 cmp r3, #0 8004e6c: d005 beq.n 8004e7a { hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_CRC_MISMATCH; 8004e6e: 687b ldr r3, [r7, #4] 8004e70: 689b ldr r3, [r3, #8] 8004e72: f043 0204 orr.w r2, r3, #4 8004e76: 687b ldr r3, [r7, #4] 8004e78: 609a str r2, [r3, #8] } #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->RxCpltCallback(hsubghz); #else HAL_SUBGHZ_RxCpltCallback(hsubghz); 8004e7a: 6878 ldr r0, [r7, #4] 8004e7c: f005 fdc6 bl 800aa0c #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Preamble Detected Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET) 8004e80: 89fb ldrh r3, [r7, #14] 8004e82: 089b lsrs r3, r3, #2 8004e84: f003 0301 and.w r3, r3, #1 8004e88: 2b00 cmp r3, #0 8004e8a: d002 beq.n 8004e92 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->PreambleDetectedCallback(hsubghz); #else HAL_SUBGHZ_PreambleDetectedCallback(hsubghz); 8004e8c: 6878 ldr r0, [r7, #4] 8004e8e: f005 fe15 bl 800aabc #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Valid sync word detected Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET) 8004e92: 89fb ldrh r3, [r7, #14] 8004e94: 08db lsrs r3, r3, #3 8004e96: f003 0301 and.w r3, r3, #1 8004e9a: 2b00 cmp r3, #0 8004e9c: d002 beq.n 8004ea4 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->SyncWordValidCallback(hsubghz); #else HAL_SUBGHZ_SyncWordValidCallback(hsubghz); 8004e9e: 6878 ldr r0, [r7, #4] 8004ea0: f005 fe1a bl 800aad8 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Valid LoRa header received Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET) 8004ea4: 89fb ldrh r3, [r7, #14] 8004ea6: 091b lsrs r3, r3, #4 8004ea8: f003 0301 and.w r3, r3, #1 8004eac: 2b00 cmp r3, #0 8004eae: d002 beq.n 8004eb6 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->HeaderValidCallback(hsubghz); #else HAL_SUBGHZ_HeaderValidCallback(hsubghz); 8004eb0: 6878 ldr r0, [r7, #4] 8004eb2: f005 fe1f bl 800aaf4 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* LoRa header CRC error Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET) 8004eb6: 89fb ldrh r3, [r7, #14] 8004eb8: 095b lsrs r3, r3, #5 8004eba: f003 0301 and.w r3, r3, #1 8004ebe: 2b00 cmp r3, #0 8004ec0: d002 beq.n 8004ec8 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->HeaderErrorCallback(hsubghz); #else HAL_SUBGHZ_HeaderErrorCallback(hsubghz); 8004ec2: 6878 ldr r0, [r7, #4] 8004ec4: f005 fdec bl 800aaa0 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Wrong CRC received Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) 8004ec8: 89fb ldrh r3, [r7, #14] 8004eca: 099b lsrs r3, r3, #6 8004ecc: f003 0301 and.w r3, r3, #1 8004ed0: 2b00 cmp r3, #0 8004ed2: d002 beq.n 8004eda { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->CRCErrorCallback(hsubghz); #else HAL_SUBGHZ_CRCErrorCallback(hsubghz); 8004ed4: 6878 ldr r0, [r7, #4] 8004ed6: f005 fda7 bl 800aa28 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Channel activity detection finished Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET) 8004eda: 89fb ldrh r3, [r7, #14] 8004edc: 09db lsrs r3, r3, #7 8004ede: f003 0301 and.w r3, r3, #1 8004ee2: 2b00 cmp r3, #0 8004ee4: d00e beq.n 8004f04 { hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); } #else /* Channel activity Detected Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) 8004ee6: 89fb ldrh r3, [r7, #14] 8004ee8: 0a1b lsrs r3, r3, #8 8004eea: f003 0301 and.w r3, r3, #1 8004eee: 2b00 cmp r3, #0 8004ef0: d004 beq.n 8004efc { HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); 8004ef2: 2101 movs r1, #1 8004ef4: 6878 ldr r0, [r7, #4] 8004ef6: f005 fda5 bl 800aa44 8004efa: e003 b.n 8004f04 } else { HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); 8004efc: 2100 movs r1, #0 8004efe: 6878 ldr r0, [r7, #4] 8004f00: f005 fda0 bl 800aa44 } #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* Rx or Tx Timeout Interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET) 8004f04: 89fb ldrh r3, [r7, #14] 8004f06: 0a5b lsrs r3, r3, #9 8004f08: f003 0301 and.w r3, r3, #1 8004f0c: 2b00 cmp r3, #0 8004f0e: d002 beq.n 8004f16 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->RxTxTimeoutCallback(hsubghz); #else HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz); 8004f10: 6878 ldr r0, [r7, #4] 8004f12: f005 fdb5 bl 800aa80 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } /* LR_FHSS Hop interrupt */ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) 8004f16: 89fb ldrh r3, [r7, #14] 8004f18: 0b9b lsrs r3, r3, #14 8004f1a: f003 0301 and.w r3, r3, #1 8004f1e: 2b00 cmp r3, #0 8004f20: d002 beq.n 8004f28 { #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) hsubghz->LrFhssHopCallback(hsubghz); #else HAL_SUBGHZ_LrFhssHopCallback(hsubghz); 8004f22: 6878 ldr r0, [r7, #4] 8004f24: f005 fdf4 bl 800ab10 #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ } } 8004f28: bf00 nop 8004f2a: 3710 adds r7, #16 8004f2c: 46bd mov sp, r7 8004f2e: bd80 pop {r7, pc} 08004f30 : * @brief Initializes the SUBGHZSPI peripheral * @param BaudratePrescaler SPI Baudrate prescaler * @retval None */ void SUBGHZSPI_Init(uint32_t BaudratePrescaler) { 8004f30: b480 push {r7} 8004f32: b083 sub sp, #12 8004f34: af00 add r7, sp, #0 8004f36: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); /* Disable SUBGHZSPI Peripheral */ CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); 8004f38: 4b0c ldr r3, [pc, #48] @ (8004f6c ) 8004f3a: 681b ldr r3, [r3, #0] 8004f3c: 4a0b ldr r2, [pc, #44] @ (8004f6c ) 8004f3e: f023 0340 bic.w r3, r3, #64 @ 0x40 8004f42: 6013 str r3, [r2, #0] * NSS management: Internal (Done with External bit inside PWR * * Communication speed: BaudratePrescaler * * First bit: MSB * * CRC calculation: Disable * *--------------------------------------------------------------------------*/ WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); 8004f44: 4a09 ldr r2, [pc, #36] @ (8004f6c ) 8004f46: 687b ldr r3, [r7, #4] 8004f48: f443 7341 orr.w r3, r3, #772 @ 0x304 8004f4c: 6013 str r3, [r2, #0] * Data Size: 8bits * * TI Mode: Disable * * NSS Pulse: Disable * * Rx FIFO Threshold: 8bits * *--------------------------------------------------------------------------*/ WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); 8004f4e: 4b07 ldr r3, [pc, #28] @ (8004f6c ) 8004f50: f44f 52b8 mov.w r2, #5888 @ 0x1700 8004f54: 605a str r2, [r3, #4] /* Enable SUBGHZSPI Peripheral */ SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); 8004f56: 4b05 ldr r3, [pc, #20] @ (8004f6c ) 8004f58: 681b ldr r3, [r3, #0] 8004f5a: 4a04 ldr r2, [pc, #16] @ (8004f6c ) 8004f5c: f043 0340 orr.w r3, r3, #64 @ 0x40 8004f60: 6013 str r3, [r2, #0] } 8004f62: bf00 nop 8004f64: 370c adds r7, #12 8004f66: 46bd mov sp, r7 8004f68: bc80 pop {r7} 8004f6a: 4770 bx lr 8004f6c: 58010000 .word 0x58010000 08004f70 : * @param Data data to transmit * @retval HAL status */ HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Data) { 8004f70: b480 push {r7} 8004f72: b087 sub sp, #28 8004f74: af00 add r7, sp, #0 8004f76: 6078 str r0, [r7, #4] 8004f78: 460b mov r3, r1 8004f7a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef status = HAL_OK; 8004f7c: 2300 movs r3, #0 8004f7e: 75fb strb r3, [r7, #23] __IO uint32_t count; /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; 8004f80: 4b23 ldr r3, [pc, #140] @ (8005010 ) 8004f82: 681a ldr r2, [r3, #0] 8004f84: 4613 mov r3, r2 8004f86: 00db lsls r3, r3, #3 8004f88: 1a9b subs r3, r3, r2 8004f8a: 009b lsls r3, r3, #2 8004f8c: 0cdb lsrs r3, r3, #19 8004f8e: 2264 movs r2, #100 @ 0x64 8004f90: fb02 f303 mul.w r3, r2, r3 8004f94: 60fb str r3, [r7, #12] /* Wait until TXE flag is set */ do { if (count == 0U) 8004f96: 68fb ldr r3, [r7, #12] 8004f98: 2b00 cmp r3, #0 8004f9a: d105 bne.n 8004fa8 { status = HAL_ERROR; 8004f9c: 2301 movs r3, #1 8004f9e: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; 8004fa0: 687b ldr r3, [r7, #4] 8004fa2: 2201 movs r2, #1 8004fa4: 609a str r2, [r3, #8] break; 8004fa6: e008 b.n 8004fba } count--; 8004fa8: 68fb ldr r3, [r7, #12] 8004faa: 3b01 subs r3, #1 8004fac: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); 8004fae: 4b19 ldr r3, [pc, #100] @ (8005014 ) 8004fb0: 689b ldr r3, [r3, #8] 8004fb2: f003 0302 and.w r3, r3, #2 8004fb6: 2b02 cmp r3, #2 8004fb8: d1ed bne.n 8004f96 /* Transmit Data*/ #if defined (__GNUC__) __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); 8004fba: 4b17 ldr r3, [pc, #92] @ (8005018 ) 8004fbc: 613b str r3, [r7, #16] *spidr = Data; 8004fbe: 693b ldr r3, [r7, #16] 8004fc0: 78fa ldrb r2, [r7, #3] 8004fc2: 701a strb r2, [r3, #0] *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; #endif /* __GNUC__ */ /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; 8004fc4: 4b12 ldr r3, [pc, #72] @ (8005010 ) 8004fc6: 681a ldr r2, [r3, #0] 8004fc8: 4613 mov r3, r2 8004fca: 00db lsls r3, r3, #3 8004fcc: 1a9b subs r3, r3, r2 8004fce: 009b lsls r3, r3, #2 8004fd0: 0cdb lsrs r3, r3, #19 8004fd2: 2264 movs r2, #100 @ 0x64 8004fd4: fb02 f303 mul.w r3, r2, r3 8004fd8: 60fb str r3, [r7, #12] /* Wait until RXNE flag is set */ do { if (count == 0U) 8004fda: 68fb ldr r3, [r7, #12] 8004fdc: 2b00 cmp r3, #0 8004fde: d105 bne.n 8004fec { status = HAL_ERROR; 8004fe0: 2301 movs r3, #1 8004fe2: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 2201 movs r2, #1 8004fe8: 609a str r2, [r3, #8] break; 8004fea: e008 b.n 8004ffe } count--; 8004fec: 68fb ldr r3, [r7, #12] 8004fee: 3b01 subs r3, #1 8004ff0: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); 8004ff2: 4b08 ldr r3, [pc, #32] @ (8005014 ) 8004ff4: 689b ldr r3, [r3, #8] 8004ff6: f003 0301 and.w r3, r3, #1 8004ffa: 2b01 cmp r3, #1 8004ffc: d1ed bne.n 8004fda /* Flush Rx data */ READ_REG(SUBGHZSPI->DR); 8004ffe: 4b05 ldr r3, [pc, #20] @ (8005014 ) 8005000: 68db ldr r3, [r3, #12] return status; 8005002: 7dfb ldrb r3, [r7, #23] } 8005004: 4618 mov r0, r3 8005006: 371c adds r7, #28 8005008: 46bd mov sp, r7 800500a: bc80 pop {r7} 800500c: 4770 bx lr 800500e: bf00 nop 8005010: 20000000 .word 0x20000000 8005014: 58010000 .word 0x58010000 8005018: 5801000c .word 0x5801000c 0800501c : * @param pData pointer on data to receive * @retval HAL status */ HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, uint8_t *pData) { 800501c: b480 push {r7} 800501e: b087 sub sp, #28 8005020: af00 add r7, sp, #0 8005022: 6078 str r0, [r7, #4] 8005024: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005026: 2300 movs r3, #0 8005028: 75fb strb r3, [r7, #23] __IO uint32_t count; /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; 800502a: 4b25 ldr r3, [pc, #148] @ (80050c0 ) 800502c: 681a ldr r2, [r3, #0] 800502e: 4613 mov r3, r2 8005030: 00db lsls r3, r3, #3 8005032: 1a9b subs r3, r3, r2 8005034: 009b lsls r3, r3, #2 8005036: 0cdb lsrs r3, r3, #19 8005038: 2264 movs r2, #100 @ 0x64 800503a: fb02 f303 mul.w r3, r2, r3 800503e: 60fb str r3, [r7, #12] /* Wait until TXE flag is set */ do { if (count == 0U) 8005040: 68fb ldr r3, [r7, #12] 8005042: 2b00 cmp r3, #0 8005044: d105 bne.n 8005052 { status = HAL_ERROR; 8005046: 2301 movs r3, #1 8005048: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; 800504a: 687b ldr r3, [r7, #4] 800504c: 2201 movs r2, #1 800504e: 609a str r2, [r3, #8] break; 8005050: e008 b.n 8005064 } count--; 8005052: 68fb ldr r3, [r7, #12] 8005054: 3b01 subs r3, #1 8005056: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); 8005058: 4b1a ldr r3, [pc, #104] @ (80050c4 ) 800505a: 689b ldr r3, [r3, #8] 800505c: f003 0302 and.w r3, r3, #2 8005060: 2b02 cmp r3, #2 8005062: d1ed bne.n 8005040 /* Transmit Data*/ #if defined (__GNUC__) __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); 8005064: 4b18 ldr r3, [pc, #96] @ (80050c8 ) 8005066: 613b str r3, [r7, #16] *spidr = SUBGHZ_DUMMY_DATA; 8005068: 693b ldr r3, [r7, #16] 800506a: 22ff movs r2, #255 @ 0xff 800506c: 701a strb r2, [r3, #0] *((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA; #endif /* __GNUC__ */ /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; 800506e: 4b14 ldr r3, [pc, #80] @ (80050c0 ) 8005070: 681a ldr r2, [r3, #0] 8005072: 4613 mov r3, r2 8005074: 00db lsls r3, r3, #3 8005076: 1a9b subs r3, r3, r2 8005078: 009b lsls r3, r3, #2 800507a: 0cdb lsrs r3, r3, #19 800507c: 2264 movs r2, #100 @ 0x64 800507e: fb02 f303 mul.w r3, r2, r3 8005082: 60fb str r3, [r7, #12] /* Wait until RXNE flag is set */ do { if (count == 0U) 8005084: 68fb ldr r3, [r7, #12] 8005086: 2b00 cmp r3, #0 8005088: d105 bne.n 8005096 { status = HAL_ERROR; 800508a: 2301 movs r3, #1 800508c: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; 800508e: 687b ldr r3, [r7, #4] 8005090: 2201 movs r2, #1 8005092: 609a str r2, [r3, #8] break; 8005094: e008 b.n 80050a8 } count--; 8005096: 68fb ldr r3, [r7, #12] 8005098: 3b01 subs r3, #1 800509a: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); 800509c: 4b09 ldr r3, [pc, #36] @ (80050c4 ) 800509e: 689b ldr r3, [r3, #8] 80050a0: f003 0301 and.w r3, r3, #1 80050a4: 2b01 cmp r3, #1 80050a6: d1ed bne.n 8005084 /* Retrieve pData */ *pData = (uint8_t)(READ_REG(SUBGHZSPI->DR)); 80050a8: 4b06 ldr r3, [pc, #24] @ (80050c4 ) 80050aa: 68db ldr r3, [r3, #12] 80050ac: b2da uxtb r2, r3 80050ae: 683b ldr r3, [r7, #0] 80050b0: 701a strb r2, [r3, #0] return status; 80050b2: 7dfb ldrb r3, [r7, #23] } 80050b4: 4618 mov r0, r3 80050b6: 371c adds r7, #28 80050b8: 46bd mov sp, r7 80050ba: bc80 pop {r7} 80050bc: 4770 bx lr 80050be: bf00 nop 80050c0: 20000000 .word 0x20000000 80050c4: 58010000 .word 0x58010000 80050c8: 5801000c .word 0x5801000c 080050cc : * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @retval HAL status */ HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) { 80050cc: b580 push {r7, lr} 80050ce: b084 sub sp, #16 80050d0: af00 add r7, sp, #0 80050d2: 6078 str r0, [r7, #4] __IO uint32_t count; /* Wakeup radio in case of sleep mode: Select-Unselect radio */ if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) 80050d4: 687b ldr r3, [r7, #4] 80050d6: 791b ldrb r3, [r3, #4] 80050d8: 2b01 cmp r3, #1 80050da: d10d bne.n 80050f8 { /* Initialize NSS switch Delay */ count = SUBGHZ_NSS_LOOP_TIME; 80050dc: 4b0a ldr r3, [pc, #40] @ (8005108 ) 80050de: 681b ldr r3, [r3, #0] 80050e0: 0c1b lsrs r3, r3, #16 80050e2: 60fb str r3, [r7, #12] /* NSS = 0; */ LL_PWR_SelectSUBGHZSPI_NSS(); 80050e4: f7ff fb98 bl 8004818 /* Wait Radio wakeup */ do { count--; 80050e8: 68fb ldr r3, [r7, #12] 80050ea: 3b01 subs r3, #1 80050ec: 60fb str r3, [r7, #12] } while (count != 0UL); 80050ee: 68fb ldr r3, [r7, #12] 80050f0: 2b00 cmp r3, #0 80050f2: d1f9 bne.n 80050e8 /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); 80050f4: f7ff fb80 bl 80047f8 } return (SUBGHZ_WaitOnBusy(hsubghz)); 80050f8: 6878 ldr r0, [r7, #4] 80050fa: f000 f807 bl 800510c 80050fe: 4603 mov r3, r0 } 8005100: 4618 mov r0, r3 8005102: 3710 adds r7, #16 8005104: 46bd mov sp, r7 8005106: bd80 pop {r7, pc} 8005108: 20000000 .word 0x20000000 0800510c : * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @retval HAL status */ HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) { 800510c: b580 push {r7, lr} 800510e: b086 sub sp, #24 8005110: af00 add r7, sp, #0 8005112: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; __IO uint32_t count; uint32_t mask; status = HAL_OK; 8005114: 2300 movs r3, #0 8005116: 75fb strb r3, [r7, #23] count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; 8005118: 4b12 ldr r3, [pc, #72] @ (8005164 ) 800511a: 681a ldr r2, [r3, #0] 800511c: 4613 mov r3, r2 800511e: 005b lsls r3, r3, #1 8005120: 4413 add r3, r2 8005122: 00db lsls r3, r3, #3 8005124: 0d1b lsrs r3, r3, #20 8005126: 2264 movs r2, #100 @ 0x64 8005128: fb02 f303 mul.w r3, r2, r3 800512c: 60fb str r3, [r7, #12] /* Wait until Busy signal is set */ do { mask = LL_PWR_IsActiveFlag_RFBUSYMS(); 800512e: f7ff fba1 bl 8004874 8005132: 6138 str r0, [r7, #16] if (count == 0U) 8005134: 68fb ldr r3, [r7, #12] 8005136: 2b00 cmp r3, #0 8005138: d105 bne.n 8005146 { status = HAL_ERROR; 800513a: 2301 movs r3, #1 800513c: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; 800513e: 687b ldr r3, [r7, #4] 8005140: 2202 movs r2, #2 8005142: 609a str r2, [r3, #8] break; 8005144: e009 b.n 800515a } count--; 8005146: 68fb ldr r3, [r7, #12] 8005148: 3b01 subs r3, #1 800514a: 60fb str r3, [r7, #12] } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); 800514c: f7ff fb80 bl 8004850 8005150: 4602 mov r2, r0 8005152: 693b ldr r3, [r7, #16] 8005154: 4013 ands r3, r2 8005156: 2b01 cmp r3, #1 8005158: d0e9 beq.n 800512e return status; 800515a: 7dfb ldrb r3, [r7, #23] } 800515c: 4618 mov r0, r3 800515e: 3718 adds r7, #24 8005160: 46bd mov sp, r7 8005162: bd80 pop {r7, pc} 8005164: 20000000 .word 0x20000000 08005168 : { 8005168: b480 push {r7} 800516a: b083 sub sp, #12 800516c: af00 add r7, sp, #0 800516e: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); 8005170: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005174: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8005178: 687b ldr r3, [r7, #4] 800517a: 401a ands r2, r3 800517c: 687b ldr r3, [r7, #4] 800517e: 041b lsls r3, r3, #16 8005180: 4313 orrs r3, r2 } 8005182: 4618 mov r0, r3 8005184: 370c adds r7, #12 8005186: 46bd mov sp, r7 8005188: bc80 pop {r7} 800518a: 4770 bx lr 0800518c : { 800518c: b480 push {r7} 800518e: b083 sub sp, #12 8005190: af00 add r7, sp, #0 8005192: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); 8005194: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005198: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800519c: 687b ldr r3, [r7, #4] 800519e: 4013 ands r3, r2 } 80051a0: 4618 mov r0, r3 80051a2: 370c adds r7, #12 80051a4: 46bd mov sp, r7 80051a6: bc80 pop {r7} 80051a8: 4770 bx lr 080051aa : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80051aa: b580 push {r7, lr} 80051ac: b082 sub sp, #8 80051ae: af00 add r7, sp, #0 80051b0: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80051b2: 687b ldr r3, [r7, #4] 80051b4: 2b00 cmp r3, #0 80051b6: d101 bne.n 80051bc { return HAL_ERROR; 80051b8: 2301 movs r3, #1 80051ba: e042 b.n 8005242 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80051bc: 687b ldr r3, [r7, #4] 80051be: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80051c2: 2b00 cmp r3, #0 80051c4: d106 bne.n 80051d4 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80051c6: 687b ldr r3, [r7, #4] 80051c8: 2200 movs r2, #0 80051ca: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80051ce: 6878 ldr r0, [r7, #4] 80051d0: f7fc f8d0 bl 8001374 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80051d4: 687b ldr r3, [r7, #4] 80051d6: 2224 movs r2, #36 @ 0x24 80051d8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80051dc: 687b ldr r3, [r7, #4] 80051de: 681b ldr r3, [r3, #0] 80051e0: 681a ldr r2, [r3, #0] 80051e2: 687b ldr r3, [r7, #4] 80051e4: 681b ldr r3, [r3, #0] 80051e6: f022 0201 bic.w r2, r2, #1 80051ea: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80051ec: 687b ldr r3, [r7, #4] 80051ee: 6a9b ldr r3, [r3, #40] @ 0x28 80051f0: 2b00 cmp r3, #0 80051f2: d002 beq.n 80051fa { UART_AdvFeatureConfig(huart); 80051f4: 6878 ldr r0, [r7, #4] 80051f6: f001 f813 bl 8006220 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80051fa: 6878 ldr r0, [r7, #4] 80051fc: f000 fd9c bl 8005d38 8005200: 4603 mov r3, r0 8005202: 2b01 cmp r3, #1 8005204: d101 bne.n 800520a { return HAL_ERROR; 8005206: 2301 movs r3, #1 8005208: e01b b.n 8005242 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800520a: 687b ldr r3, [r7, #4] 800520c: 681b ldr r3, [r3, #0] 800520e: 685a ldr r2, [r3, #4] 8005210: 687b ldr r3, [r7, #4] 8005212: 681b ldr r3, [r3, #0] 8005214: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005218: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800521a: 687b ldr r3, [r7, #4] 800521c: 681b ldr r3, [r3, #0] 800521e: 689a ldr r2, [r3, #8] 8005220: 687b ldr r3, [r7, #4] 8005222: 681b ldr r3, [r3, #0] 8005224: f022 022a bic.w r2, r2, #42 @ 0x2a 8005228: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800522a: 687b ldr r3, [r7, #4] 800522c: 681b ldr r3, [r3, #0] 800522e: 681a ldr r2, [r3, #0] 8005230: 687b ldr r3, [r7, #4] 8005232: 681b ldr r3, [r3, #0] 8005234: f042 0201 orr.w r2, r2, #1 8005238: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800523a: 6878 ldr r0, [r7, #4] 800523c: f001 f891 bl 8006362 8005240: 4603 mov r3, r0 } 8005242: 4618 mov r0, r3 8005244: 3708 adds r7, #8 8005246: 46bd mov sp, r7 8005248: bd80 pop {r7, pc} 0800524a : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800524a: b580 push {r7, lr} 800524c: b08a sub sp, #40 @ 0x28 800524e: af02 add r7, sp, #8 8005250: 60f8 str r0, [r7, #12] 8005252: 60b9 str r1, [r7, #8] 8005254: 603b str r3, [r7, #0] 8005256: 4613 mov r3, r2 8005258: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800525a: 68fb ldr r3, [r7, #12] 800525c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005260: 2b20 cmp r3, #32 8005262: f040 8086 bne.w 8005372 { if ((pData == NULL) || (Size == 0U)) 8005266: 68bb ldr r3, [r7, #8] 8005268: 2b00 cmp r3, #0 800526a: d002 beq.n 8005272 800526c: 88fb ldrh r3, [r7, #6] 800526e: 2b00 cmp r3, #0 8005270: d101 bne.n 8005276 { return HAL_ERROR; 8005272: 2301 movs r3, #1 8005274: e07e b.n 8005374 return HAL_ERROR; } } #endif /* CORE_CM0PLUS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005276: 68fb ldr r3, [r7, #12] 8005278: 2200 movs r2, #0 800527a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 800527e: 68fb ldr r3, [r7, #12] 8005280: 2221 movs r2, #33 @ 0x21 8005282: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005286: f7fb fcdf bl 8000c48 800528a: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 800528c: 68fb ldr r3, [r7, #12] 800528e: 88fa ldrh r2, [r7, #6] 8005290: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8005294: 68fb ldr r3, [r7, #12] 8005296: 88fa ldrh r2, [r7, #6] 8005298: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800529c: 68fb ldr r3, [r7, #12] 800529e: 689b ldr r3, [r3, #8] 80052a0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80052a4: d108 bne.n 80052b8 80052a6: 68fb ldr r3, [r7, #12] 80052a8: 691b ldr r3, [r3, #16] 80052aa: 2b00 cmp r3, #0 80052ac: d104 bne.n 80052b8 { pdata8bits = NULL; 80052ae: 2300 movs r3, #0 80052b0: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 80052b2: 68bb ldr r3, [r7, #8] 80052b4: 61bb str r3, [r7, #24] 80052b6: e003 b.n 80052c0 } else { pdata8bits = pData; 80052b8: 68bb ldr r3, [r7, #8] 80052ba: 61fb str r3, [r7, #28] pdata16bits = NULL; 80052bc: 2300 movs r3, #0 80052be: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 80052c0: e03a b.n 8005338 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80052c2: 683b ldr r3, [r7, #0] 80052c4: 9300 str r3, [sp, #0] 80052c6: 697b ldr r3, [r7, #20] 80052c8: 2200 movs r2, #0 80052ca: 2180 movs r1, #128 @ 0x80 80052cc: 68f8 ldr r0, [r7, #12] 80052ce: f001 f8f2 bl 80064b6 80052d2: 4603 mov r3, r0 80052d4: 2b00 cmp r3, #0 80052d6: d005 beq.n 80052e4 { huart->gState = HAL_UART_STATE_READY; 80052d8: 68fb ldr r3, [r7, #12] 80052da: 2220 movs r2, #32 80052dc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 80052e0: 2303 movs r3, #3 80052e2: e047 b.n 8005374 } if (pdata8bits == NULL) 80052e4: 69fb ldr r3, [r7, #28] 80052e6: 2b00 cmp r3, #0 80052e8: d10b bne.n 8005302 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 80052ea: 69bb ldr r3, [r7, #24] 80052ec: 881b ldrh r3, [r3, #0] 80052ee: 461a mov r2, r3 80052f0: 68fb ldr r3, [r7, #12] 80052f2: 681b ldr r3, [r3, #0] 80052f4: f3c2 0208 ubfx r2, r2, #0, #9 80052f8: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 80052fa: 69bb ldr r3, [r7, #24] 80052fc: 3302 adds r3, #2 80052fe: 61bb str r3, [r7, #24] 8005300: e007 b.n 8005312 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 8005302: 69fb ldr r3, [r7, #28] 8005304: 781a ldrb r2, [r3, #0] 8005306: 68fb ldr r3, [r7, #12] 8005308: 681b ldr r3, [r3, #0] 800530a: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 800530c: 69fb ldr r3, [r7, #28] 800530e: 3301 adds r3, #1 8005310: 61fb str r3, [r7, #28] } if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) 8005312: 68fb ldr r3, [r7, #12] 8005314: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005318: f003 0321 and.w r3, r3, #33 @ 0x21 800531c: 2b21 cmp r3, #33 @ 0x21 800531e: d109 bne.n 8005334 { huart->TxXferCount--; 8005320: 68fb ldr r3, [r7, #12] 8005322: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8005326: b29b uxth r3, r3 8005328: 3b01 subs r3, #1 800532a: b29a uxth r2, r3 800532c: 68fb ldr r3, [r7, #12] 800532e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 8005332: e001 b.n 8005338 } else { /* Process was aborted during the transmission */ return HAL_ERROR; 8005334: 2301 movs r3, #1 8005336: e01d b.n 8005374 while (huart->TxXferCount > 0U) 8005338: 68fb ldr r3, [r7, #12] 800533a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800533e: b29b uxth r3, r3 8005340: 2b00 cmp r3, #0 8005342: d1be bne.n 80052c2 } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8005344: 683b ldr r3, [r7, #0] 8005346: 9300 str r3, [sp, #0] 8005348: 697b ldr r3, [r7, #20] 800534a: 2200 movs r2, #0 800534c: 2140 movs r1, #64 @ 0x40 800534e: 68f8 ldr r0, [r7, #12] 8005350: f001 f8b1 bl 80064b6 8005354: 4603 mov r3, r0 8005356: 2b00 cmp r3, #0 8005358: d005 beq.n 8005366 { huart->gState = HAL_UART_STATE_READY; 800535a: 68fb ldr r3, [r7, #12] 800535c: 2220 movs r2, #32 800535e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 8005362: 2303 movs r3, #3 8005364: e006 b.n 8005374 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8005366: 68fb ldr r3, [r7, #12] 8005368: 2220 movs r2, #32 800536a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; 800536e: 2300 movs r3, #0 8005370: e000 b.n 8005374 } else { return HAL_BUSY; 8005372: 2302 movs r3, #2 } } 8005374: 4618 mov r0, r3 8005376: 3720 adds r7, #32 8005378: 46bd mov sp, r7 800537a: bd80 pop {r7, pc} 0800537c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 800537c: b580 push {r7, lr} 800537e: b08a sub sp, #40 @ 0x28 8005380: af00 add r7, sp, #0 8005382: 60f8 str r0, [r7, #12] 8005384: 60b9 str r1, [r7, #8] 8005386: 4613 mov r3, r2 8005388: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 800538a: 68fb ldr r3, [r7, #12] 800538c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8005390: 2b20 cmp r3, #32 8005392: d137 bne.n 8005404 { if ((pData == NULL) || (Size == 0U)) 8005394: 68bb ldr r3, [r7, #8] 8005396: 2b00 cmp r3, #0 8005398: d002 beq.n 80053a0 800539a: 88fb ldrh r3, [r7, #6] 800539c: 2b00 cmp r3, #0 800539e: d101 bne.n 80053a4 { return HAL_ERROR; 80053a0: 2301 movs r3, #1 80053a2: e030 b.n 8005406 } } #endif /* CORE_CM0PLUS */ /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80053a4: 68fb ldr r3, [r7, #12] 80053a6: 2200 movs r2, #0 80053a8: 66da str r2, [r3, #108] @ 0x6c if (!(IS_LPUART_INSTANCE(huart->Instance))) 80053aa: 68fb ldr r3, [r7, #12] 80053ac: 681b ldr r3, [r3, #0] 80053ae: 4a18 ldr r2, [pc, #96] @ (8005410 ) 80053b0: 4293 cmp r3, r2 80053b2: d01f beq.n 80053f4 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80053b4: 68fb ldr r3, [r7, #12] 80053b6: 681b ldr r3, [r3, #0] 80053b8: 685b ldr r3, [r3, #4] 80053ba: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80053be: 2b00 cmp r3, #0 80053c0: d018 beq.n 80053f4 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80053c2: 68fb ldr r3, [r7, #12] 80053c4: 681b ldr r3, [r3, #0] 80053c6: 617b str r3, [r7, #20] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80053c8: 697b ldr r3, [r7, #20] 80053ca: e853 3f00 ldrex r3, [r3] 80053ce: 613b str r3, [r7, #16] return(result); 80053d0: 693b ldr r3, [r7, #16] 80053d2: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 80053d6: 627b str r3, [r7, #36] @ 0x24 80053d8: 68fb ldr r3, [r7, #12] 80053da: 681b ldr r3, [r3, #0] 80053dc: 461a mov r2, r3 80053de: 6a7b ldr r3, [r7, #36] @ 0x24 80053e0: 623b str r3, [r7, #32] 80053e2: 61fa str r2, [r7, #28] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80053e4: 69f9 ldr r1, [r7, #28] 80053e6: 6a3a ldr r2, [r7, #32] 80053e8: e841 2300 strex r3, r2, [r1] 80053ec: 61bb str r3, [r7, #24] return(result); 80053ee: 69bb ldr r3, [r7, #24] 80053f0: 2b00 cmp r3, #0 80053f2: d1e6 bne.n 80053c2 } } return (UART_Start_Receive_IT(huart, pData, Size)); 80053f4: 88fb ldrh r3, [r7, #6] 80053f6: 461a mov r2, r3 80053f8: 68b9 ldr r1, [r7, #8] 80053fa: 68f8 ldr r0, [r7, #12] 80053fc: f001 f8c8 bl 8006590 8005400: 4603 mov r3, r0 8005402: e000 b.n 8005406 } else { return HAL_BUSY; 8005404: 2302 movs r3, #2 } } 8005406: 4618 mov r0, r3 8005408: 3728 adds r7, #40 @ 0x28 800540a: 46bd mov sp, r7 800540c: bd80 pop {r7, pc} 800540e: bf00 nop 8005410: 40008000 .word 0x40008000 08005414 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005414: b580 push {r7, lr} 8005416: b08a sub sp, #40 @ 0x28 8005418: af00 add r7, sp, #0 800541a: 60f8 str r0, [r7, #12] 800541c: 60b9 str r1, [r7, #8] 800541e: 4613 mov r3, r2 8005420: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005422: 68fb ldr r3, [r7, #12] 8005424: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005428: 2b20 cmp r3, #32 800542a: d167 bne.n 80054fc { if ((pData == NULL) || (Size == 0U)) 800542c: 68bb ldr r3, [r7, #8] 800542e: 2b00 cmp r3, #0 8005430: d002 beq.n 8005438 8005432: 88fb ldrh r3, [r7, #6] 8005434: 2b00 cmp r3, #0 8005436: d101 bne.n 800543c { return HAL_ERROR; 8005438: 2301 movs r3, #1 800543a: e060 b.n 80054fe return HAL_ERROR; } } #endif /* CORE_CM0PLUS */ huart->pTxBuffPtr = pData; 800543c: 68fb ldr r3, [r7, #12] 800543e: 68ba ldr r2, [r7, #8] 8005440: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 8005442: 68fb ldr r3, [r7, #12] 8005444: 88fa ldrh r2, [r7, #6] 8005446: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 800544a: 68fb ldr r3, [r7, #12] 800544c: 88fa ldrh r2, [r7, #6] 800544e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005452: 68fb ldr r3, [r7, #12] 8005454: 2200 movs r2, #0 8005456: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 800545a: 68fb ldr r3, [r7, #12] 800545c: 2221 movs r2, #33 @ 0x21 800545e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 if (huart->hdmatx != NULL) 8005462: 68fb ldr r3, [r7, #12] 8005464: 6fdb ldr r3, [r3, #124] @ 0x7c 8005466: 2b00 cmp r3, #0 8005468: d028 beq.n 80054bc { /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 800546a: 68fb ldr r3, [r7, #12] 800546c: 6fdb ldr r3, [r3, #124] @ 0x7c 800546e: 4a26 ldr r2, [pc, #152] @ (8005508 ) 8005470: 62da str r2, [r3, #44] @ 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005472: 68fb ldr r3, [r7, #12] 8005474: 6fdb ldr r3, [r3, #124] @ 0x7c 8005476: 4a25 ldr r2, [pc, #148] @ (800550c ) 8005478: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 800547a: 68fb ldr r3, [r7, #12] 800547c: 6fdb ldr r3, [r3, #124] @ 0x7c 800547e: 4a24 ldr r2, [pc, #144] @ (8005510 ) 8005480: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005482: 68fb ldr r3, [r7, #12] 8005484: 6fdb ldr r3, [r3, #124] @ 0x7c 8005486: 2200 movs r2, #0 8005488: 639a str r2, [r3, #56] @ 0x38 /* Enable the UART transmit DMA channel */ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) 800548a: 68fb ldr r3, [r7, #12] 800548c: 6fd8 ldr r0, [r3, #124] @ 0x7c 800548e: 68fb ldr r3, [r7, #12] 8005490: 6d1b ldr r3, [r3, #80] @ 0x50 8005492: 4619 mov r1, r3 8005494: 68fb ldr r3, [r7, #12] 8005496: 681b ldr r3, [r3, #0] 8005498: 3328 adds r3, #40 @ 0x28 800549a: 461a mov r2, r3 800549c: 88fb ldrh r3, [r7, #6] 800549e: f7fc fce3 bl 8001e68 80054a2: 4603 mov r3, r0 80054a4: 2b00 cmp r3, #0 80054a6: d009 beq.n 80054bc { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80054a8: 68fb ldr r3, [r7, #12] 80054aa: 2210 movs r2, #16 80054ac: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 80054b0: 68fb ldr r3, [r7, #12] 80054b2: 2220 movs r2, #32 80054b4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_ERROR; 80054b8: 2301 movs r3, #1 80054ba: e020 b.n 80054fe } } /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); 80054bc: 68fb ldr r3, [r7, #12] 80054be: 681b ldr r3, [r3, #0] 80054c0: 2240 movs r2, #64 @ 0x40 80054c2: 621a str r2, [r3, #32] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80054c4: 68fb ldr r3, [r7, #12] 80054c6: 681b ldr r3, [r3, #0] 80054c8: 3308 adds r3, #8 80054ca: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80054cc: 697b ldr r3, [r7, #20] 80054ce: e853 3f00 ldrex r3, [r3] 80054d2: 613b str r3, [r7, #16] return(result); 80054d4: 693b ldr r3, [r7, #16] 80054d6: f043 0380 orr.w r3, r3, #128 @ 0x80 80054da: 627b str r3, [r7, #36] @ 0x24 80054dc: 68fb ldr r3, [r7, #12] 80054de: 681b ldr r3, [r3, #0] 80054e0: 3308 adds r3, #8 80054e2: 6a7a ldr r2, [r7, #36] @ 0x24 80054e4: 623a str r2, [r7, #32] 80054e6: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80054e8: 69f9 ldr r1, [r7, #28] 80054ea: 6a3a ldr r2, [r7, #32] 80054ec: e841 2300 strex r3, r2, [r1] 80054f0: 61bb str r3, [r7, #24] return(result); 80054f2: 69bb ldr r3, [r7, #24] 80054f4: 2b00 cmp r3, #0 80054f6: d1e5 bne.n 80054c4 return HAL_OK; 80054f8: 2300 movs r3, #0 80054fa: e000 b.n 80054fe } else { return HAL_BUSY; 80054fc: 2302 movs r3, #2 } } 80054fe: 4618 mov r0, r3 8005500: 3728 adds r7, #40 @ 0x28 8005502: 46bd mov sp, r7 8005504: bd80 pop {r7, pc} 8005506: bf00 nop 8005508: 0800691b .word 0x0800691b 800550c: 080069ad .word 0x080069ad 8005510: 080069c9 .word 0x080069c9 08005514 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { 8005514: b580 push {r7, lr} 8005516: b09a sub sp, #104 @ 0x68 8005518: af00 add r7, sp, #0 800551a: 6078 str r0, [r7, #4] /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); 800551c: 687b ldr r3, [r7, #4] 800551e: 681b ldr r3, [r3, #0] 8005520: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005522: 6cbb ldr r3, [r7, #72] @ 0x48 8005524: e853 3f00 ldrex r3, [r3] 8005528: 647b str r3, [r7, #68] @ 0x44 return(result); 800552a: 6c7b ldr r3, [r7, #68] @ 0x44 800552c: f423 7390 bic.w r3, r3, #288 @ 0x120 8005530: 667b str r3, [r7, #100] @ 0x64 8005532: 687b ldr r3, [r7, #4] 8005534: 681b ldr r3, [r3, #0] 8005536: 461a mov r2, r3 8005538: 6e7b ldr r3, [r7, #100] @ 0x64 800553a: 657b str r3, [r7, #84] @ 0x54 800553c: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800553e: 6d39 ldr r1, [r7, #80] @ 0x50 8005540: 6d7a ldr r2, [r7, #84] @ 0x54 8005542: e841 2300 strex r3, r2, [r1] 8005546: 64fb str r3, [r7, #76] @ 0x4c return(result); 8005548: 6cfb ldr r3, [r7, #76] @ 0x4c 800554a: 2b00 cmp r3, #0 800554c: d1e6 bne.n 800551c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); 800554e: 687b ldr r3, [r7, #4] 8005550: 681b ldr r3, [r3, #0] 8005552: 3308 adds r3, #8 8005554: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005556: 6b7b ldr r3, [r7, #52] @ 0x34 8005558: e853 3f00 ldrex r3, [r3] 800555c: 633b str r3, [r7, #48] @ 0x30 return(result); 800555e: 6b3b ldr r3, [r7, #48] @ 0x30 8005560: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005564: f023 0301 bic.w r3, r3, #1 8005568: 663b str r3, [r7, #96] @ 0x60 800556a: 687b ldr r3, [r7, #4] 800556c: 681b ldr r3, [r3, #0] 800556e: 3308 adds r3, #8 8005570: 6e3a ldr r2, [r7, #96] @ 0x60 8005572: 643a str r2, [r7, #64] @ 0x40 8005574: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005576: 6bf9 ldr r1, [r7, #60] @ 0x3c 8005578: 6c3a ldr r2, [r7, #64] @ 0x40 800557a: e841 2300 strex r3, r2, [r1] 800557e: 63bb str r3, [r7, #56] @ 0x38 return(result); 8005580: 6bbb ldr r3, [r7, #56] @ 0x38 8005582: 2b00 cmp r3, #0 8005584: d1e3 bne.n 800554e /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005586: 687b ldr r3, [r7, #4] 8005588: 6edb ldr r3, [r3, #108] @ 0x6c 800558a: 2b01 cmp r3, #1 800558c: d118 bne.n 80055c0 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 800558e: 687b ldr r3, [r7, #4] 8005590: 681b ldr r3, [r3, #0] 8005592: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005594: 6a3b ldr r3, [r7, #32] 8005596: e853 3f00 ldrex r3, [r3] 800559a: 61fb str r3, [r7, #28] return(result); 800559c: 69fb ldr r3, [r7, #28] 800559e: f023 0310 bic.w r3, r3, #16 80055a2: 65fb str r3, [r7, #92] @ 0x5c 80055a4: 687b ldr r3, [r7, #4] 80055a6: 681b ldr r3, [r3, #0] 80055a8: 461a mov r2, r3 80055aa: 6dfb ldr r3, [r7, #92] @ 0x5c 80055ac: 62fb str r3, [r7, #44] @ 0x2c 80055ae: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80055b0: 6ab9 ldr r1, [r7, #40] @ 0x28 80055b2: 6afa ldr r2, [r7, #44] @ 0x2c 80055b4: e841 2300 strex r3, r2, [r1] 80055b8: 627b str r3, [r7, #36] @ 0x24 return(result); 80055ba: 6a7b ldr r3, [r7, #36] @ 0x24 80055bc: 2b00 cmp r3, #0 80055be: d1e6 bne.n 800558e } /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80055c0: 687b ldr r3, [r7, #4] 80055c2: 681b ldr r3, [r3, #0] 80055c4: 689b ldr r3, [r3, #8] 80055c6: f003 0340 and.w r3, r3, #64 @ 0x40 80055ca: 2b40 cmp r3, #64 @ 0x40 80055cc: d13b bne.n 8005646 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80055ce: 687b ldr r3, [r7, #4] 80055d0: 681b ldr r3, [r3, #0] 80055d2: 3308 adds r3, #8 80055d4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80055d6: 68fb ldr r3, [r7, #12] 80055d8: e853 3f00 ldrex r3, [r3] 80055dc: 60bb str r3, [r7, #8] return(result); 80055de: 68bb ldr r3, [r7, #8] 80055e0: f023 0340 bic.w r3, r3, #64 @ 0x40 80055e4: 65bb str r3, [r7, #88] @ 0x58 80055e6: 687b ldr r3, [r7, #4] 80055e8: 681b ldr r3, [r3, #0] 80055ea: 3308 adds r3, #8 80055ec: 6dba ldr r2, [r7, #88] @ 0x58 80055ee: 61ba str r2, [r7, #24] 80055f0: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80055f2: 6979 ldr r1, [r7, #20] 80055f4: 69ba ldr r2, [r7, #24] 80055f6: e841 2300 strex r3, r2, [r1] 80055fa: 613b str r3, [r7, #16] return(result); 80055fc: 693b ldr r3, [r7, #16] 80055fe: 2b00 cmp r3, #0 8005600: d1e5 bne.n 80055ce /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) 8005602: 687b ldr r3, [r7, #4] 8005604: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005608: 2b00 cmp r3, #0 800560a: d01c beq.n 8005646 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; 800560c: 687b ldr r3, [r7, #4] 800560e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005612: 2200 movs r2, #0 8005614: 639a str r2, [r3, #56] @ 0x38 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 8005616: 687b ldr r3, [r7, #4] 8005618: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800561c: 4618 mov r0, r3 800561e: f7fc fca1 bl 8001f64 8005622: 4603 mov r3, r0 8005624: 2b00 cmp r3, #0 8005626: d00e beq.n 8005646 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 8005628: 687b ldr r3, [r7, #4] 800562a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800562e: 4618 mov r0, r3 8005630: f7fc fe1c bl 800226c 8005634: 4603 mov r3, r0 8005636: 2b20 cmp r3, #32 8005638: d105 bne.n 8005646 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 800563a: 687b ldr r3, [r7, #4] 800563c: 2210 movs r2, #16 800563e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 return HAL_TIMEOUT; 8005642: 2303 movs r3, #3 8005644: e013 b.n 800566e } } } /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); 8005646: 687b ldr r3, [r7, #4] 8005648: 681b ldr r3, [r3, #0] 800564a: 220f movs r2, #15 800564c: 621a str r2, [r3, #32] /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800564e: 687b ldr r3, [r7, #4] 8005650: 681b ldr r3, [r3, #0] 8005652: 699a ldr r2, [r3, #24] 8005654: 687b ldr r3, [r7, #4] 8005656: 681b ldr r3, [r3, #0] 8005658: f042 0208 orr.w r2, r2, #8 800565c: 619a str r2, [r3, #24] /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800565e: 687b ldr r3, [r7, #4] 8005660: 2220 movs r2, #32 8005662: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005666: 687b ldr r3, [r7, #4] 8005668: 2200 movs r2, #0 800566a: 66da str r2, [r3, #108] @ 0x6c return HAL_OK; 800566c: 2300 movs r3, #0 } 800566e: 4618 mov r0, r3 8005670: 3768 adds r7, #104 @ 0x68 8005672: 46bd mov sp, r7 8005674: bd80 pop {r7, pc} ... 08005678 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005678: b580 push {r7, lr} 800567a: b0ba sub sp, #232 @ 0xe8 800567c: af00 add r7, sp, #0 800567e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8005680: 687b ldr r3, [r7, #4] 8005682: 681b ldr r3, [r3, #0] 8005684: 69db ldr r3, [r3, #28] 8005686: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800568a: 687b ldr r3, [r7, #4] 800568c: 681b ldr r3, [r3, #0] 800568e: 681b ldr r3, [r3, #0] 8005690: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005694: 687b ldr r3, [r7, #4] 8005696: 681b ldr r3, [r3, #0] 8005698: 689b ldr r3, [r3, #8] 800569a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 800569e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 80056a2: f640 030f movw r3, #2063 @ 0x80f 80056a6: 4013 ands r3, r2 80056a8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 80056ac: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80056b0: 2b00 cmp r3, #0 80056b2: d11b bne.n 80056ec { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80056b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80056b8: f003 0320 and.w r3, r3, #32 80056bc: 2b00 cmp r3, #0 80056be: d015 beq.n 80056ec && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80056c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80056c4: f003 0320 and.w r3, r3, #32 80056c8: 2b00 cmp r3, #0 80056ca: d105 bne.n 80056d8 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80056cc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80056d0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80056d4: 2b00 cmp r3, #0 80056d6: d009 beq.n 80056ec { if (huart->RxISR != NULL) 80056d8: 687b ldr r3, [r7, #4] 80056da: 6f5b ldr r3, [r3, #116] @ 0x74 80056dc: 2b00 cmp r3, #0 80056de: f000 8300 beq.w 8005ce2 { huart->RxISR(huart); 80056e2: 687b ldr r3, [r7, #4] 80056e4: 6f5b ldr r3, [r3, #116] @ 0x74 80056e6: 6878 ldr r0, [r7, #4] 80056e8: 4798 blx r3 } return; 80056ea: e2fa b.n 8005ce2 } } /* If some errors occur */ if ((errorflags != 0U) 80056ec: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80056f0: 2b00 cmp r3, #0 80056f2: f000 8123 beq.w 800593c && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 80056f6: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80056fa: 4b8d ldr r3, [pc, #564] @ (8005930 ) 80056fc: 4013 ands r3, r2 80056fe: 2b00 cmp r3, #0 8005700: d106 bne.n 8005710 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8005702: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8005706: 4b8b ldr r3, [pc, #556] @ (8005934 ) 8005708: 4013 ands r3, r2 800570a: 2b00 cmp r3, #0 800570c: f000 8116 beq.w 800593c { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8005710: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005714: f003 0301 and.w r3, r3, #1 8005718: 2b00 cmp r3, #0 800571a: d011 beq.n 8005740 800571c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005720: f403 7380 and.w r3, r3, #256 @ 0x100 8005724: 2b00 cmp r3, #0 8005726: d00b beq.n 8005740 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8005728: 687b ldr r3, [r7, #4] 800572a: 681b ldr r3, [r3, #0] 800572c: 2201 movs r2, #1 800572e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8005730: 687b ldr r3, [r7, #4] 8005732: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005736: f043 0201 orr.w r2, r3, #1 800573a: 687b ldr r3, [r7, #4] 800573c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8005740: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005744: f003 0302 and.w r3, r3, #2 8005748: 2b00 cmp r3, #0 800574a: d011 beq.n 8005770 800574c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005750: f003 0301 and.w r3, r3, #1 8005754: 2b00 cmp r3, #0 8005756: d00b beq.n 8005770 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8005758: 687b ldr r3, [r7, #4] 800575a: 681b ldr r3, [r3, #0] 800575c: 2202 movs r2, #2 800575e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8005760: 687b ldr r3, [r7, #4] 8005762: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005766: f043 0204 orr.w r2, r3, #4 800576a: 687b ldr r3, [r7, #4] 800576c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8005770: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005774: f003 0304 and.w r3, r3, #4 8005778: 2b00 cmp r3, #0 800577a: d011 beq.n 80057a0 800577c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005780: f003 0301 and.w r3, r3, #1 8005784: 2b00 cmp r3, #0 8005786: d00b beq.n 80057a0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8005788: 687b ldr r3, [r7, #4] 800578a: 681b ldr r3, [r3, #0] 800578c: 2204 movs r2, #4 800578e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8005790: 687b ldr r3, [r7, #4] 8005792: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005796: f043 0202 orr.w r2, r3, #2 800579a: 687b ldr r3, [r7, #4] 800579c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80057a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80057a4: f003 0308 and.w r3, r3, #8 80057a8: 2b00 cmp r3, #0 80057aa: d017 beq.n 80057dc && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80057ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80057b0: f003 0320 and.w r3, r3, #32 80057b4: 2b00 cmp r3, #0 80057b6: d105 bne.n 80057c4 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80057b8: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80057bc: 4b5c ldr r3, [pc, #368] @ (8005930 ) 80057be: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80057c0: 2b00 cmp r3, #0 80057c2: d00b beq.n 80057dc { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80057c4: 687b ldr r3, [r7, #4] 80057c6: 681b ldr r3, [r3, #0] 80057c8: 2208 movs r2, #8 80057ca: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80057cc: 687b ldr r3, [r7, #4] 80057ce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80057d2: f043 0208 orr.w r2, r3, #8 80057d6: 687b ldr r3, [r7, #4] 80057d8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80057dc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80057e0: f403 6300 and.w r3, r3, #2048 @ 0x800 80057e4: 2b00 cmp r3, #0 80057e6: d012 beq.n 800580e 80057e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80057ec: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80057f0: 2b00 cmp r3, #0 80057f2: d00c beq.n 800580e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 80057f4: 687b ldr r3, [r7, #4] 80057f6: 681b ldr r3, [r3, #0] 80057f8: f44f 6200 mov.w r2, #2048 @ 0x800 80057fc: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 80057fe: 687b ldr r3, [r7, #4] 8005800: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005804: f043 0220 orr.w r2, r3, #32 8005808: 687b ldr r3, [r7, #4] 800580a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800580e: 687b ldr r3, [r7, #4] 8005810: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005814: 2b00 cmp r3, #0 8005816: f000 8266 beq.w 8005ce6 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800581a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800581e: f003 0320 and.w r3, r3, #32 8005822: 2b00 cmp r3, #0 8005824: d013 beq.n 800584e && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8005826: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800582a: f003 0320 and.w r3, r3, #32 800582e: 2b00 cmp r3, #0 8005830: d105 bne.n 800583e || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8005832: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005836: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800583a: 2b00 cmp r3, #0 800583c: d007 beq.n 800584e { if (huart->RxISR != NULL) 800583e: 687b ldr r3, [r7, #4] 8005840: 6f5b ldr r3, [r3, #116] @ 0x74 8005842: 2b00 cmp r3, #0 8005844: d003 beq.n 800584e { huart->RxISR(huart); 8005846: 687b ldr r3, [r7, #4] 8005848: 6f5b ldr r3, [r3, #116] @ 0x74 800584a: 6878 ldr r0, [r7, #4] 800584c: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 800584e: 687b ldr r3, [r7, #4] 8005850: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005854: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8005858: 687b ldr r3, [r7, #4] 800585a: 681b ldr r3, [r3, #0] 800585c: 689b ldr r3, [r3, #8] 800585e: f003 0340 and.w r3, r3, #64 @ 0x40 8005862: 2b40 cmp r3, #64 @ 0x40 8005864: d005 beq.n 8005872 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8005866: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800586a: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800586e: 2b00 cmp r3, #0 8005870: d054 beq.n 800591c { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005872: 6878 ldr r0, [r7, #4] 8005874: f000 ffec bl 8006850 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005878: 687b ldr r3, [r7, #4] 800587a: 681b ldr r3, [r3, #0] 800587c: 689b ldr r3, [r3, #8] 800587e: f003 0340 and.w r3, r3, #64 @ 0x40 8005882: 2b40 cmp r3, #64 @ 0x40 8005884: d146 bne.n 8005914 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005886: 687b ldr r3, [r7, #4] 8005888: 681b ldr r3, [r3, #0] 800588a: 3308 adds r3, #8 800588c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005890: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005894: e853 3f00 ldrex r3, [r3] 8005898: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 800589c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80058a0: f023 0340 bic.w r3, r3, #64 @ 0x40 80058a4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80058a8: 687b ldr r3, [r7, #4] 80058aa: 681b ldr r3, [r3, #0] 80058ac: 3308 adds r3, #8 80058ae: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80058b2: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80058b6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80058ba: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80058be: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80058c2: e841 2300 strex r3, r2, [r1] 80058c6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80058ca: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80058ce: 2b00 cmp r3, #0 80058d0: d1d9 bne.n 8005886 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80058d2: 687b ldr r3, [r7, #4] 80058d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80058d8: 2b00 cmp r3, #0 80058da: d017 beq.n 800590c { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80058dc: 687b ldr r3, [r7, #4] 80058de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80058e2: 4a15 ldr r2, [pc, #84] @ (8005938 ) 80058e4: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80058e6: 687b ldr r3, [r7, #4] 80058e8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80058ec: 4618 mov r0, r3 80058ee: f7fc fb97 bl 8002020 80058f2: 4603 mov r3, r0 80058f4: 2b00 cmp r3, #0 80058f6: d019 beq.n 800592c { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80058f8: 687b ldr r3, [r7, #4] 80058fa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80058fe: 6b9b ldr r3, [r3, #56] @ 0x38 8005900: 687a ldr r2, [r7, #4] 8005902: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8005906: 4610 mov r0, r2 8005908: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800590a: e00f b.n 800592c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800590c: 6878 ldr r0, [r7, #4] 800590e: f000 f9fe bl 8005d0e if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005912: e00b b.n 800592c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005914: 6878 ldr r0, [r7, #4] 8005916: f000 f9fa bl 8005d0e if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800591a: e007 b.n 800592c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800591c: 6878 ldr r0, [r7, #4] 800591e: f000 f9f6 bl 8005d0e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005922: 687b ldr r3, [r7, #4] 8005924: 2200 movs r2, #0 8005926: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 800592a: e1dc b.n 8005ce6 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800592c: bf00 nop return; 800592e: e1da b.n 8005ce6 8005930: 10000001 .word 0x10000001 8005934: 04000120 .word 0x04000120 8005938: 08006a39 .word 0x08006a39 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800593c: 687b ldr r3, [r7, #4] 800593e: 6edb ldr r3, [r3, #108] @ 0x6c 8005940: 2b01 cmp r3, #1 8005942: f040 8170 bne.w 8005c26 && ((isrflags & USART_ISR_IDLE) != 0U) 8005946: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800594a: f003 0310 and.w r3, r3, #16 800594e: 2b00 cmp r3, #0 8005950: f000 8169 beq.w 8005c26 && ((cr1its & USART_ISR_IDLE) != 0U)) 8005954: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005958: f003 0310 and.w r3, r3, #16 800595c: 2b00 cmp r3, #0 800595e: f000 8162 beq.w 8005c26 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8005962: 687b ldr r3, [r7, #4] 8005964: 681b ldr r3, [r3, #0] 8005966: 2210 movs r2, #16 8005968: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800596a: 687b ldr r3, [r7, #4] 800596c: 681b ldr r3, [r3, #0] 800596e: 689b ldr r3, [r3, #8] 8005970: f003 0340 and.w r3, r3, #64 @ 0x40 8005974: 2b40 cmp r3, #64 @ 0x40 8005976: f040 80d8 bne.w 8005b2a { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800597a: 687b ldr r3, [r7, #4] 800597c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005980: 681b ldr r3, [r3, #0] 8005982: 685b ldr r3, [r3, #4] 8005984: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005988: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 800598c: 2b00 cmp r3, #0 800598e: f000 80af beq.w 8005af0 && (nb_remaining_rx_data < huart->RxXferSize)) 8005992: 687b ldr r3, [r7, #4] 8005994: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8005998: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800599c: 429a cmp r2, r3 800599e: f080 80a7 bcs.w 8005af0 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80059a2: 687b ldr r3, [r7, #4] 80059a4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80059a8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 80059ac: 687b ldr r3, [r7, #4] 80059ae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80059b2: 681b ldr r3, [r3, #0] 80059b4: 681b ldr r3, [r3, #0] 80059b6: f003 0320 and.w r3, r3, #32 80059ba: 2b00 cmp r3, #0 80059bc: f040 8087 bne.w 8005ace { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80059c0: 687b ldr r3, [r7, #4] 80059c2: 681b ldr r3, [r3, #0] 80059c4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80059c8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80059cc: e853 3f00 ldrex r3, [r3] 80059d0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80059d4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80059d8: f423 7380 bic.w r3, r3, #256 @ 0x100 80059dc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80059e0: 687b ldr r3, [r7, #4] 80059e2: 681b ldr r3, [r3, #0] 80059e4: 461a mov r2, r3 80059e6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80059ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80059ee: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80059f2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80059f6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80059fa: e841 2300 strex r3, r2, [r1] 80059fe: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005a02: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005a06: 2b00 cmp r3, #0 8005a08: d1da bne.n 80059c0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005a0a: 687b ldr r3, [r7, #4] 8005a0c: 681b ldr r3, [r3, #0] 8005a0e: 3308 adds r3, #8 8005a10: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005a12: 6f7b ldr r3, [r7, #116] @ 0x74 8005a14: e853 3f00 ldrex r3, [r3] 8005a18: 673b str r3, [r7, #112] @ 0x70 return(result); 8005a1a: 6f3b ldr r3, [r7, #112] @ 0x70 8005a1c: f023 0301 bic.w r3, r3, #1 8005a20: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005a24: 687b ldr r3, [r7, #4] 8005a26: 681b ldr r3, [r3, #0] 8005a28: 3308 adds r3, #8 8005a2a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8005a2e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8005a32: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005a34: 6ff9 ldr r1, [r7, #124] @ 0x7c 8005a36: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8005a3a: e841 2300 strex r3, r2, [r1] 8005a3e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8005a40: 6fbb ldr r3, [r7, #120] @ 0x78 8005a42: 2b00 cmp r3, #0 8005a44: d1e1 bne.n 8005a0a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005a46: 687b ldr r3, [r7, #4] 8005a48: 681b ldr r3, [r3, #0] 8005a4a: 3308 adds r3, #8 8005a4c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005a4e: 6e3b ldr r3, [r7, #96] @ 0x60 8005a50: e853 3f00 ldrex r3, [r3] 8005a54: 65fb str r3, [r7, #92] @ 0x5c return(result); 8005a56: 6dfb ldr r3, [r7, #92] @ 0x5c 8005a58: f023 0340 bic.w r3, r3, #64 @ 0x40 8005a5c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8005a60: 687b ldr r3, [r7, #4] 8005a62: 681b ldr r3, [r3, #0] 8005a64: 3308 adds r3, #8 8005a66: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8005a6a: 66fa str r2, [r7, #108] @ 0x6c 8005a6c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005a6e: 6eb9 ldr r1, [r7, #104] @ 0x68 8005a70: 6efa ldr r2, [r7, #108] @ 0x6c 8005a72: e841 2300 strex r3, r2, [r1] 8005a76: 667b str r3, [r7, #100] @ 0x64 return(result); 8005a78: 6e7b ldr r3, [r7, #100] @ 0x64 8005a7a: 2b00 cmp r3, #0 8005a7c: d1e3 bne.n 8005a46 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005a7e: 687b ldr r3, [r7, #4] 8005a80: 2220 movs r2, #32 8005a82: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005a86: 687b ldr r3, [r7, #4] 8005a88: 2200 movs r2, #0 8005a8a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005a8c: 687b ldr r3, [r7, #4] 8005a8e: 681b ldr r3, [r3, #0] 8005a90: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005a92: 6cfb ldr r3, [r7, #76] @ 0x4c 8005a94: e853 3f00 ldrex r3, [r3] 8005a98: 64bb str r3, [r7, #72] @ 0x48 return(result); 8005a9a: 6cbb ldr r3, [r7, #72] @ 0x48 8005a9c: f023 0310 bic.w r3, r3, #16 8005aa0: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8005aa4: 687b ldr r3, [r7, #4] 8005aa6: 681b ldr r3, [r3, #0] 8005aa8: 461a mov r2, r3 8005aaa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8005aae: 65bb str r3, [r7, #88] @ 0x58 8005ab0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ab2: 6d79 ldr r1, [r7, #84] @ 0x54 8005ab4: 6dba ldr r2, [r7, #88] @ 0x58 8005ab6: e841 2300 strex r3, r2, [r1] 8005aba: 653b str r3, [r7, #80] @ 0x50 return(result); 8005abc: 6d3b ldr r3, [r7, #80] @ 0x50 8005abe: 2b00 cmp r3, #0 8005ac0: d1e4 bne.n 8005a8c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8005ac2: 687b ldr r3, [r7, #4] 8005ac4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005ac8: 4618 mov r0, r3 8005aca: f7fc fa4b bl 8001f64 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005ace: 687b ldr r3, [r7, #4] 8005ad0: 2202 movs r2, #2 8005ad2: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8005ada: 687b ldr r3, [r7, #4] 8005adc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8005ae0: b29b uxth r3, r3 8005ae2: 1ad3 subs r3, r2, r3 8005ae4: b29b uxth r3, r3 8005ae6: 4619 mov r1, r3 8005ae8: 6878 ldr r0, [r7, #4] 8005aea: f000 f919 bl 8005d20 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8005aee: e0fc b.n 8005cea if (nb_remaining_rx_data == huart->RxXferSize) 8005af0: 687b ldr r3, [r7, #4] 8005af2: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8005af6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005afa: 429a cmp r2, r3 8005afc: f040 80f5 bne.w 8005cea if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 8005b00: 687b ldr r3, [r7, #4] 8005b02: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005b06: 681b ldr r3, [r3, #0] 8005b08: 681b ldr r3, [r3, #0] 8005b0a: f003 0320 and.w r3, r3, #32 8005b0e: 2b20 cmp r3, #32 8005b10: f040 80eb bne.w 8005cea huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005b14: 687b ldr r3, [r7, #4] 8005b16: 2202 movs r2, #2 8005b18: 671a str r2, [r3, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8005b1a: 687b ldr r3, [r7, #4] 8005b1c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8005b20: 4619 mov r1, r3 8005b22: 6878 ldr r0, [r7, #4] 8005b24: f000 f8fc bl 8005d20 return; 8005b28: e0df b.n 8005cea else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8005b2a: 687b ldr r3, [r7, #4] 8005b2c: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8005b30: 687b ldr r3, [r7, #4] 8005b32: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8005b36: b29b uxth r3, r3 8005b38: 1ad3 subs r3, r2, r3 8005b3a: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8005b3e: 687b ldr r3, [r7, #4] 8005b40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8005b44: b29b uxth r3, r3 8005b46: 2b00 cmp r3, #0 8005b48: f000 80d1 beq.w 8005cee && (nb_rx_data > 0U)) 8005b4c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8005b50: 2b00 cmp r3, #0 8005b52: f000 80cc beq.w 8005cee { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8005b56: 687b ldr r3, [r7, #4] 8005b58: 681b ldr r3, [r3, #0] 8005b5a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b5c: 6bbb ldr r3, [r7, #56] @ 0x38 8005b5e: e853 3f00 ldrex r3, [r3] 8005b62: 637b str r3, [r7, #52] @ 0x34 return(result); 8005b64: 6b7b ldr r3, [r7, #52] @ 0x34 8005b66: f423 7390 bic.w r3, r3, #288 @ 0x120 8005b6a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8005b6e: 687b ldr r3, [r7, #4] 8005b70: 681b ldr r3, [r3, #0] 8005b72: 461a mov r2, r3 8005b74: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8005b78: 647b str r3, [r7, #68] @ 0x44 8005b7a: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005b7c: 6c39 ldr r1, [r7, #64] @ 0x40 8005b7e: 6c7a ldr r2, [r7, #68] @ 0x44 8005b80: e841 2300 strex r3, r2, [r1] 8005b84: 63fb str r3, [r7, #60] @ 0x3c return(result); 8005b86: 6bfb ldr r3, [r7, #60] @ 0x3c 8005b88: 2b00 cmp r3, #0 8005b8a: d1e4 bne.n 8005b56 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8005b8c: 687b ldr r3, [r7, #4] 8005b8e: 681b ldr r3, [r3, #0] 8005b90: 3308 adds r3, #8 8005b92: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b94: 6a7b ldr r3, [r7, #36] @ 0x24 8005b96: e853 3f00 ldrex r3, [r3] 8005b9a: 623b str r3, [r7, #32] return(result); 8005b9c: 6a3b ldr r3, [r7, #32] 8005b9e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005ba2: f023 0301 bic.w r3, r3, #1 8005ba6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8005baa: 687b ldr r3, [r7, #4] 8005bac: 681b ldr r3, [r3, #0] 8005bae: 3308 adds r3, #8 8005bb0: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8005bb4: 633a str r2, [r7, #48] @ 0x30 8005bb6: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005bb8: 6af9 ldr r1, [r7, #44] @ 0x2c 8005bba: 6b3a ldr r2, [r7, #48] @ 0x30 8005bbc: e841 2300 strex r3, r2, [r1] 8005bc0: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005bc2: 6abb ldr r3, [r7, #40] @ 0x28 8005bc4: 2b00 cmp r3, #0 8005bc6: d1e1 bne.n 8005b8c /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005bc8: 687b ldr r3, [r7, #4] 8005bca: 2220 movs r2, #32 8005bcc: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 2200 movs r2, #0 8005bd4: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8005bd6: 687b ldr r3, [r7, #4] 8005bd8: 2200 movs r2, #0 8005bda: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 681b ldr r3, [r3, #0] 8005be0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005be2: 693b ldr r3, [r7, #16] 8005be4: e853 3f00 ldrex r3, [r3] 8005be8: 60fb str r3, [r7, #12] return(result); 8005bea: 68fb ldr r3, [r7, #12] 8005bec: f023 0310 bic.w r3, r3, #16 8005bf0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005bf4: 687b ldr r3, [r7, #4] 8005bf6: 681b ldr r3, [r3, #0] 8005bf8: 461a mov r2, r3 8005bfa: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8005bfe: 61fb str r3, [r7, #28] 8005c00: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005c02: 69b9 ldr r1, [r7, #24] 8005c04: 69fa ldr r2, [r7, #28] 8005c06: e841 2300 strex r3, r2, [r1] 8005c0a: 617b str r3, [r7, #20] return(result); 8005c0c: 697b ldr r3, [r7, #20] 8005c0e: 2b00 cmp r3, #0 8005c10: d1e4 bne.n 8005bdc /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005c12: 687b ldr r3, [r7, #4] 8005c14: 2202 movs r2, #2 8005c16: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8005c18: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8005c1c: 4619 mov r1, r3 8005c1e: 6878 ldr r0, [r7, #4] 8005c20: f000 f87e bl 8005d20 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8005c24: e063 b.n 8005cee } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8005c26: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c2a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8005c2e: 2b00 cmp r3, #0 8005c30: d00e beq.n 8005c50 8005c32: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005c36: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005c3a: 2b00 cmp r3, #0 8005c3c: d008 beq.n 8005c50 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8005c3e: 687b ldr r3, [r7, #4] 8005c40: 681b ldr r3, [r3, #0] 8005c42: f44f 1280 mov.w r2, #1048576 @ 0x100000 8005c46: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8005c48: 6878 ldr r0, [r7, #4] 8005c4a: f001 fc4f bl 80074ec #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8005c4e: e051 b.n 8005cf4 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8005c50: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c54: f003 0380 and.w r3, r3, #128 @ 0x80 8005c58: 2b00 cmp r3, #0 8005c5a: d014 beq.n 8005c86 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8005c5c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005c60: f003 0380 and.w r3, r3, #128 @ 0x80 8005c64: 2b00 cmp r3, #0 8005c66: d105 bne.n 8005c74 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8005c68: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005c6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8005c70: 2b00 cmp r3, #0 8005c72: d008 beq.n 8005c86 { if (huart->TxISR != NULL) 8005c74: 687b ldr r3, [r7, #4] 8005c76: 6f9b ldr r3, [r3, #120] @ 0x78 8005c78: 2b00 cmp r3, #0 8005c7a: d03a beq.n 8005cf2 { huart->TxISR(huart); 8005c7c: 687b ldr r3, [r7, #4] 8005c7e: 6f9b ldr r3, [r3, #120] @ 0x78 8005c80: 6878 ldr r0, [r7, #4] 8005c82: 4798 blx r3 } return; 8005c84: e035 b.n 8005cf2 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8005c86: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c8a: f003 0340 and.w r3, r3, #64 @ 0x40 8005c8e: 2b00 cmp r3, #0 8005c90: d009 beq.n 8005ca6 8005c92: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005c96: f003 0340 and.w r3, r3, #64 @ 0x40 8005c9a: 2b00 cmp r3, #0 8005c9c: d003 beq.n 8005ca6 { UART_EndTransmit_IT(huart); 8005c9e: 6878 ldr r0, [r7, #4] 8005ca0: f000 fed8 bl 8006a54 return; 8005ca4: e026 b.n 8005cf4 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8005ca6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005caa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8005cae: 2b00 cmp r3, #0 8005cb0: d009 beq.n 8005cc6 8005cb2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005cb6: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8005cba: 2b00 cmp r3, #0 8005cbc: d003 beq.n 8005cc6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8005cbe: 6878 ldr r0, [r7, #4] 8005cc0: f001 fc26 bl 8007510 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8005cc4: e016 b.n 8005cf4 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8005cc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005cca: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8005cce: 2b00 cmp r3, #0 8005cd0: d010 beq.n 8005cf4 8005cd2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005cd6: 2b00 cmp r3, #0 8005cd8: da0c bge.n 8005cf4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8005cda: 6878 ldr r0, [r7, #4] 8005cdc: f001 fc0f bl 80074fe #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8005ce0: e008 b.n 8005cf4 return; 8005ce2: bf00 nop 8005ce4: e006 b.n 8005cf4 return; 8005ce6: bf00 nop 8005ce8: e004 b.n 8005cf4 return; 8005cea: bf00 nop 8005cec: e002 b.n 8005cf4 return; 8005cee: bf00 nop 8005cf0: e000 b.n 8005cf4 return; 8005cf2: bf00 nop } } 8005cf4: 37e8 adds r7, #232 @ 0xe8 8005cf6: 46bd mov sp, r7 8005cf8: bd80 pop {r7, pc} 8005cfa: bf00 nop 08005cfc : * @brief Tx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8005cfc: b480 push {r7} 8005cfe: b083 sub sp, #12 8005d00: af00 add r7, sp, #0 8005d02: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ } 8005d04: bf00 nop 8005d06: 370c adds r7, #12 8005d08: 46bd mov sp, r7 8005d0a: bc80 pop {r7} 8005d0c: 4770 bx lr 08005d0e : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8005d0e: b480 push {r7} 8005d10: b083 sub sp, #12 8005d12: af00 add r7, sp, #0 8005d14: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8005d16: bf00 nop 8005d18: 370c adds r7, #12 8005d1a: 46bd mov sp, r7 8005d1c: bc80 pop {r7} 8005d1e: 4770 bx lr 08005d20 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8005d20: b480 push {r7} 8005d22: b083 sub sp, #12 8005d24: af00 add r7, sp, #0 8005d26: 6078 str r0, [r7, #4] 8005d28: 460b mov r3, r1 8005d2a: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8005d2c: bf00 nop 8005d2e: 370c adds r7, #12 8005d30: 46bd mov sp, r7 8005d32: bc80 pop {r7} 8005d34: 4770 bx lr ... 08005d38 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8005d38: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8005d3c: b08c sub sp, #48 @ 0x30 8005d3e: af00 add r7, sp, #0 8005d40: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8005d42: 2300 movs r3, #0 8005d44: f887 302a strb.w r3, [r7, #42] @ 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8005d48: 697b ldr r3, [r7, #20] 8005d4a: 689a ldr r2, [r3, #8] 8005d4c: 697b ldr r3, [r7, #20] 8005d4e: 691b ldr r3, [r3, #16] 8005d50: 431a orrs r2, r3 8005d52: 697b ldr r3, [r7, #20] 8005d54: 695b ldr r3, [r3, #20] 8005d56: 431a orrs r2, r3 8005d58: 697b ldr r3, [r7, #20] 8005d5a: 69db ldr r3, [r3, #28] 8005d5c: 4313 orrs r3, r2 8005d5e: 62fb str r3, [r7, #44] @ 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8005d60: 697b ldr r3, [r7, #20] 8005d62: 681b ldr r3, [r3, #0] 8005d64: 681a ldr r2, [r3, #0] 8005d66: 4b94 ldr r3, [pc, #592] @ (8005fb8 ) 8005d68: 4013 ands r3, r2 8005d6a: 697a ldr r2, [r7, #20] 8005d6c: 6812 ldr r2, [r2, #0] 8005d6e: 6af9 ldr r1, [r7, #44] @ 0x2c 8005d70: 430b orrs r3, r1 8005d72: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005d74: 697b ldr r3, [r7, #20] 8005d76: 681b ldr r3, [r3, #0] 8005d78: 685b ldr r3, [r3, #4] 8005d7a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8005d7e: 697b ldr r3, [r7, #20] 8005d80: 68da ldr r2, [r3, #12] 8005d82: 697b ldr r3, [r7, #20] 8005d84: 681b ldr r3, [r3, #0] 8005d86: 430a orrs r2, r1 8005d88: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8005d8a: 697b ldr r3, [r7, #20] 8005d8c: 699b ldr r3, [r3, #24] 8005d8e: 62fb str r3, [r7, #44] @ 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) 8005d90: 697b ldr r3, [r7, #20] 8005d92: 681b ldr r3, [r3, #0] 8005d94: 4a89 ldr r2, [pc, #548] @ (8005fbc ) 8005d96: 4293 cmp r3, r2 8005d98: d004 beq.n 8005da4 { tmpreg |= huart->Init.OneBitSampling; 8005d9a: 697b ldr r3, [r7, #20] 8005d9c: 6a1b ldr r3, [r3, #32] 8005d9e: 6afa ldr r2, [r7, #44] @ 0x2c 8005da0: 4313 orrs r3, r2 8005da2: 62fb str r3, [r7, #44] @ 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8005da4: 697b ldr r3, [r7, #20] 8005da6: 681b ldr r3, [r3, #0] 8005da8: 689b ldr r3, [r3, #8] 8005daa: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 8005dae: f423 6330 bic.w r3, r3, #2816 @ 0xb00 8005db2: 697a ldr r2, [r7, #20] 8005db4: 6812 ldr r2, [r2, #0] 8005db6: 6af9 ldr r1, [r7, #44] @ 0x2c 8005db8: 430b orrs r3, r1 8005dba: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8005dbc: 697b ldr r3, [r7, #20] 8005dbe: 681b ldr r3, [r3, #0] 8005dc0: 6adb ldr r3, [r3, #44] @ 0x2c 8005dc2: f023 010f bic.w r1, r3, #15 8005dc6: 697b ldr r3, [r7, #20] 8005dc8: 6a5a ldr r2, [r3, #36] @ 0x24 8005dca: 697b ldr r3, [r7, #20] 8005dcc: 681b ldr r3, [r3, #0] 8005dce: 430a orrs r2, r1 8005dd0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8005dd2: 697b ldr r3, [r7, #20] 8005dd4: 681b ldr r3, [r3, #0] 8005dd6: 4a7a ldr r2, [pc, #488] @ (8005fc0 ) 8005dd8: 4293 cmp r3, r2 8005dda: d127 bne.n 8005e2c 8005ddc: 2003 movs r0, #3 8005dde: f7ff f9c3 bl 8005168 8005de2: 4603 mov r3, r0 8005de4: f5a3 3340 sub.w r3, r3, #196608 @ 0x30000 8005de8: 2b03 cmp r3, #3 8005dea: d81b bhi.n 8005e24 8005dec: a201 add r2, pc, #4 @ (adr r2, 8005df4 ) 8005dee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005df2: bf00 nop 8005df4: 08005e05 .word 0x08005e05 8005df8: 08005e15 .word 0x08005e15 8005dfc: 08005e0d .word 0x08005e0d 8005e00: 08005e1d .word 0x08005e1d 8005e04: 2301 movs r3, #1 8005e06: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e0a: e080 b.n 8005f0e 8005e0c: 2302 movs r3, #2 8005e0e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e12: e07c b.n 8005f0e 8005e14: 2304 movs r3, #4 8005e16: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e1a: e078 b.n 8005f0e 8005e1c: 2308 movs r3, #8 8005e1e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e22: e074 b.n 8005f0e 8005e24: 2310 movs r3, #16 8005e26: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e2a: e070 b.n 8005f0e 8005e2c: 697b ldr r3, [r7, #20] 8005e2e: 681b ldr r3, [r3, #0] 8005e30: 4a64 ldr r2, [pc, #400] @ (8005fc4 ) 8005e32: 4293 cmp r3, r2 8005e34: d138 bne.n 8005ea8 8005e36: 200c movs r0, #12 8005e38: f7ff f996 bl 8005168 8005e3c: 4603 mov r3, r0 8005e3e: f5a3 2340 sub.w r3, r3, #786432 @ 0xc0000 8005e42: 2b0c cmp r3, #12 8005e44: d82c bhi.n 8005ea0 8005e46: a201 add r2, pc, #4 @ (adr r2, 8005e4c ) 8005e48: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005e4c: 08005e81 .word 0x08005e81 8005e50: 08005ea1 .word 0x08005ea1 8005e54: 08005ea1 .word 0x08005ea1 8005e58: 08005ea1 .word 0x08005ea1 8005e5c: 08005e91 .word 0x08005e91 8005e60: 08005ea1 .word 0x08005ea1 8005e64: 08005ea1 .word 0x08005ea1 8005e68: 08005ea1 .word 0x08005ea1 8005e6c: 08005e89 .word 0x08005e89 8005e70: 08005ea1 .word 0x08005ea1 8005e74: 08005ea1 .word 0x08005ea1 8005e78: 08005ea1 .word 0x08005ea1 8005e7c: 08005e99 .word 0x08005e99 8005e80: 2300 movs r3, #0 8005e82: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e86: e042 b.n 8005f0e 8005e88: 2302 movs r3, #2 8005e8a: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e8e: e03e b.n 8005f0e 8005e90: 2304 movs r3, #4 8005e92: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e96: e03a b.n 8005f0e 8005e98: 2308 movs r3, #8 8005e9a: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005e9e: e036 b.n 8005f0e 8005ea0: 2310 movs r3, #16 8005ea2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005ea6: e032 b.n 8005f0e 8005ea8: 697b ldr r3, [r7, #20] 8005eaa: 681b ldr r3, [r3, #0] 8005eac: 4a43 ldr r2, [pc, #268] @ (8005fbc ) 8005eae: 4293 cmp r3, r2 8005eb0: d12a bne.n 8005f08 8005eb2: f44f 6040 mov.w r0, #3072 @ 0xc00 8005eb6: f7ff f969 bl 800518c 8005eba: 4603 mov r3, r0 8005ebc: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8005ec0: d01a beq.n 8005ef8 8005ec2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8005ec6: d81b bhi.n 8005f00 8005ec8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8005ecc: d00c beq.n 8005ee8 8005ece: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8005ed2: d815 bhi.n 8005f00 8005ed4: 2b00 cmp r3, #0 8005ed6: d003 beq.n 8005ee0 8005ed8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005edc: d008 beq.n 8005ef0 8005ede: e00f b.n 8005f00 8005ee0: 2300 movs r3, #0 8005ee2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005ee6: e012 b.n 8005f0e 8005ee8: 2302 movs r3, #2 8005eea: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005eee: e00e b.n 8005f0e 8005ef0: 2304 movs r3, #4 8005ef2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005ef6: e00a b.n 8005f0e 8005ef8: 2308 movs r3, #8 8005efa: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005efe: e006 b.n 8005f0e 8005f00: 2310 movs r3, #16 8005f02: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005f06: e002 b.n 8005f0e 8005f08: 2310 movs r3, #16 8005f0a: f887 302b strb.w r3, [r7, #43] @ 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8005f0e: 697b ldr r3, [r7, #20] 8005f10: 681b ldr r3, [r3, #0] 8005f12: 4a2a ldr r2, [pc, #168] @ (8005fbc ) 8005f14: 4293 cmp r3, r2 8005f16: f040 80a4 bne.w 8006062 { /* Retrieve frequency clock */ switch (clocksource) 8005f1a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8005f1e: 2b08 cmp r3, #8 8005f20: d823 bhi.n 8005f6a 8005f22: a201 add r2, pc, #4 @ (adr r2, 8005f28 ) 8005f24: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005f28: 08005f4d .word 0x08005f4d 8005f2c: 08005f6b .word 0x08005f6b 8005f30: 08005f55 .word 0x08005f55 8005f34: 08005f6b .word 0x08005f6b 8005f38: 08005f5b .word 0x08005f5b 8005f3c: 08005f6b .word 0x08005f6b 8005f40: 08005f6b .word 0x08005f6b 8005f44: 08005f6b .word 0x08005f6b 8005f48: 08005f63 .word 0x08005f63 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005f4c: f7fd fdc6 bl 8003adc 8005f50: 6278 str r0, [r7, #36] @ 0x24 break; 8005f52: e010 b.n 8005f76 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8005f54: 4b1c ldr r3, [pc, #112] @ (8005fc8 ) 8005f56: 627b str r3, [r7, #36] @ 0x24 break; 8005f58: e00d b.n 8005f76 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8005f5a: f7fd fd0b bl 8003974 8005f5e: 6278 str r0, [r7, #36] @ 0x24 break; 8005f60: e009 b.n 8005f76 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8005f62: f44f 4300 mov.w r3, #32768 @ 0x8000 8005f66: 627b str r3, [r7, #36] @ 0x24 break; 8005f68: e005 b.n 8005f76 default: pclk = 0U; 8005f6a: 2300 movs r3, #0 8005f6c: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8005f6e: 2301 movs r3, #1 8005f70: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8005f74: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 8005f76: 6a7b ldr r3, [r7, #36] @ 0x24 8005f78: 2b00 cmp r3, #0 8005f7a: f000 8137 beq.w 80061ec { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8005f7e: 697b ldr r3, [r7, #20] 8005f80: 6a5b ldr r3, [r3, #36] @ 0x24 8005f82: 4a12 ldr r2, [pc, #72] @ (8005fcc ) 8005f84: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005f88: 461a mov r2, r3 8005f8a: 6a7b ldr r3, [r7, #36] @ 0x24 8005f8c: fbb3 f3f2 udiv r3, r3, r2 8005f90: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8005f92: 697b ldr r3, [r7, #20] 8005f94: 685a ldr r2, [r3, #4] 8005f96: 4613 mov r3, r2 8005f98: 005b lsls r3, r3, #1 8005f9a: 4413 add r3, r2 8005f9c: 69ba ldr r2, [r7, #24] 8005f9e: 429a cmp r2, r3 8005fa0: d305 bcc.n 8005fae (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8005fa2: 697b ldr r3, [r7, #20] 8005fa4: 685b ldr r3, [r3, #4] 8005fa6: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8005fa8: 69ba ldr r2, [r7, #24] 8005faa: 429a cmp r2, r3 8005fac: d910 bls.n 8005fd0 { ret = HAL_ERROR; 8005fae: 2301 movs r3, #1 8005fb0: f887 302a strb.w r3, [r7, #42] @ 0x2a 8005fb4: e11a b.n 80061ec 8005fb6: bf00 nop 8005fb8: cfff69f3 .word 0xcfff69f3 8005fbc: 40008000 .word 0x40008000 8005fc0: 40013800 .word 0x40013800 8005fc4: 40004400 .word 0x40004400 8005fc8: 00f42400 .word 0x00f42400 8005fcc: 0800fb54 .word 0x0800fb54 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8005fd0: 6a7b ldr r3, [r7, #36] @ 0x24 8005fd2: 2200 movs r2, #0 8005fd4: 60bb str r3, [r7, #8] 8005fd6: 60fa str r2, [r7, #12] 8005fd8: 697b ldr r3, [r7, #20] 8005fda: 6a5b ldr r3, [r3, #36] @ 0x24 8005fdc: 4a8e ldr r2, [pc, #568] @ (8006218 ) 8005fde: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005fe2: b29b uxth r3, r3 8005fe4: 2200 movs r2, #0 8005fe6: 603b str r3, [r7, #0] 8005fe8: 607a str r2, [r7, #4] 8005fea: e9d7 2300 ldrd r2, r3, [r7] 8005fee: e9d7 0102 ldrd r0, r1, [r7, #8] 8005ff2: f7fa f92d bl 8000250 <__aeabi_uldivmod> 8005ff6: 4602 mov r2, r0 8005ff8: 460b mov r3, r1 8005ffa: 4610 mov r0, r2 8005ffc: 4619 mov r1, r3 8005ffe: f04f 0200 mov.w r2, #0 8006002: f04f 0300 mov.w r3, #0 8006006: 020b lsls r3, r1, #8 8006008: ea43 6310 orr.w r3, r3, r0, lsr #24 800600c: 0202 lsls r2, r0, #8 800600e: 6979 ldr r1, [r7, #20] 8006010: 6849 ldr r1, [r1, #4] 8006012: 0849 lsrs r1, r1, #1 8006014: 2000 movs r0, #0 8006016: 460c mov r4, r1 8006018: 4605 mov r5, r0 800601a: eb12 0804 adds.w r8, r2, r4 800601e: eb43 0905 adc.w r9, r3, r5 8006022: 697b ldr r3, [r7, #20] 8006024: 685b ldr r3, [r3, #4] 8006026: 2200 movs r2, #0 8006028: 469a mov sl, r3 800602a: 4693 mov fp, r2 800602c: 4652 mov r2, sl 800602e: 465b mov r3, fp 8006030: 4640 mov r0, r8 8006032: 4649 mov r1, r9 8006034: f7fa f90c bl 8000250 <__aeabi_uldivmod> 8006038: 4602 mov r2, r0 800603a: 460b mov r3, r1 800603c: 4613 mov r3, r2 800603e: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8006040: 6a3b ldr r3, [r7, #32] 8006042: f5b3 7f40 cmp.w r3, #768 @ 0x300 8006046: d308 bcc.n 800605a 8006048: 6a3b ldr r3, [r7, #32] 800604a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800604e: d204 bcs.n 800605a { huart->Instance->BRR = usartdiv; 8006050: 697b ldr r3, [r7, #20] 8006052: 681b ldr r3, [r3, #0] 8006054: 6a3a ldr r2, [r7, #32] 8006056: 60da str r2, [r3, #12] 8006058: e0c8 b.n 80061ec } else { ret = HAL_ERROR; 800605a: 2301 movs r3, #1 800605c: f887 302a strb.w r3, [r7, #42] @ 0x2a 8006060: e0c4 b.n 80061ec } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006062: 697b ldr r3, [r7, #20] 8006064: 69db ldr r3, [r3, #28] 8006066: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800606a: d167 bne.n 800613c { switch (clocksource) 800606c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8006070: 2b08 cmp r3, #8 8006072: d828 bhi.n 80060c6 8006074: a201 add r2, pc, #4 @ (adr r2, 800607c ) 8006076: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800607a: bf00 nop 800607c: 080060a1 .word 0x080060a1 8006080: 080060a9 .word 0x080060a9 8006084: 080060b1 .word 0x080060b1 8006088: 080060c7 .word 0x080060c7 800608c: 080060b7 .word 0x080060b7 8006090: 080060c7 .word 0x080060c7 8006094: 080060c7 .word 0x080060c7 8006098: 080060c7 .word 0x080060c7 800609c: 080060bf .word 0x080060bf { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80060a0: f7fd fd1c bl 8003adc 80060a4: 6278 str r0, [r7, #36] @ 0x24 break; 80060a6: e014 b.n 80060d2 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80060a8: f7fd fd2a bl 8003b00 80060ac: 6278 str r0, [r7, #36] @ 0x24 break; 80060ae: e010 b.n 80060d2 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 80060b0: 4b5a ldr r3, [pc, #360] @ (800621c ) 80060b2: 627b str r3, [r7, #36] @ 0x24 break; 80060b4: e00d b.n 80060d2 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 80060b6: f7fd fc5d bl 8003974 80060ba: 6278 str r0, [r7, #36] @ 0x24 break; 80060bc: e009 b.n 80060d2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80060be: f44f 4300 mov.w r3, #32768 @ 0x8000 80060c2: 627b str r3, [r7, #36] @ 0x24 break; 80060c4: e005 b.n 80060d2 default: pclk = 0U; 80060c6: 2300 movs r3, #0 80060c8: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 80060ca: 2301 movs r3, #1 80060cc: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 80060d0: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80060d2: 6a7b ldr r3, [r7, #36] @ 0x24 80060d4: 2b00 cmp r3, #0 80060d6: f000 8089 beq.w 80061ec { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80060da: 697b ldr r3, [r7, #20] 80060dc: 6a5b ldr r3, [r3, #36] @ 0x24 80060de: 4a4e ldr r2, [pc, #312] @ (8006218 ) 80060e0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80060e4: 461a mov r2, r3 80060e6: 6a7b ldr r3, [r7, #36] @ 0x24 80060e8: fbb3 f3f2 udiv r3, r3, r2 80060ec: 005a lsls r2, r3, #1 80060ee: 697b ldr r3, [r7, #20] 80060f0: 685b ldr r3, [r3, #4] 80060f2: 085b lsrs r3, r3, #1 80060f4: 441a add r2, r3 80060f6: 697b ldr r3, [r7, #20] 80060f8: 685b ldr r3, [r3, #4] 80060fa: fbb2 f3f3 udiv r3, r2, r3 80060fe: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8006100: 6a3b ldr r3, [r7, #32] 8006102: 2b0f cmp r3, #15 8006104: d916 bls.n 8006134 8006106: 6a3b ldr r3, [r7, #32] 8006108: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800610c: d212 bcs.n 8006134 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800610e: 6a3b ldr r3, [r7, #32] 8006110: b29b uxth r3, r3 8006112: f023 030f bic.w r3, r3, #15 8006116: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8006118: 6a3b ldr r3, [r7, #32] 800611a: 085b lsrs r3, r3, #1 800611c: b29b uxth r3, r3 800611e: f003 0307 and.w r3, r3, #7 8006122: b29a uxth r2, r3 8006124: 8bfb ldrh r3, [r7, #30] 8006126: 4313 orrs r3, r2 8006128: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; 800612a: 697b ldr r3, [r7, #20] 800612c: 681b ldr r3, [r3, #0] 800612e: 8bfa ldrh r2, [r7, #30] 8006130: 60da str r2, [r3, #12] 8006132: e05b b.n 80061ec } else { ret = HAL_ERROR; 8006134: 2301 movs r3, #1 8006136: f887 302a strb.w r3, [r7, #42] @ 0x2a 800613a: e057 b.n 80061ec } } } else { switch (clocksource) 800613c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8006140: 2b08 cmp r3, #8 8006142: d828 bhi.n 8006196 8006144: a201 add r2, pc, #4 @ (adr r2, 800614c ) 8006146: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800614a: bf00 nop 800614c: 08006171 .word 0x08006171 8006150: 08006179 .word 0x08006179 8006154: 08006181 .word 0x08006181 8006158: 08006197 .word 0x08006197 800615c: 08006187 .word 0x08006187 8006160: 08006197 .word 0x08006197 8006164: 08006197 .word 0x08006197 8006168: 08006197 .word 0x08006197 800616c: 0800618f .word 0x0800618f { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8006170: f7fd fcb4 bl 8003adc 8006174: 6278 str r0, [r7, #36] @ 0x24 break; 8006176: e014 b.n 80061a2 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8006178: f7fd fcc2 bl 8003b00 800617c: 6278 str r0, [r7, #36] @ 0x24 break; 800617e: e010 b.n 80061a2 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8006180: 4b26 ldr r3, [pc, #152] @ (800621c ) 8006182: 627b str r3, [r7, #36] @ 0x24 break; 8006184: e00d b.n 80061a2 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8006186: f7fd fbf5 bl 8003974 800618a: 6278 str r0, [r7, #36] @ 0x24 break; 800618c: e009 b.n 80061a2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800618e: f44f 4300 mov.w r3, #32768 @ 0x8000 8006192: 627b str r3, [r7, #36] @ 0x24 break; 8006194: e005 b.n 80061a2 default: pclk = 0U; 8006196: 2300 movs r3, #0 8006198: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 800619a: 2301 movs r3, #1 800619c: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 80061a0: bf00 nop } if (pclk != 0U) 80061a2: 6a7b ldr r3, [r7, #36] @ 0x24 80061a4: 2b00 cmp r3, #0 80061a6: d021 beq.n 80061ec { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80061a8: 697b ldr r3, [r7, #20] 80061aa: 6a5b ldr r3, [r3, #36] @ 0x24 80061ac: 4a1a ldr r2, [pc, #104] @ (8006218 ) 80061ae: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80061b2: 461a mov r2, r3 80061b4: 6a7b ldr r3, [r7, #36] @ 0x24 80061b6: fbb3 f2f2 udiv r2, r3, r2 80061ba: 697b ldr r3, [r7, #20] 80061bc: 685b ldr r3, [r3, #4] 80061be: 085b lsrs r3, r3, #1 80061c0: 441a add r2, r3 80061c2: 697b ldr r3, [r7, #20] 80061c4: 685b ldr r3, [r3, #4] 80061c6: fbb2 f3f3 udiv r3, r2, r3 80061ca: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80061cc: 6a3b ldr r3, [r7, #32] 80061ce: 2b0f cmp r3, #15 80061d0: d909 bls.n 80061e6 80061d2: 6a3b ldr r3, [r7, #32] 80061d4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80061d8: d205 bcs.n 80061e6 { huart->Instance->BRR = (uint16_t)usartdiv; 80061da: 6a3b ldr r3, [r7, #32] 80061dc: b29a uxth r2, r3 80061de: 697b ldr r3, [r7, #20] 80061e0: 681b ldr r3, [r3, #0] 80061e2: 60da str r2, [r3, #12] 80061e4: e002 b.n 80061ec } else { ret = HAL_ERROR; 80061e6: 2301 movs r3, #1 80061e8: f887 302a strb.w r3, [r7, #42] @ 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80061ec: 697b ldr r3, [r7, #20] 80061ee: 2201 movs r2, #1 80061f0: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 80061f4: 697b ldr r3, [r7, #20] 80061f6: 2201 movs r2, #1 80061f8: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 80061fc: 697b ldr r3, [r7, #20] 80061fe: 2200 movs r2, #0 8006200: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8006202: 697b ldr r3, [r7, #20] 8006204: 2200 movs r2, #0 8006206: 679a str r2, [r3, #120] @ 0x78 return ret; 8006208: f897 302a ldrb.w r3, [r7, #42] @ 0x2a } 800620c: 4618 mov r0, r3 800620e: 3730 adds r7, #48 @ 0x30 8006210: 46bd mov sp, r7 8006212: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006216: bf00 nop 8006218: 0800fb54 .word 0x0800fb54 800621c: 00f42400 .word 0x00f42400 08006220 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8006220: b480 push {r7} 8006222: b083 sub sp, #12 8006224: af00 add r7, sp, #0 8006226: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8006228: 687b ldr r3, [r7, #4] 800622a: 6a9b ldr r3, [r3, #40] @ 0x28 800622c: f003 0308 and.w r3, r3, #8 8006230: 2b00 cmp r3, #0 8006232: d00a beq.n 800624a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8006234: 687b ldr r3, [r7, #4] 8006236: 681b ldr r3, [r3, #0] 8006238: 685b ldr r3, [r3, #4] 800623a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 800623e: 687b ldr r3, [r7, #4] 8006240: 6b9a ldr r2, [r3, #56] @ 0x38 8006242: 687b ldr r3, [r7, #4] 8006244: 681b ldr r3, [r3, #0] 8006246: 430a orrs r2, r1 8006248: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800624a: 687b ldr r3, [r7, #4] 800624c: 6a9b ldr r3, [r3, #40] @ 0x28 800624e: f003 0301 and.w r3, r3, #1 8006252: 2b00 cmp r3, #0 8006254: d00a beq.n 800626c { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8006256: 687b ldr r3, [r7, #4] 8006258: 681b ldr r3, [r3, #0] 800625a: 685b ldr r3, [r3, #4] 800625c: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8006260: 687b ldr r3, [r7, #4] 8006262: 6ada ldr r2, [r3, #44] @ 0x2c 8006264: 687b ldr r3, [r7, #4] 8006266: 681b ldr r3, [r3, #0] 8006268: 430a orrs r2, r1 800626a: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800626c: 687b ldr r3, [r7, #4] 800626e: 6a9b ldr r3, [r3, #40] @ 0x28 8006270: f003 0302 and.w r3, r3, #2 8006274: 2b00 cmp r3, #0 8006276: d00a beq.n 800628e { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8006278: 687b ldr r3, [r7, #4] 800627a: 681b ldr r3, [r3, #0] 800627c: 685b ldr r3, [r3, #4] 800627e: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8006282: 687b ldr r3, [r7, #4] 8006284: 6b1a ldr r2, [r3, #48] @ 0x30 8006286: 687b ldr r3, [r7, #4] 8006288: 681b ldr r3, [r3, #0] 800628a: 430a orrs r2, r1 800628c: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800628e: 687b ldr r3, [r7, #4] 8006290: 6a9b ldr r3, [r3, #40] @ 0x28 8006292: f003 0304 and.w r3, r3, #4 8006296: 2b00 cmp r3, #0 8006298: d00a beq.n 80062b0 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800629a: 687b ldr r3, [r7, #4] 800629c: 681b ldr r3, [r3, #0] 800629e: 685b ldr r3, [r3, #4] 80062a0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 80062a4: 687b ldr r3, [r7, #4] 80062a6: 6b5a ldr r2, [r3, #52] @ 0x34 80062a8: 687b ldr r3, [r7, #4] 80062aa: 681b ldr r3, [r3, #0] 80062ac: 430a orrs r2, r1 80062ae: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80062b0: 687b ldr r3, [r7, #4] 80062b2: 6a9b ldr r3, [r3, #40] @ 0x28 80062b4: f003 0310 and.w r3, r3, #16 80062b8: 2b00 cmp r3, #0 80062ba: d00a beq.n 80062d2 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 80062bc: 687b ldr r3, [r7, #4] 80062be: 681b ldr r3, [r3, #0] 80062c0: 689b ldr r3, [r3, #8] 80062c2: f423 5180 bic.w r1, r3, #4096 @ 0x1000 80062c6: 687b ldr r3, [r7, #4] 80062c8: 6bda ldr r2, [r3, #60] @ 0x3c 80062ca: 687b ldr r3, [r7, #4] 80062cc: 681b ldr r3, [r3, #0] 80062ce: 430a orrs r2, r1 80062d0: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 80062d2: 687b ldr r3, [r7, #4] 80062d4: 6a9b ldr r3, [r3, #40] @ 0x28 80062d6: f003 0320 and.w r3, r3, #32 80062da: 2b00 cmp r3, #0 80062dc: d00a beq.n 80062f4 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80062de: 687b ldr r3, [r7, #4] 80062e0: 681b ldr r3, [r3, #0] 80062e2: 689b ldr r3, [r3, #8] 80062e4: f423 5100 bic.w r1, r3, #8192 @ 0x2000 80062e8: 687b ldr r3, [r7, #4] 80062ea: 6c1a ldr r2, [r3, #64] @ 0x40 80062ec: 687b ldr r3, [r7, #4] 80062ee: 681b ldr r3, [r3, #0] 80062f0: 430a orrs r2, r1 80062f2: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 80062f4: 687b ldr r3, [r7, #4] 80062f6: 6a9b ldr r3, [r3, #40] @ 0x28 80062f8: f003 0340 and.w r3, r3, #64 @ 0x40 80062fc: 2b00 cmp r3, #0 80062fe: d01a beq.n 8006336 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8006300: 687b ldr r3, [r7, #4] 8006302: 681b ldr r3, [r3, #0] 8006304: 685b ldr r3, [r3, #4] 8006306: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 800630a: 687b ldr r3, [r7, #4] 800630c: 6c5a ldr r2, [r3, #68] @ 0x44 800630e: 687b ldr r3, [r7, #4] 8006310: 681b ldr r3, [r3, #0] 8006312: 430a orrs r2, r1 8006314: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8006316: 687b ldr r3, [r7, #4] 8006318: 6c5b ldr r3, [r3, #68] @ 0x44 800631a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800631e: d10a bne.n 8006336 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8006320: 687b ldr r3, [r7, #4] 8006322: 681b ldr r3, [r3, #0] 8006324: 685b ldr r3, [r3, #4] 8006326: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 800632a: 687b ldr r3, [r7, #4] 800632c: 6c9a ldr r2, [r3, #72] @ 0x48 800632e: 687b ldr r3, [r7, #4] 8006330: 681b ldr r3, [r3, #0] 8006332: 430a orrs r2, r1 8006334: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8006336: 687b ldr r3, [r7, #4] 8006338: 6a9b ldr r3, [r3, #40] @ 0x28 800633a: f003 0380 and.w r3, r3, #128 @ 0x80 800633e: 2b00 cmp r3, #0 8006340: d00a beq.n 8006358 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8006342: 687b ldr r3, [r7, #4] 8006344: 681b ldr r3, [r3, #0] 8006346: 685b ldr r3, [r3, #4] 8006348: f423 2100 bic.w r1, r3, #524288 @ 0x80000 800634c: 687b ldr r3, [r7, #4] 800634e: 6cda ldr r2, [r3, #76] @ 0x4c 8006350: 687b ldr r3, [r7, #4] 8006352: 681b ldr r3, [r3, #0] 8006354: 430a orrs r2, r1 8006356: 605a str r2, [r3, #4] } } 8006358: bf00 nop 800635a: 370c adds r7, #12 800635c: 46bd mov sp, r7 800635e: bc80 pop {r7} 8006360: 4770 bx lr 08006362 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8006362: b580 push {r7, lr} 8006364: b098 sub sp, #96 @ 0x60 8006366: af02 add r7, sp, #8 8006368: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800636a: 687b ldr r3, [r7, #4] 800636c: 2200 movs r2, #0 800636e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8006372: f7fa fc69 bl 8000c48 8006376: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8006378: 687b ldr r3, [r7, #4] 800637a: 681b ldr r3, [r3, #0] 800637c: 681b ldr r3, [r3, #0] 800637e: f003 0308 and.w r3, r3, #8 8006382: 2b08 cmp r3, #8 8006384: d12f bne.n 80063e6 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8006386: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 800638a: 9300 str r3, [sp, #0] 800638c: 6d7b ldr r3, [r7, #84] @ 0x54 800638e: 2200 movs r2, #0 8006390: f44f 1100 mov.w r1, #2097152 @ 0x200000 8006394: 6878 ldr r0, [r7, #4] 8006396: f000 f88e bl 80064b6 800639a: 4603 mov r3, r0 800639c: 2b00 cmp r3, #0 800639e: d022 beq.n 80063e6 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063a6: 6bbb ldr r3, [r7, #56] @ 0x38 80063a8: e853 3f00 ldrex r3, [r3] 80063ac: 637b str r3, [r7, #52] @ 0x34 return(result); 80063ae: 6b7b ldr r3, [r7, #52] @ 0x34 80063b0: f023 0380 bic.w r3, r3, #128 @ 0x80 80063b4: 653b str r3, [r7, #80] @ 0x50 80063b6: 687b ldr r3, [r7, #4] 80063b8: 681b ldr r3, [r3, #0] 80063ba: 461a mov r2, r3 80063bc: 6d3b ldr r3, [r7, #80] @ 0x50 80063be: 647b str r3, [r7, #68] @ 0x44 80063c0: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063c2: 6c39 ldr r1, [r7, #64] @ 0x40 80063c4: 6c7a ldr r2, [r7, #68] @ 0x44 80063c6: e841 2300 strex r3, r2, [r1] 80063ca: 63fb str r3, [r7, #60] @ 0x3c return(result); 80063cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80063ce: 2b00 cmp r3, #0 80063d0: d1e6 bne.n 80063a0 huart->gState = HAL_UART_STATE_READY; 80063d2: 687b ldr r3, [r7, #4] 80063d4: 2220 movs r2, #32 80063d6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 80063da: 687b ldr r3, [r7, #4] 80063dc: 2200 movs r2, #0 80063de: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 80063e2: 2303 movs r3, #3 80063e4: e063 b.n 80064ae } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 80063e6: 687b ldr r3, [r7, #4] 80063e8: 681b ldr r3, [r3, #0] 80063ea: 681b ldr r3, [r3, #0] 80063ec: f003 0304 and.w r3, r3, #4 80063f0: 2b04 cmp r3, #4 80063f2: d149 bne.n 8006488 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80063f4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80063f8: 9300 str r3, [sp, #0] 80063fa: 6d7b ldr r3, [r7, #84] @ 0x54 80063fc: 2200 movs r2, #0 80063fe: f44f 0180 mov.w r1, #4194304 @ 0x400000 8006402: 6878 ldr r0, [r7, #4] 8006404: f000 f857 bl 80064b6 8006408: 4603 mov r3, r0 800640a: 2b00 cmp r3, #0 800640c: d03c beq.n 8006488 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800640e: 687b ldr r3, [r7, #4] 8006410: 681b ldr r3, [r3, #0] 8006412: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006414: 6a7b ldr r3, [r7, #36] @ 0x24 8006416: e853 3f00 ldrex r3, [r3] 800641a: 623b str r3, [r7, #32] return(result); 800641c: 6a3b ldr r3, [r7, #32] 800641e: f423 7390 bic.w r3, r3, #288 @ 0x120 8006422: 64fb str r3, [r7, #76] @ 0x4c 8006424: 687b ldr r3, [r7, #4] 8006426: 681b ldr r3, [r3, #0] 8006428: 461a mov r2, r3 800642a: 6cfb ldr r3, [r7, #76] @ 0x4c 800642c: 633b str r3, [r7, #48] @ 0x30 800642e: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006430: 6af9 ldr r1, [r7, #44] @ 0x2c 8006432: 6b3a ldr r2, [r7, #48] @ 0x30 8006434: e841 2300 strex r3, r2, [r1] 8006438: 62bb str r3, [r7, #40] @ 0x28 return(result); 800643a: 6abb ldr r3, [r7, #40] @ 0x28 800643c: 2b00 cmp r3, #0 800643e: d1e6 bne.n 800640e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006440: 687b ldr r3, [r7, #4] 8006442: 681b ldr r3, [r3, #0] 8006444: 3308 adds r3, #8 8006446: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006448: 693b ldr r3, [r7, #16] 800644a: e853 3f00 ldrex r3, [r3] 800644e: 60fb str r3, [r7, #12] return(result); 8006450: 68fb ldr r3, [r7, #12] 8006452: f023 0301 bic.w r3, r3, #1 8006456: 64bb str r3, [r7, #72] @ 0x48 8006458: 687b ldr r3, [r7, #4] 800645a: 681b ldr r3, [r3, #0] 800645c: 3308 adds r3, #8 800645e: 6cba ldr r2, [r7, #72] @ 0x48 8006460: 61fa str r2, [r7, #28] 8006462: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006464: 69b9 ldr r1, [r7, #24] 8006466: 69fa ldr r2, [r7, #28] 8006468: e841 2300 strex r3, r2, [r1] 800646c: 617b str r3, [r7, #20] return(result); 800646e: 697b ldr r3, [r7, #20] 8006470: 2b00 cmp r3, #0 8006472: d1e5 bne.n 8006440 huart->RxState = HAL_UART_STATE_READY; 8006474: 687b ldr r3, [r7, #4] 8006476: 2220 movs r2, #32 8006478: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 800647c: 687b ldr r3, [r7, #4] 800647e: 2200 movs r2, #0 8006480: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8006484: 2303 movs r3, #3 8006486: e012 b.n 80064ae } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8006488: 687b ldr r3, [r7, #4] 800648a: 2220 movs r2, #32 800648c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8006490: 687b ldr r3, [r7, #4] 8006492: 2220 movs r2, #32 8006494: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006498: 687b ldr r3, [r7, #4] 800649a: 2200 movs r2, #0 800649c: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800649e: 687b ldr r3, [r7, #4] 80064a0: 2200 movs r2, #0 80064a2: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 80064a4: 687b ldr r3, [r7, #4] 80064a6: 2200 movs r2, #0 80064a8: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80064ac: 2300 movs r3, #0 } 80064ae: 4618 mov r0, r3 80064b0: 3758 adds r7, #88 @ 0x58 80064b2: 46bd mov sp, r7 80064b4: bd80 pop {r7, pc} 080064b6 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80064b6: b580 push {r7, lr} 80064b8: b084 sub sp, #16 80064ba: af00 add r7, sp, #0 80064bc: 60f8 str r0, [r7, #12] 80064be: 60b9 str r1, [r7, #8] 80064c0: 603b str r3, [r7, #0] 80064c2: 4613 mov r3, r2 80064c4: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80064c6: e04f b.n 8006568 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80064c8: 69bb ldr r3, [r7, #24] 80064ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80064ce: d04b beq.n 8006568 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80064d0: f7fa fbba bl 8000c48 80064d4: 4602 mov r2, r0 80064d6: 683b ldr r3, [r7, #0] 80064d8: 1ad3 subs r3, r2, r3 80064da: 69ba ldr r2, [r7, #24] 80064dc: 429a cmp r2, r3 80064de: d302 bcc.n 80064e6 80064e0: 69bb ldr r3, [r7, #24] 80064e2: 2b00 cmp r3, #0 80064e4: d101 bne.n 80064ea { return HAL_TIMEOUT; 80064e6: 2303 movs r3, #3 80064e8: e04e b.n 8006588 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 80064ea: 68fb ldr r3, [r7, #12] 80064ec: 681b ldr r3, [r3, #0] 80064ee: 681b ldr r3, [r3, #0] 80064f0: f003 0304 and.w r3, r3, #4 80064f4: 2b00 cmp r3, #0 80064f6: d037 beq.n 8006568 80064f8: 68bb ldr r3, [r7, #8] 80064fa: 2b80 cmp r3, #128 @ 0x80 80064fc: d034 beq.n 8006568 80064fe: 68bb ldr r3, [r7, #8] 8006500: 2b40 cmp r3, #64 @ 0x40 8006502: d031 beq.n 8006568 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8006504: 68fb ldr r3, [r7, #12] 8006506: 681b ldr r3, [r3, #0] 8006508: 69db ldr r3, [r3, #28] 800650a: f003 0308 and.w r3, r3, #8 800650e: 2b08 cmp r3, #8 8006510: d110 bne.n 8006534 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8006512: 68fb ldr r3, [r7, #12] 8006514: 681b ldr r3, [r3, #0] 8006516: 2208 movs r2, #8 8006518: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800651a: 68f8 ldr r0, [r7, #12] 800651c: f000 f998 bl 8006850 huart->ErrorCode = HAL_UART_ERROR_ORE; 8006520: 68fb ldr r3, [r7, #12] 8006522: 2208 movs r2, #8 8006524: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8006528: 68fb ldr r3, [r7, #12] 800652a: 2200 movs r2, #0 800652c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8006530: 2301 movs r3, #1 8006532: e029 b.n 8006588 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8006534: 68fb ldr r3, [r7, #12] 8006536: 681b ldr r3, [r3, #0] 8006538: 69db ldr r3, [r3, #28] 800653a: f403 6300 and.w r3, r3, #2048 @ 0x800 800653e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8006542: d111 bne.n 8006568 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8006544: 68fb ldr r3, [r7, #12] 8006546: 681b ldr r3, [r3, #0] 8006548: f44f 6200 mov.w r2, #2048 @ 0x800 800654c: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800654e: 68f8 ldr r0, [r7, #12] 8006550: f000 f97e bl 8006850 huart->ErrorCode = HAL_UART_ERROR_RTO; 8006554: 68fb ldr r3, [r7, #12] 8006556: 2220 movs r2, #32 8006558: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 800655c: 68fb ldr r3, [r7, #12] 800655e: 2200 movs r2, #0 8006560: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8006564: 2303 movs r3, #3 8006566: e00f b.n 8006588 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8006568: 68fb ldr r3, [r7, #12] 800656a: 681b ldr r3, [r3, #0] 800656c: 69da ldr r2, [r3, #28] 800656e: 68bb ldr r3, [r7, #8] 8006570: 4013 ands r3, r2 8006572: 68ba ldr r2, [r7, #8] 8006574: 429a cmp r2, r3 8006576: bf0c ite eq 8006578: 2301 moveq r3, #1 800657a: 2300 movne r3, #0 800657c: b2db uxtb r3, r3 800657e: 461a mov r2, r3 8006580: 79fb ldrb r3, [r7, #7] 8006582: 429a cmp r2, r3 8006584: d0a0 beq.n 80064c8 } } } } return HAL_OK; 8006586: 2300 movs r3, #0 } 8006588: 4618 mov r0, r3 800658a: 3710 adds r7, #16 800658c: 46bd mov sp, r7 800658e: bd80 pop {r7, pc} 08006590 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006590: b480 push {r7} 8006592: b0a3 sub sp, #140 @ 0x8c 8006594: af00 add r7, sp, #0 8006596: 60f8 str r0, [r7, #12] 8006598: 60b9 str r1, [r7, #8] 800659a: 4613 mov r3, r2 800659c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 800659e: 68fb ldr r3, [r7, #12] 80065a0: 68ba ldr r2, [r7, #8] 80065a2: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 80065a4: 68fb ldr r3, [r7, #12] 80065a6: 88fa ldrh r2, [r7, #6] 80065a8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 80065ac: 68fb ldr r3, [r7, #12] 80065ae: 88fa ldrh r2, [r7, #6] 80065b0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 80065b4: 68fb ldr r3, [r7, #12] 80065b6: 2200 movs r2, #0 80065b8: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 80065ba: 68fb ldr r3, [r7, #12] 80065bc: 689b ldr r3, [r3, #8] 80065be: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80065c2: d10e bne.n 80065e2 80065c4: 68fb ldr r3, [r7, #12] 80065c6: 691b ldr r3, [r3, #16] 80065c8: 2b00 cmp r3, #0 80065ca: d105 bne.n 80065d8 80065cc: 68fb ldr r3, [r7, #12] 80065ce: f240 12ff movw r2, #511 @ 0x1ff 80065d2: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80065d6: e02d b.n 8006634 80065d8: 68fb ldr r3, [r7, #12] 80065da: 22ff movs r2, #255 @ 0xff 80065dc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80065e0: e028 b.n 8006634 80065e2: 68fb ldr r3, [r7, #12] 80065e4: 689b ldr r3, [r3, #8] 80065e6: 2b00 cmp r3, #0 80065e8: d10d bne.n 8006606 80065ea: 68fb ldr r3, [r7, #12] 80065ec: 691b ldr r3, [r3, #16] 80065ee: 2b00 cmp r3, #0 80065f0: d104 bne.n 80065fc 80065f2: 68fb ldr r3, [r7, #12] 80065f4: 22ff movs r2, #255 @ 0xff 80065f6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80065fa: e01b b.n 8006634 80065fc: 68fb ldr r3, [r7, #12] 80065fe: 227f movs r2, #127 @ 0x7f 8006600: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8006604: e016 b.n 8006634 8006606: 68fb ldr r3, [r7, #12] 8006608: 689b ldr r3, [r3, #8] 800660a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800660e: d10d bne.n 800662c 8006610: 68fb ldr r3, [r7, #12] 8006612: 691b ldr r3, [r3, #16] 8006614: 2b00 cmp r3, #0 8006616: d104 bne.n 8006622 8006618: 68fb ldr r3, [r7, #12] 800661a: 227f movs r2, #127 @ 0x7f 800661c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8006620: e008 b.n 8006634 8006622: 68fb ldr r3, [r7, #12] 8006624: 223f movs r2, #63 @ 0x3f 8006626: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800662a: e003 b.n 8006634 800662c: 68fb ldr r3, [r7, #12] 800662e: 2200 movs r2, #0 8006630: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8006634: 68fb ldr r3, [r7, #12] 8006636: 2200 movs r2, #0 8006638: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 800663c: 68fb ldr r3, [r7, #12] 800663e: 2222 movs r2, #34 @ 0x22 8006640: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006644: 68fb ldr r3, [r7, #12] 8006646: 681b ldr r3, [r3, #0] 8006648: 3308 adds r3, #8 800664a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800664c: 6e7b ldr r3, [r7, #100] @ 0x64 800664e: e853 3f00 ldrex r3, [r3] 8006652: 663b str r3, [r7, #96] @ 0x60 return(result); 8006654: 6e3b ldr r3, [r7, #96] @ 0x60 8006656: f043 0301 orr.w r3, r3, #1 800665a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800665e: 68fb ldr r3, [r7, #12] 8006660: 681b ldr r3, [r3, #0] 8006662: 3308 adds r3, #8 8006664: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8006668: 673a str r2, [r7, #112] @ 0x70 800666a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800666c: 6ef9 ldr r1, [r7, #108] @ 0x6c 800666e: 6f3a ldr r2, [r7, #112] @ 0x70 8006670: e841 2300 strex r3, r2, [r1] 8006674: 66bb str r3, [r7, #104] @ 0x68 return(result); 8006676: 6ebb ldr r3, [r7, #104] @ 0x68 8006678: 2b00 cmp r3, #0 800667a: d1e3 bne.n 8006644 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800667c: 68fb ldr r3, [r7, #12] 800667e: 6e5b ldr r3, [r3, #100] @ 0x64 8006680: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006684: d14f bne.n 8006726 8006686: 68fb ldr r3, [r7, #12] 8006688: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800668c: 88fa ldrh r2, [r7, #6] 800668e: 429a cmp r2, r3 8006690: d349 bcc.n 8006726 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006692: 68fb ldr r3, [r7, #12] 8006694: 689b ldr r3, [r3, #8] 8006696: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800669a: d107 bne.n 80066ac 800669c: 68fb ldr r3, [r7, #12] 800669e: 691b ldr r3, [r3, #16] 80066a0: 2b00 cmp r3, #0 80066a2: d103 bne.n 80066ac { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 80066a4: 68fb ldr r3, [r7, #12] 80066a6: 4a46 ldr r2, [pc, #280] @ (80067c0 ) 80066a8: 675a str r2, [r3, #116] @ 0x74 80066aa: e002 b.n 80066b2 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 80066ac: 68fb ldr r3, [r7, #12] 80066ae: 4a45 ldr r2, [pc, #276] @ (80067c4 ) 80066b0: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 80066b2: 68fb ldr r3, [r7, #12] 80066b4: 691b ldr r3, [r3, #16] 80066b6: 2b00 cmp r3, #0 80066b8: d01a beq.n 80066f0 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80066ba: 68fb ldr r3, [r7, #12] 80066bc: 681b ldr r3, [r3, #0] 80066be: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066c0: 6d3b ldr r3, [r7, #80] @ 0x50 80066c2: e853 3f00 ldrex r3, [r3] 80066c6: 64fb str r3, [r7, #76] @ 0x4c return(result); 80066c8: 6cfb ldr r3, [r7, #76] @ 0x4c 80066ca: f443 7380 orr.w r3, r3, #256 @ 0x100 80066ce: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80066d2: 68fb ldr r3, [r7, #12] 80066d4: 681b ldr r3, [r3, #0] 80066d6: 461a mov r2, r3 80066d8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80066dc: 65fb str r3, [r7, #92] @ 0x5c 80066de: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066e0: 6db9 ldr r1, [r7, #88] @ 0x58 80066e2: 6dfa ldr r2, [r7, #92] @ 0x5c 80066e4: e841 2300 strex r3, r2, [r1] 80066e8: 657b str r3, [r7, #84] @ 0x54 return(result); 80066ea: 6d7b ldr r3, [r7, #84] @ 0x54 80066ec: 2b00 cmp r3, #0 80066ee: d1e4 bne.n 80066ba } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80066f0: 68fb ldr r3, [r7, #12] 80066f2: 681b ldr r3, [r3, #0] 80066f4: 3308 adds r3, #8 80066f6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80066fa: e853 3f00 ldrex r3, [r3] 80066fe: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006700: 6bbb ldr r3, [r7, #56] @ 0x38 8006702: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8006706: 67fb str r3, [r7, #124] @ 0x7c 8006708: 68fb ldr r3, [r7, #12] 800670a: 681b ldr r3, [r3, #0] 800670c: 3308 adds r3, #8 800670e: 6ffa ldr r2, [r7, #124] @ 0x7c 8006710: 64ba str r2, [r7, #72] @ 0x48 8006712: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006714: 6c79 ldr r1, [r7, #68] @ 0x44 8006716: 6cba ldr r2, [r7, #72] @ 0x48 8006718: e841 2300 strex r3, r2, [r1] 800671c: 643b str r3, [r7, #64] @ 0x40 return(result); 800671e: 6c3b ldr r3, [r7, #64] @ 0x40 8006720: 2b00 cmp r3, #0 8006722: d1e5 bne.n 80066f0 8006724: e046 b.n 80067b4 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006726: 68fb ldr r3, [r7, #12] 8006728: 689b ldr r3, [r3, #8] 800672a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800672e: d107 bne.n 8006740 8006730: 68fb ldr r3, [r7, #12] 8006732: 691b ldr r3, [r3, #16] 8006734: 2b00 cmp r3, #0 8006736: d103 bne.n 8006740 { huart->RxISR = UART_RxISR_16BIT; 8006738: 68fb ldr r3, [r7, #12] 800673a: 4a23 ldr r2, [pc, #140] @ (80067c8 ) 800673c: 675a str r2, [r3, #116] @ 0x74 800673e: e002 b.n 8006746 } else { huart->RxISR = UART_RxISR_8BIT; 8006740: 68fb ldr r3, [r7, #12] 8006742: 4a22 ldr r2, [pc, #136] @ (80067cc ) 8006744: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8006746: 68fb ldr r3, [r7, #12] 8006748: 691b ldr r3, [r3, #16] 800674a: 2b00 cmp r3, #0 800674c: d019 beq.n 8006782 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 800674e: 68fb ldr r3, [r7, #12] 8006750: 681b ldr r3, [r3, #0] 8006752: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006754: 6abb ldr r3, [r7, #40] @ 0x28 8006756: e853 3f00 ldrex r3, [r3] 800675a: 627b str r3, [r7, #36] @ 0x24 return(result); 800675c: 6a7b ldr r3, [r7, #36] @ 0x24 800675e: f443 7390 orr.w r3, r3, #288 @ 0x120 8006762: 677b str r3, [r7, #116] @ 0x74 8006764: 68fb ldr r3, [r7, #12] 8006766: 681b ldr r3, [r3, #0] 8006768: 461a mov r2, r3 800676a: 6f7b ldr r3, [r7, #116] @ 0x74 800676c: 637b str r3, [r7, #52] @ 0x34 800676e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006770: 6b39 ldr r1, [r7, #48] @ 0x30 8006772: 6b7a ldr r2, [r7, #52] @ 0x34 8006774: e841 2300 strex r3, r2, [r1] 8006778: 62fb str r3, [r7, #44] @ 0x2c return(result); 800677a: 6afb ldr r3, [r7, #44] @ 0x2c 800677c: 2b00 cmp r3, #0 800677e: d1e6 bne.n 800674e 8006780: e018 b.n 80067b4 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8006782: 68fb ldr r3, [r7, #12] 8006784: 681b ldr r3, [r3, #0] 8006786: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006788: 697b ldr r3, [r7, #20] 800678a: e853 3f00 ldrex r3, [r3] 800678e: 613b str r3, [r7, #16] return(result); 8006790: 693b ldr r3, [r7, #16] 8006792: f043 0320 orr.w r3, r3, #32 8006796: 67bb str r3, [r7, #120] @ 0x78 8006798: 68fb ldr r3, [r7, #12] 800679a: 681b ldr r3, [r3, #0] 800679c: 461a mov r2, r3 800679e: 6fbb ldr r3, [r7, #120] @ 0x78 80067a0: 623b str r3, [r7, #32] 80067a2: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067a4: 69f9 ldr r1, [r7, #28] 80067a6: 6a3a ldr r2, [r7, #32] 80067a8: e841 2300 strex r3, r2, [r1] 80067ac: 61bb str r3, [r7, #24] return(result); 80067ae: 69bb ldr r3, [r7, #24] 80067b0: 2b00 cmp r3, #0 80067b2: d1e6 bne.n 8006782 } } return HAL_OK; 80067b4: 2300 movs r3, #0 } 80067b6: 4618 mov r0, r3 80067b8: 378c adds r7, #140 @ 0x8c 80067ba: 46bd mov sp, r7 80067bc: bc80 pop {r7} 80067be: 4770 bx lr 80067c0: 08007181 .word 0x08007181 80067c4: 08006e1d .word 0x08006e1d 80067c8: 08006c65 .word 0x08006c65 80067cc: 08006aad .word 0x08006aad 080067d0 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80067d0: b480 push {r7} 80067d2: b08f sub sp, #60 @ 0x3c 80067d4: af00 add r7, sp, #0 80067d6: 6078 str r0, [r7, #4] /* Disable TXEIE, TCIE, TXFT interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); 80067d8: 687b ldr r3, [r7, #4] 80067da: 681b ldr r3, [r3, #0] 80067dc: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067de: 6a3b ldr r3, [r7, #32] 80067e0: e853 3f00 ldrex r3, [r3] 80067e4: 61fb str r3, [r7, #28] return(result); 80067e6: 69fb ldr r3, [r7, #28] 80067e8: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80067ec: 637b str r3, [r7, #52] @ 0x34 80067ee: 687b ldr r3, [r7, #4] 80067f0: 681b ldr r3, [r3, #0] 80067f2: 461a mov r2, r3 80067f4: 6b7b ldr r3, [r7, #52] @ 0x34 80067f6: 62fb str r3, [r7, #44] @ 0x2c 80067f8: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067fa: 6ab9 ldr r1, [r7, #40] @ 0x28 80067fc: 6afa ldr r2, [r7, #44] @ 0x2c 80067fe: e841 2300 strex r3, r2, [r1] 8006802: 627b str r3, [r7, #36] @ 0x24 return(result); 8006804: 6a7b ldr r3, [r7, #36] @ 0x24 8006806: 2b00 cmp r3, #0 8006808: d1e6 bne.n 80067d8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); 800680a: 687b ldr r3, [r7, #4] 800680c: 681b ldr r3, [r3, #0] 800680e: 3308 adds r3, #8 8006810: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006812: 68fb ldr r3, [r7, #12] 8006814: e853 3f00 ldrex r3, [r3] 8006818: 60bb str r3, [r7, #8] return(result); 800681a: 68bb ldr r3, [r7, #8] 800681c: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8006820: 633b str r3, [r7, #48] @ 0x30 8006822: 687b ldr r3, [r7, #4] 8006824: 681b ldr r3, [r3, #0] 8006826: 3308 adds r3, #8 8006828: 6b3a ldr r2, [r7, #48] @ 0x30 800682a: 61ba str r2, [r7, #24] 800682c: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800682e: 6979 ldr r1, [r7, #20] 8006830: 69ba ldr r2, [r7, #24] 8006832: e841 2300 strex r3, r2, [r1] 8006836: 613b str r3, [r7, #16] return(result); 8006838: 693b ldr r3, [r7, #16] 800683a: 2b00 cmp r3, #0 800683c: d1e5 bne.n 800680a /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800683e: 687b ldr r3, [r7, #4] 8006840: 2220 movs r2, #32 8006842: f8c3 2088 str.w r2, [r3, #136] @ 0x88 } 8006846: bf00 nop 8006848: 373c adds r7, #60 @ 0x3c 800684a: 46bd mov sp, r7 800684c: bc80 pop {r7} 800684e: 4770 bx lr 08006850 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006850: b480 push {r7} 8006852: b095 sub sp, #84 @ 0x54 8006854: af00 add r7, sp, #0 8006856: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8006858: 687b ldr r3, [r7, #4] 800685a: 681b ldr r3, [r3, #0] 800685c: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800685e: 6b7b ldr r3, [r7, #52] @ 0x34 8006860: e853 3f00 ldrex r3, [r3] 8006864: 633b str r3, [r7, #48] @ 0x30 return(result); 8006866: 6b3b ldr r3, [r7, #48] @ 0x30 8006868: f423 7390 bic.w r3, r3, #288 @ 0x120 800686c: 64fb str r3, [r7, #76] @ 0x4c 800686e: 687b ldr r3, [r7, #4] 8006870: 681b ldr r3, [r3, #0] 8006872: 461a mov r2, r3 8006874: 6cfb ldr r3, [r7, #76] @ 0x4c 8006876: 643b str r3, [r7, #64] @ 0x40 8006878: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800687a: 6bf9 ldr r1, [r7, #60] @ 0x3c 800687c: 6c3a ldr r2, [r7, #64] @ 0x40 800687e: e841 2300 strex r3, r2, [r1] 8006882: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006884: 6bbb ldr r3, [r7, #56] @ 0x38 8006886: 2b00 cmp r3, #0 8006888: d1e6 bne.n 8006858 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800688a: 687b ldr r3, [r7, #4] 800688c: 681b ldr r3, [r3, #0] 800688e: 3308 adds r3, #8 8006890: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006892: 6a3b ldr r3, [r7, #32] 8006894: e853 3f00 ldrex r3, [r3] 8006898: 61fb str r3, [r7, #28] return(result); 800689a: 69fb ldr r3, [r7, #28] 800689c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80068a0: f023 0301 bic.w r3, r3, #1 80068a4: 64bb str r3, [r7, #72] @ 0x48 80068a6: 687b ldr r3, [r7, #4] 80068a8: 681b ldr r3, [r3, #0] 80068aa: 3308 adds r3, #8 80068ac: 6cba ldr r2, [r7, #72] @ 0x48 80068ae: 62fa str r2, [r7, #44] @ 0x2c 80068b0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068b2: 6ab9 ldr r1, [r7, #40] @ 0x28 80068b4: 6afa ldr r2, [r7, #44] @ 0x2c 80068b6: e841 2300 strex r3, r2, [r1] 80068ba: 627b str r3, [r7, #36] @ 0x24 return(result); 80068bc: 6a7b ldr r3, [r7, #36] @ 0x24 80068be: 2b00 cmp r3, #0 80068c0: d1e3 bne.n 800688a /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80068c2: 687b ldr r3, [r7, #4] 80068c4: 6edb ldr r3, [r3, #108] @ 0x6c 80068c6: 2b01 cmp r3, #1 80068c8: d118 bne.n 80068fc { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80068ca: 687b ldr r3, [r7, #4] 80068cc: 681b ldr r3, [r3, #0] 80068ce: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80068d0: 68fb ldr r3, [r7, #12] 80068d2: e853 3f00 ldrex r3, [r3] 80068d6: 60bb str r3, [r7, #8] return(result); 80068d8: 68bb ldr r3, [r7, #8] 80068da: f023 0310 bic.w r3, r3, #16 80068de: 647b str r3, [r7, #68] @ 0x44 80068e0: 687b ldr r3, [r7, #4] 80068e2: 681b ldr r3, [r3, #0] 80068e4: 461a mov r2, r3 80068e6: 6c7b ldr r3, [r7, #68] @ 0x44 80068e8: 61bb str r3, [r7, #24] 80068ea: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068ec: 6979 ldr r1, [r7, #20] 80068ee: 69ba ldr r2, [r7, #24] 80068f0: e841 2300 strex r3, r2, [r1] 80068f4: 613b str r3, [r7, #16] return(result); 80068f6: 693b ldr r3, [r7, #16] 80068f8: 2b00 cmp r3, #0 80068fa: d1e6 bne.n 80068ca } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80068fc: 687b ldr r3, [r7, #4] 80068fe: 2220 movs r2, #32 8006900: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006904: 687b ldr r3, [r7, #4] 8006906: 2200 movs r2, #0 8006908: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800690a: 687b ldr r3, [r7, #4] 800690c: 2200 movs r2, #0 800690e: 675a str r2, [r3, #116] @ 0x74 } 8006910: bf00 nop 8006912: 3754 adds r7, #84 @ 0x54 8006914: 46bd mov sp, r7 8006916: bc80 pop {r7} 8006918: 4770 bx lr 0800691a : * @brief DMA UART transmit process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 800691a: b580 push {r7, lr} 800691c: b090 sub sp, #64 @ 0x40 800691e: af00 add r7, sp, #0 8006920: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8006922: 687b ldr r3, [r7, #4] 8006924: 6a9b ldr r3, [r3, #40] @ 0x28 8006926: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) 8006928: 687b ldr r3, [r7, #4] 800692a: 681b ldr r3, [r3, #0] 800692c: 681b ldr r3, [r3, #0] 800692e: f003 0320 and.w r3, r3, #32 8006932: 2b00 cmp r3, #0 8006934: d133 bne.n 800699e { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8006936: 6bfb ldr r3, [r7, #60] @ 0x3c 8006938: 681b ldr r3, [r3, #0] 800693a: 3308 adds r3, #8 800693c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800693e: 6a7b ldr r3, [r7, #36] @ 0x24 8006940: e853 3f00 ldrex r3, [r3] 8006944: 623b str r3, [r7, #32] return(result); 8006946: 6a3b ldr r3, [r7, #32] 8006948: f023 0380 bic.w r3, r3, #128 @ 0x80 800694c: 63bb str r3, [r7, #56] @ 0x38 800694e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006950: 681b ldr r3, [r3, #0] 8006952: 3308 adds r3, #8 8006954: 6bba ldr r2, [r7, #56] @ 0x38 8006956: 633a str r2, [r7, #48] @ 0x30 8006958: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800695a: 6af9 ldr r1, [r7, #44] @ 0x2c 800695c: 6b3a ldr r2, [r7, #48] @ 0x30 800695e: e841 2300 strex r3, r2, [r1] 8006962: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006964: 6abb ldr r3, [r7, #40] @ 0x28 8006966: 2b00 cmp r3, #0 8006968: d1e5 bne.n 8006936 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800696a: 6bfb ldr r3, [r7, #60] @ 0x3c 800696c: 681b ldr r3, [r3, #0] 800696e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006970: 693b ldr r3, [r7, #16] 8006972: e853 3f00 ldrex r3, [r3] 8006976: 60fb str r3, [r7, #12] return(result); 8006978: 68fb ldr r3, [r7, #12] 800697a: f043 0340 orr.w r3, r3, #64 @ 0x40 800697e: 637b str r3, [r7, #52] @ 0x34 8006980: 6bfb ldr r3, [r7, #60] @ 0x3c 8006982: 681b ldr r3, [r3, #0] 8006984: 461a mov r2, r3 8006986: 6b7b ldr r3, [r7, #52] @ 0x34 8006988: 61fb str r3, [r7, #28] 800698a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800698c: 69b9 ldr r1, [r7, #24] 800698e: 69fa ldr r2, [r7, #28] 8006990: e841 2300 strex r3, r2, [r1] 8006994: 617b str r3, [r7, #20] return(result); 8006996: 697b ldr r3, [r7, #20] 8006998: 2b00 cmp r3, #0 800699a: d1e6 bne.n 800696a #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 800699c: e002 b.n 80069a4 HAL_UART_TxCpltCallback(huart); 800699e: 6bf8 ldr r0, [r7, #60] @ 0x3c 80069a0: f7fa fe5a bl 8001658 } 80069a4: bf00 nop 80069a6: 3740 adds r7, #64 @ 0x40 80069a8: 46bd mov sp, r7 80069aa: bd80 pop {r7, pc} 080069ac : * @brief DMA UART transmit process half complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80069ac: b580 push {r7, lr} 80069ae: b084 sub sp, #16 80069b0: af00 add r7, sp, #0 80069b2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 80069b4: 687b ldr r3, [r7, #4] 80069b6: 6a9b ldr r3, [r3, #40] @ 0x28 80069b8: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx Half complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx Half complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 80069ba: 68f8 ldr r0, [r7, #12] 80069bc: f7ff f99e bl 8005cfc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80069c0: bf00 nop 80069c2: 3710 adds r7, #16 80069c4: 46bd mov sp, r7 80069c6: bd80 pop {r7, pc} 080069c8 : * @brief DMA UART communication error callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 80069c8: b580 push {r7, lr} 80069ca: b086 sub sp, #24 80069cc: af00 add r7, sp, #0 80069ce: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 80069d0: 687b ldr r3, [r7, #4] 80069d2: 6a9b ldr r3, [r3, #40] @ 0x28 80069d4: 617b str r3, [r7, #20] const HAL_UART_StateTypeDef gstate = huart->gState; 80069d6: 697b ldr r3, [r7, #20] 80069d8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80069dc: 613b str r3, [r7, #16] const HAL_UART_StateTypeDef rxstate = huart->RxState; 80069de: 697b ldr r3, [r7, #20] 80069e0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80069e4: 60fb str r3, [r7, #12] /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && 80069e6: 697b ldr r3, [r7, #20] 80069e8: 681b ldr r3, [r3, #0] 80069ea: 689b ldr r3, [r3, #8] 80069ec: f003 0380 and.w r3, r3, #128 @ 0x80 80069f0: 2b80 cmp r3, #128 @ 0x80 80069f2: d105 bne.n 8006a00 80069f4: 693b ldr r3, [r7, #16] 80069f6: 2b21 cmp r3, #33 @ 0x21 80069f8: d102 bne.n 8006a00 (gstate == HAL_UART_STATE_BUSY_TX)) { UART_EndTxTransfer(huart); 80069fa: 6978 ldr r0, [r7, #20] 80069fc: f7ff fee8 bl 80067d0 } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && 8006a00: 697b ldr r3, [r7, #20] 8006a02: 681b ldr r3, [r3, #0] 8006a04: 689b ldr r3, [r3, #8] 8006a06: f003 0340 and.w r3, r3, #64 @ 0x40 8006a0a: 2b40 cmp r3, #64 @ 0x40 8006a0c: d105 bne.n 8006a1a 8006a0e: 68fb ldr r3, [r7, #12] 8006a10: 2b22 cmp r3, #34 @ 0x22 8006a12: d102 bne.n 8006a1a (rxstate == HAL_UART_STATE_BUSY_RX)) { UART_EndRxTransfer(huart); 8006a14: 6978 ldr r0, [r7, #20] 8006a16: f7ff ff1b bl 8006850 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8006a1a: 697b ldr r3, [r7, #20] 8006a1c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006a20: f043 0210 orr.w r2, r3, #16 8006a24: 697b ldr r3, [r7, #20] 8006a26: f8c3 2090 str.w r2, [r3, #144] @ 0x90 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006a2a: 6978 ldr r0, [r7, #20] 8006a2c: f7ff f96f bl 8005d0e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006a30: bf00 nop 8006a32: 3718 adds r7, #24 8006a34: 46bd mov sp, r7 8006a36: bd80 pop {r7, pc} 08006a38 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8006a38: b580 push {r7, lr} 8006a3a: b084 sub sp, #16 8006a3c: af00 add r7, sp, #0 8006a3e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8006a40: 687b ldr r3, [r7, #4] 8006a42: 6a9b ldr r3, [r3, #40] @ 0x28 8006a44: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006a46: 68f8 ldr r0, [r7, #12] 8006a48: f7ff f961 bl 8005d0e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006a4c: bf00 nop 8006a4e: 3710 adds r7, #16 8006a50: 46bd mov sp, r7 8006a52: bd80 pop {r7, pc} 08006a54 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8006a54: b580 push {r7, lr} 8006a56: b088 sub sp, #32 8006a58: af00 add r7, sp, #0 8006a5a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006a5c: 687b ldr r3, [r7, #4] 8006a5e: 681b ldr r3, [r3, #0] 8006a60: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006a62: 68fb ldr r3, [r7, #12] 8006a64: e853 3f00 ldrex r3, [r3] 8006a68: 60bb str r3, [r7, #8] return(result); 8006a6a: 68bb ldr r3, [r7, #8] 8006a6c: f023 0340 bic.w r3, r3, #64 @ 0x40 8006a70: 61fb str r3, [r7, #28] 8006a72: 687b ldr r3, [r7, #4] 8006a74: 681b ldr r3, [r3, #0] 8006a76: 461a mov r2, r3 8006a78: 69fb ldr r3, [r7, #28] 8006a7a: 61bb str r3, [r7, #24] 8006a7c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a7e: 6979 ldr r1, [r7, #20] 8006a80: 69ba ldr r2, [r7, #24] 8006a82: e841 2300 strex r3, r2, [r1] 8006a86: 613b str r3, [r7, #16] return(result); 8006a88: 693b ldr r3, [r7, #16] 8006a8a: 2b00 cmp r3, #0 8006a8c: d1e6 bne.n 8006a5c /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006a8e: 687b ldr r3, [r7, #4] 8006a90: 2220 movs r2, #32 8006a92: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8006a96: 687b ldr r3, [r7, #4] 8006a98: 2200 movs r2, #0 8006a9a: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8006a9c: 6878 ldr r0, [r7, #4] 8006a9e: f7fa fddb bl 8001658 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006aa2: bf00 nop 8006aa4: 3720 adds r7, #32 8006aa6: 46bd mov sp, r7 8006aa8: bd80 pop {r7, pc} ... 08006aac : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8006aac: b580 push {r7, lr} 8006aae: b09c sub sp, #112 @ 0x70 8006ab0: af00 add r7, sp, #0 8006ab2: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8006ab4: 687b ldr r3, [r7, #4] 8006ab6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8006aba: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006abe: 687b ldr r3, [r7, #4] 8006ac0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8006ac4: 2b22 cmp r3, #34 @ 0x22 8006ac6: f040 80be bne.w 8006c46 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006aca: 687b ldr r3, [r7, #4] 8006acc: 681b ldr r3, [r3, #0] 8006ace: 6a5b ldr r3, [r3, #36] @ 0x24 8006ad0: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8006ad4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8006ad8: b2d9 uxtb r1, r3 8006ada: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8006ade: b2da uxtb r2, r3 8006ae0: 687b ldr r3, [r7, #4] 8006ae2: 6d9b ldr r3, [r3, #88] @ 0x58 8006ae4: 400a ands r2, r1 8006ae6: b2d2 uxtb r2, r2 8006ae8: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8006aea: 687b ldr r3, [r7, #4] 8006aec: 6d9b ldr r3, [r3, #88] @ 0x58 8006aee: 1c5a adds r2, r3, #1 8006af0: 687b ldr r3, [r7, #4] 8006af2: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006af4: 687b ldr r3, [r7, #4] 8006af6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006afa: b29b uxth r3, r3 8006afc: 3b01 subs r3, #1 8006afe: b29a uxth r2, r3 8006b00: 687b ldr r3, [r7, #4] 8006b02: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8006b06: 687b ldr r3, [r7, #4] 8006b08: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006b0c: b29b uxth r3, r3 8006b0e: 2b00 cmp r3, #0 8006b10: f040 80a1 bne.w 8006c56 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8006b14: 687b ldr r3, [r7, #4] 8006b16: 681b ldr r3, [r3, #0] 8006b18: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b1a: 6cfb ldr r3, [r7, #76] @ 0x4c 8006b1c: e853 3f00 ldrex r3, [r3] 8006b20: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006b22: 6cbb ldr r3, [r7, #72] @ 0x48 8006b24: f423 7390 bic.w r3, r3, #288 @ 0x120 8006b28: 66bb str r3, [r7, #104] @ 0x68 8006b2a: 687b ldr r3, [r7, #4] 8006b2c: 681b ldr r3, [r3, #0] 8006b2e: 461a mov r2, r3 8006b30: 6ebb ldr r3, [r7, #104] @ 0x68 8006b32: 65bb str r3, [r7, #88] @ 0x58 8006b34: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b36: 6d79 ldr r1, [r7, #84] @ 0x54 8006b38: 6dba ldr r2, [r7, #88] @ 0x58 8006b3a: e841 2300 strex r3, r2, [r1] 8006b3e: 653b str r3, [r7, #80] @ 0x50 return(result); 8006b40: 6d3b ldr r3, [r7, #80] @ 0x50 8006b42: 2b00 cmp r3, #0 8006b44: d1e6 bne.n 8006b14 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006b46: 687b ldr r3, [r7, #4] 8006b48: 681b ldr r3, [r3, #0] 8006b4a: 3308 adds r3, #8 8006b4c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b4e: 6bbb ldr r3, [r7, #56] @ 0x38 8006b50: e853 3f00 ldrex r3, [r3] 8006b54: 637b str r3, [r7, #52] @ 0x34 return(result); 8006b56: 6b7b ldr r3, [r7, #52] @ 0x34 8006b58: f023 0301 bic.w r3, r3, #1 8006b5c: 667b str r3, [r7, #100] @ 0x64 8006b5e: 687b ldr r3, [r7, #4] 8006b60: 681b ldr r3, [r3, #0] 8006b62: 3308 adds r3, #8 8006b64: 6e7a ldr r2, [r7, #100] @ 0x64 8006b66: 647a str r2, [r7, #68] @ 0x44 8006b68: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b6a: 6c39 ldr r1, [r7, #64] @ 0x40 8006b6c: 6c7a ldr r2, [r7, #68] @ 0x44 8006b6e: e841 2300 strex r3, r2, [r1] 8006b72: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006b74: 6bfb ldr r3, [r7, #60] @ 0x3c 8006b76: 2b00 cmp r3, #0 8006b78: d1e5 bne.n 8006b46 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006b7a: 687b ldr r3, [r7, #4] 8006b7c: 2220 movs r2, #32 8006b7e: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006b82: 687b ldr r3, [r7, #4] 8006b84: 2200 movs r2, #0 8006b86: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006b88: 687b ldr r3, [r7, #4] 8006b8a: 2200 movs r2, #0 8006b8c: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8006b8e: 687b ldr r3, [r7, #4] 8006b90: 681b ldr r3, [r3, #0] 8006b92: 4a33 ldr r2, [pc, #204] @ (8006c60 ) 8006b94: 4293 cmp r3, r2 8006b96: d01f beq.n 8006bd8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8006b98: 687b ldr r3, [r7, #4] 8006b9a: 681b ldr r3, [r3, #0] 8006b9c: 685b ldr r3, [r3, #4] 8006b9e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006ba2: 2b00 cmp r3, #0 8006ba4: d018 beq.n 8006bd8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8006ba6: 687b ldr r3, [r7, #4] 8006ba8: 681b ldr r3, [r3, #0] 8006baa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006bac: 6a7b ldr r3, [r7, #36] @ 0x24 8006bae: e853 3f00 ldrex r3, [r3] 8006bb2: 623b str r3, [r7, #32] return(result); 8006bb4: 6a3b ldr r3, [r7, #32] 8006bb6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8006bba: 663b str r3, [r7, #96] @ 0x60 8006bbc: 687b ldr r3, [r7, #4] 8006bbe: 681b ldr r3, [r3, #0] 8006bc0: 461a mov r2, r3 8006bc2: 6e3b ldr r3, [r7, #96] @ 0x60 8006bc4: 633b str r3, [r7, #48] @ 0x30 8006bc6: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006bc8: 6af9 ldr r1, [r7, #44] @ 0x2c 8006bca: 6b3a ldr r2, [r7, #48] @ 0x30 8006bcc: e841 2300 strex r3, r2, [r1] 8006bd0: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006bd2: 6abb ldr r3, [r7, #40] @ 0x28 8006bd4: 2b00 cmp r3, #0 8006bd6: d1e6 bne.n 8006ba6 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006bd8: 687b ldr r3, [r7, #4] 8006bda: 6edb ldr r3, [r3, #108] @ 0x6c 8006bdc: 2b01 cmp r3, #1 8006bde: d12e bne.n 8006c3e { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006be0: 687b ldr r3, [r7, #4] 8006be2: 2200 movs r2, #0 8006be4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006be6: 687b ldr r3, [r7, #4] 8006be8: 681b ldr r3, [r3, #0] 8006bea: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006bec: 693b ldr r3, [r7, #16] 8006bee: e853 3f00 ldrex r3, [r3] 8006bf2: 60fb str r3, [r7, #12] return(result); 8006bf4: 68fb ldr r3, [r7, #12] 8006bf6: f023 0310 bic.w r3, r3, #16 8006bfa: 65fb str r3, [r7, #92] @ 0x5c 8006bfc: 687b ldr r3, [r7, #4] 8006bfe: 681b ldr r3, [r3, #0] 8006c00: 461a mov r2, r3 8006c02: 6dfb ldr r3, [r7, #92] @ 0x5c 8006c04: 61fb str r3, [r7, #28] 8006c06: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c08: 69b9 ldr r1, [r7, #24] 8006c0a: 69fa ldr r2, [r7, #28] 8006c0c: e841 2300 strex r3, r2, [r1] 8006c10: 617b str r3, [r7, #20] return(result); 8006c12: 697b ldr r3, [r7, #20] 8006c14: 2b00 cmp r3, #0 8006c16: d1e6 bne.n 8006be6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006c18: 687b ldr r3, [r7, #4] 8006c1a: 681b ldr r3, [r3, #0] 8006c1c: 69db ldr r3, [r3, #28] 8006c1e: f003 0310 and.w r3, r3, #16 8006c22: 2b10 cmp r3, #16 8006c24: d103 bne.n 8006c2e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006c26: 687b ldr r3, [r7, #4] 8006c28: 681b ldr r3, [r3, #0] 8006c2a: 2210 movs r2, #16 8006c2c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006c2e: 687b ldr r3, [r7, #4] 8006c30: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8006c34: 4619 mov r1, r3 8006c36: 6878 ldr r0, [r7, #4] 8006c38: f7ff f872 bl 8005d20 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006c3c: e00b b.n 8006c56 HAL_UART_RxCpltCallback(huart); 8006c3e: 6878 ldr r0, [r7, #4] 8006c40: f7fa fd20 bl 8001684 } 8006c44: e007 b.n 8006c56 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006c46: 687b ldr r3, [r7, #4] 8006c48: 681b ldr r3, [r3, #0] 8006c4a: 699a ldr r2, [r3, #24] 8006c4c: 687b ldr r3, [r7, #4] 8006c4e: 681b ldr r3, [r3, #0] 8006c50: f042 0208 orr.w r2, r2, #8 8006c54: 619a str r2, [r3, #24] } 8006c56: bf00 nop 8006c58: 3770 adds r7, #112 @ 0x70 8006c5a: 46bd mov sp, r7 8006c5c: bd80 pop {r7, pc} 8006c5e: bf00 nop 8006c60: 40008000 .word 0x40008000 08006c64 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8006c64: b580 push {r7, lr} 8006c66: b09c sub sp, #112 @ 0x70 8006c68: af00 add r7, sp, #0 8006c6a: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8006c6c: 687b ldr r3, [r7, #4] 8006c6e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8006c72: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006c76: 687b ldr r3, [r7, #4] 8006c78: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8006c7c: 2b22 cmp r3, #34 @ 0x22 8006c7e: f040 80be bne.w 8006dfe { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006c82: 687b ldr r3, [r7, #4] 8006c84: 681b ldr r3, [r3, #0] 8006c86: 6a5b ldr r3, [r3, #36] @ 0x24 8006c88: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8006c8c: 687b ldr r3, [r7, #4] 8006c8e: 6d9b ldr r3, [r3, #88] @ 0x58 8006c90: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8006c92: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8006c96: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8006c9a: 4013 ands r3, r2 8006c9c: b29a uxth r2, r3 8006c9e: 6ebb ldr r3, [r7, #104] @ 0x68 8006ca0: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006ca2: 687b ldr r3, [r7, #4] 8006ca4: 6d9b ldr r3, [r3, #88] @ 0x58 8006ca6: 1c9a adds r2, r3, #2 8006ca8: 687b ldr r3, [r7, #4] 8006caa: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006cac: 687b ldr r3, [r7, #4] 8006cae: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006cb2: b29b uxth r3, r3 8006cb4: 3b01 subs r3, #1 8006cb6: b29a uxth r2, r3 8006cb8: 687b ldr r3, [r7, #4] 8006cba: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8006cbe: 687b ldr r3, [r7, #4] 8006cc0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006cc4: b29b uxth r3, r3 8006cc6: 2b00 cmp r3, #0 8006cc8: f040 80a1 bne.w 8006e0e { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8006ccc: 687b ldr r3, [r7, #4] 8006cce: 681b ldr r3, [r3, #0] 8006cd0: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006cd2: 6cbb ldr r3, [r7, #72] @ 0x48 8006cd4: e853 3f00 ldrex r3, [r3] 8006cd8: 647b str r3, [r7, #68] @ 0x44 return(result); 8006cda: 6c7b ldr r3, [r7, #68] @ 0x44 8006cdc: f423 7390 bic.w r3, r3, #288 @ 0x120 8006ce0: 667b str r3, [r7, #100] @ 0x64 8006ce2: 687b ldr r3, [r7, #4] 8006ce4: 681b ldr r3, [r3, #0] 8006ce6: 461a mov r2, r3 8006ce8: 6e7b ldr r3, [r7, #100] @ 0x64 8006cea: 657b str r3, [r7, #84] @ 0x54 8006cec: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006cee: 6d39 ldr r1, [r7, #80] @ 0x50 8006cf0: 6d7a ldr r2, [r7, #84] @ 0x54 8006cf2: e841 2300 strex r3, r2, [r1] 8006cf6: 64fb str r3, [r7, #76] @ 0x4c return(result); 8006cf8: 6cfb ldr r3, [r7, #76] @ 0x4c 8006cfa: 2b00 cmp r3, #0 8006cfc: d1e6 bne.n 8006ccc /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006cfe: 687b ldr r3, [r7, #4] 8006d00: 681b ldr r3, [r3, #0] 8006d02: 3308 adds r3, #8 8006d04: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d06: 6b7b ldr r3, [r7, #52] @ 0x34 8006d08: e853 3f00 ldrex r3, [r3] 8006d0c: 633b str r3, [r7, #48] @ 0x30 return(result); 8006d0e: 6b3b ldr r3, [r7, #48] @ 0x30 8006d10: f023 0301 bic.w r3, r3, #1 8006d14: 663b str r3, [r7, #96] @ 0x60 8006d16: 687b ldr r3, [r7, #4] 8006d18: 681b ldr r3, [r3, #0] 8006d1a: 3308 adds r3, #8 8006d1c: 6e3a ldr r2, [r7, #96] @ 0x60 8006d1e: 643a str r2, [r7, #64] @ 0x40 8006d20: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d22: 6bf9 ldr r1, [r7, #60] @ 0x3c 8006d24: 6c3a ldr r2, [r7, #64] @ 0x40 8006d26: e841 2300 strex r3, r2, [r1] 8006d2a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006d2c: 6bbb ldr r3, [r7, #56] @ 0x38 8006d2e: 2b00 cmp r3, #0 8006d30: d1e5 bne.n 8006cfe /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006d32: 687b ldr r3, [r7, #4] 8006d34: 2220 movs r2, #32 8006d36: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006d3a: 687b ldr r3, [r7, #4] 8006d3c: 2200 movs r2, #0 8006d3e: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006d40: 687b ldr r3, [r7, #4] 8006d42: 2200 movs r2, #0 8006d44: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8006d46: 687b ldr r3, [r7, #4] 8006d48: 681b ldr r3, [r3, #0] 8006d4a: 4a33 ldr r2, [pc, #204] @ (8006e18 ) 8006d4c: 4293 cmp r3, r2 8006d4e: d01f beq.n 8006d90 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8006d50: 687b ldr r3, [r7, #4] 8006d52: 681b ldr r3, [r3, #0] 8006d54: 685b ldr r3, [r3, #4] 8006d56: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d5a: 2b00 cmp r3, #0 8006d5c: d018 beq.n 8006d90 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8006d5e: 687b ldr r3, [r7, #4] 8006d60: 681b ldr r3, [r3, #0] 8006d62: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d64: 6a3b ldr r3, [r7, #32] 8006d66: e853 3f00 ldrex r3, [r3] 8006d6a: 61fb str r3, [r7, #28] return(result); 8006d6c: 69fb ldr r3, [r7, #28] 8006d6e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8006d72: 65fb str r3, [r7, #92] @ 0x5c 8006d74: 687b ldr r3, [r7, #4] 8006d76: 681b ldr r3, [r3, #0] 8006d78: 461a mov r2, r3 8006d7a: 6dfb ldr r3, [r7, #92] @ 0x5c 8006d7c: 62fb str r3, [r7, #44] @ 0x2c 8006d7e: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d80: 6ab9 ldr r1, [r7, #40] @ 0x28 8006d82: 6afa ldr r2, [r7, #44] @ 0x2c 8006d84: e841 2300 strex r3, r2, [r1] 8006d88: 627b str r3, [r7, #36] @ 0x24 return(result); 8006d8a: 6a7b ldr r3, [r7, #36] @ 0x24 8006d8c: 2b00 cmp r3, #0 8006d8e: d1e6 bne.n 8006d5e } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006d90: 687b ldr r3, [r7, #4] 8006d92: 6edb ldr r3, [r3, #108] @ 0x6c 8006d94: 2b01 cmp r3, #1 8006d96: d12e bne.n 8006df6 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006d98: 687b ldr r3, [r7, #4] 8006d9a: 2200 movs r2, #0 8006d9c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006d9e: 687b ldr r3, [r7, #4] 8006da0: 681b ldr r3, [r3, #0] 8006da2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006da4: 68fb ldr r3, [r7, #12] 8006da6: e853 3f00 ldrex r3, [r3] 8006daa: 60bb str r3, [r7, #8] return(result); 8006dac: 68bb ldr r3, [r7, #8] 8006dae: f023 0310 bic.w r3, r3, #16 8006db2: 65bb str r3, [r7, #88] @ 0x58 8006db4: 687b ldr r3, [r7, #4] 8006db6: 681b ldr r3, [r3, #0] 8006db8: 461a mov r2, r3 8006dba: 6dbb ldr r3, [r7, #88] @ 0x58 8006dbc: 61bb str r3, [r7, #24] 8006dbe: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006dc0: 6979 ldr r1, [r7, #20] 8006dc2: 69ba ldr r2, [r7, #24] 8006dc4: e841 2300 strex r3, r2, [r1] 8006dc8: 613b str r3, [r7, #16] return(result); 8006dca: 693b ldr r3, [r7, #16] 8006dcc: 2b00 cmp r3, #0 8006dce: d1e6 bne.n 8006d9e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006dd0: 687b ldr r3, [r7, #4] 8006dd2: 681b ldr r3, [r3, #0] 8006dd4: 69db ldr r3, [r3, #28] 8006dd6: f003 0310 and.w r3, r3, #16 8006dda: 2b10 cmp r3, #16 8006ddc: d103 bne.n 8006de6 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006dde: 687b ldr r3, [r7, #4] 8006de0: 681b ldr r3, [r3, #0] 8006de2: 2210 movs r2, #16 8006de4: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006de6: 687b ldr r3, [r7, #4] 8006de8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8006dec: 4619 mov r1, r3 8006dee: 6878 ldr r0, [r7, #4] 8006df0: f7fe ff96 bl 8005d20 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006df4: e00b b.n 8006e0e HAL_UART_RxCpltCallback(huart); 8006df6: 6878 ldr r0, [r7, #4] 8006df8: f7fa fc44 bl 8001684 } 8006dfc: e007 b.n 8006e0e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006dfe: 687b ldr r3, [r7, #4] 8006e00: 681b ldr r3, [r3, #0] 8006e02: 699a ldr r2, [r3, #24] 8006e04: 687b ldr r3, [r7, #4] 8006e06: 681b ldr r3, [r3, #0] 8006e08: f042 0208 orr.w r2, r2, #8 8006e0c: 619a str r2, [r3, #24] } 8006e0e: bf00 nop 8006e10: 3770 adds r7, #112 @ 0x70 8006e12: 46bd mov sp, r7 8006e14: bd80 pop {r7, pc} 8006e16: bf00 nop 8006e18: 40008000 .word 0x40008000 08006e1c : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8006e1c: b580 push {r7, lr} 8006e1e: b0ac sub sp, #176 @ 0xb0 8006e20: af00 add r7, sp, #0 8006e22: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8006e24: 687b ldr r3, [r7, #4] 8006e26: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8006e2a: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8006e2e: 687b ldr r3, [r7, #4] 8006e30: 681b ldr r3, [r3, #0] 8006e32: 69db ldr r3, [r3, #28] 8006e34: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006e38: 687b ldr r3, [r7, #4] 8006e3a: 681b ldr r3, [r3, #0] 8006e3c: 681b ldr r3, [r3, #0] 8006e3e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006e42: 687b ldr r3, [r7, #4] 8006e44: 681b ldr r3, [r3, #0] 8006e46: 689b ldr r3, [r3, #8] 8006e48: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006e4c: 687b ldr r3, [r7, #4] 8006e4e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8006e52: 2b22 cmp r3, #34 @ 0x22 8006e54: f040 8183 bne.w 800715e { nb_rx_data = huart->NbRxDataToProcess; 8006e58: 687b ldr r3, [r7, #4] 8006e5a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8006e5e: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006e62: e126 b.n 80070b2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006e64: 687b ldr r3, [r7, #4] 8006e66: 681b ldr r3, [r3, #0] 8006e68: 6a5b ldr r3, [r3, #36] @ 0x24 8006e6a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8006e6e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8006e72: b2d9 uxtb r1, r3 8006e74: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8006e78: b2da uxtb r2, r3 8006e7a: 687b ldr r3, [r7, #4] 8006e7c: 6d9b ldr r3, [r3, #88] @ 0x58 8006e7e: 400a ands r2, r1 8006e80: b2d2 uxtb r2, r2 8006e82: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8006e84: 687b ldr r3, [r7, #4] 8006e86: 6d9b ldr r3, [r3, #88] @ 0x58 8006e88: 1c5a adds r2, r3, #1 8006e8a: 687b ldr r3, [r7, #4] 8006e8c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006e8e: 687b ldr r3, [r7, #4] 8006e90: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006e94: b29b uxth r3, r3 8006e96: 3b01 subs r3, #1 8006e98: b29a uxth r2, r3 8006e9a: 687b ldr r3, [r7, #4] 8006e9c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8006ea0: 687b ldr r3, [r7, #4] 8006ea2: 681b ldr r3, [r3, #0] 8006ea4: 69db ldr r3, [r3, #28] 8006ea6: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8006eaa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006eae: f003 0307 and.w r3, r3, #7 8006eb2: 2b00 cmp r3, #0 8006eb4: d053 beq.n 8006f5e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8006eb6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006eba: f003 0301 and.w r3, r3, #1 8006ebe: 2b00 cmp r3, #0 8006ec0: d011 beq.n 8006ee6 8006ec2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8006ec6: f403 7380 and.w r3, r3, #256 @ 0x100 8006eca: 2b00 cmp r3, #0 8006ecc: d00b beq.n 8006ee6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8006ece: 687b ldr r3, [r7, #4] 8006ed0: 681b ldr r3, [r3, #0] 8006ed2: 2201 movs r2, #1 8006ed4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8006ed6: 687b ldr r3, [r7, #4] 8006ed8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006edc: f043 0201 orr.w r2, r3, #1 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006ee6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006eea: f003 0302 and.w r3, r3, #2 8006eee: 2b00 cmp r3, #0 8006ef0: d011 beq.n 8006f16 8006ef2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006ef6: f003 0301 and.w r3, r3, #1 8006efa: 2b00 cmp r3, #0 8006efc: d00b beq.n 8006f16 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8006efe: 687b ldr r3, [r7, #4] 8006f00: 681b ldr r3, [r3, #0] 8006f02: 2202 movs r2, #2 8006f04: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8006f06: 687b ldr r3, [r7, #4] 8006f08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006f0c: f043 0204 orr.w r2, r3, #4 8006f10: 687b ldr r3, [r7, #4] 8006f12: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006f16: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006f1a: f003 0304 and.w r3, r3, #4 8006f1e: 2b00 cmp r3, #0 8006f20: d011 beq.n 8006f46 8006f22: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006f26: f003 0301 and.w r3, r3, #1 8006f2a: 2b00 cmp r3, #0 8006f2c: d00b beq.n 8006f46 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8006f2e: 687b ldr r3, [r7, #4] 8006f30: 681b ldr r3, [r3, #0] 8006f32: 2204 movs r2, #4 8006f34: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8006f36: 687b ldr r3, [r7, #4] 8006f38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006f3c: f043 0202 orr.w r2, r3, #2 8006f40: 687b ldr r3, [r7, #4] 8006f42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006f46: 687b ldr r3, [r7, #4] 8006f48: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006f4c: 2b00 cmp r3, #0 8006f4e: d006 beq.n 8006f5e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006f50: 6878 ldr r0, [r7, #4] 8006f52: f7fe fedc bl 8005d0e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006f56: 687b ldr r3, [r7, #4] 8006f58: 2200 movs r2, #0 8006f5a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8006f5e: 687b ldr r3, [r7, #4] 8006f60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006f64: b29b uxth r3, r3 8006f66: 2b00 cmp r3, #0 8006f68: f040 80a3 bne.w 80070b2 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006f6c: 687b ldr r3, [r7, #4] 8006f6e: 681b ldr r3, [r3, #0] 8006f70: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f72: 6f3b ldr r3, [r7, #112] @ 0x70 8006f74: e853 3f00 ldrex r3, [r3] 8006f78: 66fb str r3, [r7, #108] @ 0x6c return(result); 8006f7a: 6efb ldr r3, [r7, #108] @ 0x6c 8006f7c: f423 7380 bic.w r3, r3, #256 @ 0x100 8006f80: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006f84: 687b ldr r3, [r7, #4] 8006f86: 681b ldr r3, [r3, #0] 8006f88: 461a mov r2, r3 8006f8a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8006f8e: 67fb str r3, [r7, #124] @ 0x7c 8006f90: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f92: 6fb9 ldr r1, [r7, #120] @ 0x78 8006f94: 6ffa ldr r2, [r7, #124] @ 0x7c 8006f96: e841 2300 strex r3, r2, [r1] 8006f9a: 677b str r3, [r7, #116] @ 0x74 return(result); 8006f9c: 6f7b ldr r3, [r7, #116] @ 0x74 8006f9e: 2b00 cmp r3, #0 8006fa0: d1e4 bne.n 8006f6c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8006fa2: 687b ldr r3, [r7, #4] 8006fa4: 681b ldr r3, [r3, #0] 8006fa6: 3308 adds r3, #8 8006fa8: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006faa: 6dfb ldr r3, [r7, #92] @ 0x5c 8006fac: e853 3f00 ldrex r3, [r3] 8006fb0: 65bb str r3, [r7, #88] @ 0x58 return(result); 8006fb2: 6dbb ldr r3, [r7, #88] @ 0x58 8006fb4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8006fb8: f023 0301 bic.w r3, r3, #1 8006fbc: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8006fc0: 687b ldr r3, [r7, #4] 8006fc2: 681b ldr r3, [r3, #0] 8006fc4: 3308 adds r3, #8 8006fc6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8006fca: 66ba str r2, [r7, #104] @ 0x68 8006fcc: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006fce: 6e79 ldr r1, [r7, #100] @ 0x64 8006fd0: 6eba ldr r2, [r7, #104] @ 0x68 8006fd2: e841 2300 strex r3, r2, [r1] 8006fd6: 663b str r3, [r7, #96] @ 0x60 return(result); 8006fd8: 6e3b ldr r3, [r7, #96] @ 0x60 8006fda: 2b00 cmp r3, #0 8006fdc: d1e1 bne.n 8006fa2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006fde: 687b ldr r3, [r7, #4] 8006fe0: 2220 movs r2, #32 8006fe2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006fe6: 687b ldr r3, [r7, #4] 8006fe8: 2200 movs r2, #0 8006fea: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006fec: 687b ldr r3, [r7, #4] 8006fee: 2200 movs r2, #0 8006ff0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8006ff2: 687b ldr r3, [r7, #4] 8006ff4: 681b ldr r3, [r3, #0] 8006ff6: 4a60 ldr r2, [pc, #384] @ (8007178 ) 8006ff8: 4293 cmp r3, r2 8006ffa: d021 beq.n 8007040 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8006ffc: 687b ldr r3, [r7, #4] 8006ffe: 681b ldr r3, [r3, #0] 8007000: 685b ldr r3, [r3, #4] 8007002: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8007006: 2b00 cmp r3, #0 8007008: d01a beq.n 8007040 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800700a: 687b ldr r3, [r7, #4] 800700c: 681b ldr r3, [r3, #0] 800700e: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007010: 6cbb ldr r3, [r7, #72] @ 0x48 8007012: e853 3f00 ldrex r3, [r3] 8007016: 647b str r3, [r7, #68] @ 0x44 return(result); 8007018: 6c7b ldr r3, [r7, #68] @ 0x44 800701a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800701e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8007022: 687b ldr r3, [r7, #4] 8007024: 681b ldr r3, [r3, #0] 8007026: 461a mov r2, r3 8007028: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800702c: 657b str r3, [r7, #84] @ 0x54 800702e: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007030: 6d39 ldr r1, [r7, #80] @ 0x50 8007032: 6d7a ldr r2, [r7, #84] @ 0x54 8007034: e841 2300 strex r3, r2, [r1] 8007038: 64fb str r3, [r7, #76] @ 0x4c return(result); 800703a: 6cfb ldr r3, [r7, #76] @ 0x4c 800703c: 2b00 cmp r3, #0 800703e: d1e4 bne.n 800700a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007040: 687b ldr r3, [r7, #4] 8007042: 6edb ldr r3, [r3, #108] @ 0x6c 8007044: 2b01 cmp r3, #1 8007046: d130 bne.n 80070aa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007048: 687b ldr r3, [r7, #4] 800704a: 2200 movs r2, #0 800704c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800704e: 687b ldr r3, [r7, #4] 8007050: 681b ldr r3, [r3, #0] 8007052: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007054: 6b7b ldr r3, [r7, #52] @ 0x34 8007056: e853 3f00 ldrex r3, [r3] 800705a: 633b str r3, [r7, #48] @ 0x30 return(result); 800705c: 6b3b ldr r3, [r7, #48] @ 0x30 800705e: f023 0310 bic.w r3, r3, #16 8007062: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8007066: 687b ldr r3, [r7, #4] 8007068: 681b ldr r3, [r3, #0] 800706a: 461a mov r2, r3 800706c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007070: 643b str r3, [r7, #64] @ 0x40 8007072: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007074: 6bf9 ldr r1, [r7, #60] @ 0x3c 8007076: 6c3a ldr r2, [r7, #64] @ 0x40 8007078: e841 2300 strex r3, r2, [r1] 800707c: 63bb str r3, [r7, #56] @ 0x38 return(result); 800707e: 6bbb ldr r3, [r7, #56] @ 0x38 8007080: 2b00 cmp r3, #0 8007082: d1e4 bne.n 800704e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8007084: 687b ldr r3, [r7, #4] 8007086: 681b ldr r3, [r3, #0] 8007088: 69db ldr r3, [r3, #28] 800708a: f003 0310 and.w r3, r3, #16 800708e: 2b10 cmp r3, #16 8007090: d103 bne.n 800709a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8007092: 687b ldr r3, [r7, #4] 8007094: 681b ldr r3, [r3, #0] 8007096: 2210 movs r2, #16 8007098: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800709a: 687b ldr r3, [r7, #4] 800709c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80070a0: 4619 mov r1, r3 80070a2: 6878 ldr r0, [r7, #4] 80070a4: f7fe fe3c bl 8005d20 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 80070a8: e00e b.n 80070c8 HAL_UART_RxCpltCallback(huart); 80070aa: 6878 ldr r0, [r7, #4] 80070ac: f7fa faea bl 8001684 break; 80070b0: e00a b.n 80070c8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80070b2: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 80070b6: 2b00 cmp r3, #0 80070b8: d006 beq.n 80070c8 80070ba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80070be: f003 0320 and.w r3, r3, #32 80070c2: 2b00 cmp r3, #0 80070c4: f47f aece bne.w 8006e64 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 80070c8: 687b ldr r3, [r7, #4] 80070ca: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80070ce: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 80070d2: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 80070d6: 2b00 cmp r3, #0 80070d8: d049 beq.n 800716e 80070da: 687b ldr r3, [r7, #4] 80070dc: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80070e0: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 80070e4: 429a cmp r2, r3 80070e6: d242 bcs.n 800716e { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80070e8: 687b ldr r3, [r7, #4] 80070ea: 681b ldr r3, [r3, #0] 80070ec: 3308 adds r3, #8 80070ee: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070f0: 6a3b ldr r3, [r7, #32] 80070f2: e853 3f00 ldrex r3, [r3] 80070f6: 61fb str r3, [r7, #28] return(result); 80070f8: 69fb ldr r3, [r7, #28] 80070fa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80070fe: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8007102: 687b ldr r3, [r7, #4] 8007104: 681b ldr r3, [r3, #0] 8007106: 3308 adds r3, #8 8007108: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 800710c: 62fa str r2, [r7, #44] @ 0x2c 800710e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007110: 6ab9 ldr r1, [r7, #40] @ 0x28 8007112: 6afa ldr r2, [r7, #44] @ 0x2c 8007114: e841 2300 strex r3, r2, [r1] 8007118: 627b str r3, [r7, #36] @ 0x24 return(result); 800711a: 6a7b ldr r3, [r7, #36] @ 0x24 800711c: 2b00 cmp r3, #0 800711e: d1e3 bne.n 80070e8 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8007120: 687b ldr r3, [r7, #4] 8007122: 4a16 ldr r2, [pc, #88] @ (800717c ) 8007124: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8007126: 687b ldr r3, [r7, #4] 8007128: 681b ldr r3, [r3, #0] 800712a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800712c: 68fb ldr r3, [r7, #12] 800712e: e853 3f00 ldrex r3, [r3] 8007132: 60bb str r3, [r7, #8] return(result); 8007134: 68bb ldr r3, [r7, #8] 8007136: f043 0320 orr.w r3, r3, #32 800713a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800713e: 687b ldr r3, [r7, #4] 8007140: 681b ldr r3, [r3, #0] 8007142: 461a mov r2, r3 8007144: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8007148: 61bb str r3, [r7, #24] 800714a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800714c: 6979 ldr r1, [r7, #20] 800714e: 69ba ldr r2, [r7, #24] 8007150: e841 2300 strex r3, r2, [r1] 8007154: 613b str r3, [r7, #16] return(result); 8007156: 693b ldr r3, [r7, #16] 8007158: 2b00 cmp r3, #0 800715a: d1e4 bne.n 8007126 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800715c: e007 b.n 800716e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800715e: 687b ldr r3, [r7, #4] 8007160: 681b ldr r3, [r3, #0] 8007162: 699a ldr r2, [r3, #24] 8007164: 687b ldr r3, [r7, #4] 8007166: 681b ldr r3, [r3, #0] 8007168: f042 0208 orr.w r2, r2, #8 800716c: 619a str r2, [r3, #24] } 800716e: bf00 nop 8007170: 37b0 adds r7, #176 @ 0xb0 8007172: 46bd mov sp, r7 8007174: bd80 pop {r7, pc} 8007176: bf00 nop 8007178: 40008000 .word 0x40008000 800717c: 08006aad .word 0x08006aad 08007180 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8007180: b580 push {r7, lr} 8007182: b0ae sub sp, #184 @ 0xb8 8007184: af00 add r7, sp, #0 8007186: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8007188: 687b ldr r3, [r7, #4] 800718a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800718e: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8007192: 687b ldr r3, [r7, #4] 8007194: 681b ldr r3, [r3, #0] 8007196: 69db ldr r3, [r3, #28] 8007198: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800719c: 687b ldr r3, [r7, #4] 800719e: 681b ldr r3, [r3, #0] 80071a0: 681b ldr r3, [r3, #0] 80071a2: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 80071a6: 687b ldr r3, [r7, #4] 80071a8: 681b ldr r3, [r3, #0] 80071aa: 689b ldr r3, [r3, #8] 80071ac: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80071b0: 687b ldr r3, [r7, #4] 80071b2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80071b6: 2b22 cmp r3, #34 @ 0x22 80071b8: f040 8187 bne.w 80074ca { nb_rx_data = huart->NbRxDataToProcess; 80071bc: 687b ldr r3, [r7, #4] 80071be: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80071c2: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80071c6: e12a b.n 800741e { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80071c8: 687b ldr r3, [r7, #4] 80071ca: 681b ldr r3, [r3, #0] 80071cc: 6a5b ldr r3, [r3, #36] @ 0x24 80071ce: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 80071d2: 687b ldr r3, [r7, #4] 80071d4: 6d9b ldr r3, [r3, #88] @ 0x58 80071d6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 80071da: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 80071de: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 80071e2: 4013 ands r3, r2 80071e4: b29a uxth r2, r3 80071e6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80071ea: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80071ec: 687b ldr r3, [r7, #4] 80071ee: 6d9b ldr r3, [r3, #88] @ 0x58 80071f0: 1c9a adds r2, r3, #2 80071f2: 687b ldr r3, [r7, #4] 80071f4: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80071f6: 687b ldr r3, [r7, #4] 80071f8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80071fc: b29b uxth r3, r3 80071fe: 3b01 subs r3, #1 8007200: b29a uxth r2, r3 8007202: 687b ldr r3, [r7, #4] 8007204: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8007208: 687b ldr r3, [r7, #4] 800720a: 681b ldr r3, [r3, #0] 800720c: 69db ldr r3, [r3, #28] 800720e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8007212: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8007216: f003 0307 and.w r3, r3, #7 800721a: 2b00 cmp r3, #0 800721c: d053 beq.n 80072c6 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800721e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8007222: f003 0301 and.w r3, r3, #1 8007226: 2b00 cmp r3, #0 8007228: d011 beq.n 800724e 800722a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800722e: f403 7380 and.w r3, r3, #256 @ 0x100 8007232: 2b00 cmp r3, #0 8007234: d00b beq.n 800724e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8007236: 687b ldr r3, [r7, #4] 8007238: 681b ldr r3, [r3, #0] 800723a: 2201 movs r2, #1 800723c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800723e: 687b ldr r3, [r7, #4] 8007240: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8007244: f043 0201 orr.w r2, r3, #1 8007248: 687b ldr r3, [r7, #4] 800724a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800724e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8007252: f003 0302 and.w r3, r3, #2 8007256: 2b00 cmp r3, #0 8007258: d011 beq.n 800727e 800725a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800725e: f003 0301 and.w r3, r3, #1 8007262: 2b00 cmp r3, #0 8007264: d00b beq.n 800727e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8007266: 687b ldr r3, [r7, #4] 8007268: 681b ldr r3, [r3, #0] 800726a: 2202 movs r2, #2 800726c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800726e: 687b ldr r3, [r7, #4] 8007270: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8007274: f043 0204 orr.w r2, r3, #4 8007278: 687b ldr r3, [r7, #4] 800727a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800727e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8007282: f003 0304 and.w r3, r3, #4 8007286: 2b00 cmp r3, #0 8007288: d011 beq.n 80072ae 800728a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800728e: f003 0301 and.w r3, r3, #1 8007292: 2b00 cmp r3, #0 8007294: d00b beq.n 80072ae { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8007296: 687b ldr r3, [r7, #4] 8007298: 681b ldr r3, [r3, #0] 800729a: 2204 movs r2, #4 800729c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800729e: 687b ldr r3, [r7, #4] 80072a0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80072a4: f043 0202 orr.w r2, r3, #2 80072a8: 687b ldr r3, [r7, #4] 80072aa: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80072ae: 687b ldr r3, [r7, #4] 80072b0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80072b4: 2b00 cmp r3, #0 80072b6: d006 beq.n 80072c6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80072b8: 6878 ldr r0, [r7, #4] 80072ba: f7fe fd28 bl 8005d0e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80072be: 687b ldr r3, [r7, #4] 80072c0: 2200 movs r2, #0 80072c2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80072c6: 687b ldr r3, [r7, #4] 80072c8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80072cc: b29b uxth r3, r3 80072ce: 2b00 cmp r3, #0 80072d0: f040 80a5 bne.w 800741e { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80072d4: 687b ldr r3, [r7, #4] 80072d6: 681b ldr r3, [r3, #0] 80072d8: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80072da: 6f7b ldr r3, [r7, #116] @ 0x74 80072dc: e853 3f00 ldrex r3, [r3] 80072e0: 673b str r3, [r7, #112] @ 0x70 return(result); 80072e2: 6f3b ldr r3, [r7, #112] @ 0x70 80072e4: f423 7380 bic.w r3, r3, #256 @ 0x100 80072e8: f8c7 309c str.w r3, [r7, #156] @ 0x9c 80072ec: 687b ldr r3, [r7, #4] 80072ee: 681b ldr r3, [r3, #0] 80072f0: 461a mov r2, r3 80072f2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80072f6: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80072fa: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80072fc: 6ff9 ldr r1, [r7, #124] @ 0x7c 80072fe: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8007302: e841 2300 strex r3, r2, [r1] 8007306: 67bb str r3, [r7, #120] @ 0x78 return(result); 8007308: 6fbb ldr r3, [r7, #120] @ 0x78 800730a: 2b00 cmp r3, #0 800730c: d1e2 bne.n 80072d4 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800730e: 687b ldr r3, [r7, #4] 8007310: 681b ldr r3, [r3, #0] 8007312: 3308 adds r3, #8 8007314: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007316: 6e3b ldr r3, [r7, #96] @ 0x60 8007318: e853 3f00 ldrex r3, [r3] 800731c: 65fb str r3, [r7, #92] @ 0x5c return(result); 800731e: 6dfb ldr r3, [r7, #92] @ 0x5c 8007320: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8007324: f023 0301 bic.w r3, r3, #1 8007328: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800732c: 687b ldr r3, [r7, #4] 800732e: 681b ldr r3, [r3, #0] 8007330: 3308 adds r3, #8 8007332: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8007336: 66fa str r2, [r7, #108] @ 0x6c 8007338: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800733a: 6eb9 ldr r1, [r7, #104] @ 0x68 800733c: 6efa ldr r2, [r7, #108] @ 0x6c 800733e: e841 2300 strex r3, r2, [r1] 8007342: 667b str r3, [r7, #100] @ 0x64 return(result); 8007344: 6e7b ldr r3, [r7, #100] @ 0x64 8007346: 2b00 cmp r3, #0 8007348: d1e1 bne.n 800730e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800734a: 687b ldr r3, [r7, #4] 800734c: 2220 movs r2, #32 800734e: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8007352: 687b ldr r3, [r7, #4] 8007354: 2200 movs r2, #0 8007356: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8007358: 687b ldr r3, [r7, #4] 800735a: 2200 movs r2, #0 800735c: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800735e: 687b ldr r3, [r7, #4] 8007360: 681b ldr r3, [r3, #0] 8007362: 4a60 ldr r2, [pc, #384] @ (80074e4 ) 8007364: 4293 cmp r3, r2 8007366: d021 beq.n 80073ac { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8007368: 687b ldr r3, [r7, #4] 800736a: 681b ldr r3, [r3, #0] 800736c: 685b ldr r3, [r3, #4] 800736e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8007372: 2b00 cmp r3, #0 8007374: d01a beq.n 80073ac { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8007376: 687b ldr r3, [r7, #4] 8007378: 681b ldr r3, [r3, #0] 800737a: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800737c: 6cfb ldr r3, [r7, #76] @ 0x4c 800737e: e853 3f00 ldrex r3, [r3] 8007382: 64bb str r3, [r7, #72] @ 0x48 return(result); 8007384: 6cbb ldr r3, [r7, #72] @ 0x48 8007386: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800738a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800738e: 687b ldr r3, [r7, #4] 8007390: 681b ldr r3, [r3, #0] 8007392: 461a mov r2, r3 8007394: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8007398: 65bb str r3, [r7, #88] @ 0x58 800739a: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800739c: 6d79 ldr r1, [r7, #84] @ 0x54 800739e: 6dba ldr r2, [r7, #88] @ 0x58 80073a0: e841 2300 strex r3, r2, [r1] 80073a4: 653b str r3, [r7, #80] @ 0x50 return(result); 80073a6: 6d3b ldr r3, [r7, #80] @ 0x50 80073a8: 2b00 cmp r3, #0 80073aa: d1e4 bne.n 8007376 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80073ac: 687b ldr r3, [r7, #4] 80073ae: 6edb ldr r3, [r3, #108] @ 0x6c 80073b0: 2b01 cmp r3, #1 80073b2: d130 bne.n 8007416 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80073b4: 687b ldr r3, [r7, #4] 80073b6: 2200 movs r2, #0 80073b8: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80073ba: 687b ldr r3, [r7, #4] 80073bc: 681b ldr r3, [r3, #0] 80073be: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80073c0: 6bbb ldr r3, [r7, #56] @ 0x38 80073c2: e853 3f00 ldrex r3, [r3] 80073c6: 637b str r3, [r7, #52] @ 0x34 return(result); 80073c8: 6b7b ldr r3, [r7, #52] @ 0x34 80073ca: f023 0310 bic.w r3, r3, #16 80073ce: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80073d2: 687b ldr r3, [r7, #4] 80073d4: 681b ldr r3, [r3, #0] 80073d6: 461a mov r2, r3 80073d8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80073dc: 647b str r3, [r7, #68] @ 0x44 80073de: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80073e0: 6c39 ldr r1, [r7, #64] @ 0x40 80073e2: 6c7a ldr r2, [r7, #68] @ 0x44 80073e4: e841 2300 strex r3, r2, [r1] 80073e8: 63fb str r3, [r7, #60] @ 0x3c return(result); 80073ea: 6bfb ldr r3, [r7, #60] @ 0x3c 80073ec: 2b00 cmp r3, #0 80073ee: d1e4 bne.n 80073ba if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80073f0: 687b ldr r3, [r7, #4] 80073f2: 681b ldr r3, [r3, #0] 80073f4: 69db ldr r3, [r3, #28] 80073f6: f003 0310 and.w r3, r3, #16 80073fa: 2b10 cmp r3, #16 80073fc: d103 bne.n 8007406 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80073fe: 687b ldr r3, [r7, #4] 8007400: 681b ldr r3, [r3, #0] 8007402: 2210 movs r2, #16 8007404: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8007406: 687b ldr r3, [r7, #4] 8007408: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800740c: 4619 mov r1, r3 800740e: 6878 ldr r0, [r7, #4] 8007410: f7fe fc86 bl 8005d20 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 8007414: e00e b.n 8007434 HAL_UART_RxCpltCallback(huart); 8007416: 6878 ldr r0, [r7, #4] 8007418: f7fa f934 bl 8001684 break; 800741c: e00a b.n 8007434 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800741e: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8007422: 2b00 cmp r3, #0 8007424: d006 beq.n 8007434 8007426: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800742a: f003 0320 and.w r3, r3, #32 800742e: 2b00 cmp r3, #0 8007430: f47f aeca bne.w 80071c8 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8007434: 687b ldr r3, [r7, #4] 8007436: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800743a: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800743e: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8007442: 2b00 cmp r3, #0 8007444: d049 beq.n 80074da 8007446: 687b ldr r3, [r7, #4] 8007448: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800744c: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8007450: 429a cmp r2, r3 8007452: d242 bcs.n 80074da { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8007454: 687b ldr r3, [r7, #4] 8007456: 681b ldr r3, [r3, #0] 8007458: 3308 adds r3, #8 800745a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800745c: 6a7b ldr r3, [r7, #36] @ 0x24 800745e: e853 3f00 ldrex r3, [r3] 8007462: 623b str r3, [r7, #32] return(result); 8007464: 6a3b ldr r3, [r7, #32] 8007466: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800746a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800746e: 687b ldr r3, [r7, #4] 8007470: 681b ldr r3, [r3, #0] 8007472: 3308 adds r3, #8 8007474: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8007478: 633a str r2, [r7, #48] @ 0x30 800747a: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800747c: 6af9 ldr r1, [r7, #44] @ 0x2c 800747e: 6b3a ldr r2, [r7, #48] @ 0x30 8007480: e841 2300 strex r3, r2, [r1] 8007484: 62bb str r3, [r7, #40] @ 0x28 return(result); 8007486: 6abb ldr r3, [r7, #40] @ 0x28 8007488: 2b00 cmp r3, #0 800748a: d1e3 bne.n 8007454 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 800748c: 687b ldr r3, [r7, #4] 800748e: 4a16 ldr r2, [pc, #88] @ (80074e8 ) 8007490: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8007492: 687b ldr r3, [r7, #4] 8007494: 681b ldr r3, [r3, #0] 8007496: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007498: 693b ldr r3, [r7, #16] 800749a: e853 3f00 ldrex r3, [r3] 800749e: 60fb str r3, [r7, #12] return(result); 80074a0: 68fb ldr r3, [r7, #12] 80074a2: f043 0320 orr.w r3, r3, #32 80074a6: f8c7 3084 str.w r3, [r7, #132] @ 0x84 80074aa: 687b ldr r3, [r7, #4] 80074ac: 681b ldr r3, [r3, #0] 80074ae: 461a mov r2, r3 80074b0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80074b4: 61fb str r3, [r7, #28] 80074b6: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80074b8: 69b9 ldr r1, [r7, #24] 80074ba: 69fa ldr r2, [r7, #28] 80074bc: e841 2300 strex r3, r2, [r1] 80074c0: 617b str r3, [r7, #20] return(result); 80074c2: 697b ldr r3, [r7, #20] 80074c4: 2b00 cmp r3, #0 80074c6: d1e4 bne.n 8007492 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80074c8: e007 b.n 80074da __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80074ca: 687b ldr r3, [r7, #4] 80074cc: 681b ldr r3, [r3, #0] 80074ce: 699a ldr r2, [r3, #24] 80074d0: 687b ldr r3, [r7, #4] 80074d2: 681b ldr r3, [r3, #0] 80074d4: f042 0208 orr.w r2, r2, #8 80074d8: 619a str r2, [r3, #24] } 80074da: bf00 nop 80074dc: 37b8 adds r7, #184 @ 0xb8 80074de: 46bd mov sp, r7 80074e0: bd80 pop {r7, pc} 80074e2: bf00 nop 80074e4: 40008000 .word 0x40008000 80074e8: 08006c65 .word 0x08006c65 080074ec : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 80074ec: b480 push {r7} 80074ee: b083 sub sp, #12 80074f0: af00 add r7, sp, #0 80074f2: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 80074f4: bf00 nop 80074f6: 370c adds r7, #12 80074f8: 46bd mov sp, r7 80074fa: bc80 pop {r7} 80074fc: 4770 bx lr 080074fe : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 80074fe: b480 push {r7} 8007500: b083 sub sp, #12 8007502: af00 add r7, sp, #0 8007504: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8007506: bf00 nop 8007508: 370c adds r7, #12 800750a: 46bd mov sp, r7 800750c: bc80 pop {r7} 800750e: 4770 bx lr 08007510 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8007510: b480 push {r7} 8007512: b083 sub sp, #12 8007514: af00 add r7, sp, #0 8007516: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8007518: bf00 nop 800751a: 370c adds r7, #12 800751c: 46bd mov sp, r7 800751e: bc80 pop {r7} 8007520: 4770 bx lr 08007522 : * @arg @ref UART_WAKEUP_ON_STARTBIT * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { 8007522: b580 push {r7, lr} 8007524: b088 sub sp, #32 8007526: af02 add r7, sp, #8 8007528: 60f8 str r0, [r7, #12] 800752a: 1d3b adds r3, r7, #4 800752c: e883 0006 stmia.w r3, {r1, r2} HAL_StatusTypeDef status = HAL_OK; 8007530: 2300 movs r3, #0 8007532: 75fb strb r3, [r7, #23] assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); /* Process Locked */ __HAL_LOCK(huart); 8007534: 68fb ldr r3, [r7, #12] 8007536: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800753a: 2b01 cmp r3, #1 800753c: d101 bne.n 8007542 800753e: 2302 movs r3, #2 8007540: e046 b.n 80075d0 8007542: 68fb ldr r3, [r7, #12] 8007544: 2201 movs r2, #1 8007546: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800754a: 68fb ldr r3, [r7, #12] 800754c: 2224 movs r2, #36 @ 0x24 800754e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); 8007552: 68fb ldr r3, [r7, #12] 8007554: 681b ldr r3, [r3, #0] 8007556: 681a ldr r2, [r3, #0] 8007558: 68fb ldr r3, [r7, #12] 800755a: 681b ldr r3, [r3, #0] 800755c: f022 0201 bic.w r2, r2, #1 8007560: 601a str r2, [r3, #0] /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); 8007562: 68fb ldr r3, [r7, #12] 8007564: 681b ldr r3, [r3, #0] 8007566: 689b ldr r3, [r3, #8] 8007568: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800756c: 687a ldr r2, [r7, #4] 800756e: 68fb ldr r3, [r7, #12] 8007570: 681b ldr r3, [r3, #0] 8007572: 430a orrs r2, r1 8007574: 609a str r2, [r3, #8] if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) 8007576: 687b ldr r3, [r7, #4] 8007578: 2b00 cmp r3, #0 800757a: d105 bne.n 8007588 { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); 800757c: 1d3b adds r3, r7, #4 800757e: e893 0006 ldmia.w r3, {r1, r2} 8007582: 68f8 ldr r0, [r7, #12] 8007584: f000 f911 bl 80077aa } /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); 8007588: 68fb ldr r3, [r7, #12] 800758a: 681b ldr r3, [r3, #0] 800758c: 681a ldr r2, [r3, #0] 800758e: 68fb ldr r3, [r7, #12] 8007590: 681b ldr r3, [r3, #0] 8007592: f042 0201 orr.w r2, r2, #1 8007596: 601a str r2, [r3, #0] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8007598: f7f9 fb56 bl 8000c48 800759c: 6138 str r0, [r7, #16] /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800759e: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80075a2: 9300 str r3, [sp, #0] 80075a4: 693b ldr r3, [r7, #16] 80075a6: 2200 movs r2, #0 80075a8: f44f 0180 mov.w r1, #4194304 @ 0x400000 80075ac: 68f8 ldr r0, [r7, #12] 80075ae: f7fe ff82 bl 80064b6 80075b2: 4603 mov r3, r0 80075b4: 2b00 cmp r3, #0 80075b6: d002 beq.n 80075be { status = HAL_TIMEOUT; 80075b8: 2303 movs r3, #3 80075ba: 75fb strb r3, [r7, #23] 80075bc: e003 b.n 80075c6 } else { /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 80075be: 68fb ldr r3, [r7, #12] 80075c0: 2220 movs r2, #32 80075c2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 } /* Process Unlocked */ __HAL_UNLOCK(huart); 80075c6: 68fb ldr r3, [r7, #12] 80075c8: 2200 movs r2, #0 80075ca: f883 2084 strb.w r2, [r3, #132] @ 0x84 return status; 80075ce: 7dfb ldrb r3, [r7, #23] } 80075d0: 4618 mov r0, r3 80075d2: 3718 adds r7, #24 80075d4: 46bd mov sp, r7 80075d6: bd80 pop {r7, pc} 080075d8 : * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { 80075d8: b480 push {r7} 80075da: b089 sub sp, #36 @ 0x24 80075dc: af00 add r7, sp, #0 80075de: 6078 str r0, [r7, #4] /* Process Locked */ __HAL_LOCK(huart); 80075e0: 687b ldr r3, [r7, #4] 80075e2: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80075e6: 2b01 cmp r3, #1 80075e8: d101 bne.n 80075ee 80075ea: 2302 movs r3, #2 80075ec: e021 b.n 8007632 80075ee: 687b ldr r3, [r7, #4] 80075f0: 2201 movs r2, #1 80075f2: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Set UESM bit */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); 80075f6: 687b ldr r3, [r7, #4] 80075f8: 681b ldr r3, [r3, #0] 80075fa: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80075fc: 68fb ldr r3, [r7, #12] 80075fe: e853 3f00 ldrex r3, [r3] 8007602: 60bb str r3, [r7, #8] return(result); 8007604: 68bb ldr r3, [r7, #8] 8007606: f043 0302 orr.w r3, r3, #2 800760a: 61fb str r3, [r7, #28] 800760c: 687b ldr r3, [r7, #4] 800760e: 681b ldr r3, [r3, #0] 8007610: 461a mov r2, r3 8007612: 69fb ldr r3, [r7, #28] 8007614: 61bb str r3, [r7, #24] 8007616: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007618: 6979 ldr r1, [r7, #20] 800761a: 69ba ldr r2, [r7, #24] 800761c: e841 2300 strex r3, r2, [r1] 8007620: 613b str r3, [r7, #16] return(result); 8007622: 693b ldr r3, [r7, #16] 8007624: 2b00 cmp r3, #0 8007626: d1e6 bne.n 80075f6 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007628: 687b ldr r3, [r7, #4] 800762a: 2200 movs r2, #0 800762c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8007630: 2300 movs r3, #0 } 8007632: 4618 mov r0, r3 8007634: 3724 adds r7, #36 @ 0x24 8007636: 46bd mov sp, r7 8007638: bc80 pop {r7} 800763a: 4770 bx lr 0800763c : * @brief Enable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { 800763c: b580 push {r7, lr} 800763e: b084 sub sp, #16 8007640: af00 add r7, sp, #0 8007642: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8007644: 687b ldr r3, [r7, #4] 8007646: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800764a: 2b01 cmp r3, #1 800764c: d101 bne.n 8007652 800764e: 2302 movs r3, #2 8007650: e02b b.n 80076aa 8007652: 687b ldr r3, [r7, #4] 8007654: 2201 movs r2, #1 8007656: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800765a: 687b ldr r3, [r7, #4] 800765c: 2224 movs r2, #36 @ 0x24 800765e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007662: 687b ldr r3, [r7, #4] 8007664: 681b ldr r3, [r3, #0] 8007666: 681b ldr r3, [r3, #0] 8007668: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800766a: 687b ldr r3, [r7, #4] 800766c: 681b ldr r3, [r3, #0] 800766e: 681a ldr r2, [r3, #0] 8007670: 687b ldr r3, [r7, #4] 8007672: 681b ldr r3, [r3, #0] 8007674: f022 0201 bic.w r2, r2, #1 8007678: 601a str r2, [r3, #0] /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); 800767a: 68fb ldr r3, [r7, #12] 800767c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007680: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_ENABLE; 8007682: 687b ldr r3, [r7, #4] 8007684: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8007688: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800768a: 687b ldr r3, [r7, #4] 800768c: 681b ldr r3, [r3, #0] 800768e: 68fa ldr r2, [r7, #12] 8007690: 601a str r2, [r3, #0] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007692: 6878 ldr r0, [r7, #4] 8007694: f000 f8ac bl 80077f0 huart->gState = HAL_UART_STATE_READY; 8007698: 687b ldr r3, [r7, #4] 800769a: 2220 movs r2, #32 800769c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80076a0: 687b ldr r3, [r7, #4] 80076a2: 2200 movs r2, #0 80076a4: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80076a8: 2300 movs r3, #0 } 80076aa: 4618 mov r0, r3 80076ac: 3710 adds r7, #16 80076ae: 46bd mov sp, r7 80076b0: bd80 pop {r7, pc} 080076b2 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80076b2: b580 push {r7, lr} 80076b4: b084 sub sp, #16 80076b6: af00 add r7, sp, #0 80076b8: 6078 str r0, [r7, #4] 80076ba: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80076bc: 687b ldr r3, [r7, #4] 80076be: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80076c2: 2b01 cmp r3, #1 80076c4: d101 bne.n 80076ca 80076c6: 2302 movs r3, #2 80076c8: e02d b.n 8007726 80076ca: 687b ldr r3, [r7, #4] 80076cc: 2201 movs r2, #1 80076ce: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80076d2: 687b ldr r3, [r7, #4] 80076d4: 2224 movs r2, #36 @ 0x24 80076d6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80076da: 687b ldr r3, [r7, #4] 80076dc: 681b ldr r3, [r3, #0] 80076de: 681b ldr r3, [r3, #0] 80076e0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80076e2: 687b ldr r3, [r7, #4] 80076e4: 681b ldr r3, [r3, #0] 80076e6: 681a ldr r2, [r3, #0] 80076e8: 687b ldr r3, [r7, #4] 80076ea: 681b ldr r3, [r3, #0] 80076ec: f022 0201 bic.w r2, r2, #1 80076f0: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 80076f2: 687b ldr r3, [r7, #4] 80076f4: 681b ldr r3, [r3, #0] 80076f6: 689b ldr r3, [r3, #8] 80076f8: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 80076fc: 687b ldr r3, [r7, #4] 80076fe: 681b ldr r3, [r3, #0] 8007700: 683a ldr r2, [r7, #0] 8007702: 430a orrs r2, r1 8007704: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007706: 6878 ldr r0, [r7, #4] 8007708: f000 f872 bl 80077f0 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800770c: 687b ldr r3, [r7, #4] 800770e: 681b ldr r3, [r3, #0] 8007710: 68fa ldr r2, [r7, #12] 8007712: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8007714: 687b ldr r3, [r7, #4] 8007716: 2220 movs r2, #32 8007718: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800771c: 687b ldr r3, [r7, #4] 800771e: 2200 movs r2, #0 8007720: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8007724: 2300 movs r3, #0 } 8007726: 4618 mov r0, r3 8007728: 3710 adds r7, #16 800772a: 46bd mov sp, r7 800772c: bd80 pop {r7, pc} 0800772e : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800772e: b580 push {r7, lr} 8007730: b084 sub sp, #16 8007732: af00 add r7, sp, #0 8007734: 6078 str r0, [r7, #4] 8007736: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8007738: 687b ldr r3, [r7, #4] 800773a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800773e: 2b01 cmp r3, #1 8007740: d101 bne.n 8007746 8007742: 2302 movs r3, #2 8007744: e02d b.n 80077a2 8007746: 687b ldr r3, [r7, #4] 8007748: 2201 movs r2, #1 800774a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800774e: 687b ldr r3, [r7, #4] 8007750: 2224 movs r2, #36 @ 0x24 8007752: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007756: 687b ldr r3, [r7, #4] 8007758: 681b ldr r3, [r3, #0] 800775a: 681b ldr r3, [r3, #0] 800775c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800775e: 687b ldr r3, [r7, #4] 8007760: 681b ldr r3, [r3, #0] 8007762: 681a ldr r2, [r3, #0] 8007764: 687b ldr r3, [r7, #4] 8007766: 681b ldr r3, [r3, #0] 8007768: f022 0201 bic.w r2, r2, #1 800776c: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800776e: 687b ldr r3, [r7, #4] 8007770: 681b ldr r3, [r3, #0] 8007772: 689b ldr r3, [r3, #8] 8007774: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8007778: 687b ldr r3, [r7, #4] 800777a: 681b ldr r3, [r3, #0] 800777c: 683a ldr r2, [r7, #0] 800777e: 430a orrs r2, r1 8007780: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007782: 6878 ldr r0, [r7, #4] 8007784: f000 f834 bl 80077f0 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8007788: 687b ldr r3, [r7, #4] 800778a: 681b ldr r3, [r3, #0] 800778c: 68fa ldr r2, [r7, #12] 800778e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8007790: 687b ldr r3, [r7, #4] 8007792: 2220 movs r2, #32 8007794: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007798: 687b ldr r3, [r7, #4] 800779a: 2200 movs r2, #0 800779c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80077a0: 2300 movs r3, #0 } 80077a2: 4618 mov r0, r3 80077a4: 3710 adds r7, #16 80077a6: 46bd mov sp, r7 80077a8: bd80 pop {r7, pc} 080077aa : * @param huart UART handle. * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { 80077aa: b480 push {r7} 80077ac: b085 sub sp, #20 80077ae: af00 add r7, sp, #0 80077b0: 60f8 str r0, [r7, #12] 80077b2: 1d3b adds r3, r7, #4 80077b4: e883 0006 stmia.w r3, {r1, r2} assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); 80077b8: 68fb ldr r3, [r7, #12] 80077ba: 681b ldr r3, [r3, #0] 80077bc: 685b ldr r3, [r3, #4] 80077be: f023 0210 bic.w r2, r3, #16 80077c2: 893b ldrh r3, [r7, #8] 80077c4: 4619 mov r1, r3 80077c6: 68fb ldr r3, [r7, #12] 80077c8: 681b ldr r3, [r3, #0] 80077ca: 430a orrs r2, r1 80077cc: 605a str r2, [r3, #4] /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); 80077ce: 68fb ldr r3, [r7, #12] 80077d0: 681b ldr r3, [r3, #0] 80077d2: 685b ldr r3, [r3, #4] 80077d4: f023 417f bic.w r1, r3, #4278190080 @ 0xff000000 80077d8: 7abb ldrb r3, [r7, #10] 80077da: 061a lsls r2, r3, #24 80077dc: 68fb ldr r3, [r7, #12] 80077de: 681b ldr r3, [r3, #0] 80077e0: 430a orrs r2, r1 80077e2: 605a str r2, [r3, #4] } 80077e4: bf00 nop 80077e6: 3714 adds r7, #20 80077e8: 46bd mov sp, r7 80077ea: bc80 pop {r7} 80077ec: 4770 bx lr ... 080077f0 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80077f0: b480 push {r7} 80077f2: b085 sub sp, #20 80077f4: af00 add r7, sp, #0 80077f6: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80077f8: 687b ldr r3, [r7, #4] 80077fa: 6e5b ldr r3, [r3, #100] @ 0x64 80077fc: 2b00 cmp r3, #0 80077fe: d108 bne.n 8007812 { huart->NbTxDataToProcess = 1U; 8007800: 687b ldr r3, [r7, #4] 8007802: 2201 movs r2, #1 8007804: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8007808: 687b ldr r3, [r7, #4] 800780a: 2201 movs r2, #1 800780c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8007810: e031 b.n 8007876 rx_fifo_depth = RX_FIFO_DEPTH; 8007812: 2308 movs r3, #8 8007814: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8007816: 2308 movs r3, #8 8007818: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800781a: 687b ldr r3, [r7, #4] 800781c: 681b ldr r3, [r3, #0] 800781e: 689b ldr r3, [r3, #8] 8007820: 0e5b lsrs r3, r3, #25 8007822: b2db uxtb r3, r3 8007824: f003 0307 and.w r3, r3, #7 8007828: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800782a: 687b ldr r3, [r7, #4] 800782c: 681b ldr r3, [r3, #0] 800782e: 689b ldr r3, [r3, #8] 8007830: 0f5b lsrs r3, r3, #29 8007832: b2db uxtb r3, r3 8007834: f003 0307 and.w r3, r3, #7 8007838: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800783a: 7bbb ldrb r3, [r7, #14] 800783c: 7b3a ldrb r2, [r7, #12] 800783e: 4910 ldr r1, [pc, #64] @ (8007880 ) 8007840: 5c8a ldrb r2, [r1, r2] 8007842: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8007846: 7b3a ldrb r2, [r7, #12] 8007848: 490e ldr r1, [pc, #56] @ (8007884 ) 800784a: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800784c: fb93 f3f2 sdiv r3, r3, r2 8007850: b29a uxth r2, r3 8007852: 687b ldr r3, [r7, #4] 8007854: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8007858: 7bfb ldrb r3, [r7, #15] 800785a: 7b7a ldrb r2, [r7, #13] 800785c: 4908 ldr r1, [pc, #32] @ (8007880 ) 800785e: 5c8a ldrb r2, [r1, r2] 8007860: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8007864: 7b7a ldrb r2, [r7, #13] 8007866: 4907 ldr r1, [pc, #28] @ (8007884 ) 8007868: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800786a: fb93 f3f2 sdiv r3, r3, r2 800786e: b29a uxth r2, r3 8007870: 687b ldr r3, [r7, #4] 8007872: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8007876: bf00 nop 8007878: 3714 adds r7, #20 800787a: 46bd mov sp, r7 800787c: bc80 pop {r7} 800787e: 4770 bx lr 8007880: 0800fb6c .word 0x0800fb6c 8007884: 0800fb74 .word 0x0800fb74 08007888 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 8007888: b480 push {r7} 800788a: b083 sub sp, #12 800788c: af00 add r7, sp, #0 800788e: 6078 str r0, [r7, #4] 8007890: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BSRR, PinMask); 8007892: 687b ldr r3, [r7, #4] 8007894: 683a ldr r2, [r7, #0] 8007896: 619a str r2, [r3, #24] } 8007898: bf00 nop 800789a: 370c adds r7, #12 800789c: 46bd mov sp, r7 800789e: bc80 pop {r7} 80078a0: 4770 bx lr 080078a2 : * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { 80078a2: b480 push {r7} 80078a4: b083 sub sp, #12 80078a6: af00 add r7, sp, #0 80078a8: 6078 str r0, [r7, #4] 80078aa: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BRR, PinMask); 80078ac: 687b ldr r3, [r7, #4] 80078ae: 683a ldr r2, [r7, #0] 80078b0: 629a str r2, [r3, #40] @ 0x28 } 80078b2: bf00 nop 80078b4: 370c adds r7, #12 80078b6: 46bd mov sp, r7 80078b8: bc80 pop {r7} 80078ba: 4770 bx lr 080078bc : TimerEvent_t RxTimeoutTimer; /* Private functions ---------------------------------------------------------*/ static void RadioInit( RadioEvents_t *events ) { 80078bc: b580 push {r7, lr} 80078be: b084 sub sp, #16 80078c0: af02 add r7, sp, #8 80078c2: 6078 str r0, [r7, #4] RadioEvents = events; 80078c4: 4a24 ldr r2, [pc, #144] @ (8007958 ) 80078c6: 687b ldr r3, [r7, #4] 80078c8: 6013 str r3, [r2, #0] SubgRf.RxContinuous = false; 80078ca: 4b24 ldr r3, [pc, #144] @ (800795c ) 80078cc: 2200 movs r2, #0 80078ce: 705a strb r2, [r3, #1] SubgRf.TxTimeout = 0; 80078d0: 4b22 ldr r3, [pc, #136] @ (800795c ) 80078d2: 2200 movs r2, #0 80078d4: 605a str r2, [r3, #4] SubgRf.RxTimeout = 0; 80078d6: 4b21 ldr r3, [pc, #132] @ (800795c ) 80078d8: 2200 movs r2, #0 80078da: 609a str r2, [r3, #8] /*See STM32WL Errata: RadioSetRxDutyCycle*/ SubgRf.RxDcPreambleDetectTimeout = 0; 80078dc: 4b1f ldr r3, [pc, #124] @ (800795c ) 80078de: 2200 movs r2, #0 80078e0: 659a str r2, [r3, #88] @ 0x58 #if( RADIO_LR_FHSS_IS_ON == 1 ) SubgRf.lr_fhss.is_lr_fhss_on = false; #endif /* RADIO_LR_FHSS_IS_ON == 1 */ SUBGRF_Init( RadioOnDioIrq ); 80078e2: 481f ldr r0, [pc, #124] @ (8007960 ) 80078e4: f001 fffa bl 80098dc /*SubgRf.publicNetwork set to false*/ SubgRf.PublicNetwork.Current = false; 80078e8: 4b1c ldr r3, [pc, #112] @ (800795c ) 80078ea: 2200 movs r2, #0 80078ec: 735a strb r2, [r3, #13] SubgRf.PublicNetwork.Previous = false; 80078ee: 4b1b ldr r3, [pc, #108] @ (800795c ) 80078f0: 2200 movs r2, #0 80078f2: 731a strb r2, [r3, #12] RADIO_IRQ_PROCESS_INIT(); SUBGRF_SetRegulatorMode( ); 80078f4: f002 fa90 bl 8009e18 SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); 80078f8: 2100 movs r1, #0 80078fa: 2000 movs r0, #0 80078fc: f002 fe5c bl 800a5b8 SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US ); 8007900: 2204 movs r2, #4 8007902: 2100 movs r1, #0 8007904: 2001 movs r0, #1 8007906: f002 fc1f bl 800a148 SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); 800790a: 2300 movs r3, #0 800790c: 2200 movs r2, #0 800790e: f64f 71ff movw r1, #65535 @ 0xffff 8007912: f64f 70ff movw r0, #65535 @ 0xffff 8007916: f002 fb4f bl 8009fb8 RadioSleep(); 800791a: f000 fe9f bl 800865c // Initialize driver timeout timers TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); 800791e: 2300 movs r3, #0 8007920: 9300 str r3, [sp, #0] 8007922: 4b10 ldr r3, [pc, #64] @ (8007964 ) 8007924: 2200 movs r2, #0 8007926: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800792a: 480f ldr r0, [pc, #60] @ (8007968 ) 800792c: f006 f8e0 bl 800daf0 TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); 8007930: 2300 movs r3, #0 8007932: 9300 str r3, [sp, #0] 8007934: 4b0d ldr r3, [pc, #52] @ (800796c ) 8007936: 2200 movs r2, #0 8007938: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800793c: 480c ldr r0, [pc, #48] @ (8007970 ) 800793e: f006 f8d7 bl 800daf0 TimerStop( &TxTimeoutTimer ); 8007942: 4809 ldr r0, [pc, #36] @ (8007968 ) 8007944: f006 f978 bl 800dc38 TimerStop( &RxTimeoutTimer ); 8007948: 4809 ldr r0, [pc, #36] @ (8007970 ) 800794a: f006 f975 bl 800dc38 } 800794e: bf00 nop 8007950: 3708 adds r7, #8 8007952: 46bd mov sp, r7 8007954: bd80 pop {r7, pc} 8007956: bf00 nop 8007958: 200002fc .word 0x200002fc 800795c: 20000300 .word 0x20000300 8007960: 08008a81 .word 0x08008a81 8007964: 080089f1 .word 0x080089f1 8007968: 2000035c .word 0x2000035c 800796c: 08008a05 .word 0x08008a05 8007970: 20000374 .word 0x20000374 08007974 : static RadioState_t RadioGetStatus( void ) { 8007974: b580 push {r7, lr} 8007976: af00 add r7, sp, #0 switch( SUBGRF_GetOperatingMode( ) ) 8007978: f001 fff8 bl 800996c 800797c: 4603 mov r3, r0 800797e: 2b07 cmp r3, #7 8007980: d00a beq.n 8007998 8007982: 2b07 cmp r3, #7 8007984: dc0a bgt.n 800799c 8007986: 2b04 cmp r3, #4 8007988: d002 beq.n 8007990 800798a: 2b05 cmp r3, #5 800798c: d002 beq.n 8007994 800798e: e005 b.n 800799c { case MODE_TX: return RF_TX_RUNNING; 8007990: 2302 movs r3, #2 8007992: e004 b.n 800799e case MODE_RX: return RF_RX_RUNNING; 8007994: 2301 movs r3, #1 8007996: e002 b.n 800799e case MODE_CAD: return RF_CAD; 8007998: 2303 movs r3, #3 800799a: e000 b.n 800799e default: return RF_IDLE; 800799c: 2300 movs r3, #0 } } 800799e: 4618 mov r0, r3 80079a0: bd80 pop {r7, pc} ... 080079a4 : static void RadioSetModem( RadioModems_t modem ) { 80079a4: b580 push {r7, lr} 80079a6: b082 sub sp, #8 80079a8: af00 add r7, sp, #0 80079aa: 4603 mov r3, r0 80079ac: 71fb strb r3, [r7, #7] SubgRf.Modem = modem; 80079ae: 4a2a ldr r2, [pc, #168] @ (8007a58 ) 80079b0: 79fb ldrb r3, [r7, #7] 80079b2: 7013 strb r3, [r2, #0] RFW_SetRadioModem( modem ); 80079b4: 79fb ldrb r3, [r7, #7] 80079b6: 4618 mov r0, r3 80079b8: f003 fd82 bl 800b4c0 switch( modem ) 80079bc: 79fb ldrb r3, [r7, #7] 80079be: 2b05 cmp r3, #5 80079c0: d80e bhi.n 80079e0 80079c2: a201 add r2, pc, #4 @ (adr r2, 80079c8 ) 80079c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80079c8: 080079ef .word 0x080079ef 80079cc: 080079fd .word 0x080079fd 80079d0: 080079e1 .word 0x080079e1 80079d4: 08007a23 .word 0x08007a23 80079d8: 08007a31 .word 0x08007a31 80079dc: 08007a3f .word 0x08007a3f { default: case MODEM_MSK: SUBGRF_SetPacketType( PACKET_TYPE_GMSK ); 80079e0: 2003 movs r0, #3 80079e2: f002 fb8b bl 800a0fc // When switching to GFSK mode the LoRa SyncWord register value is reset // Thus, we also reset the RadioPublicNetwork variable SubgRf.PublicNetwork.Current = false; 80079e6: 4b1c ldr r3, [pc, #112] @ (8007a58 ) 80079e8: 2200 movs r2, #0 80079ea: 735a strb r2, [r3, #13] break; 80079ec: e02f b.n 8007a4e case MODEM_FSK: SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); 80079ee: 2000 movs r0, #0 80079f0: f002 fb84 bl 800a0fc // When switching to GFSK mode the LoRa SyncWord register value is reset // Thus, we also reset the RadioPublicNetwork variable SubgRf.PublicNetwork.Current = false; 80079f4: 4b18 ldr r3, [pc, #96] @ (8007a58 ) 80079f6: 2200 movs r2, #0 80079f8: 735a strb r2, [r3, #13] break; 80079fa: e028 b.n 8007a4e case MODEM_LORA: SUBGRF_SetPacketType( PACKET_TYPE_LORA ); 80079fc: 2001 movs r0, #1 80079fe: f002 fb7d bl 800a0fc // Public/Private network register is reset when switching modems if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous ) 8007a02: 4b15 ldr r3, [pc, #84] @ (8007a58 ) 8007a04: 7b5a ldrb r2, [r3, #13] 8007a06: 4b14 ldr r3, [pc, #80] @ (8007a58 ) 8007a08: 7b1b ldrb r3, [r3, #12] 8007a0a: 429a cmp r2, r3 8007a0c: d01e beq.n 8007a4c { SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous; 8007a0e: 4b12 ldr r3, [pc, #72] @ (8007a58 ) 8007a10: 7b1a ldrb r2, [r3, #12] 8007a12: 4b11 ldr r3, [pc, #68] @ (8007a58 ) 8007a14: 735a strb r2, [r3, #13] RadioSetPublicNetwork( SubgRf.PublicNetwork.Current ); 8007a16: 4b10 ldr r3, [pc, #64] @ (8007a58 ) 8007a18: 7b5b ldrb r3, [r3, #13] 8007a1a: 4618 mov r0, r3 8007a1c: f000 ffb2 bl 8008984 } break; 8007a20: e014 b.n 8007a4c case MODEM_BPSK: SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); 8007a22: 2002 movs r0, #2 8007a24: f002 fb6a bl 800a0fc // When switching to BPSK mode the LoRa SyncWord register value is reset // Thus, we also reset the RadioPublicNetwork variable SubgRf.PublicNetwork.Current = false; 8007a28: 4b0b ldr r3, [pc, #44] @ (8007a58 ) 8007a2a: 2200 movs r2, #0 8007a2c: 735a strb r2, [r3, #13] break; 8007a2e: e00e b.n 8007a4e #if (RADIO_SIGFOX_ENABLE == 1) case MODEM_SIGFOX_TX: SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); 8007a30: 2002 movs r0, #2 8007a32: f002 fb63 bl 800a0fc // When switching to BPSK mode the LoRa SyncWord register value is reset // Thus, we also reset the RadioPublicNetwork variable SubgRf.PublicNetwork.Current = false; 8007a36: 4b08 ldr r3, [pc, #32] @ (8007a58 ) 8007a38: 2200 movs r2, #0 8007a3a: 735a strb r2, [r3, #13] break; 8007a3c: e007 b.n 8007a4e case MODEM_SIGFOX_RX: SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); 8007a3e: 2000 movs r0, #0 8007a40: f002 fb5c bl 800a0fc // When switching to GFSK mode the LoRa SyncWord register value is reset // Thus, we also reset the RadioPublicNetwork variable SubgRf.PublicNetwork.Current = false; 8007a44: 4b04 ldr r3, [pc, #16] @ (8007a58 ) 8007a46: 2200 movs r2, #0 8007a48: 735a strb r2, [r3, #13] break; 8007a4a: e000 b.n 8007a4e break; 8007a4c: bf00 nop #endif /*RADIO_SIGFOX_ENABLE == 1*/ } } 8007a4e: bf00 nop 8007a50: 3708 adds r7, #8 8007a52: 46bd mov sp, r7 8007a54: bd80 pop {r7, pc} 8007a56: bf00 nop 8007a58: 20000300 .word 0x20000300 08007a5c : static void RadioSetChannel( uint32_t freq ) { 8007a5c: b580 push {r7, lr} 8007a5e: b082 sub sp, #8 8007a60: af00 add r7, sp, #0 8007a62: 6078 str r0, [r7, #4] SUBGRF_SetRfFrequency( freq ); 8007a64: 6878 ldr r0, [r7, #4] 8007a66: f002 fb03 bl 800a070 } 8007a6a: bf00 nop 8007a6c: 3708 adds r7, #8 8007a6e: 46bd mov sp, r7 8007a70: bd80 pop {r7, pc} 08007a72 : static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) { 8007a72: b580 push {r7, lr} 8007a74: b090 sub sp, #64 @ 0x40 8007a76: af0a add r7, sp, #40 @ 0x28 8007a78: 60f8 str r0, [r7, #12] 8007a7a: 60b9 str r1, [r7, #8] 8007a7c: 603b str r3, [r7, #0] 8007a7e: 4613 mov r3, r2 8007a80: 80fb strh r3, [r7, #6] bool status = true; 8007a82: 2301 movs r3, #1 8007a84: 75fb strb r3, [r7, #23] int16_t rssi = 0; 8007a86: 2300 movs r3, #0 8007a88: 82bb strh r3, [r7, #20] uint32_t carrierSenseTime = 0; 8007a8a: 2300 movs r3, #0 8007a8c: 613b str r3, [r7, #16] RadioStandby( ); 8007a8e: f000 fdf8 bl 8008682 RadioSetModem( MODEM_FSK ); 8007a92: 2000 movs r0, #0 8007a94: f7ff ff86 bl 80079a4 RadioSetChannel( freq ); 8007a98: 68f8 ldr r0, [r7, #12] 8007a9a: f7ff ffdf bl 8007a5c // Set Rx bandwidth. Other parameters are not used. RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false, 8007a9e: 2301 movs r3, #1 8007aa0: 9309 str r3, [sp, #36] @ 0x24 8007aa2: 2300 movs r3, #0 8007aa4: 9308 str r3, [sp, #32] 8007aa6: 2300 movs r3, #0 8007aa8: 9307 str r3, [sp, #28] 8007aaa: 2300 movs r3, #0 8007aac: 9306 str r3, [sp, #24] 8007aae: 2300 movs r3, #0 8007ab0: 9305 str r3, [sp, #20] 8007ab2: 2300 movs r3, #0 8007ab4: 9304 str r3, [sp, #16] 8007ab6: 2300 movs r3, #0 8007ab8: 9303 str r3, [sp, #12] 8007aba: 2300 movs r3, #0 8007abc: 9302 str r3, [sp, #8] 8007abe: 2303 movs r3, #3 8007ac0: 9301 str r3, [sp, #4] 8007ac2: 68bb ldr r3, [r7, #8] 8007ac4: 9300 str r3, [sp, #0] 8007ac6: 2300 movs r3, #0 8007ac8: f44f 7216 mov.w r2, #600 @ 0x258 8007acc: 68b9 ldr r1, [r7, #8] 8007ace: 2000 movs r0, #0 8007ad0: f000 f83c bl 8007b4c 0, false, 0, 0, false, true ); RadioRx( 0 ); 8007ad4: 2000 movs r0, #0 8007ad6: f000 fddb bl 8008690 RADIO_DELAY_MS( RadioGetWakeupTime( ) ); 8007ada: f000 ff81 bl 80089e0 8007ade: 4603 mov r3, r0 8007ae0: 4618 mov r0, r3 8007ae2: f7f9 f8c5 bl 8000c70 carrierSenseTime = TimerGetCurrentTime( ); 8007ae6: f006 f9c1 bl 800de6c 8007aea: 6138 str r0, [r7, #16] // Perform carrier sense for maxCarrierSenseTime while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) 8007aec: e00d b.n 8007b0a { rssi = RadioRssi( MODEM_FSK ); 8007aee: 2000 movs r0, #0 8007af0: f000 fec8 bl 8008884 8007af4: 4603 mov r3, r0 8007af6: 82bb strh r3, [r7, #20] if( rssi > rssiThresh ) 8007af8: f9b7 2014 ldrsh.w r2, [r7, #20] 8007afc: f9b7 3006 ldrsh.w r3, [r7, #6] 8007b00: 429a cmp r2, r3 8007b02: dd02 ble.n 8007b0a { status = false; 8007b04: 2300 movs r3, #0 8007b06: 75fb strb r3, [r7, #23] break; 8007b08: e006 b.n 8007b18 while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) 8007b0a: 6938 ldr r0, [r7, #16] 8007b0c: f006 f9c0 bl 800de90 8007b10: 4602 mov r2, r0 8007b12: 683b ldr r3, [r7, #0] 8007b14: 4293 cmp r3, r2 8007b16: d8ea bhi.n 8007aee } } RadioStandby( ); 8007b18: f000 fdb3 bl 8008682 return status; 8007b1c: 7dfb ldrb r3, [r7, #23] } 8007b1e: 4618 mov r0, r3 8007b20: 3718 adds r7, #24 8007b22: 46bd mov sp, r7 8007b24: bd80 pop {r7, pc} 08007b26 : static uint32_t RadioRandom( void ) { 8007b26: b580 push {r7, lr} 8007b28: b082 sub sp, #8 8007b2a: af00 add r7, sp, #0 uint32_t rnd = 0; 8007b2c: 2300 movs r3, #0 8007b2e: 607b str r3, [r7, #4] /* * Radio setup for random number generation */ // Disable modem interrupts SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); 8007b30: 2300 movs r3, #0 8007b32: 2200 movs r2, #0 8007b34: 2100 movs r1, #0 8007b36: 2000 movs r0, #0 8007b38: f002 fa3e bl 8009fb8 rnd = SUBGRF_GetRandom(); 8007b3c: f001 ffe7 bl 8009b0e 8007b40: 6078 str r0, [r7, #4] return rnd; 8007b42: 687b ldr r3, [r7, #4] } 8007b44: 4618 mov r0, r3 8007b46: 3708 adds r7, #8 8007b48: 46bd mov sp, r7 8007b4a: bd80 pop {r7, pc} 08007b4c : uint32_t bandwidthAfc, uint16_t preambleLen, uint16_t symbTimeout, bool fixLen, uint8_t payloadLen, bool crcOn, bool freqHopOn, uint8_t hopPeriod, bool iqInverted, bool rxContinuous ) { 8007b4c: b580 push {r7, lr} 8007b4e: b08a sub sp, #40 @ 0x28 8007b50: af00 add r7, sp, #0 8007b52: 60b9 str r1, [r7, #8] 8007b54: 607a str r2, [r7, #4] 8007b56: 461a mov r2, r3 8007b58: 4603 mov r3, r0 8007b5a: 73fb strb r3, [r7, #15] 8007b5c: 4613 mov r3, r2 8007b5e: 73bb strb r3, [r7, #14] #if (RADIO_SIGFOX_ENABLE == 1) uint8_t modReg; #endif SubgRf.RxContinuous = rxContinuous; 8007b60: 4ab9 ldr r2, [pc, #740] @ (8007e48 ) 8007b62: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 8007b66: 7053 strb r3, [r2, #1] RFW_DeInit(); 8007b68: f003 fb40 bl 800b1ec if( rxContinuous == true ) 8007b6c: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 8007b70: 2b00 cmp r3, #0 8007b72: d001 beq.n 8007b78 { symbTimeout = 0; 8007b74: 2300 movs r3, #0 8007b76: 873b strh r3, [r7, #56] @ 0x38 } if( fixLen == true ) 8007b78: f897 303c ldrb.w r3, [r7, #60] @ 0x3c 8007b7c: 2b00 cmp r3, #0 8007b7e: d004 beq.n 8007b8a { MaxPayloadLength = payloadLen; 8007b80: 4ab2 ldr r2, [pc, #712] @ (8007e4c ) 8007b82: f897 3040 ldrb.w r3, [r7, #64] @ 0x40 8007b86: 7013 strb r3, [r2, #0] 8007b88: e002 b.n 8007b90 } else { MaxPayloadLength = 0xFF; 8007b8a: 4bb0 ldr r3, [pc, #704] @ (8007e4c ) 8007b8c: 22ff movs r2, #255 @ 0xff 8007b8e: 701a strb r2, [r3, #0] } switch( modem ) 8007b90: 7bfb ldrb r3, [r7, #15] 8007b92: 2b05 cmp r3, #5 8007b94: d009 beq.n 8007baa 8007b96: 2b05 cmp r3, #5 8007b98: f300 81d7 bgt.w 8007f4a 8007b9c: 2b00 cmp r3, #0 8007b9e: f000 80bf beq.w 8007d20 8007ba2: 2b01 cmp r3, #1 8007ba4: f000 8124 beq.w 8007df0 // Timeout Max, Timeout handled directly in SetRx function SubgRf.RxTimeout = 0xFFFF; break; default: break; 8007ba8: e1cf b.n 8007f4a SUBGRF_SetStopRxTimerOnPreambleDetect( true ); 8007baa: 2001 movs r0, #1 8007bac: f002 f8f6 bl 8009d9c SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 8007bb0: 4ba5 ldr r3, [pc, #660] @ (8007e48 ) 8007bb2: 2200 movs r2, #0 8007bb4: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; 8007bb8: 4aa3 ldr r2, [pc, #652] @ (8007e48 ) 8007bba: 687b ldr r3, [r7, #4] 8007bbc: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05; 8007bbe: 4ba2 ldr r3, [pc, #648] @ (8007e48 ) 8007bc0: 2209 movs r2, #9 8007bc2: f883 2044 strb.w r2, [r3, #68] @ 0x44 SubgRf.ModulationParams.Params.Gfsk.Fdev = 800; 8007bc6: 4ba0 ldr r3, [pc, #640] @ (8007e48 ) 8007bc8: f44f 7248 mov.w r2, #800 @ 0x320 8007bcc: 641a str r2, [r3, #64] @ 0x40 SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); 8007bce: 68b8 ldr r0, [r7, #8] 8007bd0: f002 ffd0 bl 800ab74 8007bd4: 4603 mov r3, r0 8007bd6: 461a mov r2, r3 8007bd8: 4b9b ldr r3, [pc, #620] @ (8007e48 ) 8007bda: f883 2045 strb.w r2, [r3, #69] @ 0x45 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 8007bde: 4b9a ldr r3, [pc, #616] @ (8007e48 ) 8007be0: 2200 movs r2, #0 8007be2: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit 8007be4: 8ebb ldrh r3, [r7, #52] @ 0x34 8007be6: 00db lsls r3, r3, #3 8007be8: b29a uxth r2, r3 8007bea: 4b97 ldr r3, [pc, #604] @ (8007e48 ) 8007bec: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF; 8007bee: 4b96 ldr r3, [pc, #600] @ (8007e48 ) 8007bf0: 2200 movs r2, #0 8007bf2: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit 8007bf4: 4b94 ldr r3, [pc, #592] @ (8007e48 ) 8007bf6: 2210 movs r2, #16 8007bf8: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; 8007bfa: 4b93 ldr r3, [pc, #588] @ (8007e48 ) 8007bfc: 2200 movs r2, #0 8007bfe: 751a strb r2, [r3, #20] SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH; 8007c00: 4b91 ldr r3, [pc, #580] @ (8007e48 ) 8007c02: 2200 movs r2, #0 8007c04: 755a strb r2, [r3, #21] SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; 8007c06: 4b91 ldr r3, [pc, #580] @ (8007e4c ) 8007c08: 781a ldrb r2, [r3, #0] 8007c0a: 4b8f ldr r3, [pc, #572] @ (8007e48 ) 8007c0c: 759a strb r2, [r3, #22] SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; 8007c0e: 4b8e ldr r3, [pc, #568] @ (8007e48 ) 8007c10: 2201 movs r2, #1 8007c12: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF; 8007c14: 4b8c ldr r3, [pc, #560] @ (8007e48 ) 8007c16: 2200 movs r2, #0 8007c18: 761a strb r2, [r3, #24] RadioSetModem( MODEM_SIGFOX_RX ); 8007c1a: 2005 movs r0, #5 8007c1c: f7ff fec2 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8007c20: 488b ldr r0, [pc, #556] @ (8007e50 ) 8007c22: f002 fb5f bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8007c26: 488b ldr r0, [pc, #556] @ (8007e54 ) 8007c28: f002 fc2a bl 800a480 SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } ); 8007c2c: 4a8a ldr r2, [pc, #552] @ (8007e58 ) 8007c2e: f107 031c add.w r3, r7, #28 8007c32: e892 0003 ldmia.w r2, {r0, r1} 8007c36: e883 0003 stmia.w r3, {r0, r1} 8007c3a: f107 031c add.w r3, r7, #28 8007c3e: 4618 mov r0, r3 8007c40: f001 fee3 bl 8009a0a SUBGRF_SetWhiteningSeed( 0x01FF ); 8007c44: f240 10ff movw r0, #511 @ 0x1ff 8007c48: f001 ff2e bl 8009aa8 modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR); 8007c4c: f640 00b8 movw r0, #2232 @ 0x8b8 8007c50: f000 fe36 bl 80088c0 8007c54: 4603 mov r3, r0 8007c56: f887 3027 strb.w r3, [r7, #39] @ 0x27 modReg&=RADIO_BIT_MASK(4); 8007c5a: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007c5e: f023 0310 bic.w r3, r3, #16 8007c62: f887 3027 strb.w r3, [r7, #39] @ 0x27 RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg); 8007c66: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007c6a: 4619 mov r1, r3 8007c6c: f640 00b8 movw r0, #2232 @ 0x8b8 8007c70: f000 fe14 bl 800889c RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 ); 8007c74: 2104 movs r1, #4 8007c76: f640 00b9 movw r0, #2233 @ 0x8b9 8007c7a: f000 fe0f bl 800889c modReg= RadioRead(SUBGHZ_AGCRSSICTL0R); 8007c7e: f640 009b movw r0, #2203 @ 0x89b 8007c82: f000 fe1d bl 80088c0 8007c86: 4603 mov r3, r0 8007c88: f887 3027 strb.w r3, [r7, #39] @ 0x27 modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); 8007c8c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007c90: f023 031c bic.w r3, r3, #28 8007c94: f887 3027 strb.w r3, [r7, #39] @ 0x27 RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) ); 8007c98: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007c9c: f043 0308 orr.w r3, r3, #8 8007ca0: b2db uxtb r3, r3 8007ca2: 4619 mov r1, r3 8007ca4: f640 009b movw r0, #2203 @ 0x89b 8007ca8: f000 fdf8 bl 800889c modReg= RadioRead(SUBGHZ_GAFCR); 8007cac: f240 60d1 movw r0, #1745 @ 0x6d1 8007cb0: f000 fe06 bl 80088c0 8007cb4: 4603 mov r3, r0 8007cb6: f887 3027 strb.w r3, [r7, #39] @ 0x27 modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); 8007cba: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007cbe: f023 0318 bic.w r3, r3, #24 8007cc2: f887 3027 strb.w r3, [r7, #39] @ 0x27 RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) )); 8007cc6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007cca: f043 0318 orr.w r3, r3, #24 8007cce: b2db uxtb r3, r3 8007cd0: 4619 mov r1, r3 8007cd2: f240 60d1 movw r0, #1745 @ 0x6d1 8007cd6: f000 fde1 bl 800889c modReg= RadioRead(SUBGHZ_GBSYNCR); 8007cda: f240 60ac movw r0, #1708 @ 0x6ac 8007cde: f000 fdef bl 80088c0 8007ce2: 4603 mov r3, r0 8007ce4: f887 3027 strb.w r3, [r7, #39] @ 0x27 modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) ); 8007ce8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007cec: f023 0370 bic.w r3, r3, #112 @ 0x70 8007cf0: f887 3027 strb.w r3, [r7, #39] @ 0x27 RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) )); 8007cf4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007cf8: f043 0350 orr.w r3, r3, #80 @ 0x50 8007cfc: b2db uxtb r3, r3 8007cfe: 4619 mov r1, r3 8007d00: f240 60ac movw r0, #1708 @ 0x6ac 8007d04: f000 fdca bl 800889c SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); 8007d08: 8f3b ldrh r3, [r7, #56] @ 0x38 8007d0a: f44f 52fa mov.w r2, #8000 @ 0x1f40 8007d0e: fb02 f303 mul.w r3, r2, r3 8007d12: 461a mov r2, r3 8007d14: 687b ldr r3, [r7, #4] 8007d16: fbb2 f3f3 udiv r3, r2, r3 8007d1a: 4a4b ldr r2, [pc, #300] @ (8007e48 ) 8007d1c: 6093 str r3, [r2, #8] break; 8007d1e: e115 b.n 8007f4c SUBGRF_SetStopRxTimerOnPreambleDetect( false ); 8007d20: 2000 movs r0, #0 8007d22: f002 f83b bl 8009d9c SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 8007d26: 4b48 ldr r3, [pc, #288] @ (8007e48 ) 8007d28: 2200 movs r2, #0 8007d2a: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; 8007d2e: 4a46 ldr r2, [pc, #280] @ (8007e48 ) 8007d30: 687b ldr r3, [r7, #4] 8007d32: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; 8007d34: 4b44 ldr r3, [pc, #272] @ (8007e48 ) 8007d36: 220b movs r2, #11 8007d38: f883 2044 strb.w r2, [r3, #68] @ 0x44 SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); 8007d3c: 68b8 ldr r0, [r7, #8] 8007d3e: f002 ff19 bl 800ab74 8007d42: 4603 mov r3, r0 8007d44: 461a mov r2, r3 8007d46: 4b40 ldr r3, [pc, #256] @ (8007e48 ) 8007d48: f883 2045 strb.w r2, [r3, #69] @ 0x45 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 8007d4c: 4b3e ldr r3, [pc, #248] @ (8007e48 ) 8007d4e: 2200 movs r2, #0 8007d50: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit 8007d52: 8ebb ldrh r3, [r7, #52] @ 0x34 8007d54: 00db lsls r3, r3, #3 8007d56: b29a uxth r2, r3 8007d58: 4b3b ldr r3, [pc, #236] @ (8007e48 ) 8007d5a: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; 8007d5c: 4b3a ldr r3, [pc, #232] @ (8007e48 ) 8007d5e: 2204 movs r2, #4 8007d60: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit 8007d62: 4b39 ldr r3, [pc, #228] @ (8007e48 ) 8007d64: 2218 movs r2, #24 8007d66: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; 8007d68: 4b37 ldr r3, [pc, #220] @ (8007e48 ) 8007d6a: 2200 movs r2, #0 8007d6c: 751a strb r2, [r3, #20] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; 8007d6e: f897 303c ldrb.w r3, [r7, #60] @ 0x3c 8007d72: f083 0301 eor.w r3, r3, #1 8007d76: b2db uxtb r3, r3 8007d78: 461a mov r2, r3 8007d7a: 4b33 ldr r3, [pc, #204] @ (8007e48 ) 8007d7c: 755a strb r2, [r3, #21] SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; 8007d7e: 4b33 ldr r3, [pc, #204] @ (8007e4c ) 8007d80: 781a ldrb r2, [r3, #0] 8007d82: 4b31 ldr r3, [pc, #196] @ (8007e48 ) 8007d84: 759a strb r2, [r3, #22] if( crcOn == true ) 8007d86: f897 3044 ldrb.w r3, [r7, #68] @ 0x44 8007d8a: 2b00 cmp r3, #0 8007d8c: d003 beq.n 8007d96 SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; 8007d8e: 4b2e ldr r3, [pc, #184] @ (8007e48 ) 8007d90: 22f2 movs r2, #242 @ 0xf2 8007d92: 75da strb r2, [r3, #23] 8007d94: e002 b.n 8007d9c SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; 8007d96: 4b2c ldr r3, [pc, #176] @ (8007e48 ) 8007d98: 2201 movs r2, #1 8007d9a: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; 8007d9c: 4b2a ldr r3, [pc, #168] @ (8007e48 ) 8007d9e: 2201 movs r2, #1 8007da0: 761a strb r2, [r3, #24] RadioStandby( ); 8007da2: f000 fc6e bl 8008682 RadioSetModem( MODEM_FSK ); 8007da6: 2000 movs r0, #0 8007da8: f7ff fdfc bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8007dac: 4828 ldr r0, [pc, #160] @ (8007e50 ) 8007dae: f002 fa99 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8007db2: 4828 ldr r0, [pc, #160] @ (8007e54 ) 8007db4: f002 fb64 bl 800a480 SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); 8007db8: 4a28 ldr r2, [pc, #160] @ (8007e5c ) 8007dba: f107 0314 add.w r3, r7, #20 8007dbe: e892 0003 ldmia.w r2, {r0, r1} 8007dc2: e883 0003 stmia.w r3, {r0, r1} 8007dc6: f107 0314 add.w r3, r7, #20 8007dca: 4618 mov r0, r3 8007dcc: f001 fe1d bl 8009a0a SUBGRF_SetWhiteningSeed( 0x01FF ); 8007dd0: f240 10ff movw r0, #511 @ 0x1ff 8007dd4: f001 fe68 bl 8009aa8 SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); 8007dd8: 8f3b ldrh r3, [r7, #56] @ 0x38 8007dda: f44f 52fa mov.w r2, #8000 @ 0x1f40 8007dde: fb02 f303 mul.w r3, r2, r3 8007de2: 461a mov r2, r3 8007de4: 687b ldr r3, [r7, #4] 8007de6: fbb2 f3f3 udiv r3, r2, r3 8007dea: 4a17 ldr r2, [pc, #92] @ (8007e48 ) 8007dec: 6093 str r3, [r2, #8] break; 8007dee: e0ad b.n 8007f4c SUBGRF_SetStopRxTimerOnPreambleDetect( false ); 8007df0: 2000 movs r0, #0 8007df2: f001 ffd3 bl 8009d9c SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; 8007df6: 4b14 ldr r3, [pc, #80] @ (8007e48 ) 8007df8: 2201 movs r2, #1 8007dfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; 8007dfe: 687b ldr r3, [r7, #4] 8007e00: b2da uxtb r2, r3 8007e02: 4b11 ldr r3, [pc, #68] @ (8007e48 ) 8007e04: f883 2050 strb.w r2, [r3, #80] @ 0x50 SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; 8007e08: 4a15 ldr r2, [pc, #84] @ (8007e60 ) 8007e0a: 68bb ldr r3, [r7, #8] 8007e0c: 4413 add r3, r2 8007e0e: 781a ldrb r2, [r3, #0] 8007e10: 4b0d ldr r3, [pc, #52] @ (8007e48 ) 8007e12: f883 2051 strb.w r2, [r3, #81] @ 0x51 SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; 8007e16: 4a0c ldr r2, [pc, #48] @ (8007e48 ) 8007e18: 7bbb ldrb r3, [r7, #14] 8007e1a: f882 3052 strb.w r3, [r2, #82] @ 0x52 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 8007e1e: 68bb ldr r3, [r7, #8] 8007e20: 2b00 cmp r3, #0 8007e22: d105 bne.n 8007e30 8007e24: 687b ldr r3, [r7, #4] 8007e26: 2b0b cmp r3, #11 8007e28: d008 beq.n 8007e3c 8007e2a: 687b ldr r3, [r7, #4] 8007e2c: 2b0c cmp r3, #12 8007e2e: d005 beq.n 8007e3c 8007e30: 68bb ldr r3, [r7, #8] 8007e32: 2b01 cmp r3, #1 8007e34: d116 bne.n 8007e64 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) 8007e36: 687b ldr r3, [r7, #4] 8007e38: 2b0c cmp r3, #12 8007e3a: d113 bne.n 8007e64 SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; 8007e3c: 4b02 ldr r3, [pc, #8] @ (8007e48 ) 8007e3e: 2201 movs r2, #1 8007e40: f883 2053 strb.w r2, [r3, #83] @ 0x53 8007e44: e012 b.n 8007e6c 8007e46: bf00 nop 8007e48: 20000300 .word 0x20000300 8007e4c: 20000008 .word 0x20000008 8007e50: 20000338 .word 0x20000338 8007e54: 2000030e .word 0x2000030e 8007e58: 0800f0e8 .word 0x0800f0e8 8007e5c: 0800f0f0 .word 0x0800f0f0 8007e60: 0800fc08 .word 0x0800fc08 SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; 8007e64: 4b3b ldr r3, [pc, #236] @ (8007f54 ) 8007e66: 2200 movs r2, #0 8007e68: f883 2053 strb.w r2, [r3, #83] @ 0x53 SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; 8007e6c: 4b39 ldr r3, [pc, #228] @ (8007f54 ) 8007e6e: 2201 movs r2, #1 8007e70: 739a strb r2, [r3, #14] if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || 8007e72: 4b38 ldr r3, [pc, #224] @ (8007f54 ) 8007e74: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007e78: 2b05 cmp r3, #5 8007e7a: d004 beq.n 8007e86 ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) 8007e7c: 4b35 ldr r3, [pc, #212] @ (8007f54 ) 8007e7e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || 8007e82: 2b06 cmp r3, #6 8007e84: d10a bne.n 8007e9c if( preambleLen < 12 ) 8007e86: 8ebb ldrh r3, [r7, #52] @ 0x34 8007e88: 2b0b cmp r3, #11 8007e8a: d803 bhi.n 8007e94 SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; 8007e8c: 4b31 ldr r3, [pc, #196] @ (8007f54 ) 8007e8e: 220c movs r2, #12 8007e90: 839a strh r2, [r3, #28] if( preambleLen < 12 ) 8007e92: e006 b.n 8007ea2 SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; 8007e94: 4a2f ldr r2, [pc, #188] @ (8007f54 ) 8007e96: 8ebb ldrh r3, [r7, #52] @ 0x34 8007e98: 8393 strh r3, [r2, #28] if( preambleLen < 12 ) 8007e9a: e002 b.n 8007ea2 SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; 8007e9c: 4a2d ldr r2, [pc, #180] @ (8007f54 ) 8007e9e: 8ebb ldrh r3, [r7, #52] @ 0x34 8007ea0: 8393 strh r3, [r2, #28] SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; 8007ea2: f897 203c ldrb.w r2, [r7, #60] @ 0x3c 8007ea6: 4b2b ldr r3, [pc, #172] @ (8007f54 ) 8007ea8: 779a strb r2, [r3, #30] SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; 8007eaa: 4b2b ldr r3, [pc, #172] @ (8007f58 ) 8007eac: 781a ldrb r2, [r3, #0] 8007eae: 4b29 ldr r3, [pc, #164] @ (8007f54 ) 8007eb0: 77da strb r2, [r3, #31] SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; 8007eb2: f897 2044 ldrb.w r2, [r7, #68] @ 0x44 8007eb6: 4b27 ldr r3, [pc, #156] @ (8007f54 ) 8007eb8: f883 2020 strb.w r2, [r3, #32] SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; 8007ebc: f897 2050 ldrb.w r2, [r7, #80] @ 0x50 8007ec0: 4b24 ldr r3, [pc, #144] @ (8007f54 ) 8007ec2: f883 2021 strb.w r2, [r3, #33] @ 0x21 RadioStandby( ); 8007ec6: f000 fbdc bl 8008682 RadioSetModem( MODEM_LORA ); 8007eca: 2001 movs r0, #1 8007ecc: f7ff fd6a bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8007ed0: 4822 ldr r0, [pc, #136] @ (8007f5c ) 8007ed2: f002 fa07 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8007ed6: 4822 ldr r0, [pc, #136] @ (8007f60 ) 8007ed8: f002 fad2 bl 800a480 SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); 8007edc: 8f3b ldrh r3, [r7, #56] @ 0x38 8007ede: b2db uxtb r3, r3 8007ee0: 4618 mov r0, r3 8007ee2: f001 ff6a bl 8009dba SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1); 8007ee6: f640 00a3 movw r0, #2211 @ 0x8a3 8007eea: f002 fc31 bl 800a750 8007eee: 4603 mov r3, r0 8007ef0: f003 0301 and.w r3, r3, #1 8007ef4: b2db uxtb r3, r3 8007ef6: 4619 mov r1, r3 8007ef8: f640 00a3 movw r0, #2211 @ 0x8a3 8007efc: f002 fc06 bl 800a70c if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) 8007f00: 4b14 ldr r3, [pc, #80] @ (8007f54 ) 8007f02: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8007f06: 2b01 cmp r3, #1 8007f08: d10d bne.n 8007f26 SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); 8007f0a: f240 7036 movw r0, #1846 @ 0x736 8007f0e: f002 fc1f bl 800a750 8007f12: 4603 mov r3, r0 8007f14: f023 0304 bic.w r3, r3, #4 8007f18: b2db uxtb r3, r3 8007f1a: 4619 mov r1, r3 8007f1c: f240 7036 movw r0, #1846 @ 0x736 8007f20: f002 fbf4 bl 800a70c 8007f24: e00c b.n 8007f40 SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); 8007f26: f240 7036 movw r0, #1846 @ 0x736 8007f2a: f002 fc11 bl 800a750 8007f2e: 4603 mov r3, r0 8007f30: f043 0304 orr.w r3, r3, #4 8007f34: b2db uxtb r3, r3 8007f36: 4619 mov r1, r3 8007f38: f240 7036 movw r0, #1846 @ 0x736 8007f3c: f002 fbe6 bl 800a70c SubgRf.RxTimeout = 0xFFFF; 8007f40: 4b04 ldr r3, [pc, #16] @ (8007f54 ) 8007f42: f64f 72ff movw r2, #65535 @ 0xffff 8007f46: 609a str r2, [r3, #8] break; 8007f48: e000 b.n 8007f4c break; 8007f4a: bf00 nop } } 8007f4c: bf00 nop 8007f4e: 3728 adds r7, #40 @ 0x28 8007f50: 46bd mov sp, r7 8007f52: bd80 pop {r7, pc} 8007f54: 20000300 .word 0x20000300 8007f58: 20000008 .word 0x20000008 8007f5c: 20000338 .word 0x20000338 8007f60: 2000030e .word 0x2000030e 08007f64 : static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, uint32_t bandwidth, uint32_t datarate, uint8_t coderate, uint16_t preambleLen, bool fixLen, bool crcOn, bool freqHopOn, uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) { 8007f64: b580 push {r7, lr} 8007f66: b086 sub sp, #24 8007f68: af00 add r7, sp, #0 8007f6a: 60ba str r2, [r7, #8] 8007f6c: 607b str r3, [r7, #4] 8007f6e: 4603 mov r3, r0 8007f70: 73fb strb r3, [r7, #15] 8007f72: 460b mov r3, r1 8007f74: 73bb strb r3, [r7, #14] #if( RADIO_LR_FHSS_IS_ON == 1 ) /*disable LrFhss*/ SubgRf.lr_fhss.is_lr_fhss_on = false; #endif /* RADIO_LR_FHSS_IS_ON == 1 */ RFW_DeInit(); 8007f76: f003 f939 bl 800b1ec switch( modem ) 8007f7a: 7bfb ldrb r3, [r7, #15] 8007f7c: 2b04 cmp r3, #4 8007f7e: f000 80c7 beq.w 8008110 8007f82: 2b04 cmp r3, #4 8007f84: f300 80d6 bgt.w 8008134 8007f88: 2b00 cmp r3, #0 8007f8a: d002 beq.n 8007f92 8007f8c: 2b01 cmp r3, #1 8007f8e: d059 beq.n 8008044 SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); break; #endif /*RADIO_SIGFOX_ENABLE == 1*/ default: break; 8007f90: e0d0 b.n 8008134 SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 8007f92: 4b77 ldr r3, [pc, #476] @ (8008170 ) 8007f94: 2200 movs r2, #0 8007f96: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; 8007f9a: 4a75 ldr r2, [pc, #468] @ (8008170 ) 8007f9c: 6a3b ldr r3, [r7, #32] 8007f9e: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; 8007fa0: 4b73 ldr r3, [pc, #460] @ (8008170 ) 8007fa2: 220b movs r2, #11 8007fa4: f883 2044 strb.w r2, [r3, #68] @ 0x44 SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); 8007fa8: 6878 ldr r0, [r7, #4] 8007faa: f002 fde3 bl 800ab74 8007fae: 4603 mov r3, r0 8007fb0: 461a mov r2, r3 8007fb2: 4b6f ldr r3, [pc, #444] @ (8008170 ) 8007fb4: f883 2045 strb.w r2, [r3, #69] @ 0x45 SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev; 8007fb8: 4a6d ldr r2, [pc, #436] @ (8008170 ) 8007fba: 68bb ldr r3, [r7, #8] 8007fbc: 6413 str r3, [r2, #64] @ 0x40 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 8007fbe: 4b6c ldr r3, [pc, #432] @ (8008170 ) 8007fc0: 2200 movs r2, #0 8007fc2: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit 8007fc4: 8d3b ldrh r3, [r7, #40] @ 0x28 8007fc6: 00db lsls r3, r3, #3 8007fc8: b29a uxth r2, r3 8007fca: 4b69 ldr r3, [pc, #420] @ (8008170 ) 8007fcc: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; 8007fce: 4b68 ldr r3, [pc, #416] @ (8008170 ) 8007fd0: 2204 movs r2, #4 8007fd2: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit 8007fd4: 4b66 ldr r3, [pc, #408] @ (8008170 ) 8007fd6: 2218 movs r2, #24 8007fd8: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; 8007fda: 4b65 ldr r3, [pc, #404] @ (8008170 ) 8007fdc: 2200 movs r2, #0 8007fde: 751a strb r2, [r3, #20] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; 8007fe0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8007fe4: f083 0301 eor.w r3, r3, #1 8007fe8: b2db uxtb r3, r3 8007fea: 461a mov r2, r3 8007fec: 4b60 ldr r3, [pc, #384] @ (8008170 ) 8007fee: 755a strb r2, [r3, #21] if( crcOn == true ) 8007ff0: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8007ff4: 2b00 cmp r3, #0 8007ff6: d003 beq.n 8008000 SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; 8007ff8: 4b5d ldr r3, [pc, #372] @ (8008170 ) 8007ffa: 22f2 movs r2, #242 @ 0xf2 8007ffc: 75da strb r2, [r3, #23] 8007ffe: e002 b.n 8008006 SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; 8008000: 4b5b ldr r3, [pc, #364] @ (8008170 ) 8008002: 2201 movs r2, #1 8008004: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; 8008006: 4b5a ldr r3, [pc, #360] @ (8008170 ) 8008008: 2201 movs r2, #1 800800a: 761a strb r2, [r3, #24] RadioStandby( ); 800800c: f000 fb39 bl 8008682 RadioSetModem( MODEM_FSK ); 8008010: 2000 movs r0, #0 8008012: f7ff fcc7 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8008016: 4857 ldr r0, [pc, #348] @ (8008174 ) 8008018: f002 f964 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 800801c: 4856 ldr r0, [pc, #344] @ (8008178 ) 800801e: f002 fa2f bl 800a480 SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); 8008022: 4a56 ldr r2, [pc, #344] @ (800817c ) 8008024: f107 0310 add.w r3, r7, #16 8008028: e892 0003 ldmia.w r2, {r0, r1} 800802c: e883 0003 stmia.w r3, {r0, r1} 8008030: f107 0310 add.w r3, r7, #16 8008034: 4618 mov r0, r3 8008036: f001 fce8 bl 8009a0a SUBGRF_SetWhiteningSeed( 0x01FF ); 800803a: f240 10ff movw r0, #511 @ 0x1ff 800803e: f001 fd33 bl 8009aa8 break; 8008042: e078 b.n 8008136 SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; 8008044: 4b4a ldr r3, [pc, #296] @ (8008170 ) 8008046: 2201 movs r2, #1 8008048: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; 800804c: 6a3b ldr r3, [r7, #32] 800804e: b2da uxtb r2, r3 8008050: 4b47 ldr r3, [pc, #284] @ (8008170 ) 8008052: f883 2050 strb.w r2, [r3, #80] @ 0x50 SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; 8008056: 4a4a ldr r2, [pc, #296] @ (8008180 ) 8008058: 687b ldr r3, [r7, #4] 800805a: 4413 add r3, r2 800805c: 781a ldrb r2, [r3, #0] 800805e: 4b44 ldr r3, [pc, #272] @ (8008170 ) 8008060: f883 2051 strb.w r2, [r3, #81] @ 0x51 SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; 8008064: 4a42 ldr r2, [pc, #264] @ (8008170 ) 8008066: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 800806a: f882 3052 strb.w r3, [r2, #82] @ 0x52 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 800806e: 687b ldr r3, [r7, #4] 8008070: 2b00 cmp r3, #0 8008072: d105 bne.n 8008080 8008074: 6a3b ldr r3, [r7, #32] 8008076: 2b0b cmp r3, #11 8008078: d008 beq.n 800808c 800807a: 6a3b ldr r3, [r7, #32] 800807c: 2b0c cmp r3, #12 800807e: d005 beq.n 800808c 8008080: 687b ldr r3, [r7, #4] 8008082: 2b01 cmp r3, #1 8008084: d107 bne.n 8008096 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) 8008086: 6a3b ldr r3, [r7, #32] 8008088: 2b0c cmp r3, #12 800808a: d104 bne.n 8008096 SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; 800808c: 4b38 ldr r3, [pc, #224] @ (8008170 ) 800808e: 2201 movs r2, #1 8008090: f883 2053 strb.w r2, [r3, #83] @ 0x53 8008094: e003 b.n 800809e SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; 8008096: 4b36 ldr r3, [pc, #216] @ (8008170 ) 8008098: 2200 movs r2, #0 800809a: f883 2053 strb.w r2, [r3, #83] @ 0x53 SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; 800809e: 4b34 ldr r3, [pc, #208] @ (8008170 ) 80080a0: 2201 movs r2, #1 80080a2: 739a strb r2, [r3, #14] if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || 80080a4: 4b32 ldr r3, [pc, #200] @ (8008170 ) 80080a6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80080aa: 2b05 cmp r3, #5 80080ac: d004 beq.n 80080b8 ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) 80080ae: 4b30 ldr r3, [pc, #192] @ (8008170 ) 80080b0: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || 80080b4: 2b06 cmp r3, #6 80080b6: d10a bne.n 80080ce if( preambleLen < 12 ) 80080b8: 8d3b ldrh r3, [r7, #40] @ 0x28 80080ba: 2b0b cmp r3, #11 80080bc: d803 bhi.n 80080c6 SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; 80080be: 4b2c ldr r3, [pc, #176] @ (8008170 ) 80080c0: 220c movs r2, #12 80080c2: 839a strh r2, [r3, #28] if( preambleLen < 12 ) 80080c4: e006 b.n 80080d4 SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; 80080c6: 4a2a ldr r2, [pc, #168] @ (8008170 ) 80080c8: 8d3b ldrh r3, [r7, #40] @ 0x28 80080ca: 8393 strh r3, [r2, #28] if( preambleLen < 12 ) 80080cc: e002 b.n 80080d4 SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; 80080ce: 4a28 ldr r2, [pc, #160] @ (8008170 ) 80080d0: 8d3b ldrh r3, [r7, #40] @ 0x28 80080d2: 8393 strh r3, [r2, #28] SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; 80080d4: f897 202c ldrb.w r2, [r7, #44] @ 0x2c 80080d8: 4b25 ldr r3, [pc, #148] @ (8008170 ) 80080da: 779a strb r2, [r3, #30] SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; 80080dc: 4b29 ldr r3, [pc, #164] @ (8008184 ) 80080de: 781a ldrb r2, [r3, #0] 80080e0: 4b23 ldr r3, [pc, #140] @ (8008170 ) 80080e2: 77da strb r2, [r3, #31] SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; 80080e4: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 80080e8: 4b21 ldr r3, [pc, #132] @ (8008170 ) 80080ea: f883 2020 strb.w r2, [r3, #32] SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; 80080ee: f897 203c ldrb.w r2, [r7, #60] @ 0x3c 80080f2: 4b1f ldr r3, [pc, #124] @ (8008170 ) 80080f4: f883 2021 strb.w r2, [r3, #33] @ 0x21 RadioStandby( ); 80080f8: f000 fac3 bl 8008682 RadioSetModem( MODEM_LORA ); 80080fc: 2001 movs r0, #1 80080fe: f7ff fc51 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8008102: 481c ldr r0, [pc, #112] @ (8008174 ) 8008104: f002 f8ee bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8008108: 481b ldr r0, [pc, #108] @ (8008178 ) 800810a: f002 f9b9 bl 800a480 break; 800810e: e012 b.n 8008136 RadioSetModem(MODEM_SIGFOX_TX); 8008110: 2004 movs r0, #4 8008112: f7ff fc47 bl 80079a4 SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; 8008116: 4b16 ldr r3, [pc, #88] @ (8008170 ) 8008118: 2202 movs r2, #2 800811a: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate; 800811e: 4a14 ldr r2, [pc, #80] @ (8008170 ) 8008120: 6a3b ldr r3, [r7, #32] 8008122: 6493 str r3, [r2, #72] @ 0x48 SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; 8008124: 4b12 ldr r3, [pc, #72] @ (8008170 ) 8008126: 2216 movs r2, #22 8008128: f883 204c strb.w r2, [r3, #76] @ 0x4c SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 800812c: 4811 ldr r0, [pc, #68] @ (8008174 ) 800812e: f002 f8d9 bl 800a2e4 break; 8008132: e000 b.n 8008136 break; 8008134: bf00 nop } SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); 8008136: f997 300e ldrsb.w r3, [r7, #14] 800813a: 4618 mov r0, r3 800813c: f002 fc1c bl 800a978 8008140: 4603 mov r3, r0 8008142: 461a mov r2, r3 8008144: 4b0a ldr r3, [pc, #40] @ (8008170 ) 8008146: f883 2056 strb.w r2, [r3, #86] @ 0x56 /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); 800814a: 210e movs r1, #14 800814c: f640 101f movw r0, #2335 @ 0x91f 8008150: f002 fadc bl 800a70c RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); 8008154: 4b06 ldr r3, [pc, #24] @ (8008170 ) 8008156: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 800815a: 4618 mov r0, r3 800815c: f003 f866 bl 800b22c SubgRf.TxTimeout = timeout; 8008160: 4a03 ldr r2, [pc, #12] @ (8008170 ) 8008162: 6c3b ldr r3, [r7, #64] @ 0x40 8008164: 6053 str r3, [r2, #4] } 8008166: bf00 nop 8008168: 3718 adds r7, #24 800816a: 46bd mov sp, r7 800816c: bd80 pop {r7, pc} 800816e: bf00 nop 8008170: 20000300 .word 0x20000300 8008174: 20000338 .word 0x20000338 8008178: 2000030e .word 0x2000030e 800817c: 0800f0f0 .word 0x0800f0f0 8008180: 0800fc08 .word 0x0800fc08 8008184: 20000008 .word 0x20000008 08008188 : static bool RadioCheckRfFrequency( uint32_t frequency ) { 8008188: b480 push {r7} 800818a: b083 sub sp, #12 800818c: af00 add r7, sp, #0 800818e: 6078 str r0, [r7, #4] return true; 8008190: 2301 movs r3, #1 } 8008192: 4618 mov r0, r3 8008194: 370c adds r7, #12 8008196: 46bd mov sp, r7 8008198: bc80 pop {r7} 800819a: 4770 bx lr 0800819c : static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ) { 800819c: b480 push {r7} 800819e: b085 sub sp, #20 80081a0: af00 add r7, sp, #0 80081a2: 4603 mov r3, r0 80081a4: 71fb strb r3, [r7, #7] uint32_t bandwidthInHz = 0; 80081a6: 2300 movs r3, #0 80081a8: 60fb str r3, [r7, #12] switch( bw ) 80081aa: 79fb ldrb r3, [r7, #7] 80081ac: 2b0a cmp r3, #10 80081ae: d83e bhi.n 800822e 80081b0: a201 add r2, pc, #4 @ (adr r2, 80081b8 ) 80081b2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80081b6: bf00 nop 80081b8: 080081e5 .word 0x080081e5 80081bc: 080081f5 .word 0x080081f5 80081c0: 08008205 .word 0x08008205 80081c4: 08008215 .word 0x08008215 80081c8: 0800821d .word 0x0800821d 80081cc: 08008223 .word 0x08008223 80081d0: 08008229 .word 0x08008229 80081d4: 0800822f .word 0x0800822f 80081d8: 080081ed .word 0x080081ed 80081dc: 080081fd .word 0x080081fd 80081e0: 0800820d .word 0x0800820d { case LORA_BW_007: bandwidthInHz = 7812UL; 80081e4: f641 6384 movw r3, #7812 @ 0x1e84 80081e8: 60fb str r3, [r7, #12] break; 80081ea: e020 b.n 800822e case LORA_BW_010: bandwidthInHz = 10417UL; 80081ec: f642 03b1 movw r3, #10417 @ 0x28b1 80081f0: 60fb str r3, [r7, #12] break; 80081f2: e01c b.n 800822e case LORA_BW_015: bandwidthInHz = 15625UL; 80081f4: f643 5309 movw r3, #15625 @ 0x3d09 80081f8: 60fb str r3, [r7, #12] break; 80081fa: e018 b.n 800822e case LORA_BW_020: bandwidthInHz = 20833UL; 80081fc: f245 1361 movw r3, #20833 @ 0x5161 8008200: 60fb str r3, [r7, #12] break; 8008202: e014 b.n 800822e case LORA_BW_031: bandwidthInHz = 31250UL; 8008204: f647 2312 movw r3, #31250 @ 0x7a12 8008208: 60fb str r3, [r7, #12] break; 800820a: e010 b.n 800822e case LORA_BW_041: bandwidthInHz = 41667UL; 800820c: f24a 23c3 movw r3, #41667 @ 0xa2c3 8008210: 60fb str r3, [r7, #12] break; 8008212: e00c b.n 800822e case LORA_BW_062: bandwidthInHz = 62500UL; 8008214: f24f 4324 movw r3, #62500 @ 0xf424 8008218: 60fb str r3, [r7, #12] break; 800821a: e008 b.n 800822e case LORA_BW_125: bandwidthInHz = 125000UL; 800821c: 4b07 ldr r3, [pc, #28] @ (800823c ) 800821e: 60fb str r3, [r7, #12] break; 8008220: e005 b.n 800822e case LORA_BW_250: bandwidthInHz = 250000UL; 8008222: 4b07 ldr r3, [pc, #28] @ (8008240 ) 8008224: 60fb str r3, [r7, #12] break; 8008226: e002 b.n 800822e case LORA_BW_500: bandwidthInHz = 500000UL; 8008228: 4b06 ldr r3, [pc, #24] @ (8008244 ) 800822a: 60fb str r3, [r7, #12] break; 800822c: bf00 nop } return bandwidthInHz; 800822e: 68fb ldr r3, [r7, #12] } 8008230: 4618 mov r0, r3 8008232: 3714 adds r7, #20 8008234: 46bd mov sp, r7 8008236: bc80 pop {r7} 8008238: 4770 bx lr 800823a: bf00 nop 800823c: 0001e848 .word 0x0001e848 8008240: 0003d090 .word 0x0003d090 8008244: 0007a120 .word 0x0007a120 08008248 : static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, uint16_t preambleLen, bool fixLen, uint8_t payloadLen, bool crcOn ) { 8008248: b480 push {r7} 800824a: b083 sub sp, #12 800824c: af00 add r7, sp, #0 800824e: 6078 str r0, [r7, #4] 8008250: 4608 mov r0, r1 8008252: 4611 mov r1, r2 8008254: 461a mov r2, r3 8008256: 4603 mov r3, r0 8008258: 70fb strb r3, [r7, #3] 800825a: 460b mov r3, r1 800825c: 803b strh r3, [r7, #0] 800825e: 4613 mov r3, r2 8008260: 70bb strb r3, [r7, #2] return ( preambleLen << 3 ) + 8008262: 883b ldrh r3, [r7, #0] 8008264: 00db lsls r3, r3, #3 ( ( fixLen == false ) ? 8 : 0 ) + 24 + 8008266: 78ba ldrb r2, [r7, #2] 8008268: f082 0201 eor.w r2, r2, #1 800826c: b2d2 uxtb r2, r2 800826e: 2a00 cmp r2, #0 8008270: d001 beq.n 8008276 8008272: 2208 movs r2, #8 8008274: e000 b.n 8008278 8008276: 2200 movs r2, #0 return ( preambleLen << 3 ) + 8008278: 4413 add r3, r2 ( ( fixLen == false ) ? 8 : 0 ) + 24 + 800827a: f103 0218 add.w r2, r3, #24 ( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 ); 800827e: 7c3b ldrb r3, [r7, #16] 8008280: 7d39 ldrb r1, [r7, #20] 8008282: 2900 cmp r1, #0 8008284: d001 beq.n 800828a 8008286: 2102 movs r1, #2 8008288: e000 b.n 800828c 800828a: 2100 movs r1, #0 800828c: 440b add r3, r1 800828e: 00db lsls r3, r3, #3 ( ( fixLen == false ) ? 8 : 0 ) + 24 + 8008290: 4413 add r3, r2 } 8008292: 4618 mov r0, r3 8008294: 370c adds r7, #12 8008296: 46bd mov sp, r7 8008298: bc80 pop {r7} 800829a: 4770 bx lr 0800829c : static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, uint32_t datarate, uint8_t coderate, uint16_t preambleLen, bool fixLen, uint8_t payloadLen, bool crcOn ) { 800829c: b480 push {r7} 800829e: b08b sub sp, #44 @ 0x2c 80082a0: af00 add r7, sp, #0 80082a2: 60f8 str r0, [r7, #12] 80082a4: 60b9 str r1, [r7, #8] 80082a6: 4611 mov r1, r2 80082a8: 461a mov r2, r3 80082aa: 460b mov r3, r1 80082ac: 71fb strb r3, [r7, #7] 80082ae: 4613 mov r3, r2 80082b0: 80bb strh r3, [r7, #4] int32_t crDenom = coderate + 4; 80082b2: 79fb ldrb r3, [r7, #7] 80082b4: 3304 adds r3, #4 80082b6: 617b str r3, [r7, #20] bool lowDatareOptimize = false; 80082b8: 2300 movs r3, #0 80082ba: f887 3027 strb.w r3, [r7, #39] @ 0x27 // Ensure that the preamble length is at least 12 symbols when using SF5 or SF6 if( ( datarate == 5 ) || ( datarate == 6 ) ) 80082be: 68bb ldr r3, [r7, #8] 80082c0: 2b05 cmp r3, #5 80082c2: d002 beq.n 80082ca 80082c4: 68bb ldr r3, [r7, #8] 80082c6: 2b06 cmp r3, #6 80082c8: d104 bne.n 80082d4 { if( preambleLen < 12 ) 80082ca: 88bb ldrh r3, [r7, #4] 80082cc: 2b0b cmp r3, #11 80082ce: d801 bhi.n 80082d4 { preambleLen = 12; 80082d0: 230c movs r3, #12 80082d2: 80bb strh r3, [r7, #4] } } if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 80082d4: 68fb ldr r3, [r7, #12] 80082d6: 2b00 cmp r3, #0 80082d8: d105 bne.n 80082e6 80082da: 68bb ldr r3, [r7, #8] 80082dc: 2b0b cmp r3, #11 80082de: d008 beq.n 80082f2 80082e0: 68bb ldr r3, [r7, #8] 80082e2: 2b0c cmp r3, #12 80082e4: d005 beq.n 80082f2 80082e6: 68fb ldr r3, [r7, #12] 80082e8: 2b01 cmp r3, #1 80082ea: d105 bne.n 80082f8 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) 80082ec: 68bb ldr r3, [r7, #8] 80082ee: 2b0c cmp r3, #12 80082f0: d102 bne.n 80082f8 { lowDatareOptimize = true; 80082f2: 2301 movs r3, #1 80082f4: f887 3027 strb.w r3, [r7, #39] @ 0x27 } int32_t ceilDenominator; int32_t ceilNumerator = ( payloadLen << 3 ) + 80082f8: f897 3034 ldrb.w r3, [r7, #52] @ 0x34 80082fc: 00db lsls r3, r3, #3 ( crcOn ? 16 : 0 ) - 80082fe: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8008302: 2a00 cmp r2, #0 8008304: d001 beq.n 800830a 8008306: 2210 movs r2, #16 8008308: e000 b.n 800830c 800830a: 2200 movs r2, #0 int32_t ceilNumerator = ( payloadLen << 3 ) + 800830c: 4413 add r3, r2 800830e: 461a mov r2, r3 ( 4 * datarate ) + 8008310: 68bb ldr r3, [r7, #8] 8008312: 009b lsls r3, r3, #2 ( crcOn ? 16 : 0 ) - 8008314: 1ad3 subs r3, r2, r3 ( fixLen ? 0 : 20 ); 8008316: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 800831a: 2a00 cmp r2, #0 800831c: d001 beq.n 8008322 800831e: 2200 movs r2, #0 8008320: e000 b.n 8008324 8008322: 2214 movs r2, #20 ( 4 * datarate ) + 8008324: 4413 add r3, r2 int32_t ceilNumerator = ( payloadLen << 3 ) + 8008326: 61fb str r3, [r7, #28] if( datarate <= 6 ) 8008328: 68bb ldr r3, [r7, #8] 800832a: 2b06 cmp r3, #6 800832c: d803 bhi.n 8008336 { ceilDenominator = 4 * datarate; 800832e: 68bb ldr r3, [r7, #8] 8008330: 009b lsls r3, r3, #2 8008332: 623b str r3, [r7, #32] 8008334: e00e b.n 8008354 } else { ceilNumerator += 8; 8008336: 69fb ldr r3, [r7, #28] 8008338: 3308 adds r3, #8 800833a: 61fb str r3, [r7, #28] if( lowDatareOptimize == true ) 800833c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8008340: 2b00 cmp r3, #0 8008342: d004 beq.n 800834e { ceilDenominator = 4 * ( datarate - 2 ); 8008344: 68bb ldr r3, [r7, #8] 8008346: 3b02 subs r3, #2 8008348: 009b lsls r3, r3, #2 800834a: 623b str r3, [r7, #32] 800834c: e002 b.n 8008354 } else { ceilDenominator = 4 * datarate; 800834e: 68bb ldr r3, [r7, #8] 8008350: 009b lsls r3, r3, #2 8008352: 623b str r3, [r7, #32] } } if( ceilNumerator < 0 ) 8008354: 69fb ldr r3, [r7, #28] 8008356: 2b00 cmp r3, #0 8008358: da01 bge.n 800835e { ceilNumerator = 0; 800835a: 2300 movs r3, #0 800835c: 61fb str r3, [r7, #28] } // Perform integral ceil() int32_t intermediate = ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12; 800835e: 69fa ldr r2, [r7, #28] 8008360: 6a3b ldr r3, [r7, #32] 8008362: 4413 add r3, r2 8008364: 1e5a subs r2, r3, #1 8008366: 6a3b ldr r3, [r7, #32] 8008368: fb92 f3f3 sdiv r3, r2, r3 800836c: 697a ldr r2, [r7, #20] 800836e: fb03 f202 mul.w r2, r3, r2 8008372: 88bb ldrh r3, [r7, #4] 8008374: 4413 add r3, r2 int32_t intermediate = 8008376: 330c adds r3, #12 8008378: 61bb str r3, [r7, #24] if( datarate <= 6 ) 800837a: 68bb ldr r3, [r7, #8] 800837c: 2b06 cmp r3, #6 800837e: d802 bhi.n 8008386 { intermediate += 2; 8008380: 69bb ldr r3, [r7, #24] 8008382: 3302 adds r3, #2 8008384: 61bb str r3, [r7, #24] } return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) ); 8008386: 69bb ldr r3, [r7, #24] 8008388: 009b lsls r3, r3, #2 800838a: 1c5a adds r2, r3, #1 800838c: 68bb ldr r3, [r7, #8] 800838e: 3b02 subs r3, #2 8008390: fa02 f303 lsl.w r3, r2, r3 } 8008394: 4618 mov r0, r3 8008396: 372c adds r7, #44 @ 0x2c 8008398: 46bd mov sp, r7 800839a: bc80 pop {r7} 800839c: 4770 bx lr ... 080083a0 : static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, uint32_t datarate, uint8_t coderate, uint16_t preambleLen, bool fixLen, uint8_t payloadLen, bool crcOn ) { 80083a0: b580 push {r7, lr} 80083a2: b08a sub sp, #40 @ 0x28 80083a4: af04 add r7, sp, #16 80083a6: 60b9 str r1, [r7, #8] 80083a8: 607a str r2, [r7, #4] 80083aa: 461a mov r2, r3 80083ac: 4603 mov r3, r0 80083ae: 73fb strb r3, [r7, #15] 80083b0: 4613 mov r3, r2 80083b2: 73bb strb r3, [r7, #14] uint32_t numerator = 0; 80083b4: 2300 movs r3, #0 80083b6: 617b str r3, [r7, #20] uint32_t denominator = 1; 80083b8: 2301 movs r3, #1 80083ba: 613b str r3, [r7, #16] switch( modem ) 80083bc: 7bfb ldrb r3, [r7, #15] 80083be: 2b00 cmp r3, #0 80083c0: d002 beq.n 80083c8 80083c2: 2b01 cmp r3, #1 80083c4: d017 beq.n 80083f6 fixLen, payloadLen, crcOn ); denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); } break; default: break; 80083c6: e035 b.n 8008434 numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate, 80083c8: f897 0024 ldrb.w r0, [r7, #36] @ 0x24 80083cc: 8c3a ldrh r2, [r7, #32] 80083ce: 7bb9 ldrb r1, [r7, #14] 80083d0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80083d4: 9301 str r3, [sp, #4] 80083d6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 80083da: 9300 str r3, [sp, #0] 80083dc: 4603 mov r3, r0 80083de: 6878 ldr r0, [r7, #4] 80083e0: f7ff ff32 bl 8008248 80083e4: 4603 mov r3, r0 80083e6: f44f 727a mov.w r2, #1000 @ 0x3e8 80083ea: fb02 f303 mul.w r3, r2, r3 80083ee: 617b str r3, [r7, #20] denominator = datarate; 80083f0: 687b ldr r3, [r7, #4] 80083f2: 613b str r3, [r7, #16] break; 80083f4: e01e b.n 8008434 numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate, 80083f6: 8c39 ldrh r1, [r7, #32] 80083f8: 7bba ldrb r2, [r7, #14] 80083fa: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80083fe: 9302 str r3, [sp, #8] 8008400: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8008404: 9301 str r3, [sp, #4] 8008406: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 800840a: 9300 str r3, [sp, #0] 800840c: 460b mov r3, r1 800840e: 6879 ldr r1, [r7, #4] 8008410: 68b8 ldr r0, [r7, #8] 8008412: f7ff ff43 bl 800829c 8008416: 4603 mov r3, r0 8008418: f44f 727a mov.w r2, #1000 @ 0x3e8 800841c: fb02 f303 mul.w r3, r2, r3 8008420: 617b str r3, [r7, #20] denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); 8008422: 4a0a ldr r2, [pc, #40] @ (800844c ) 8008424: 68bb ldr r3, [r7, #8] 8008426: 4413 add r3, r2 8008428: 781b ldrb r3, [r3, #0] 800842a: 4618 mov r0, r3 800842c: f7ff feb6 bl 800819c 8008430: 6138 str r0, [r7, #16] break; 8008432: bf00 nop } // Perform integral ceil() return DIVC( numerator, denominator ); 8008434: 697a ldr r2, [r7, #20] 8008436: 693b ldr r3, [r7, #16] 8008438: 4413 add r3, r2 800843a: 1e5a subs r2, r3, #1 800843c: 693b ldr r3, [r7, #16] 800843e: fbb2 f3f3 udiv r3, r2, r3 } 8008442: 4618 mov r0, r3 8008444: 3718 adds r7, #24 8008446: 46bd mov sp, r7 8008448: bd80 pop {r7, pc} 800844a: bf00 nop 800844c: 0800fc08 .word 0x0800fc08 08008450 : static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ) { 8008450: b580 push {r7, lr} 8008452: b084 sub sp, #16 8008454: af00 add r7, sp, #0 8008456: 6078 str r0, [r7, #4] 8008458: 460b mov r3, r1 800845a: 70fb strb r3, [r7, #3] SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, 800845c: 2300 movs r3, #0 800845e: 2200 movs r2, #0 8008460: f240 2101 movw r1, #513 @ 0x201 8008464: f240 2001 movw r0, #513 @ 0x201 8008468: f001 fda6 bl 8009fb8 IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); /* Set DBG pin */ DBG_GPIO_RADIO_TX( SET ); 800846c: f44f 5100 mov.w r1, #8192 @ 0x2000 8008470: 4874 ldr r0, [pc, #464] @ (8008644 ) 8008472: f7ff fa09 bl 8007888 /* Set RF switch */ SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); 8008476: 4b74 ldr r3, [pc, #464] @ (8008648 ) 8008478: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 800847c: 2101 movs r1, #1 800847e: 4618 mov r0, r3 8008480: f002 fa52 bl 800a928 /* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/ /* RegTxModulation = @address 0x0889 */ if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) ) 8008484: 4b70 ldr r3, [pc, #448] @ (8008648 ) 8008486: 781b ldrb r3, [r3, #0] 8008488: 2b01 cmp r3, #1 800848a: d112 bne.n 80084b2 800848c: 4b6e ldr r3, [pc, #440] @ (8008648 ) 800848e: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 8008492: 2b06 cmp r3, #6 8008494: d10d bne.n 80084b2 { SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); 8008496: f640 0089 movw r0, #2185 @ 0x889 800849a: f002 f959 bl 800a750 800849e: 4603 mov r3, r0 80084a0: f023 0304 bic.w r3, r3, #4 80084a4: b2db uxtb r3, r3 80084a6: 4619 mov r1, r3 80084a8: f640 0089 movw r0, #2185 @ 0x889 80084ac: f002 f92e bl 800a70c 80084b0: e00c b.n 80084cc } else { SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); 80084b2: f640 0089 movw r0, #2185 @ 0x889 80084b6: f002 f94b bl 800a750 80084ba: 4603 mov r3, r0 80084bc: f043 0304 orr.w r3, r3, #4 80084c0: b2db uxtb r3, r3 80084c2: 4619 mov r1, r3 80084c4: f640 0089 movw r0, #2185 @ 0x889 80084c8: f002 f920 bl 800a70c } else #endif /* RADIO_LR_FHSS_IS_ON == 1 */ { /* WORKAROUND END */ switch( SubgRf.Modem ) 80084cc: 4b5e ldr r3, [pc, #376] @ (8008648 ) 80084ce: 781b ldrb r3, [r3, #0] 80084d0: 2b04 cmp r3, #4 80084d2: f200 80a7 bhi.w 8008624 80084d6: a201 add r2, pc, #4 @ (adr r2, 80084dc ) 80084d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80084dc: 0800850b .word 0x0800850b 80084e0: 080084f1 .word 0x080084f1 80084e4: 0800850b .word 0x0800850b 80084e8: 0800856d .word 0x0800856d 80084ec: 0800858d .word 0x0800858d { case MODEM_LORA: { SubgRf.PacketParams.Params.LoRa.PayloadLength = size; 80084f0: 4a55 ldr r2, [pc, #340] @ (8008648 ) 80084f2: 78fb ldrb r3, [r7, #3] 80084f4: 77d3 strb r3, [r2, #31] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80084f6: 4855 ldr r0, [pc, #340] @ (800864c ) 80084f8: f001 ffc2 bl 800a480 SUBGRF_SendPayload( buffer, size, 0 ); 80084fc: 78fb ldrb r3, [r7, #3] 80084fe: 2200 movs r2, #0 8008500: 4619 mov r1, r3 8008502: 6878 ldr r0, [r7, #4] 8008504: f001 fa6e bl 80099e4 break; 8008508: e08d b.n 8008626 } case MODEM_MSK: case MODEM_FSK: { if ( 1UL == RFW_Is_Init( ) ) 800850a: f002 fe7b bl 800b204 800850e: 4603 mov r3, r0 8008510: 2b01 cmp r3, #1 8008512: d11e bne.n 8008552 { uint8_t outsize; if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) ) 8008514: f107 020d add.w r2, r7, #13 8008518: 78fb ldrb r3, [r7, #3] 800851a: 4619 mov r1, r3 800851c: 6878 ldr r0, [r7, #4] 800851e: f002 fe95 bl 800b24c 8008522: 4603 mov r3, r0 8008524: 2b00 cmp r3, #0 8008526: d10c bne.n 8008542 { SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize; 8008528: 7b7a ldrb r2, [r7, #13] 800852a: 4b47 ldr r3, [pc, #284] @ (8008648 ) 800852c: 759a strb r2, [r3, #22] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 800852e: 4847 ldr r0, [pc, #284] @ (800864c ) 8008530: f001 ffa6 bl 800a480 SUBGRF_SendPayload( buffer, outsize, 0 ); 8008534: 7b7b ldrb r3, [r7, #13] 8008536: 2200 movs r2, #0 8008538: 4619 mov r1, r3 800853a: 6878 ldr r0, [r7, #4] 800853c: f001 fa52 bl 80099e4 { SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; SUBGRF_SetPacketParams( &SubgRf.PacketParams ); SUBGRF_SendPayload( buffer, size, 0 ); } break; 8008540: e071 b.n 8008626 MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); 8008542: 4b43 ldr r3, [pc, #268] @ (8008650 ) 8008544: 2201 movs r2, #1 8008546: 2100 movs r1, #0 8008548: 2002 movs r0, #2 800854a: f005 fd6d bl 800e028 return RADIO_STATUS_ERROR; 800854e: 2303 movs r3, #3 8008550: e073 b.n 800863a SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; 8008552: 4a3d ldr r2, [pc, #244] @ (8008648 ) 8008554: 78fb ldrb r3, [r7, #3] 8008556: 7593 strb r3, [r2, #22] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8008558: 483c ldr r0, [pc, #240] @ (800864c ) 800855a: f001 ff91 bl 800a480 SUBGRF_SendPayload( buffer, size, 0 ); 800855e: 78fb ldrb r3, [r7, #3] 8008560: 2200 movs r2, #0 8008562: 4619 mov r1, r3 8008564: 6878 ldr r0, [r7, #4] 8008566: f001 fa3d bl 80099e4 break; 800856a: e05c b.n 8008626 } case MODEM_BPSK: { SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; 800856c: 4b36 ldr r3, [pc, #216] @ (8008648 ) 800856e: 2202 movs r2, #2 8008570: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Bpsk.PayloadLength = size; 8008572: 4a35 ldr r2, [pc, #212] @ (8008648 ) 8008574: 78fb ldrb r3, [r7, #3] 8008576: 7693 strb r3, [r2, #26] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8008578: 4834 ldr r0, [pc, #208] @ (800864c ) 800857a: f001 ff81 bl 800a480 SUBGRF_SendPayload( buffer, size, 0 ); 800857e: 78fb ldrb r3, [r7, #3] 8008580: 2200 movs r2, #0 8008582: 4619 mov r1, r3 8008584: 6878 ldr r0, [r7, #4] 8008586: f001 fa2d bl 80099e4 break; 800858a: e04c b.n 8008626 case MODEM_SIGFOX_TX: { /* from bpsk to dbpsk */ /* first 1 bit duplicated */ /* RadioBuffer is 1 bytes more */ payload_integration( RadioBuffer, buffer, size ); 800858c: 78fb ldrb r3, [r7, #3] 800858e: 461a mov r2, r3 8008590: 6879 ldr r1, [r7, #4] 8008592: 4830 ldr r0, [pc, #192] @ (8008654 ) 8008594: f000 fcfa bl 8008f8c SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; 8008598: 4b2b ldr r3, [pc, #172] @ (8008648 ) 800859a: 2202 movs r2, #2 800859c: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1; 800859e: 78fb ldrb r3, [r7, #3] 80085a0: 3301 adds r3, #1 80085a2: b2da uxtb r2, r3 80085a4: 4b28 ldr r3, [pc, #160] @ (8008648 ) 80085a6: 769a strb r2, [r3, #26] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80085a8: 4828 ldr r0, [pc, #160] @ (800864c ) 80085aa: f001 ff69 bl 800a480 RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB 80085ae: 2100 movs r1, #0 80085b0: 20f1 movs r0, #241 @ 0xf1 80085b2: f000 f973 bl 800889c RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB 80085b6: 2100 movs r1, #0 80085b8: 20f0 movs r0, #240 @ 0xf0 80085ba: f000 f96f bl 800889c if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 ) 80085be: 4b22 ldr r3, [pc, #136] @ (8008648 ) 80085c0: 6c9b ldr r3, [r3, #72] @ 0x48 80085c2: 2b64 cmp r3, #100 @ 0x64 80085c4: d108 bne.n 80085d8 { RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB 80085c6: 2170 movs r1, #112 @ 0x70 80085c8: 20f3 movs r0, #243 @ 0xf3 80085ca: f000 f967 bl 800889c RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB 80085ce: 211d movs r1, #29 80085d0: 20f2 movs r0, #242 @ 0xf2 80085d2: f000 f963 bl 800889c 80085d6: e007 b.n 80085e8 } else // 600 bps { RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB 80085d8: 21e1 movs r1, #225 @ 0xe1 80085da: 20f3 movs r0, #243 @ 0xf3 80085dc: f000 f95e bl 800889c RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB 80085e0: 2104 movs r1, #4 80085e2: 20f2 movs r0, #242 @ 0xf2 80085e4: f000 f95a bl 800889c } uint16_t bitNum = ( size * 8 ) + 2; 80085e8: 78fb ldrb r3, [r7, #3] 80085ea: b29b uxth r3, r3 80085ec: 00db lsls r3, r3, #3 80085ee: b29b uxth r3, r3 80085f0: 3302 adds r3, #2 80085f2: 81fb strh r3, [r7, #14] RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame 80085f4: 89fb ldrh r3, [r7, #14] 80085f6: 0a1b lsrs r3, r3, #8 80085f8: b29b uxth r3, r3 80085fa: b2db uxtb r3, r3 80085fc: 4619 mov r1, r3 80085fe: 20f4 movs r0, #244 @ 0xf4 8008600: f000 f94c bl 800889c RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame 8008604: 89fb ldrh r3, [r7, #14] 8008606: b2db uxtb r3, r3 8008608: 4619 mov r1, r3 800860a: 20f5 movs r0, #245 @ 0xf5 800860c: f000 f946 bl 800889c SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF ); 8008610: 78fb ldrb r3, [r7, #3] 8008612: 3301 adds r3, #1 8008614: b2db uxtb r3, r3 8008616: f06f 427f mvn.w r2, #4278190080 @ 0xff000000 800861a: 4619 mov r1, r3 800861c: 480d ldr r0, [pc, #52] @ (8008654 ) 800861e: f001 f9e1 bl 80099e4 break; 8008622: e000 b.n 8008626 } #endif /*RADIO_SIGFOX_ENABLE == 1*/ default: break; 8008624: bf00 nop } TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout ); 8008626: 4b08 ldr r3, [pc, #32] @ (8008648 ) 8008628: 685b ldr r3, [r3, #4] 800862a: 4619 mov r1, r3 800862c: 480a ldr r0, [pc, #40] @ (8008658 ) 800862e: f005 fb73 bl 800dd18 TimerStart( &TxTimeoutTimer ); 8008632: 4809 ldr r0, [pc, #36] @ (8008658 ) 8008634: f005 fa92 bl 800db5c } return RADIO_STATUS_OK; 8008638: 2300 movs r3, #0 } 800863a: 4618 mov r0, r3 800863c: 3710 adds r7, #16 800863e: 46bd mov sp, r7 8008640: bd80 pop {r7, pc} 8008642: bf00 nop 8008644: 48000400 .word 0x48000400 8008648: 20000300 .word 0x20000300 800864c: 2000030e .word 0x2000030e 8008650: 0800f0f8 .word 0x0800f0f8 8008654: 200001fc .word 0x200001fc 8008658: 2000035c .word 0x2000035c 0800865c : static void RadioSleep( void ) { 800865c: b580 push {r7, lr} 800865e: b082 sub sp, #8 8008660: af00 add r7, sp, #0 SleepParams_t params = { 0 }; 8008662: 2300 movs r3, #0 8008664: 713b strb r3, [r7, #4] params.Fields.WarmStart = 1; 8008666: 793b ldrb r3, [r7, #4] 8008668: f043 0304 orr.w r3, r3, #4 800866c: 713b strb r3, [r7, #4] SUBGRF_SetSleep( params ); 800866e: 7938 ldrb r0, [r7, #4] 8008670: f001 fa94 bl 8009b9c RADIO_DELAY_MS( 2 ); 8008674: 2002 movs r0, #2 8008676: f7f8 fafb bl 8000c70 } 800867a: bf00 nop 800867c: 3708 adds r7, #8 800867e: 46bd mov sp, r7 8008680: bd80 pop {r7, pc} 08008682 : static void RadioStandby( void ) { 8008682: b580 push {r7, lr} 8008684: af00 add r7, sp, #0 SUBGRF_SetStandby( STDBY_RC ); 8008686: 2000 movs r0, #0 8008688: f001 fabc bl 8009c04 } 800868c: bf00 nop 800868e: bd80 pop {r7, pc} 08008690 : static void RadioRx( uint32_t timeout ) { 8008690: b580 push {r7, lr} 8008692: b082 sub sp, #8 8008694: af00 add r7, sp, #0 8008696: 6078 str r0, [r7, #4] if( SubgRf.lr_fhss.is_lr_fhss_on == true ) { //return LORAMAC_RADIO_STATUS_ERROR; } #endif /* RADIO_LR_FHSS_IS_ON == 1 */ if( 1UL == RFW_Is_Init( ) ) 8008698: f002 fdb4 bl 800b204 800869c: 4603 mov r3, r0 800869e: 2b01 cmp r3, #1 80086a0: d102 bne.n 80086a8 { RFW_ReceiveInit( ); 80086a2: f002 fe59 bl 800b358 80086a6: e007 b.n 80086b8 } else { SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, 80086a8: 2300 movs r3, #0 80086aa: 2200 movs r2, #0 80086ac: f240 2162 movw r1, #610 @ 0x262 80086b0: f240 2062 movw r0, #610 @ 0x262 80086b4: f001 fc80 bl 8009fb8 IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); } if( timeout != 0 ) 80086b8: 687b ldr r3, [r7, #4] 80086ba: 2b00 cmp r3, #0 80086bc: d006 beq.n 80086cc { TimerSetValue( &RxTimeoutTimer, timeout ); 80086be: 6879 ldr r1, [r7, #4] 80086c0: 4813 ldr r0, [pc, #76] @ (8008710 ) 80086c2: f005 fb29 bl 800dd18 TimerStart( &RxTimeoutTimer ); 80086c6: 4812 ldr r0, [pc, #72] @ (8008710 ) 80086c8: f005 fa48 bl 800db5c } /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ SubgRf.RxDcPreambleDetectTimeout = 0; 80086cc: 4b11 ldr r3, [pc, #68] @ (8008714 ) 80086ce: 2200 movs r2, #0 80086d0: 659a str r2, [r3, #88] @ 0x58 /* Set DBG pin */ DBG_GPIO_RADIO_RX( SET ); 80086d2: f44f 5180 mov.w r1, #4096 @ 0x1000 80086d6: 4810 ldr r0, [pc, #64] @ (8008718 ) 80086d8: f7ff f8d6 bl 8007888 /* RF switch configuration */ SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); 80086dc: 4b0d ldr r3, [pc, #52] @ (8008714 ) 80086de: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 80086e2: 2100 movs r1, #0 80086e4: 4618 mov r0, r3 80086e6: f002 f91f bl 800a928 if( SubgRf.RxContinuous == true ) 80086ea: 4b0a ldr r3, [pc, #40] @ (8008714 ) 80086ec: 785b ldrb r3, [r3, #1] 80086ee: 2b00 cmp r3, #0 80086f0: d004 beq.n 80086fc { SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous 80086f2: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 80086f6: f001 fac1 bl 8009c7c } else { SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); } } 80086fa: e005 b.n 8008708 SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); 80086fc: 4b05 ldr r3, [pc, #20] @ (8008714 ) 80086fe: 689b ldr r3, [r3, #8] 8008700: 019b lsls r3, r3, #6 8008702: 4618 mov r0, r3 8008704: f001 faba bl 8009c7c } 8008708: bf00 nop 800870a: 3708 adds r7, #8 800870c: 46bd mov sp, r7 800870e: bd80 pop {r7, pc} 8008710: 20000374 .word 0x20000374 8008714: 20000300 .word 0x20000300 8008718: 48000400 .word 0x48000400 0800871c : static void RadioRxBoosted( uint32_t timeout ) { 800871c: b580 push {r7, lr} 800871e: b082 sub sp, #8 8008720: af00 add r7, sp, #0 8008722: 6078 str r0, [r7, #4] if( SubgRf.lr_fhss.is_lr_fhss_on == true ) { //return LORAMAC_RADIO_STATUS_ERROR; } #endif /* RADIO_LR_FHSS_IS_ON == 1 */ if( 1UL == RFW_Is_Init() ) 8008724: f002 fd6e bl 800b204 8008728: 4603 mov r3, r0 800872a: 2b01 cmp r3, #1 800872c: d102 bne.n 8008734 { RFW_ReceiveInit(); 800872e: f002 fe13 bl 800b358 8008732: e007 b.n 8008744 } else { SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, 8008734: 2300 movs r3, #0 8008736: 2200 movs r2, #0 8008738: f240 2162 movw r1, #610 @ 0x262 800873c: f240 2062 movw r0, #610 @ 0x262 8008740: f001 fc3a bl 8009fb8 IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); } if( timeout != 0 ) 8008744: 687b ldr r3, [r7, #4] 8008746: 2b00 cmp r3, #0 8008748: d006 beq.n 8008758 { TimerSetValue( &RxTimeoutTimer, timeout ); 800874a: 6879 ldr r1, [r7, #4] 800874c: 4813 ldr r0, [pc, #76] @ (800879c ) 800874e: f005 fae3 bl 800dd18 TimerStart( &RxTimeoutTimer ); 8008752: 4812 ldr r0, [pc, #72] @ (800879c ) 8008754: f005 fa02 bl 800db5c } /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ SubgRf.RxDcPreambleDetectTimeout = 0; 8008758: 4b11 ldr r3, [pc, #68] @ (80087a0 ) 800875a: 2200 movs r2, #0 800875c: 659a str r2, [r3, #88] @ 0x58 /* Set DBG pin */ DBG_GPIO_RADIO_RX( SET ); 800875e: f44f 5180 mov.w r1, #4096 @ 0x1000 8008762: 4810 ldr r0, [pc, #64] @ (80087a4 ) 8008764: f7ff f890 bl 8007888 /* RF switch configuration */ SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); 8008768: 4b0d ldr r3, [pc, #52] @ (80087a0 ) 800876a: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 800876e: 2100 movs r1, #0 8008770: 4618 mov r0, r3 8008772: f002 f8d9 bl 800a928 if( SubgRf.RxContinuous == true ) 8008776: 4b0a ldr r3, [pc, #40] @ (80087a0 ) 8008778: 785b ldrb r3, [r3, #1] 800877a: 2b00 cmp r3, #0 800877c: d004 beq.n 8008788 { SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous 800877e: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 8008782: f001 fa9b bl 8009cbc } else { SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); } } 8008786: e005 b.n 8008794 SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); 8008788: 4b05 ldr r3, [pc, #20] @ (80087a0 ) 800878a: 689b ldr r3, [r3, #8] 800878c: 019b lsls r3, r3, #6 800878e: 4618 mov r0, r3 8008790: f001 fa94 bl 8009cbc } 8008794: bf00 nop 8008796: 3708 adds r7, #8 8008798: 46bd mov sp, r7 800879a: bd80 pop {r7, pc} 800879c: 20000374 .word 0x20000374 80087a0: 20000300 .word 0x20000300 80087a4: 48000400 .word 0x48000400 080087a8 : static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) { 80087a8: b580 push {r7, lr} 80087aa: b082 sub sp, #8 80087ac: af00 add r7, sp, #0 80087ae: 6078 str r0, [r7, #4] 80087b0: 6039 str r1, [r7, #0] /*See STM32WL Errata: RadioSetRxDutyCycle*/ SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime; 80087b2: 687b ldr r3, [r7, #4] 80087b4: 005a lsls r2, r3, #1 80087b6: 683b ldr r3, [r7, #0] 80087b8: 4413 add r3, r2 80087ba: 4a0c ldr r2, [pc, #48] @ (80087ec ) 80087bc: 6593 str r3, [r2, #88] @ 0x58 /*Enable also the IRQ_PREAMBLE_DETECTED*/ SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); 80087be: 2300 movs r3, #0 80087c0: 2200 movs r2, #0 80087c2: f64f 71ff movw r1, #65535 @ 0xffff 80087c6: f64f 70ff movw r0, #65535 @ 0xffff 80087ca: f001 fbf5 bl 8009fb8 /* RF switch configuration */ SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); 80087ce: 4b07 ldr r3, [pc, #28] @ (80087ec ) 80087d0: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 80087d4: 2100 movs r1, #0 80087d6: 4618 mov r0, r3 80087d8: f002 f8a6 bl 800a928 /* Start Rx DutyCycle*/ SUBGRF_SetRxDutyCycle( rxTime, sleepTime ); 80087dc: 6839 ldr r1, [r7, #0] 80087de: 6878 ldr r0, [r7, #4] 80087e0: f001 fa90 bl 8009d04 } 80087e4: bf00 nop 80087e6: 3708 adds r7, #8 80087e8: 46bd mov sp, r7 80087ea: bd80 pop {r7, pc} 80087ec: 20000300 .word 0x20000300 080087f0 : static void RadioStartCad( void ) { 80087f0: b580 push {r7, lr} 80087f2: af00 add r7, sp, #0 /* RF switch configuration */ SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); 80087f4: 4b09 ldr r3, [pc, #36] @ (800881c ) 80087f6: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 80087fa: 2100 movs r1, #0 80087fc: 4618 mov r0, r3 80087fe: f002 f893 bl 800a928 SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, 8008802: 2300 movs r3, #0 8008804: 2200 movs r2, #0 8008806: f44f 71c0 mov.w r1, #384 @ 0x180 800880a: f44f 70c0 mov.w r0, #384 @ 0x180 800880e: f001 fbd3 bl 8009fb8 IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); SUBGRF_SetCad( ); 8008812: f001 faa3 bl 8009d5c } 8008816: bf00 nop 8008818: bd80 pop {r7, pc} 800881a: bf00 nop 800881c: 20000300 .word 0x20000300 08008820 : static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) { 8008820: b580 push {r7, lr} 8008822: b084 sub sp, #16 8008824: af00 add r7, sp, #0 8008826: 6078 str r0, [r7, #4] 8008828: 460b mov r3, r1 800882a: 70fb strb r3, [r7, #3] 800882c: 4613 mov r3, r2 800882e: 803b strh r3, [r7, #0] if( SubgRf.lr_fhss.is_lr_fhss_on == true ) { //return LORAMAC_RADIO_STATUS_ERROR; } #endif /* RADIO_LR_FHSS_IS_ON == 1 */ uint32_t timeout = ( uint32_t )time * 1000; 8008830: 883b ldrh r3, [r7, #0] 8008832: f44f 727a mov.w r2, #1000 @ 0x3e8 8008836: fb02 f303 mul.w r3, r2, r3 800883a: 60fb str r3, [r7, #12] uint8_t antswitchpow; SUBGRF_SetRfFrequency( freq ); 800883c: 6878 ldr r0, [r7, #4] 800883e: f001 fc17 bl 800a070 antswitchpow = SUBGRF_SetRfTxPower( power ); 8008842: f997 3003 ldrsb.w r3, [r7, #3] 8008846: 4618 mov r0, r3 8008848: f002 f896 bl 800a978 800884c: 4603 mov r3, r0 800884e: 72fb strb r3, [r7, #11] /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); 8008850: 210e movs r1, #14 8008852: f640 101f movw r0, #2335 @ 0x91f 8008856: f001 ff59 bl 800a70c /* Set RF switch */ SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX ); 800885a: 7afb ldrb r3, [r7, #11] 800885c: 2101 movs r1, #1 800885e: 4618 mov r0, r3 8008860: f002 f862 bl 800a928 SUBGRF_SetTxContinuousWave( ); 8008864: f001 fa88 bl 8009d78 TimerSetValue( &TxTimeoutTimer, timeout ); 8008868: 68f9 ldr r1, [r7, #12] 800886a: 4805 ldr r0, [pc, #20] @ (8008880 ) 800886c: f005 fa54 bl 800dd18 TimerStart( &TxTimeoutTimer ); 8008870: 4803 ldr r0, [pc, #12] @ (8008880 ) 8008872: f005 f973 bl 800db5c } 8008876: bf00 nop 8008878: 3710 adds r7, #16 800887a: 46bd mov sp, r7 800887c: bd80 pop {r7, pc} 800887e: bf00 nop 8008880: 2000035c .word 0x2000035c 08008884 : static int16_t RadioRssi( RadioModems_t modem ) { 8008884: b580 push {r7, lr} 8008886: b082 sub sp, #8 8008888: af00 add r7, sp, #0 800888a: 4603 mov r3, r0 800888c: 71fb strb r3, [r7, #7] return SUBGRF_GetRssiInst( ); 800888e: f001 feaa bl 800a5e6 8008892: 4603 mov r3, r0 } 8008894: 4618 mov r0, r3 8008896: 3708 adds r7, #8 8008898: 46bd mov sp, r7 800889a: bd80 pop {r7, pc} 0800889c : static void RadioWrite( uint16_t addr, uint8_t data ) { 800889c: b580 push {r7, lr} 800889e: b082 sub sp, #8 80088a0: af00 add r7, sp, #0 80088a2: 4603 mov r3, r0 80088a4: 460a mov r2, r1 80088a6: 80fb strh r3, [r7, #6] 80088a8: 4613 mov r3, r2 80088aa: 717b strb r3, [r7, #5] SUBGRF_WriteRegister( addr, data ); 80088ac: 797a ldrb r2, [r7, #5] 80088ae: 88fb ldrh r3, [r7, #6] 80088b0: 4611 mov r1, r2 80088b2: 4618 mov r0, r3 80088b4: f001 ff2a bl 800a70c } 80088b8: bf00 nop 80088ba: 3708 adds r7, #8 80088bc: 46bd mov sp, r7 80088be: bd80 pop {r7, pc} 080088c0 : static uint8_t RadioRead( uint16_t addr ) { 80088c0: b580 push {r7, lr} 80088c2: b082 sub sp, #8 80088c4: af00 add r7, sp, #0 80088c6: 4603 mov r3, r0 80088c8: 80fb strh r3, [r7, #6] return SUBGRF_ReadRegister( addr ); 80088ca: 88fb ldrh r3, [r7, #6] 80088cc: 4618 mov r0, r3 80088ce: f001 ff3f bl 800a750 80088d2: 4603 mov r3, r0 } 80088d4: 4618 mov r0, r3 80088d6: 3708 adds r7, #8 80088d8: 46bd mov sp, r7 80088da: bd80 pop {r7, pc} 080088dc : static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) { 80088dc: b580 push {r7, lr} 80088de: b082 sub sp, #8 80088e0: af00 add r7, sp, #0 80088e2: 4603 mov r3, r0 80088e4: 6039 str r1, [r7, #0] 80088e6: 80fb strh r3, [r7, #6] 80088e8: 4613 mov r3, r2 80088ea: 717b strb r3, [r7, #5] SUBGRF_WriteRegisters( addr, buffer, size ); 80088ec: 797b ldrb r3, [r7, #5] 80088ee: b29a uxth r2, r3 80088f0: 88fb ldrh r3, [r7, #6] 80088f2: 6839 ldr r1, [r7, #0] 80088f4: 4618 mov r0, r3 80088f6: f001 ff4b bl 800a790 } 80088fa: bf00 nop 80088fc: 3708 adds r7, #8 80088fe: 46bd mov sp, r7 8008900: bd80 pop {r7, pc} 08008902 : static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) { 8008902: b580 push {r7, lr} 8008904: b082 sub sp, #8 8008906: af00 add r7, sp, #0 8008908: 4603 mov r3, r0 800890a: 6039 str r1, [r7, #0] 800890c: 80fb strh r3, [r7, #6] 800890e: 4613 mov r3, r2 8008910: 717b strb r3, [r7, #5] SUBGRF_ReadRegisters( addr, buffer, size ); 8008912: 797b ldrb r3, [r7, #5] 8008914: b29a uxth r2, r3 8008916: 88fb ldrh r3, [r7, #6] 8008918: 6839 ldr r1, [r7, #0] 800891a: 4618 mov r0, r3 800891c: f001 ff5a bl 800a7d4 } 8008920: bf00 nop 8008922: 3708 adds r7, #8 8008924: 46bd mov sp, r7 8008926: bd80 pop {r7, pc} 08008928 : static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) { 8008928: b580 push {r7, lr} 800892a: b082 sub sp, #8 800892c: af00 add r7, sp, #0 800892e: 4603 mov r3, r0 8008930: 460a mov r2, r1 8008932: 71fb strb r3, [r7, #7] 8008934: 4613 mov r3, r2 8008936: 71bb strb r3, [r7, #6] if( modem == MODEM_LORA ) 8008938: 79fb ldrb r3, [r7, #7] 800893a: 2b01 cmp r3, #1 800893c: d10a bne.n 8008954 { SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; 800893e: 4a0e ldr r2, [pc, #56] @ (8008978 ) 8008940: 79bb ldrb r3, [r7, #6] 8008942: 7013 strb r3, [r2, #0] 8008944: 4b0c ldr r3, [pc, #48] @ (8008978 ) 8008946: 781a ldrb r2, [r3, #0] 8008948: 4b0c ldr r3, [pc, #48] @ (800897c ) 800894a: 77da strb r2, [r3, #31] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 800894c: 480c ldr r0, [pc, #48] @ (8008980 ) 800894e: f001 fd97 bl 800a480 { SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; SUBGRF_SetPacketParams( &SubgRf.PacketParams ); } } } 8008952: e00d b.n 8008970 if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) 8008954: 4b09 ldr r3, [pc, #36] @ (800897c ) 8008956: 7d5b ldrb r3, [r3, #21] 8008958: 2b01 cmp r3, #1 800895a: d109 bne.n 8008970 SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; 800895c: 4a06 ldr r2, [pc, #24] @ (8008978 ) 800895e: 79bb ldrb r3, [r7, #6] 8008960: 7013 strb r3, [r2, #0] 8008962: 4b05 ldr r3, [pc, #20] @ (8008978 ) 8008964: 781a ldrb r2, [r3, #0] 8008966: 4b05 ldr r3, [pc, #20] @ (800897c ) 8008968: 759a strb r2, [r3, #22] SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 800896a: 4805 ldr r0, [pc, #20] @ (8008980 ) 800896c: f001 fd88 bl 800a480 } 8008970: bf00 nop 8008972: 3708 adds r7, #8 8008974: 46bd mov sp, r7 8008976: bd80 pop {r7, pc} 8008978: 20000008 .word 0x20000008 800897c: 20000300 .word 0x20000300 8008980: 2000030e .word 0x2000030e 08008984 : static void RadioSetPublicNetwork( bool enable ) { 8008984: b580 push {r7, lr} 8008986: b082 sub sp, #8 8008988: af00 add r7, sp, #0 800898a: 4603 mov r3, r0 800898c: 71fb strb r3, [r7, #7] SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable; 800898e: 4a13 ldr r2, [pc, #76] @ (80089dc ) 8008990: 79fb ldrb r3, [r7, #7] 8008992: 7313 strb r3, [r2, #12] 8008994: 4b11 ldr r3, [pc, #68] @ (80089dc ) 8008996: 7b1a ldrb r2, [r3, #12] 8008998: 4b10 ldr r3, [pc, #64] @ (80089dc ) 800899a: 735a strb r2, [r3, #13] RadioSetModem( MODEM_LORA ); 800899c: 2001 movs r0, #1 800899e: f7ff f801 bl 80079a4 if( enable == true ) 80089a2: 79fb ldrb r3, [r7, #7] 80089a4: 2b00 cmp r3, #0 80089a6: d00a beq.n 80089be { // Change LoRa modem SyncWord SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); 80089a8: 2134 movs r1, #52 @ 0x34 80089aa: f44f 60e8 mov.w r0, #1856 @ 0x740 80089ae: f001 fead bl 800a70c SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); 80089b2: 2144 movs r1, #68 @ 0x44 80089b4: f240 7041 movw r0, #1857 @ 0x741 80089b8: f001 fea8 bl 800a70c { // Change LoRa modem SyncWord SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); } } 80089bc: e009 b.n 80089d2 SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); 80089be: 2114 movs r1, #20 80089c0: f44f 60e8 mov.w r0, #1856 @ 0x740 80089c4: f001 fea2 bl 800a70c SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); 80089c8: 2124 movs r1, #36 @ 0x24 80089ca: f240 7041 movw r0, #1857 @ 0x741 80089ce: f001 fe9d bl 800a70c } 80089d2: bf00 nop 80089d4: 3708 adds r7, #8 80089d6: 46bd mov sp, r7 80089d8: bd80 pop {r7, pc} 80089da: bf00 nop 80089dc: 20000300 .word 0x20000300 080089e0 : static uint32_t RadioGetWakeupTime( void ) { 80089e0: b580 push {r7, lr} 80089e2: af00 add r7, sp, #0 return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME; 80089e4: f001 fffc bl 800a9e0 80089e8: 4603 mov r3, r0 80089ea: 3303 adds r3, #3 } 80089ec: 4618 mov r0, r3 80089ee: bd80 pop {r7, pc} 080089f0 : static void RadioOnTxTimeoutIrq( void *context ) { 80089f0: b580 push {r7, lr} 80089f2: b082 sub sp, #8 80089f4: af00 add r7, sp, #0 80089f6: 6078 str r0, [r7, #4] RADIO_TX_TIMEOUT_PROCESS(); 80089f8: f000 f80e bl 8008a18 } 80089fc: bf00 nop 80089fe: 3708 adds r7, #8 8008a00: 46bd mov sp, r7 8008a02: bd80 pop {r7, pc} 08008a04 : static void RadioOnRxTimeoutIrq( void *context ) { 8008a04: b580 push {r7, lr} 8008a06: b082 sub sp, #8 8008a08: af00 add r7, sp, #0 8008a0a: 6078 str r0, [r7, #4] RADIO_RX_TIMEOUT_PROCESS(); 8008a0c: f000 f81e bl 8008a4c } 8008a10: bf00 nop 8008a12: 3708 adds r7, #8 8008a14: 46bd mov sp, r7 8008a16: bd80 pop {r7, pc} 08008a18 : static void RadioOnTxTimeoutProcess( void ) { 8008a18: b580 push {r7, lr} 8008a1a: af00 add r7, sp, #0 DBG_GPIO_RADIO_TX( RST ); 8008a1c: f44f 5100 mov.w r1, #8192 @ 0x2000 8008a20: 4808 ldr r0, [pc, #32] @ (8008a44 ) 8008a22: f7fe ff3e bl 80078a2 if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) 8008a26: 4b08 ldr r3, [pc, #32] @ (8008a48 ) 8008a28: 681b ldr r3, [r3, #0] 8008a2a: 2b00 cmp r3, #0 8008a2c: d008 beq.n 8008a40 8008a2e: 4b06 ldr r3, [pc, #24] @ (8008a48 ) 8008a30: 681b ldr r3, [r3, #0] 8008a32: 685b ldr r3, [r3, #4] 8008a34: 2b00 cmp r3, #0 8008a36: d003 beq.n 8008a40 { RadioEvents->TxTimeout( ); 8008a38: 4b03 ldr r3, [pc, #12] @ (8008a48 ) 8008a3a: 681b ldr r3, [r3, #0] 8008a3c: 685b ldr r3, [r3, #4] 8008a3e: 4798 blx r3 } } 8008a40: bf00 nop 8008a42: bd80 pop {r7, pc} 8008a44: 48000400 .word 0x48000400 8008a48: 200002fc .word 0x200002fc 08008a4c : static void RadioOnRxTimeoutProcess( void ) { 8008a4c: b580 push {r7, lr} 8008a4e: af00 add r7, sp, #0 DBG_GPIO_RADIO_RX( RST ); 8008a50: f44f 5180 mov.w r1, #4096 @ 0x1000 8008a54: 4808 ldr r0, [pc, #32] @ (8008a78 ) 8008a56: f7fe ff24 bl 80078a2 if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) 8008a5a: 4b08 ldr r3, [pc, #32] @ (8008a7c ) 8008a5c: 681b ldr r3, [r3, #0] 8008a5e: 2b00 cmp r3, #0 8008a60: d008 beq.n 8008a74 8008a62: 4b06 ldr r3, [pc, #24] @ (8008a7c ) 8008a64: 681b ldr r3, [r3, #0] 8008a66: 68db ldr r3, [r3, #12] 8008a68: 2b00 cmp r3, #0 8008a6a: d003 beq.n 8008a74 { RadioEvents->RxTimeout( ); 8008a6c: 4b03 ldr r3, [pc, #12] @ (8008a7c ) 8008a6e: 681b ldr r3, [r3, #0] 8008a70: 68db ldr r3, [r3, #12] 8008a72: 4798 blx r3 } } 8008a74: bf00 nop 8008a76: bd80 pop {r7, pc} 8008a78: 48000400 .word 0x48000400 8008a7c: 200002fc .word 0x200002fc 08008a80 : static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ) { 8008a80: b580 push {r7, lr} 8008a82: b082 sub sp, #8 8008a84: af00 add r7, sp, #0 8008a86: 4603 mov r3, r0 8008a88: 80fb strh r3, [r7, #6] SubgRf.RadioIrq = radioIrq; 8008a8a: 4a05 ldr r2, [pc, #20] @ (8008aa0 ) 8008a8c: 88fb ldrh r3, [r7, #6] 8008a8e: f8a2 3054 strh.w r3, [r2, #84] @ 0x54 RADIO_IRQ_PROCESS(); 8008a92: f000 f807 bl 8008aa4 } 8008a96: bf00 nop 8008a98: 3708 adds r7, #8 8008a9a: 46bd mov sp, r7 8008a9c: bd80 pop {r7, pc} 8008a9e: bf00 nop 8008aa0: 20000300 .word 0x20000300 08008aa4 : static void RadioIrqProcess( void ) { 8008aa4: b5b0 push {r4, r5, r7, lr} 8008aa6: b082 sub sp, #8 8008aa8: af00 add r7, sp, #0 uint8_t size = 0; 8008aaa: 2300 movs r3, #0 8008aac: 71fb strb r3, [r7, #7] int32_t cfo = 0; 8008aae: 2300 movs r3, #0 8008ab0: 603b str r3, [r7, #0] switch( SubgRf.RadioIrq ) 8008ab2: 4bb2 ldr r3, [pc, #712] @ (8008d7c ) 8008ab4: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 8008ab8: f5b3 7f00 cmp.w r3, #512 @ 0x200 8008abc: f000 8117 beq.w 8008cee 8008ac0: f5b3 7f00 cmp.w r3, #512 @ 0x200 8008ac4: f300 81fe bgt.w 8008ec4 8008ac8: f5b3 7f80 cmp.w r3, #256 @ 0x100 8008acc: f000 80fb beq.w 8008cc6 8008ad0: f5b3 7f80 cmp.w r3, #256 @ 0x100 8008ad4: f300 81f6 bgt.w 8008ec4 8008ad8: 2b80 cmp r3, #128 @ 0x80 8008ada: f000 80e0 beq.w 8008c9e 8008ade: 2b80 cmp r3, #128 @ 0x80 8008ae0: f300 81f0 bgt.w 8008ec4 8008ae4: 2b20 cmp r3, #32 8008ae6: dc49 bgt.n 8008b7c 8008ae8: 2b00 cmp r3, #0 8008aea: f340 81eb ble.w 8008ec4 8008aee: 3b01 subs r3, #1 8008af0: 2b1f cmp r3, #31 8008af2: f200 81e7 bhi.w 8008ec4 8008af6: a201 add r2, pc, #4 @ (adr r2, 8008afc ) 8008af8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008afc: 08008b85 .word 0x08008b85 8008b00: 08008bc9 .word 0x08008bc9 8008b04: 08008ec5 .word 0x08008ec5 8008b08: 08008da1 .word 0x08008da1 8008b0c: 08008ec5 .word 0x08008ec5 8008b10: 08008ec5 .word 0x08008ec5 8008b14: 08008ec5 .word 0x08008ec5 8008b18: 08008e1d .word 0x08008e1d 8008b1c: 08008ec5 .word 0x08008ec5 8008b20: 08008ec5 .word 0x08008ec5 8008b24: 08008ec5 .word 0x08008ec5 8008b28: 08008ec5 .word 0x08008ec5 8008b2c: 08008ec5 .word 0x08008ec5 8008b30: 08008ec5 .word 0x08008ec5 8008b34: 08008ec5 .word 0x08008ec5 8008b38: 08008e39 .word 0x08008e39 8008b3c: 08008ec5 .word 0x08008ec5 8008b40: 08008ec5 .word 0x08008ec5 8008b44: 08008ec5 .word 0x08008ec5 8008b48: 08008ec5 .word 0x08008ec5 8008b4c: 08008ec5 .word 0x08008ec5 8008b50: 08008ec5 .word 0x08008ec5 8008b54: 08008ec5 .word 0x08008ec5 8008b58: 08008ec5 .word 0x08008ec5 8008b5c: 08008ec5 .word 0x08008ec5 8008b60: 08008ec5 .word 0x08008ec5 8008b64: 08008ec5 .word 0x08008ec5 8008b68: 08008ec5 .word 0x08008ec5 8008b6c: 08008ec5 .word 0x08008ec5 8008b70: 08008ec5 .word 0x08008ec5 8008b74: 08008ec5 .word 0x08008ec5 8008b78: 08008e47 .word 0x08008e47 8008b7c: 2b40 cmp r3, #64 @ 0x40 8008b7e: f000 8183 beq.w 8008e88 MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" ); break; } #endif /* RADIO_LR_FHSS_IS_ON == 1 */ default: break; 8008b82: e19f b.n 8008ec4 DBG_GPIO_RADIO_TX( RST ); 8008b84: f44f 5100 mov.w r1, #8192 @ 0x2000 8008b88: 487d ldr r0, [pc, #500] @ (8008d80 ) 8008b8a: f7fe fe8a bl 80078a2 TimerStop( &TxTimeoutTimer ); 8008b8e: 487d ldr r0, [pc, #500] @ (8008d84 ) 8008b90: f005 f852 bl 800dc38 SUBGRF_SetStandby( STDBY_RC ); 8008b94: 2000 movs r0, #0 8008b96: f001 f835 bl 8009c04 if( RFW_Is_LongPacketModeEnabled() == 1 ) 8008b9a: f002 fb3d bl 800b218 8008b9e: 4603 mov r3, r0 8008ba0: 2b01 cmp r3, #1 8008ba2: d101 bne.n 8008ba8 RFW_DeInit_TxLongPacket( ); 8008ba4: f002 fbf4 bl 800b390 if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) 8008ba8: 4b77 ldr r3, [pc, #476] @ (8008d88 ) 8008baa: 681b ldr r3, [r3, #0] 8008bac: 2b00 cmp r3, #0 8008bae: f000 818b beq.w 8008ec8 8008bb2: 4b75 ldr r3, [pc, #468] @ (8008d88 ) 8008bb4: 681b ldr r3, [r3, #0] 8008bb6: 681b ldr r3, [r3, #0] 8008bb8: 2b00 cmp r3, #0 8008bba: f000 8185 beq.w 8008ec8 RadioEvents->TxDone( ); 8008bbe: 4b72 ldr r3, [pc, #456] @ (8008d88 ) 8008bc0: 681b ldr r3, [r3, #0] 8008bc2: 681b ldr r3, [r3, #0] 8008bc4: 4798 blx r3 break; 8008bc6: e17f b.n 8008ec8 DBG_GPIO_RADIO_RX( RST ); 8008bc8: f44f 5180 mov.w r1, #4096 @ 0x1000 8008bcc: 486c ldr r0, [pc, #432] @ (8008d80 ) 8008bce: f7fe fe68 bl 80078a2 TimerStop( &RxTimeoutTimer ); 8008bd2: 486e ldr r0, [pc, #440] @ (8008d8c ) 8008bd4: f005 f830 bl 800dc38 if( SubgRf.RxContinuous == false ) 8008bd8: 4b68 ldr r3, [pc, #416] @ (8008d7c ) 8008bda: 785b ldrb r3, [r3, #1] 8008bdc: f083 0301 eor.w r3, r3, #1 8008be0: b2db uxtb r3, r3 8008be2: 2b00 cmp r3, #0 8008be4: d014 beq.n 8008c10 SUBGRF_SetStandby( STDBY_RC ); 8008be6: 2000 movs r0, #0 8008be8: f001 f80c bl 8009c04 SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 ); 8008bec: 2100 movs r1, #0 8008bee: f640 1002 movw r0, #2306 @ 0x902 8008bf2: f001 fd8b bl 800a70c SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) ); 8008bf6: f640 1044 movw r0, #2372 @ 0x944 8008bfa: f001 fda9 bl 800a750 8008bfe: 4603 mov r3, r0 8008c00: f043 0302 orr.w r3, r3, #2 8008c04: b2db uxtb r3, r3 8008c06: 4619 mov r1, r3 8008c08: f640 1044 movw r0, #2372 @ 0x944 8008c0c: f001 fd7e bl 800a70c SUBGRF_GetPayload( RadioBuffer, &size, 255 ); 8008c10: 1dfb adds r3, r7, #7 8008c12: 22ff movs r2, #255 @ 0xff 8008c14: 4619 mov r1, r3 8008c16: 485e ldr r0, [pc, #376] @ (8008d90 ) 8008c18: f000 fec2 bl 80099a0 SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) ); 8008c1c: 485d ldr r0, [pc, #372] @ (8008d94 ) 8008c1e: f001 fd23 bl 800a668 if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) 8008c22: 4b59 ldr r3, [pc, #356] @ (8008d88 ) 8008c24: 681b ldr r3, [r3, #0] 8008c26: 2b00 cmp r3, #0 8008c28: f000 8150 beq.w 8008ecc 8008c2c: 4b56 ldr r3, [pc, #344] @ (8008d88 ) 8008c2e: 681b ldr r3, [r3, #0] 8008c30: 689b ldr r3, [r3, #8] 8008c32: 2b00 cmp r3, #0 8008c34: f000 814a beq.w 8008ecc switch( SubgRf.PacketStatus.packetType ) 8008c38: 4b50 ldr r3, [pc, #320] @ (8008d7c ) 8008c3a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8008c3e: 2b01 cmp r3, #1 8008c40: d10e bne.n 8008c60 RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt, 8008c42: 4b51 ldr r3, [pc, #324] @ (8008d88 ) 8008c44: 681b ldr r3, [r3, #0] 8008c46: 689c ldr r4, [r3, #8] 8008c48: 79fb ldrb r3, [r7, #7] 8008c4a: 4619 mov r1, r3 8008c4c: 4b4b ldr r3, [pc, #300] @ (8008d7c ) 8008c4e: f993 3030 ldrsb.w r3, [r3, #48] @ 0x30 8008c52: 461a mov r2, r3 8008c54: 4b49 ldr r3, [pc, #292] @ (8008d7c ) 8008c56: f993 3031 ldrsb.w r3, [r3, #49] @ 0x31 8008c5a: 484d ldr r0, [pc, #308] @ (8008d90 ) 8008c5c: 47a0 blx r4 break; 8008c5e: e01d b.n 8008c9c SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo ); 8008c60: 4b46 ldr r3, [pc, #280] @ (8008d7c ) 8008c62: 6bdb ldr r3, [r3, #60] @ 0x3c 8008c64: 463a mov r2, r7 8008c66: 4611 mov r1, r2 8008c68: 4618 mov r0, r3 8008c6a: f001 ffab bl 800abc4 RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) ); 8008c6e: 4b46 ldr r3, [pc, #280] @ (8008d88 ) 8008c70: 681b ldr r3, [r3, #0] 8008c72: 689c ldr r4, [r3, #8] 8008c74: 79fb ldrb r3, [r7, #7] 8008c76: 4619 mov r1, r3 8008c78: 4b40 ldr r3, [pc, #256] @ (8008d7c ) 8008c7a: f993 3029 ldrsb.w r3, [r3, #41] @ 0x29 8008c7e: 4618 mov r0, r3 8008c80: 683b ldr r3, [r7, #0] 8008c82: f503 73fa add.w r3, r3, #500 @ 0x1f4 8008c86: 4a44 ldr r2, [pc, #272] @ (8008d98 ) 8008c88: fb82 5203 smull r5, r2, r2, r3 8008c8c: 1192 asrs r2, r2, #6 8008c8e: 17db asrs r3, r3, #31 8008c90: 1ad3 subs r3, r2, r3 8008c92: b25b sxtb r3, r3 8008c94: 4602 mov r2, r0 8008c96: 483e ldr r0, [pc, #248] @ (8008d90 ) 8008c98: 47a0 blx r4 break; 8008c9a: bf00 nop break; 8008c9c: e116 b.n 8008ecc SUBGRF_SetStandby( STDBY_RC ); 8008c9e: 2000 movs r0, #0 8008ca0: f000 ffb0 bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) 8008ca4: 4b38 ldr r3, [pc, #224] @ (8008d88 ) 8008ca6: 681b ldr r3, [r3, #0] 8008ca8: 2b00 cmp r3, #0 8008caa: f000 8111 beq.w 8008ed0 8008cae: 4b36 ldr r3, [pc, #216] @ (8008d88 ) 8008cb0: 681b ldr r3, [r3, #0] 8008cb2: 699b ldr r3, [r3, #24] 8008cb4: 2b00 cmp r3, #0 8008cb6: f000 810b beq.w 8008ed0 RadioEvents->CadDone( false ); 8008cba: 4b33 ldr r3, [pc, #204] @ (8008d88 ) 8008cbc: 681b ldr r3, [r3, #0] 8008cbe: 699b ldr r3, [r3, #24] 8008cc0: 2000 movs r0, #0 8008cc2: 4798 blx r3 break; 8008cc4: e104 b.n 8008ed0 SUBGRF_SetStandby( STDBY_RC ); 8008cc6: 2000 movs r0, #0 8008cc8: f000 ff9c bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) 8008ccc: 4b2e ldr r3, [pc, #184] @ (8008d88 ) 8008cce: 681b ldr r3, [r3, #0] 8008cd0: 2b00 cmp r3, #0 8008cd2: f000 80ff beq.w 8008ed4 8008cd6: 4b2c ldr r3, [pc, #176] @ (8008d88 ) 8008cd8: 681b ldr r3, [r3, #0] 8008cda: 699b ldr r3, [r3, #24] 8008cdc: 2b00 cmp r3, #0 8008cde: f000 80f9 beq.w 8008ed4 RadioEvents->CadDone( true ); 8008ce2: 4b29 ldr r3, [pc, #164] @ (8008d88 ) 8008ce4: 681b ldr r3, [r3, #0] 8008ce6: 699b ldr r3, [r3, #24] 8008ce8: 2001 movs r0, #1 8008cea: 4798 blx r3 break; 8008cec: e0f2 b.n 8008ed4 MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" ); 8008cee: 4b2b ldr r3, [pc, #172] @ (8008d9c ) 8008cf0: 2201 movs r2, #1 8008cf2: 2100 movs r1, #0 8008cf4: 2002 movs r0, #2 8008cf6: f005 f997 bl 800e028 if( SUBGRF_GetOperatingMode( ) == MODE_TX ) 8008cfa: f000 fe37 bl 800996c 8008cfe: 4603 mov r3, r0 8008d00: 2b04 cmp r3, #4 8008d02: d11a bne.n 8008d3a DBG_GPIO_RADIO_TX( RST ); 8008d04: f44f 5100 mov.w r1, #8192 @ 0x2000 8008d08: 481d ldr r0, [pc, #116] @ (8008d80 ) 8008d0a: f7fe fdca bl 80078a2 TimerStop( &TxTimeoutTimer ); 8008d0e: 481d ldr r0, [pc, #116] @ (8008d84 ) 8008d10: f004 ff92 bl 800dc38 SUBGRF_SetStandby( STDBY_RC ); 8008d14: 2000 movs r0, #0 8008d16: f000 ff75 bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) 8008d1a: 4b1b ldr r3, [pc, #108] @ (8008d88 ) 8008d1c: 681b ldr r3, [r3, #0] 8008d1e: 2b00 cmp r3, #0 8008d20: f000 80da beq.w 8008ed8 8008d24: 4b18 ldr r3, [pc, #96] @ (8008d88 ) 8008d26: 681b ldr r3, [r3, #0] 8008d28: 685b ldr r3, [r3, #4] 8008d2a: 2b00 cmp r3, #0 8008d2c: f000 80d4 beq.w 8008ed8 RadioEvents->TxTimeout( ); 8008d30: 4b15 ldr r3, [pc, #84] @ (8008d88 ) 8008d32: 681b ldr r3, [r3, #0] 8008d34: 685b ldr r3, [r3, #4] 8008d36: 4798 blx r3 break; 8008d38: e0ce b.n 8008ed8 else if( SUBGRF_GetOperatingMode( ) == MODE_RX ) 8008d3a: f000 fe17 bl 800996c 8008d3e: 4603 mov r3, r0 8008d40: 2b05 cmp r3, #5 8008d42: f040 80c9 bne.w 8008ed8 DBG_GPIO_RADIO_RX( RST ); 8008d46: f44f 5180 mov.w r1, #4096 @ 0x1000 8008d4a: 480d ldr r0, [pc, #52] @ (8008d80 ) 8008d4c: f7fe fda9 bl 80078a2 TimerStop( &RxTimeoutTimer ); 8008d50: 480e ldr r0, [pc, #56] @ (8008d8c ) 8008d52: f004 ff71 bl 800dc38 SUBGRF_SetStandby( STDBY_RC ); 8008d56: 2000 movs r0, #0 8008d58: f000 ff54 bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) 8008d5c: 4b0a ldr r3, [pc, #40] @ (8008d88 ) 8008d5e: 681b ldr r3, [r3, #0] 8008d60: 2b00 cmp r3, #0 8008d62: f000 80b9 beq.w 8008ed8 8008d66: 4b08 ldr r3, [pc, #32] @ (8008d88 ) 8008d68: 681b ldr r3, [r3, #0] 8008d6a: 68db ldr r3, [r3, #12] 8008d6c: 2b00 cmp r3, #0 8008d6e: f000 80b3 beq.w 8008ed8 RadioEvents->RxTimeout( ); 8008d72: 4b05 ldr r3, [pc, #20] @ (8008d88 ) 8008d74: 681b ldr r3, [r3, #0] 8008d76: 68db ldr r3, [r3, #12] 8008d78: 4798 blx r3 break; 8008d7a: e0ad b.n 8008ed8 8008d7c: 20000300 .word 0x20000300 8008d80: 48000400 .word 0x48000400 8008d84: 2000035c .word 0x2000035c 8008d88: 200002fc .word 0x200002fc 8008d8c: 20000374 .word 0x20000374 8008d90: 200001fc .word 0x200001fc 8008d94: 20000324 .word 0x20000324 8008d98: 10624dd3 .word 0x10624dd3 8008d9c: 0800f110 .word 0x0800f110 MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" ); 8008da0: 4b54 ldr r3, [pc, #336] @ (8008ef4 ) 8008da2: 2201 movs r2, #1 8008da4: 2100 movs r1, #0 8008da6: 2002 movs r0, #2 8008da8: f005 f93e bl 800e028 if( SubgRf.RxDcPreambleDetectTimeout != 0 ) 8008dac: 4b52 ldr r3, [pc, #328] @ (8008ef8 ) 8008dae: 6d9b ldr r3, [r3, #88] @ 0x58 8008db0: 2b00 cmp r3, #0 8008db2: f000 8093 beq.w 8008edc Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/ 8008db6: 4a51 ldr r2, [pc, #324] @ (8008efc ) 8008db8: 4b4f ldr r3, [pc, #316] @ (8008ef8 ) 8008dba: 6d9b ldr r3, [r3, #88] @ 0x58 8008dbc: 0c1b lsrs r3, r3, #16 8008dbe: b2db uxtb r3, r3 8008dc0: 4619 mov r1, r3 8008dc2: f640 1003 movw r0, #2307 @ 0x903 8008dc6: 4790 blx r2 Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/ 8008dc8: 4a4c ldr r2, [pc, #304] @ (8008efc ) 8008dca: 4b4b ldr r3, [pc, #300] @ (8008ef8 ) 8008dcc: 6d9b ldr r3, [r3, #88] @ 0x58 8008dce: 0a1b lsrs r3, r3, #8 8008dd0: b2db uxtb r3, r3 8008dd2: 4619 mov r1, r3 8008dd4: f640 1004 movw r0, #2308 @ 0x904 8008dd8: 4790 blx r2 Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/ 8008dda: 4a48 ldr r2, [pc, #288] @ (8008efc ) 8008ddc: 4b46 ldr r3, [pc, #280] @ (8008ef8 ) 8008dde: 6d9b ldr r3, [r3, #88] @ 0x58 8008de0: b2db uxtb r3, r3 8008de2: 4619 mov r1, r3 8008de4: f640 1005 movw r0, #2309 @ 0x905 8008de8: 4790 blx r2 Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/ 8008dea: 4c44 ldr r4, [pc, #272] @ (8008efc ) 8008dec: 4b44 ldr r3, [pc, #272] @ (8008f00 ) 8008dee: f640 1002 movw r0, #2306 @ 0x902 8008df2: 4798 blx r3 8008df4: 4603 mov r3, r0 8008df6: f043 0301 orr.w r3, r3, #1 8008dfa: b2db uxtb r3, r3 8008dfc: 4619 mov r1, r3 8008dfe: f640 1002 movw r0, #2306 @ 0x902 8008e02: 47a0 blx r4 SubgRf.RxDcPreambleDetectTimeout = 0; 8008e04: 4b3c ldr r3, [pc, #240] @ (8008ef8 ) 8008e06: 2200 movs r2, #0 8008e08: 659a str r2, [r3, #88] @ 0x58 SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, 8008e0a: 2300 movs r3, #0 8008e0c: 2200 movs r2, #0 8008e0e: f240 2162 movw r1, #610 @ 0x262 8008e12: f240 2062 movw r0, #610 @ 0x262 8008e16: f001 f8cf bl 8009fb8 break; 8008e1a: e05f b.n 8008edc MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" ); 8008e1c: 4b39 ldr r3, [pc, #228] @ (8008f04 ) 8008e1e: 2201 movs r2, #1 8008e20: 2100 movs r1, #0 8008e22: 2002 movs r0, #2 8008e24: f005 f900 bl 800e028 if( 1UL == RFW_Is_Init( ) ) 8008e28: f002 f9ec bl 800b204 8008e2c: 4603 mov r3, r0 8008e2e: 2b01 cmp r3, #1 8008e30: d156 bne.n 8008ee0 RFW_ReceivePayload( ); 8008e32: f002 fac9 bl 800b3c8 break; 8008e36: e053 b.n 8008ee0 MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" ); 8008e38: 4b33 ldr r3, [pc, #204] @ (8008f08 ) 8008e3a: 2201 movs r2, #1 8008e3c: 2100 movs r1, #0 8008e3e: 2002 movs r0, #2 8008e40: f005 f8f2 bl 800e028 break; 8008e44: e051 b.n 8008eea TimerStop( &RxTimeoutTimer ); 8008e46: 4831 ldr r0, [pc, #196] @ (8008f0c ) 8008e48: f004 fef6 bl 800dc38 if( SubgRf.RxContinuous == false ) 8008e4c: 4b2a ldr r3, [pc, #168] @ (8008ef8 ) 8008e4e: 785b ldrb r3, [r3, #1] 8008e50: f083 0301 eor.w r3, r3, #1 8008e54: b2db uxtb r3, r3 8008e56: 2b00 cmp r3, #0 8008e58: d002 beq.n 8008e60 SUBGRF_SetStandby( STDBY_RC ); 8008e5a: 2000 movs r0, #0 8008e5c: f000 fed2 bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) 8008e60: 4b2b ldr r3, [pc, #172] @ (8008f10 ) 8008e62: 681b ldr r3, [r3, #0] 8008e64: 2b00 cmp r3, #0 8008e66: d03d beq.n 8008ee4 8008e68: 4b29 ldr r3, [pc, #164] @ (8008f10 ) 8008e6a: 681b ldr r3, [r3, #0] 8008e6c: 68db ldr r3, [r3, #12] 8008e6e: 2b00 cmp r3, #0 8008e70: d038 beq.n 8008ee4 RadioEvents->RxTimeout( ); 8008e72: 4b27 ldr r3, [pc, #156] @ (8008f10 ) 8008e74: 681b ldr r3, [r3, #0] 8008e76: 68db ldr r3, [r3, #12] 8008e78: 4798 blx r3 MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" ); 8008e7a: 4b26 ldr r3, [pc, #152] @ (8008f14 ) 8008e7c: 2201 movs r2, #1 8008e7e: 2100 movs r1, #0 8008e80: 2002 movs r0, #2 8008e82: f005 f8d1 bl 800e028 break; 8008e86: e02d b.n 8008ee4 MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" ); 8008e88: 4b23 ldr r3, [pc, #140] @ (8008f18 ) 8008e8a: 2201 movs r2, #1 8008e8c: 2100 movs r1, #0 8008e8e: 2002 movs r0, #2 8008e90: f005 f8ca bl 800e028 if( SubgRf.RxContinuous == false ) 8008e94: 4b18 ldr r3, [pc, #96] @ (8008ef8 ) 8008e96: 785b ldrb r3, [r3, #1] 8008e98: f083 0301 eor.w r3, r3, #1 8008e9c: b2db uxtb r3, r3 8008e9e: 2b00 cmp r3, #0 8008ea0: d002 beq.n 8008ea8 SUBGRF_SetStandby( STDBY_RC ); 8008ea2: 2000 movs r0, #0 8008ea4: f000 feae bl 8009c04 if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) 8008ea8: 4b19 ldr r3, [pc, #100] @ (8008f10 ) 8008eaa: 681b ldr r3, [r3, #0] 8008eac: 2b00 cmp r3, #0 8008eae: d01b beq.n 8008ee8 8008eb0: 4b17 ldr r3, [pc, #92] @ (8008f10 ) 8008eb2: 681b ldr r3, [r3, #0] 8008eb4: 691b ldr r3, [r3, #16] 8008eb6: 2b00 cmp r3, #0 8008eb8: d016 beq.n 8008ee8 RadioEvents->RxError( ); 8008eba: 4b15 ldr r3, [pc, #84] @ (8008f10 ) 8008ebc: 681b ldr r3, [r3, #0] 8008ebe: 691b ldr r3, [r3, #16] 8008ec0: 4798 blx r3 break; 8008ec2: e011 b.n 8008ee8 break; 8008ec4: bf00 nop 8008ec6: e010 b.n 8008eea break; 8008ec8: bf00 nop 8008eca: e00e b.n 8008eea break; 8008ecc: bf00 nop 8008ece: e00c b.n 8008eea break; 8008ed0: bf00 nop 8008ed2: e00a b.n 8008eea break; 8008ed4: bf00 nop 8008ed6: e008 b.n 8008eea break; 8008ed8: bf00 nop 8008eda: e006 b.n 8008eea break; 8008edc: bf00 nop 8008ede: e004 b.n 8008eea break; 8008ee0: bf00 nop 8008ee2: e002 b.n 8008eea break; 8008ee4: bf00 nop 8008ee6: e000 b.n 8008eea break; 8008ee8: bf00 nop } } 8008eea: bf00 nop 8008eec: 3708 adds r7, #8 8008eee: 46bd mov sp, r7 8008ef0: bdb0 pop {r4, r5, r7, pc} 8008ef2: bf00 nop 8008ef4: 0800f124 .word 0x0800f124 8008ef8: 20000300 .word 0x20000300 8008efc: 0800889d .word 0x0800889d 8008f00: 080088c1 .word 0x080088c1 8008f04: 0800f130 .word 0x0800f130 8008f08: 0800f13c .word 0x0800f13c 8008f0c: 20000374 .word 0x20000374 8008f10: 200002fc .word 0x200002fc 8008f14: 0800f148 .word 0x0800f148 8008f18: 0800f154 .word 0x0800f154 08008f1c : static void RadioTxPrbs( void ) { 8008f1c: b580 push {r7, lr} 8008f1e: af00 add r7, sp, #0 SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); 8008f20: 4b09 ldr r3, [pc, #36] @ (8008f48 ) 8008f22: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 8008f26: 2101 movs r1, #1 8008f28: 4618 mov r0, r3 8008f2a: f001 fcfd bl 800a928 Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble 8008f2e: 4b07 ldr r3, [pc, #28] @ (8008f4c ) 8008f30: 212d movs r1, #45 @ 0x2d 8008f32: f44f 60d7 mov.w r0, #1720 @ 0x6b8 8008f36: 4798 blx r3 SUBGRF_SetTxInfinitePreamble( ); 8008f38: f000 ff27 bl 8009d8a SUBGRF_SetTx( 0x0fffff ); 8008f3c: 4804 ldr r0, [pc, #16] @ (8008f50 ) 8008f3e: f000 fe7d bl 8009c3c } 8008f42: bf00 nop 8008f44: bd80 pop {r7, pc} 8008f46: bf00 nop 8008f48: 20000300 .word 0x20000300 8008f4c: 0800889d .word 0x0800889d 8008f50: 000fffff .word 0x000fffff 08008f54 : static void RadioTxCw( int8_t power ) { 8008f54: b580 push {r7, lr} 8008f56: b084 sub sp, #16 8008f58: af00 add r7, sp, #0 8008f5a: 4603 mov r3, r0 8008f5c: 71fb strb r3, [r7, #7] uint8_t paselect = SUBGRF_SetRfTxPower( power ); 8008f5e: f997 3007 ldrsb.w r3, [r7, #7] 8008f62: 4618 mov r0, r3 8008f64: f001 fd08 bl 800a978 8008f68: 4603 mov r3, r0 8008f6a: 73fb strb r3, [r7, #15] /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); 8008f6c: 210e movs r1, #14 8008f6e: f640 101f movw r0, #2335 @ 0x91f 8008f72: f001 fbcb bl 800a70c SUBGRF_SetSwitch( paselect, RFSWITCH_TX ); 8008f76: 7bfb ldrb r3, [r7, #15] 8008f78: 2101 movs r1, #1 8008f7a: 4618 mov r0, r3 8008f7c: f001 fcd4 bl 800a928 SUBGRF_SetTxContinuousWave( ); 8008f80: f000 fefa bl 8009d78 } 8008f84: bf00 nop 8008f86: 3710 adds r7, #16 8008f88: 46bd mov sp, r7 8008f8a: bd80 pop {r7, pc} 08008f8c : #if (RADIO_SIGFOX_ENABLE == 1) static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ) { 8008f8c: b480 push {r7} 8008f8e: b089 sub sp, #36 @ 0x24 8008f90: af00 add r7, sp, #0 8008f92: 60f8 str r0, [r7, #12] 8008f94: 60b9 str r1, [r7, #8] 8008f96: 4613 mov r3, r2 8008f98: 71fb strb r3, [r7, #7] uint8_t prevInt = 0; 8008f9a: 2300 movs r3, #0 8008f9c: 77fb strb r3, [r7, #31] uint8_t currBit; uint8_t index_bit; uint8_t index_byte; uint8_t index_bit_out; uint8_t index_byte_out; int32_t i = 0; 8008f9e: 2300 movs r3, #0 8008fa0: 61bb str r3, [r7, #24] for( i = 0; i < size; i++ ) 8008fa2: 2300 movs r3, #0 8008fa4: 61bb str r3, [r7, #24] 8008fa6: e011 b.n 8008fcc { /* reverse all inputs */ inBuffer[i] = ~inBuffer[i]; 8008fa8: 69bb ldr r3, [r7, #24] 8008faa: 68ba ldr r2, [r7, #8] 8008fac: 4413 add r3, r2 8008fae: 781a ldrb r2, [r3, #0] 8008fb0: 69bb ldr r3, [r7, #24] 8008fb2: 68b9 ldr r1, [r7, #8] 8008fb4: 440b add r3, r1 8008fb6: 43d2 mvns r2, r2 8008fb8: b2d2 uxtb r2, r2 8008fba: 701a strb r2, [r3, #0] /* init outBuffer */ outBuffer[i] = 0; 8008fbc: 69bb ldr r3, [r7, #24] 8008fbe: 68fa ldr r2, [r7, #12] 8008fc0: 4413 add r3, r2 8008fc2: 2200 movs r2, #0 8008fc4: 701a strb r2, [r3, #0] for( i = 0; i < size; i++ ) 8008fc6: 69bb ldr r3, [r7, #24] 8008fc8: 3301 adds r3, #1 8008fca: 61bb str r3, [r7, #24] 8008fcc: 79fb ldrb r3, [r7, #7] 8008fce: 69ba ldr r2, [r7, #24] 8008fd0: 429a cmp r2, r3 8008fd2: dbe9 blt.n 8008fa8 } for( i = 0; i < ( size * 8 ); i++ ) 8008fd4: 2300 movs r3, #0 8008fd6: 61bb str r3, [r7, #24] 8008fd8: e049 b.n 800906e { /* index to take bit in inBuffer */ index_bit = 7 - ( i % 8 ); 8008fda: 69bb ldr r3, [r7, #24] 8008fdc: 425a negs r2, r3 8008fde: f003 0307 and.w r3, r3, #7 8008fe2: f002 0207 and.w r2, r2, #7 8008fe6: bf58 it pl 8008fe8: 4253 negpl r3, r2 8008fea: b2db uxtb r3, r3 8008fec: f1c3 0307 rsb r3, r3, #7 8008ff0: 75fb strb r3, [r7, #23] index_byte = i / 8; 8008ff2: 69bb ldr r3, [r7, #24] 8008ff4: 2b00 cmp r3, #0 8008ff6: da00 bge.n 8008ffa 8008ff8: 3307 adds r3, #7 8008ffa: 10db asrs r3, r3, #3 8008ffc: 75bb strb r3, [r7, #22] /* index to place bit in outBuffer is shifted 1 bit right */ index_bit_out = 7 - ( ( i + 1 ) % 8 ); 8008ffe: 69bb ldr r3, [r7, #24] 8009000: 3301 adds r3, #1 8009002: 425a negs r2, r3 8009004: f003 0307 and.w r3, r3, #7 8009008: f002 0207 and.w r2, r2, #7 800900c: bf58 it pl 800900e: 4253 negpl r3, r2 8009010: b2db uxtb r3, r3 8009012: f1c3 0307 rsb r3, r3, #7 8009016: 757b strb r3, [r7, #21] index_byte_out = ( i + 1 ) / 8; 8009018: 69bb ldr r3, [r7, #24] 800901a: 3301 adds r3, #1 800901c: 2b00 cmp r3, #0 800901e: da00 bge.n 8009022 8009020: 3307 adds r3, #7 8009022: 10db asrs r3, r3, #3 8009024: 753b strb r3, [r7, #20] /* extract current bit from input */ currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01; 8009026: 7dbb ldrb r3, [r7, #22] 8009028: 68ba ldr r2, [r7, #8] 800902a: 4413 add r3, r2 800902c: 781b ldrb r3, [r3, #0] 800902e: 461a mov r2, r3 8009030: 7dfb ldrb r3, [r7, #23] 8009032: fa42 f303 asr.w r3, r2, r3 8009036: b2db uxtb r3, r3 8009038: f003 0301 and.w r3, r3, #1 800903c: 74fb strb r3, [r7, #19] /* integration */ prevInt ^= currBit; 800903e: 7ffa ldrb r2, [r7, #31] 8009040: 7cfb ldrb r3, [r7, #19] 8009042: 4053 eors r3, r2 8009044: 77fb strb r3, [r7, #31] /* write result integration in output */ outBuffer[index_byte_out] |= ( prevInt << index_bit_out ); 8009046: 7d3b ldrb r3, [r7, #20] 8009048: 68fa ldr r2, [r7, #12] 800904a: 4413 add r3, r2 800904c: 781b ldrb r3, [r3, #0] 800904e: b25a sxtb r2, r3 8009050: 7ff9 ldrb r1, [r7, #31] 8009052: 7d7b ldrb r3, [r7, #21] 8009054: fa01 f303 lsl.w r3, r1, r3 8009058: b25b sxtb r3, r3 800905a: 4313 orrs r3, r2 800905c: b259 sxtb r1, r3 800905e: 7d3b ldrb r3, [r7, #20] 8009060: 68fa ldr r2, [r7, #12] 8009062: 4413 add r3, r2 8009064: b2ca uxtb r2, r1 8009066: 701a strb r2, [r3, #0] for( i = 0; i < ( size * 8 ); i++ ) 8009068: 69bb ldr r3, [r7, #24] 800906a: 3301 adds r3, #1 800906c: 61bb str r3, [r7, #24] 800906e: 79fb ldrb r3, [r7, #7] 8009070: 00db lsls r3, r3, #3 8009072: 69ba ldr r2, [r7, #24] 8009074: 429a cmp r2, r3 8009076: dbb0 blt.n 8008fda } outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ; 8009078: f997 301f ldrsb.w r3, [r7, #31] 800907c: 01db lsls r3, r3, #7 800907e: b25a sxtb r2, r3 8009080: f997 301f ldrsb.w r3, [r7, #31] 8009084: 019b lsls r3, r3, #6 8009086: b25b sxtb r3, r3 8009088: 4313 orrs r3, r2 800908a: b25b sxtb r3, r3 800908c: 7ffa ldrb r2, [r7, #31] 800908e: 2a00 cmp r2, #0 8009090: d101 bne.n 8009096 8009092: 2220 movs r2, #32 8009094: e000 b.n 8009098 8009096: 2200 movs r2, #0 8009098: 4313 orrs r3, r2 800909a: b259 sxtb r1, r3 800909c: 79fb ldrb r3, [r7, #7] 800909e: 68fa ldr r2, [r7, #12] 80090a0: 4413 add r3, r2 80090a2: b2ca uxtb r2, r1 80090a4: 701a strb r2, [r3, #0] } 80090a6: bf00 nop 80090a8: 3724 adds r7, #36 @ 0x24 80090aa: 46bd mov sp, r7 80090ac: bc80 pop {r7} 80090ae: 4770 bx lr 080090b0 : #endif /*RADIO_SIGFOX_ENABLE == 1*/ static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous, uint32_t symbTimeout ) { 80090b0: b580 push {r7, lr} 80090b2: b08c sub sp, #48 @ 0x30 80090b4: af00 add r7, sp, #0 80090b6: 60b9 str r1, [r7, #8] 80090b8: 607a str r2, [r7, #4] 80090ba: 603b str r3, [r7, #0] 80090bc: 4603 mov r3, r0 80090be: 73fb strb r3, [r7, #15] #if (RADIO_GENERIC_CONFIG_ENABLE == 1) int32_t status = 0; 80090c0: 2300 movs r3, #0 80090c2: 62bb str r3, [r7, #40] @ 0x28 uint8_t syncword[8] = {0}; 80090c4: f107 0320 add.w r3, r7, #32 80090c8: 2200 movs r2, #0 80090ca: 601a str r2, [r3, #0] 80090cc: 605a str r2, [r3, #4] uint8_t MaxPayloadLength; RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ 80090ce: f002 f88d bl 800b1ec if( rxContinuous != 0 ) 80090d2: 687b ldr r3, [r7, #4] 80090d4: 2b00 cmp r3, #0 80090d6: d001 beq.n 80090dc { symbTimeout = 0; 80090d8: 2300 movs r3, #0 80090da: 603b str r3, [r7, #0] } SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true; 80090dc: 687b ldr r3, [r7, #4] 80090de: 2b00 cmp r3, #0 80090e0: bf14 ite ne 80090e2: 2301 movne r3, #1 80090e4: 2300 moveq r3, #0 80090e6: b2da uxtb r2, r3 80090e8: 4ba3 ldr r3, [pc, #652] @ (8009378 ) 80090ea: 705a strb r2, [r3, #1] switch( modem ) 80090ec: 7bfb ldrb r3, [r7, #15] 80090ee: 2b00 cmp r3, #0 80090f0: d003 beq.n 80090fa 80090f2: 2b01 cmp r3, #1 80090f4: f000 80dc beq.w 80092b0 // Timeout Max, Timeout handled directly in SetRx function SubgRf.RxTimeout = 0xFFFF; break; default: break; 80090f8: e195 b.n 8009426 if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) ) 80090fa: 68bb ldr r3, [r7, #8] 80090fc: 689b ldr r3, [r3, #8] 80090fe: 2b00 cmp r3, #0 8009100: d003 beq.n 800910a 8009102: 68bb ldr r3, [r7, #8] 8009104: 68db ldr r3, [r3, #12] 8009106: 2b00 cmp r3, #0 8009108: d102 bne.n 8009110 return -1; 800910a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800910e: e18b b.n 8009428 if( config->fsk.SyncWordLength > 8 ) 8009110: 68bb ldr r3, [r7, #8] 8009112: 7f9b ldrb r3, [r3, #30] 8009114: 2b08 cmp r3, #8 8009116: d902 bls.n 800911e return -1; 8009118: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800911c: e184 b.n 8009428 RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); 800911e: 68bb ldr r3, [r7, #8] 8009120: 6919 ldr r1, [r3, #16] 8009122: 68bb ldr r3, [r7, #8] 8009124: 7f9b ldrb r3, [r3, #30] 8009126: 461a mov r2, r3 8009128: f107 0320 add.w r3, r7, #32 800912c: 4618 mov r0, r3 800912e: f004 f87d bl 800d22c SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true ); 8009132: 68bb ldr r3, [r7, #8] 8009134: 681b ldr r3, [r3, #0] 8009136: 2b00 cmp r3, #0 8009138: bf14 ite ne 800913a: 2301 movne r3, #1 800913c: 2300 moveq r3, #0 800913e: b2db uxtb r3, r3 8009140: 4618 mov r0, r3 8009142: f000 fe2b bl 8009d9c SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 8009146: 4b8c ldr r3, [pc, #560] @ (8009378 ) 8009148: 2200 movs r2, #0 800914a: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; 800914e: 68bb ldr r3, [r7, #8] 8009150: 689b ldr r3, [r3, #8] 8009152: 4a89 ldr r2, [pc, #548] @ (8009378 ) 8009154: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; 8009156: 68bb ldr r3, [r7, #8] 8009158: f893 2020 ldrb.w r2, [r3, #32] 800915c: 4b86 ldr r3, [pc, #536] @ (8009378 ) 800915e: f883 2044 strb.w r2, [r3, #68] @ 0x44 SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth ); 8009162: 68bb ldr r3, [r7, #8] 8009164: 685b ldr r3, [r3, #4] 8009166: 4618 mov r0, r3 8009168: f001 fd04 bl 800ab74 800916c: 4603 mov r3, r0 800916e: 461a mov r2, r3 8009170: 4b81 ldr r3, [pc, #516] @ (8009378 ) 8009172: f883 2045 strb.w r2, [r3, #69] @ 0x45 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 8009176: 4b80 ldr r3, [pc, #512] @ (8009378 ) 8009178: 2200 movs r2, #0 800917a: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit 800917c: 68bb ldr r3, [r7, #8] 800917e: 68db ldr r3, [r3, #12] 8009180: b29b uxth r3, r3 8009182: 00db lsls r3, r3, #3 8009184: b29a uxth r2, r3 8009186: 4b7c ldr r3, [pc, #496] @ (8009378 ) 8009188: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect; 800918a: 68bb ldr r3, [r7, #8] 800918c: 7fda ldrb r2, [r3, #31] 800918e: 4b7a ldr r3, [pc, #488] @ (8009378 ) 8009190: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit 8009192: 68bb ldr r3, [r7, #8] 8009194: 7f9b ldrb r3, [r3, #30] 8009196: 00db lsls r3, r3, #3 8009198: b2da uxtb r2, r3 800919a: 4b77 ldr r3, [pc, #476] @ (8009378 ) 800919c: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp; 800919e: 68bb ldr r3, [r7, #8] 80091a0: f893 2021 ldrb.w r2, [r3, #33] @ 0x21 80091a4: 4b74 ldr r3, [pc, #464] @ (8009378 ) 80091a6: 751a strb r2, [r3, #20] if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH ) 80091a8: 68bb ldr r3, [r7, #8] 80091aa: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 80091ae: 2b00 cmp r3, #0 80091b0: d105 bne.n 80091be SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength; 80091b2: 68bb ldr r3, [r7, #8] 80091b4: 695b ldr r3, [r3, #20] 80091b6: b2da uxtb r2, r3 80091b8: 4b6f ldr r3, [pc, #444] @ (8009378 ) 80091ba: 759a strb r2, [r3, #22] 80091bc: e00b b.n 80091d6 else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) 80091be: 68bb ldr r3, [r7, #8] 80091c0: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 80091c4: 2b02 cmp r3, #2 80091c6: d103 bne.n 80091d0 SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; 80091c8: 4b6b ldr r3, [pc, #428] @ (8009378 ) 80091ca: 22ff movs r2, #255 @ 0xff 80091cc: 759a strb r2, [r3, #22] 80091ce: e002 b.n 80091d6 SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; 80091d0: 4b69 ldr r3, [pc, #420] @ (8009378 ) 80091d2: 22ff movs r2, #255 @ 0xff 80091d4: 759a strb r2, [r3, #22] if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) 80091d6: 68bb ldr r3, [r7, #8] 80091d8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80091dc: 2b02 cmp r3, #2 80091de: d004 beq.n 80091ea || ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) 80091e0: 68bb ldr r3, [r7, #8] 80091e2: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 80091e6: 2b02 cmp r3, #2 80091e8: d12d bne.n 8009246 if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) 80091ea: 68bb ldr r3, [r7, #8] 80091ec: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 80091f0: 2bf1 cmp r3, #241 @ 0xf1 80091f2: d00c beq.n 800920e 80091f4: 68bb ldr r3, [r7, #8] 80091f6: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 80091fa: 2bf2 cmp r3, #242 @ 0xf2 80091fc: d007 beq.n 800920e && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) 80091fe: 68bb ldr r3, [r7, #8] 8009200: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 8009204: 2b01 cmp r3, #1 8009206: d002 beq.n 800920e return -1; 8009208: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800920c: e10c b.n 8009428 ConfigGeneric.rtx = CONFIG_RX; 800920e: 2300 movs r3, #0 8009210: 773b strb r3, [r7, #28] ConfigGeneric.RxConfig = config; 8009212: 68bb ldr r3, [r7, #8] 8009214: 61bb str r3, [r7, #24] if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) ) 8009216: 4b59 ldr r3, [pc, #356] @ (800937c ) 8009218: 6819 ldr r1, [r3, #0] 800921a: f107 0314 add.w r3, r7, #20 800921e: 4a58 ldr r2, [pc, #352] @ (8009380 ) 8009220: 4618 mov r0, r3 8009222: f001 ff49 bl 800b0b8 8009226: 4603 mov r3, r0 8009228: 2b00 cmp r3, #0 800922a: d002 beq.n 8009232 return -1; 800922c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8009230: e0fa b.n 8009428 SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; 8009232: 4b51 ldr r3, [pc, #324] @ (8009378 ) 8009234: 2200 movs r2, #0 8009236: 761a strb r2, [r3, #24] SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; 8009238: 4b4f ldr r3, [pc, #316] @ (8009378 ) 800923a: 2201 movs r2, #1 800923c: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; 800923e: 4b4e ldr r3, [pc, #312] @ (8009378 ) 8009240: 2200 movs r2, #0 8009242: 755a strb r2, [r3, #21] { 8009244: e00e b.n 8009264 SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; 8009246: 68bb ldr r3, [r7, #8] 8009248: f893 2023 ldrb.w r2, [r3, #35] @ 0x23 800924c: 4b4a ldr r3, [pc, #296] @ (8009378 ) 800924e: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; 8009250: 68bb ldr r3, [r7, #8] 8009252: f893 2024 ldrb.w r2, [r3, #36] @ 0x24 8009256: 4b48 ldr r3, [pc, #288] @ (8009378 ) 8009258: 761a strb r2, [r3, #24] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode; 800925a: 68bb ldr r3, [r7, #8] 800925c: f893 2022 ldrb.w r2, [r3, #34] @ 0x22 8009260: 4b45 ldr r3, [pc, #276] @ (8009378 ) 8009262: 755a strb r2, [r3, #21] RadioStandby( ); 8009264: f7ff fa0d bl 8008682 RadioSetModem( MODEM_FSK ); 8009268: 2000 movs r0, #0 800926a: f7fe fb9b bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 800926e: 4845 ldr r0, [pc, #276] @ (8009384 ) 8009270: f001 f838 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 8009274: 4844 ldr r0, [pc, #272] @ (8009388 ) 8009276: f001 f903 bl 800a480 SUBGRF_SetSyncWord( syncword ); 800927a: f107 0320 add.w r3, r7, #32 800927e: 4618 mov r0, r3 8009280: f000 fbc3 bl 8009a0a SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); 8009284: 68bb ldr r3, [r7, #8] 8009286: 8b9b ldrh r3, [r3, #28] 8009288: 4618 mov r0, r3 800928a: f000 fc0d bl 8009aa8 SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); 800928e: 68bb ldr r3, [r7, #8] 8009290: 8b1b ldrh r3, [r3, #24] 8009292: 4618 mov r0, r3 8009294: f000 fbe8 bl 8009a68 SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate ); 8009298: 683b ldr r3, [r7, #0] 800929a: f44f 52fa mov.w r2, #8000 @ 0x1f40 800929e: fb03 f202 mul.w r2, r3, r2 80092a2: 68bb ldr r3, [r7, #8] 80092a4: 689b ldr r3, [r3, #8] 80092a6: fbb2 f3f3 udiv r3, r2, r3 80092aa: 4a33 ldr r2, [pc, #204] @ (8009378 ) 80092ac: 6093 str r3, [r2, #8] break; 80092ae: e0ba b.n 8009426 if( config->lora.PreambleLen == 0 ) 80092b0: 68bb ldr r3, [r7, #8] 80092b2: 8e1b ldrh r3, [r3, #48] @ 0x30 80092b4: 2b00 cmp r3, #0 80092b6: d102 bne.n 80092be return -1; 80092b8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80092bc: e0b4 b.n 8009428 if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH ) 80092be: 68bb ldr r3, [r7, #8] 80092c0: f893 3032 ldrb.w r3, [r3, #50] @ 0x32 80092c4: 2b01 cmp r3, #1 80092c6: d105 bne.n 80092d4 MaxPayloadLength = config->lora.MaxPayloadLength; 80092c8: 68bb ldr r3, [r7, #8] 80092ca: f893 3033 ldrb.w r3, [r3, #51] @ 0x33 80092ce: f887 302f strb.w r3, [r7, #47] @ 0x2f 80092d2: e002 b.n 80092da MaxPayloadLength = 0xFF; 80092d4: 23ff movs r3, #255 @ 0xff 80092d6: f887 302f strb.w r3, [r7, #47] @ 0x2f SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true ); 80092da: 68bb ldr r3, [r7, #8] 80092dc: 6a9b ldr r3, [r3, #40] @ 0x28 80092de: 2b00 cmp r3, #0 80092e0: bf14 ite ne 80092e2: 2301 movne r3, #1 80092e4: 2300 moveq r3, #0 80092e6: b2db uxtb r3, r3 80092e8: 4618 mov r0, r3 80092ea: f000 fd57 bl 8009d9c SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); 80092ee: 683b ldr r3, [r7, #0] 80092f0: b2db uxtb r3, r3 80092f2: 4618 mov r0, r3 80092f4: f000 fd61 bl 8009dba SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; 80092f8: 4b1f ldr r3, [pc, #124] @ (8009378 ) 80092fa: 2201 movs r2, #1 80092fc: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; 8009300: 68bb ldr r3, [r7, #8] 8009302: f893 202c ldrb.w r2, [r3, #44] @ 0x2c 8009306: 4b1c ldr r3, [pc, #112] @ (8009378 ) 8009308: f883 2050 strb.w r2, [r3, #80] @ 0x50 SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; 800930c: 68bb ldr r3, [r7, #8] 800930e: f893 202d ldrb.w r2, [r3, #45] @ 0x2d 8009312: 4b19 ldr r3, [pc, #100] @ (8009378 ) 8009314: f883 2051 strb.w r2, [r3, #81] @ 0x51 SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; 8009318: 68bb ldr r3, [r7, #8] 800931a: f893 202e ldrb.w r2, [r3, #46] @ 0x2e 800931e: 4b16 ldr r3, [pc, #88] @ (8009378 ) 8009320: f883 2052 strb.w r2, [r3, #82] @ 0x52 switch( config->lora.LowDatarateOptimize ) 8009324: 68bb ldr r3, [r7, #8] 8009326: f893 302f ldrb.w r3, [r3, #47] @ 0x2f 800932a: 2b02 cmp r3, #2 800932c: d010 beq.n 8009350 800932e: 2b02 cmp r3, #2 8009330: dc2c bgt.n 800938c 8009332: 2b00 cmp r3, #0 8009334: d002 beq.n 800933c 8009336: 2b01 cmp r3, #1 8009338: d005 beq.n 8009346 break; 800933a: e027 b.n 800938c SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; 800933c: 4b0e ldr r3, [pc, #56] @ (8009378 ) 800933e: 2200 movs r2, #0 8009340: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 8009344: e023 b.n 800938e SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; 8009346: 4b0c ldr r3, [pc, #48] @ (8009378 ) 8009348: 2201 movs r2, #1 800934a: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 800934e: e01e b.n 800938e if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) 8009350: 68bb ldr r3, [r7, #8] 8009352: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8009356: 2b0b cmp r3, #11 8009358: d004 beq.n 8009364 800935a: 68bb ldr r3, [r7, #8] 800935c: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8009360: 2b0c cmp r3, #12 8009362: d104 bne.n 800936e SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; 8009364: 4b04 ldr r3, [pc, #16] @ (8009378 ) 8009366: 2201 movs r2, #1 8009368: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 800936c: e00f b.n 800938e SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; 800936e: 4b02 ldr r3, [pc, #8] @ (8009378 ) 8009370: 2200 movs r2, #0 8009372: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 8009376: e00a b.n 800938e 8009378: 20000300 .word 0x20000300 800937c: 200002fc .word 0x200002fc 8009380: 20000374 .word 0x20000374 8009384: 20000338 .word 0x20000338 8009388: 2000030e .word 0x2000030e break; 800938c: bf00 nop SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; 800938e: 4b28 ldr r3, [pc, #160] @ (8009430 ) 8009390: 2201 movs r2, #1 8009392: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; 8009394: 68bb ldr r3, [r7, #8] 8009396: 8e1a ldrh r2, [r3, #48] @ 0x30 8009398: 4b25 ldr r3, [pc, #148] @ (8009430 ) 800939a: 839a strh r2, [r3, #28] SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; 800939c: 68bb ldr r3, [r7, #8] 800939e: f893 2032 ldrb.w r2, [r3, #50] @ 0x32 80093a2: 4b23 ldr r3, [pc, #140] @ (8009430 ) 80093a4: 779a strb r2, [r3, #30] SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; 80093a6: 4a22 ldr r2, [pc, #136] @ (8009430 ) 80093a8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80093ac: 77d3 strb r3, [r2, #31] SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; 80093ae: 68bb ldr r3, [r7, #8] 80093b0: f893 2034 ldrb.w r2, [r3, #52] @ 0x34 80093b4: 4b1e ldr r3, [pc, #120] @ (8009430 ) 80093b6: f883 2020 strb.w r2, [r3, #32] SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; 80093ba: 68bb ldr r3, [r7, #8] 80093bc: f893 2035 ldrb.w r2, [r3, #53] @ 0x35 80093c0: 4b1b ldr r3, [pc, #108] @ (8009430 ) 80093c2: f883 2021 strb.w r2, [r3, #33] @ 0x21 RadioStandby( ); 80093c6: f7ff f95c bl 8008682 RadioSetModem( MODEM_LORA ); 80093ca: 2001 movs r0, #1 80093cc: f7fe faea bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 80093d0: 4818 ldr r0, [pc, #96] @ (8009434 ) 80093d2: f000 ff87 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80093d6: 4818 ldr r0, [pc, #96] @ (8009438 ) 80093d8: f001 f852 bl 800a480 if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) 80093dc: 4b14 ldr r3, [pc, #80] @ (8009430 ) 80093de: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80093e2: 2b01 cmp r3, #1 80093e4: d10d bne.n 8009402 SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); 80093e6: f240 7036 movw r0, #1846 @ 0x736 80093ea: f001 f9b1 bl 800a750 80093ee: 4603 mov r3, r0 80093f0: f023 0304 bic.w r3, r3, #4 80093f4: b2db uxtb r3, r3 80093f6: 4619 mov r1, r3 80093f8: f240 7036 movw r0, #1846 @ 0x736 80093fc: f001 f986 bl 800a70c 8009400: e00c b.n 800941c SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); 8009402: f240 7036 movw r0, #1846 @ 0x736 8009406: f001 f9a3 bl 800a750 800940a: 4603 mov r3, r0 800940c: f043 0304 orr.w r3, r3, #4 8009410: b2db uxtb r3, r3 8009412: 4619 mov r1, r3 8009414: f240 7036 movw r0, #1846 @ 0x736 8009418: f001 f978 bl 800a70c SubgRf.RxTimeout = 0xFFFF; 800941c: 4b04 ldr r3, [pc, #16] @ (8009430 ) 800941e: f64f 72ff movw r2, #65535 @ 0xffff 8009422: 609a str r2, [r3, #8] break; 8009424: bf00 nop } return status; 8009426: 6abb ldr r3, [r7, #40] @ 0x28 #else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ return -1; #endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ } 8009428: 4618 mov r0, r3 800942a: 3730 adds r7, #48 @ 0x30 800942c: 46bd mov sp, r7 800942e: bd80 pop {r7, pc} 8009430: 20000300 .word 0x20000300 8009434: 20000338 .word 0x20000338 8009438: 2000030e .word 0x2000030e 0800943c : static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power, uint32_t timeout ) { 800943c: b580 push {r7, lr} 800943e: b08e sub sp, #56 @ 0x38 8009440: af00 add r7, sp, #0 8009442: 60b9 str r1, [r7, #8] 8009444: 607b str r3, [r7, #4] 8009446: 4603 mov r3, r0 8009448: 73fb strb r3, [r7, #15] 800944a: 4613 mov r3, r2 800944c: 73bb strb r3, [r7, #14] #if( RADIO_LR_FHSS_IS_ON == 1 ) /*disable LrFhss*/ SubgRf.lr_fhss.is_lr_fhss_on = false; #endif /* RADIO_LR_FHSS_IS_ON == 1 */ #if (RADIO_GENERIC_CONFIG_ENABLE == 1) uint8_t syncword[8] = {0}; 800944e: f107 032c add.w r3, r7, #44 @ 0x2c 8009452: 2200 movs r2, #0 8009454: 601a str r2, [r3, #0] 8009456: 605a str r2, [r3, #4] RadioModems_t radio_modem; RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ 8009458: f001 fec8 bl 800b1ec switch( modem ) 800945c: 7bfb ldrb r3, [r7, #15] 800945e: 2b03 cmp r3, #3 8009460: f200 8205 bhi.w 800986e 8009464: a201 add r2, pc, #4 @ (adr r2, 800946c ) 8009466: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800946a: bf00 nop 800946c: 080095f1 .word 0x080095f1 8009470: 08009739 .word 0x08009739 8009474: 08009831 .word 0x08009831 8009478: 0800947d .word 0x0800947d { case GENERIC_MSK: if( config->msk.SyncWordLength > 8 ) 800947c: 68bb ldr r3, [r7, #8] 800947e: 7c9b ldrb r3, [r3, #18] 8009480: 2b08 cmp r3, #8 8009482: d902 bls.n 800948a { return -1; 8009484: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8009488: e206 b.n 8009898 } else { RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength ); 800948a: 68bb ldr r3, [r7, #8] 800948c: 6899 ldr r1, [r3, #8] 800948e: 68bb ldr r3, [r7, #8] 8009490: 7c9b ldrb r3, [r3, #18] 8009492: 461a mov r2, r3 8009494: f107 032c add.w r3, r7, #44 @ 0x2c 8009498: 4618 mov r0, r3 800949a: f003 fec7 bl 800d22c } if( ( config->msk.BitRate == 0 ) ) 800949e: 68bb ldr r3, [r7, #8] 80094a0: 681b ldr r3, [r3, #0] 80094a2: 2b00 cmp r3, #0 80094a4: d102 bne.n 80094ac { return -1; 80094a6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80094aa: e1f5 b.n 8009898 } else if( config->msk.BitRate <= 10000 ) 80094ac: 68bb ldr r3, [r7, #8] 80094ae: 681b ldr r3, [r3, #0] 80094b0: f242 7210 movw r2, #10000 @ 0x2710 80094b4: 4293 cmp r3, r2 80094b6: d813 bhi.n 80094e0 { /*max msk modulator datarate is 10kbps*/ radio_modem = MODEM_MSK; 80094b8: 2302 movs r3, #2 80094ba: f887 3037 strb.w r3, [r7, #55] @ 0x37 SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK; 80094be: 4b99 ldr r3, [pc, #612] @ (8009724 ) 80094c0: 2203 movs r2, #3 80094c2: 739a strb r2, [r3, #14] SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK; 80094c4: 4b97 ldr r3, [pc, #604] @ (8009724 ) 80094c6: 2203 movs r2, #3 80094c8: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; 80094cc: 68bb ldr r3, [r7, #8] 80094ce: 681b ldr r3, [r3, #0] 80094d0: 4a94 ldr r2, [pc, #592] @ (8009724 ) 80094d2: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; 80094d4: 68bb ldr r3, [r7, #8] 80094d6: 7cda ldrb r2, [r3, #19] 80094d8: 4b92 ldr r3, [pc, #584] @ (8009724 ) 80094da: f883 2044 strb.w r2, [r3, #68] @ 0x44 80094de: e017 b.n 8009510 } else { radio_modem = MODEM_FSK; 80094e0: 2300 movs r3, #0 80094e2: f887 3037 strb.w r3, [r7, #55] @ 0x37 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 80094e6: 4b8f ldr r3, [pc, #572] @ (8009724 ) 80094e8: 2200 movs r2, #0 80094ea: 739a strb r2, [r3, #14] SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 80094ec: 4b8d ldr r3, [pc, #564] @ (8009724 ) 80094ee: 2200 movs r2, #0 80094f0: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; 80094f4: 68bb ldr r3, [r7, #8] 80094f6: 681b ldr r3, [r3, #0] 80094f8: 4a8a ldr r2, [pc, #552] @ (8009724 ) 80094fa: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; 80094fc: 68bb ldr r3, [r7, #8] 80094fe: 7cda ldrb r2, [r3, #19] 8009500: 4b88 ldr r3, [pc, #544] @ (8009724 ) 8009502: f883 2044 strb.w r2, [r3, #68] @ 0x44 /*do msk with gfsk modulator*/ SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4; 8009506: 68bb ldr r3, [r7, #8] 8009508: 681b ldr r3, [r3, #0] 800950a: 089b lsrs r3, r3, #2 800950c: 4a85 ldr r2, [pc, #532] @ (8009724 ) 800950e: 6413 str r3, [r2, #64] @ 0x40 } SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit 8009510: 68bb ldr r3, [r7, #8] 8009512: 685b ldr r3, [r3, #4] 8009514: b29b uxth r3, r3 8009516: 00db lsls r3, r3, #3 8009518: b29a uxth r2, r3 800951a: 4b82 ldr r3, [pc, #520] @ (8009724 ) 800951c: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx 800951e: 4b81 ldr r3, [pc, #516] @ (8009724 ) 8009520: 2204 movs r2, #4 8009522: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit 8009524: 68bb ldr r3, [r7, #8] 8009526: 7c9b ldrb r3, [r3, #18] 8009528: 00db lsls r3, r3, #3 800952a: b2da uxtb r2, r3 800952c: 4b7d ldr r3, [pc, #500] @ (8009724 ) 800952e: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx 8009530: 4b7c ldr r3, [pc, #496] @ (8009724 ) 8009532: 2200 movs r2, #0 8009534: 751a strb r2, [r3, #20] if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) 8009536: 68bb ldr r3, [r7, #8] 8009538: 7d9b ldrb r3, [r3, #22] 800953a: 2b02 cmp r3, #2 800953c: d003 beq.n 8009546 || ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) 800953e: 68bb ldr r3, [r7, #8] 8009540: 7d1b ldrb r3, [r3, #20] 8009542: 2b02 cmp r3, #2 8009544: d12b bne.n 800959e { /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) 8009546: 68bb ldr r3, [r7, #8] 8009548: 7d5b ldrb r3, [r3, #21] 800954a: 2bf1 cmp r3, #241 @ 0xf1 800954c: d00a beq.n 8009564 800954e: 68bb ldr r3, [r7, #8] 8009550: 7d5b ldrb r3, [r3, #21] 8009552: 2bf2 cmp r3, #242 @ 0xf2 8009554: d006 beq.n 8009564 && ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) ) 8009556: 68bb ldr r3, [r7, #8] 8009558: 7d5b ldrb r3, [r3, #21] 800955a: 2b01 cmp r3, #1 800955c: d002 beq.n 8009564 { return -1; 800955e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8009562: e199 b.n 8009898 } ConfigGeneric_t ConfigGeneric; /*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/ ConfigGeneric.TxConfig = config; 8009564: 68bb ldr r3, [r7, #8] 8009566: 623b str r3, [r7, #32] ConfigGeneric.rtx = CONFIG_TX; 8009568: 2301 movs r3, #1 800956a: f887 3028 strb.w r3, [r7, #40] @ 0x28 if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) 800956e: 4b6e ldr r3, [pc, #440] @ (8009728 ) 8009570: 6819 ldr r1, [r3, #0] 8009572: f107 0320 add.w r3, r7, #32 8009576: 4a6d ldr r2, [pc, #436] @ (800972c ) 8009578: 4618 mov r0, r3 800957a: f001 fd9d bl 800b0b8 800957e: 4603 mov r3, r0 8009580: 2b00 cmp r3, #0 8009582: d002 beq.n 800958a { return -1; 8009584: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8009588: e186 b.n 8009898 } /* whitening off, will be processed by FW, switch off built-in radio whitening */ SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; 800958a: 4b66 ldr r3, [pc, #408] @ (8009724 ) 800958c: 2200 movs r2, #0 800958e: 761a strb r2, [r3, #24] /* Crc processed by FW, switch off built-in radio Crc */ SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; 8009590: 4b64 ldr r3, [pc, #400] @ (8009724 ) 8009592: 2201 movs r2, #1 8009594: 75da strb r2, [r3, #23] /* length contained in Tx, but will be processed by FW after de-whitening */ SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; 8009596: 4b63 ldr r3, [pc, #396] @ (8009724 ) 8009598: 2200 movs r2, #0 800959a: 755a strb r2, [r3, #21] { 800959c: e00b b.n 80095b6 } else { SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength; 800959e: 68bb ldr r3, [r7, #8] 80095a0: 7d5a ldrb r2, [r3, #21] 80095a2: 4b60 ldr r3, [pc, #384] @ (8009724 ) 80095a4: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening; 80095a6: 68bb ldr r3, [r7, #8] 80095a8: 7d9a ldrb r2, [r3, #22] 80095aa: 4b5e ldr r3, [pc, #376] @ (8009724 ) 80095ac: 761a strb r2, [r3, #24] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType; 80095ae: 68bb ldr r3, [r7, #8] 80095b0: 7d1a ldrb r2, [r3, #20] 80095b2: 4b5c ldr r3, [pc, #368] @ (8009724 ) 80095b4: 755a strb r2, [r3, #21] } RadioStandby( ); 80095b6: f7ff f864 bl 8008682 RadioSetModem( radio_modem ); 80095ba: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80095be: 4618 mov r0, r3 80095c0: f7fe f9f0 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 80095c4: 485a ldr r0, [pc, #360] @ (8009730 ) 80095c6: f000 fe8d bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80095ca: 485a ldr r0, [pc, #360] @ (8009734 ) 80095cc: f000 ff58 bl 800a480 SUBGRF_SetSyncWord( syncword ); 80095d0: f107 032c add.w r3, r7, #44 @ 0x2c 80095d4: 4618 mov r0, r3 80095d6: f000 fa18 bl 8009a0a SUBGRF_SetWhiteningSeed( config->msk.whiteSeed ); 80095da: 68bb ldr r3, [r7, #8] 80095dc: 8a1b ldrh r3, [r3, #16] 80095de: 4618 mov r0, r3 80095e0: f000 fa62 bl 8009aa8 SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial ); 80095e4: 68bb ldr r3, [r7, #8] 80095e6: 899b ldrh r3, [r3, #12] 80095e8: 4618 mov r0, r3 80095ea: f000 fa3d bl 8009a68 break; 80095ee: e13f b.n 8009870 case GENERIC_FSK: if( config->fsk.BitRate == 0 ) 80095f0: 68bb ldr r3, [r7, #8] 80095f2: 681b ldr r3, [r3, #0] 80095f4: 2b00 cmp r3, #0 80095f6: d102 bne.n 80095fe { return -1; 80095f8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80095fc: e14c b.n 8009898 } if( config->fsk.SyncWordLength > 8 ) 80095fe: 68bb ldr r3, [r7, #8] 8009600: 7c9b ldrb r3, [r3, #18] 8009602: 2b08 cmp r3, #8 8009604: d902 bls.n 800960c { return -1; 8009606: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800960a: e145 b.n 8009898 } else { RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); 800960c: 68bb ldr r3, [r7, #8] 800960e: 6899 ldr r1, [r3, #8] 8009610: 68bb ldr r3, [r7, #8] 8009612: 7c9b ldrb r3, [r3, #18] 8009614: 461a mov r2, r3 8009616: f107 032c add.w r3, r7, #44 @ 0x2c 800961a: 4618 mov r0, r3 800961c: f003 fe06 bl 800d22c } SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; 8009620: 4b40 ldr r3, [pc, #256] @ (8009724 ) 8009622: 2200 movs r2, #0 8009624: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; 8009628: 68bb ldr r3, [r7, #8] 800962a: 681b ldr r3, [r3, #0] 800962c: 4a3d ldr r2, [pc, #244] @ (8009724 ) 800962e: 63d3 str r3, [r2, #60] @ 0x3c SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; 8009630: 68bb ldr r3, [r7, #8] 8009632: 7cda ldrb r2, [r3, #19] 8009634: 4b3b ldr r3, [pc, #236] @ (8009724 ) 8009636: f883 2044 strb.w r2, [r3, #68] @ 0x44 SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation; 800963a: 68bb ldr r3, [r7, #8] 800963c: 699b ldr r3, [r3, #24] 800963e: 4a39 ldr r2, [pc, #228] @ (8009724 ) 8009640: 6413 str r3, [r2, #64] @ 0x40 SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; 8009642: 4b38 ldr r3, [pc, #224] @ (8009724 ) 8009644: 2200 movs r2, #0 8009646: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit 8009648: 68bb ldr r3, [r7, #8] 800964a: 685b ldr r3, [r3, #4] 800964c: b29b uxth r3, r3 800964e: 00db lsls r3, r3, #3 8009650: b29a uxth r2, r3 8009652: 4b34 ldr r3, [pc, #208] @ (8009724 ) 8009654: 821a strh r2, [r3, #16] SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx 8009656: 4b33 ldr r3, [pc, #204] @ (8009724 ) 8009658: 2204 movs r2, #4 800965a: 749a strb r2, [r3, #18] SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit 800965c: 68bb ldr r3, [r7, #8] 800965e: 7c9b ldrb r3, [r3, #18] 8009660: 00db lsls r3, r3, #3 8009662: b2da uxtb r2, r3 8009664: 4b2f ldr r3, [pc, #188] @ (8009724 ) 8009666: 74da strb r2, [r3, #19] SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx 8009668: 4b2e ldr r3, [pc, #184] @ (8009724 ) 800966a: 2200 movs r2, #0 800966c: 751a strb r2, [r3, #20] if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) 800966e: 68bb ldr r3, [r7, #8] 8009670: 7d9b ldrb r3, [r3, #22] 8009672: 2b02 cmp r3, #2 8009674: d003 beq.n 800967e || ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) 8009676: 68bb ldr r3, [r7, #8] 8009678: 7d1b ldrb r3, [r3, #20] 800967a: 2b02 cmp r3, #2 800967c: d12a bne.n 80096d4 { /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) 800967e: 68bb ldr r3, [r7, #8] 8009680: 7d5b ldrb r3, [r3, #21] 8009682: 2bf1 cmp r3, #241 @ 0xf1 8009684: d00a beq.n 800969c 8009686: 68bb ldr r3, [r7, #8] 8009688: 7d5b ldrb r3, [r3, #21] 800968a: 2bf2 cmp r3, #242 @ 0xf2 800968c: d006 beq.n 800969c && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) 800968e: 68bb ldr r3, [r7, #8] 8009690: 7d5b ldrb r3, [r3, #21] 8009692: 2b01 cmp r3, #1 8009694: d002 beq.n 800969c { return -1; 8009696: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800969a: e0fd b.n 8009898 } ConfigGeneric_t ConfigGeneric; ConfigGeneric.rtx = CONFIG_TX; 800969c: 2301 movs r3, #1 800969e: 773b strb r3, [r7, #28] ConfigGeneric.TxConfig = config; 80096a0: 68bb ldr r3, [r7, #8] 80096a2: 617b str r3, [r7, #20] if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) 80096a4: 4b20 ldr r3, [pc, #128] @ (8009728 ) 80096a6: 6819 ldr r1, [r3, #0] 80096a8: f107 0314 add.w r3, r7, #20 80096ac: 4a1f ldr r2, [pc, #124] @ (800972c ) 80096ae: 4618 mov r0, r3 80096b0: f001 fd02 bl 800b0b8 80096b4: 4603 mov r3, r0 80096b6: 2b00 cmp r3, #0 80096b8: d002 beq.n 80096c0 { return -1; 80096ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80096be: e0eb b.n 8009898 } /* whitening off, will be processed by FW, switch off built-in radio whitening */ SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; 80096c0: 4b18 ldr r3, [pc, #96] @ (8009724 ) 80096c2: 2200 movs r2, #0 80096c4: 761a strb r2, [r3, #24] /* Crc processed by FW, switch off built-in radio Crc */ SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; 80096c6: 4b17 ldr r3, [pc, #92] @ (8009724 ) 80096c8: 2201 movs r2, #1 80096ca: 75da strb r2, [r3, #23] /* length contained in Tx, but will be processed by FW after de-whitening */ SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; 80096cc: 4b15 ldr r3, [pc, #84] @ (8009724 ) 80096ce: 2200 movs r2, #0 80096d0: 755a strb r2, [r3, #21] { 80096d2: e00b b.n 80096ec } else { SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; 80096d4: 68bb ldr r3, [r7, #8] 80096d6: 7d5a ldrb r2, [r3, #21] 80096d8: 4b12 ldr r3, [pc, #72] @ (8009724 ) 80096da: 75da strb r2, [r3, #23] SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; 80096dc: 68bb ldr r3, [r7, #8] 80096de: 7d9a ldrb r2, [r3, #22] 80096e0: 4b10 ldr r3, [pc, #64] @ (8009724 ) 80096e2: 761a strb r2, [r3, #24] SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType; 80096e4: 68bb ldr r3, [r7, #8] 80096e6: 7d1a ldrb r2, [r3, #20] 80096e8: 4b0e ldr r3, [pc, #56] @ (8009724 ) 80096ea: 755a strb r2, [r3, #21] } RadioStandby( ); 80096ec: f7fe ffc9 bl 8008682 RadioSetModem( MODEM_FSK ); 80096f0: 2000 movs r0, #0 80096f2: f7fe f957 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 80096f6: 480e ldr r0, [pc, #56] @ (8009730 ) 80096f8: f000 fdf4 bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80096fc: 480d ldr r0, [pc, #52] @ (8009734 ) 80096fe: f000 febf bl 800a480 SUBGRF_SetSyncWord( syncword ); 8009702: f107 032c add.w r3, r7, #44 @ 0x2c 8009706: 4618 mov r0, r3 8009708: f000 f97f bl 8009a0a SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); 800970c: 68bb ldr r3, [r7, #8] 800970e: 8a1b ldrh r3, [r3, #16] 8009710: 4618 mov r0, r3 8009712: f000 f9c9 bl 8009aa8 SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); 8009716: 68bb ldr r3, [r7, #8] 8009718: 899b ldrh r3, [r3, #12] 800971a: 4618 mov r0, r3 800971c: f000 f9a4 bl 8009a68 break; 8009720: e0a6 b.n 8009870 8009722: bf00 nop 8009724: 20000300 .word 0x20000300 8009728: 200002fc .word 0x200002fc 800972c: 2000035c .word 0x2000035c 8009730: 20000338 .word 0x20000338 8009734: 2000030e .word 0x2000030e case GENERIC_LORA: SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; 8009738: 4b59 ldr r3, [pc, #356] @ (80098a0 ) 800973a: 2201 movs r2, #1 800973c: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; 8009740: 68bb ldr r3, [r7, #8] 8009742: 781a ldrb r2, [r3, #0] 8009744: 4b56 ldr r3, [pc, #344] @ (80098a0 ) 8009746: f883 2050 strb.w r2, [r3, #80] @ 0x50 SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; 800974a: 68bb ldr r3, [r7, #8] 800974c: 785a ldrb r2, [r3, #1] 800974e: 4b54 ldr r3, [pc, #336] @ (80098a0 ) 8009750: f883 2051 strb.w r2, [r3, #81] @ 0x51 SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; 8009754: 68bb ldr r3, [r7, #8] 8009756: 789a ldrb r2, [r3, #2] 8009758: 4b51 ldr r3, [pc, #324] @ (80098a0 ) 800975a: f883 2052 strb.w r2, [r3, #82] @ 0x52 switch( config->lora.LowDatarateOptimize ) 800975e: 68bb ldr r3, [r7, #8] 8009760: 78db ldrb r3, [r3, #3] 8009762: 2b02 cmp r3, #2 8009764: d010 beq.n 8009788 8009766: 2b02 cmp r3, #2 8009768: dc20 bgt.n 80097ac 800976a: 2b00 cmp r3, #0 800976c: d002 beq.n 8009774 800976e: 2b01 cmp r3, #1 8009770: d005 beq.n 800977e { SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; } break; default: break; 8009772: e01b b.n 80097ac SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; 8009774: 4b4a ldr r3, [pc, #296] @ (80098a0 ) 8009776: 2200 movs r2, #0 8009778: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 800977c: e017 b.n 80097ae SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; 800977e: 4b48 ldr r3, [pc, #288] @ (80098a0 ) 8009780: 2201 movs r2, #1 8009782: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 8009786: e012 b.n 80097ae if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) 8009788: 68bb ldr r3, [r7, #8] 800978a: 781b ldrb r3, [r3, #0] 800978c: 2b0b cmp r3, #11 800978e: d003 beq.n 8009798 8009790: 68bb ldr r3, [r7, #8] 8009792: 781b ldrb r3, [r3, #0] 8009794: 2b0c cmp r3, #12 8009796: d104 bne.n 80097a2 SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; 8009798: 4b41 ldr r3, [pc, #260] @ (80098a0 ) 800979a: 2201 movs r2, #1 800979c: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 80097a0: e005 b.n 80097ae SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; 80097a2: 4b3f ldr r3, [pc, #252] @ (80098a0 ) 80097a4: 2200 movs r2, #0 80097a6: f883 2053 strb.w r2, [r3, #83] @ 0x53 break; 80097aa: e000 b.n 80097ae break; 80097ac: bf00 nop } SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; 80097ae: 4b3c ldr r3, [pc, #240] @ (80098a0 ) 80097b0: 2201 movs r2, #1 80097b2: 739a strb r2, [r3, #14] SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; 80097b4: 68bb ldr r3, [r7, #8] 80097b6: 889a ldrh r2, [r3, #4] 80097b8: 4b39 ldr r3, [pc, #228] @ (80098a0 ) 80097ba: 839a strh r2, [r3, #28] SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; 80097bc: 68bb ldr r3, [r7, #8] 80097be: 799a ldrb r2, [r3, #6] 80097c0: 4b37 ldr r3, [pc, #220] @ (80098a0 ) 80097c2: 779a strb r2, [r3, #30] SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; 80097c4: 68bb ldr r3, [r7, #8] 80097c6: 79da ldrb r2, [r3, #7] 80097c8: 4b35 ldr r3, [pc, #212] @ (80098a0 ) 80097ca: f883 2020 strb.w r2, [r3, #32] SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; 80097ce: 68bb ldr r3, [r7, #8] 80097d0: 7a1a ldrb r2, [r3, #8] 80097d2: 4b33 ldr r3, [pc, #204] @ (80098a0 ) 80097d4: f883 2021 strb.w r2, [r3, #33] @ 0x21 RadioStandby( ); 80097d8: f7fe ff53 bl 8008682 RadioSetModem( MODEM_LORA ); 80097dc: 2001 movs r0, #1 80097de: f7fe f8e1 bl 80079a4 SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 80097e2: 4830 ldr r0, [pc, #192] @ (80098a4 ) 80097e4: f000 fd7e bl 800a2e4 SUBGRF_SetPacketParams( &SubgRf.PacketParams ); 80097e8: 482f ldr r0, [pc, #188] @ (80098a8 ) 80097ea: f000 fe49 bl 800a480 /* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */ if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) 80097ee: 4b2c ldr r3, [pc, #176] @ (80098a0 ) 80097f0: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 80097f4: 2b06 cmp r3, #6 80097f6: d10d bne.n 8009814 { // RegTxModulation = @address 0x0889 SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); 80097f8: f640 0089 movw r0, #2185 @ 0x889 80097fc: f000 ffa8 bl 800a750 8009800: 4603 mov r3, r0 8009802: f023 0304 bic.w r3, r3, #4 8009806: b2db uxtb r3, r3 8009808: 4619 mov r1, r3 800980a: f640 0089 movw r0, #2185 @ 0x889 800980e: f000 ff7d bl 800a70c { // RegTxModulation = @address 0x0889 SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); } /* WORKAROUND END */ break; 8009812: e02d b.n 8009870 SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); 8009814: f640 0089 movw r0, #2185 @ 0x889 8009818: f000 ff9a bl 800a750 800981c: 4603 mov r3, r0 800981e: f043 0304 orr.w r3, r3, #4 8009822: b2db uxtb r3, r3 8009824: 4619 mov r1, r3 8009826: f640 0089 movw r0, #2185 @ 0x889 800982a: f000 ff6f bl 800a70c break; 800982e: e01f b.n 8009870 case GENERIC_BPSK: if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) ) 8009830: 68bb ldr r3, [r7, #8] 8009832: 681b ldr r3, [r3, #0] 8009834: 2b00 cmp r3, #0 8009836: d004 beq.n 8009842 8009838: 68bb ldr r3, [r7, #8] 800983a: 681b ldr r3, [r3, #0] 800983c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8009840: d902 bls.n 8009848 { return -1; 8009842: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8009846: e027 b.n 8009898 } RadioSetModem( MODEM_BPSK ); 8009848: 2003 movs r0, #3 800984a: f7fe f8ab bl 80079a4 SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; 800984e: 4b14 ldr r3, [pc, #80] @ (80098a0 ) 8009850: 2202 movs r2, #2 8009852: f883 2038 strb.w r2, [r3, #56] @ 0x38 SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate; 8009856: 68bb ldr r3, [r7, #8] 8009858: 681b ldr r3, [r3, #0] 800985a: 4a11 ldr r2, [pc, #68] @ (80098a0 ) 800985c: 6493 str r3, [r2, #72] @ 0x48 SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; 800985e: 4b10 ldr r3, [pc, #64] @ (80098a0 ) 8009860: 2216 movs r2, #22 8009862: f883 204c strb.w r2, [r3, #76] @ 0x4c SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); 8009866: 480f ldr r0, [pc, #60] @ (80098a4 ) 8009868: f000 fd3c bl 800a2e4 break; 800986c: e000 b.n 8009870 default: break; 800986e: bf00 nop } SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); 8009870: f997 300e ldrsb.w r3, [r7, #14] 8009874: 4618 mov r0, r3 8009876: f001 f87f bl 800a978 800987a: 4603 mov r3, r0 800987c: 461a mov r2, r3 800987e: 4b08 ldr r3, [pc, #32] @ (80098a0 ) 8009880: f883 2056 strb.w r2, [r3, #86] @ 0x56 RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); 8009884: 4b06 ldr r3, [pc, #24] @ (80098a0 ) 8009886: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 800988a: 4618 mov r0, r3 800988c: f001 fcce bl 800b22c SubgRf.TxTimeout = timeout; 8009890: 4a03 ldr r2, [pc, #12] @ (80098a0 ) 8009892: 687b ldr r3, [r7, #4] 8009894: 6053 str r3, [r2, #4] return 0; 8009896: 2300 movs r3, #0 #else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ return -1; #endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ } 8009898: 4618 mov r0, r3 800989a: 3738 adds r7, #56 @ 0x38 800989c: 46bd mov sp, r7 800989e: bd80 pop {r7, pc} 80098a0: 20000300 .word 0x20000300 80098a4: 20000338 .word 0x20000338 80098a8: 2000030e .word 0x2000030e 080098ac : return ( prbs31_val - 1 ) % ( max ); } #endif /* RADIO_LR_FHSS_IS_ON == 1 */ static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ) { 80098ac: b480 push {r7} 80098ae: b085 sub sp, #20 80098b0: af00 add r7, sp, #0 80098b2: 6078 str r0, [r7, #4] radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE; 80098b4: 2301 movs r3, #1 80098b6: 73fb strb r3, [r7, #15] { return status; } SubgRf.lr_fhss.is_lr_fhss_on = true; #endif /* RADIO_LR_FHSS_IS_ON == 1 */ return status; 80098b8: 7bfb ldrb r3, [r7, #15] } 80098ba: 4618 mov r0, r3 80098bc: 3714 adds r7, #20 80098be: 46bd mov sp, r7 80098c0: bc80 pop {r7} 80098c2: 4770 bx lr 080098c4 : static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, uint32_t *time_on_air_in_ms ) { 80098c4: b480 push {r7} 80098c6: b083 sub sp, #12 80098c8: af00 add r7, sp, #0 80098ca: 6078 str r0, [r7, #4] 80098cc: 6039 str r1, [r7, #0] *time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params, params->pld_len_in_bytes ); return RADIO_STATUS_OK; #else return RADIO_STATUS_UNSUPPORTED_FEATURE; 80098ce: 2301 movs r3, #1 #endif /* RADIO_LR_FHSS_IS_ON */ 80098d0: 4618 mov r0, r3 80098d2: 370c adds r7, #12 80098d4: 46bd mov sp, r7 80098d6: bc80 pop {r7} 80098d8: 4770 bx lr ... 080098dc : */ static DioIrqHandler RadioOnDioIrqCb; /* Exported functions ---------------------------------------------------------*/ void SUBGRF_Init( DioIrqHandler dioIrq ) { 80098dc: b580 push {r7, lr} 80098de: b084 sub sp, #16 80098e0: af00 add r7, sp, #0 80098e2: 6078 str r0, [r7, #4] if ( dioIrq != NULL) 80098e4: 687b ldr r3, [r7, #4] 80098e6: 2b00 cmp r3, #0 80098e8: d002 beq.n 80098f0 { RadioOnDioIrqCb = dioIrq; 80098ea: 4a1d ldr r2, [pc, #116] @ (8009960 ) 80098ec: 687b ldr r3, [r7, #4] 80098ee: 6013 str r3, [r2, #0] } RADIO_INIT(); 80098f0: f7f7 f8f8 bl 8000ae4 /* set default SMPS current drive to default*/ Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); 80098f4: 2002 movs r0, #2 80098f6: f001 f91b bl 800ab30 ImageCalibrated = false; 80098fa: 4b1a ldr r3, [pc, #104] @ (8009964 ) 80098fc: 2200 movs r2, #0 80098fe: 701a strb r2, [r3, #0] SUBGRF_SetStandby( STDBY_RC ); 8009900: 2000 movs r0, #0 8009902: f000 f97f bl 8009c04 // Initialize TCXO control if (1U == RBI_IsTCXO() ) 8009906: f003 fbcf bl 800d0a8 800990a: 4603 mov r3, r0 800990c: 2b01 cmp r3, #1 800990e: d10e bne.n 800992e { SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms 8009910: 2140 movs r1, #64 @ 0x40 8009912: 2001 movs r0, #1 8009914: f000 fb8a bl 800a02c SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 ); 8009918: 2100 movs r1, #0 800991a: f640 1011 movw r0, #2321 @ 0x911 800991e: f000 fef5 bl 800a70c /*enable calibration for cut1.1 and later*/ CalibrationParams_t calibParam; calibParam.Value = 0x7F; 8009922: 237f movs r3, #127 @ 0x7f 8009924: 733b strb r3, [r7, #12] SUBGRF_Calibrate( calibParam ); 8009926: 7b38 ldrb r0, [r7, #12] 8009928: f000 fa8d bl 8009e46 800992c: e009 b.n 8009942 } else { SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE ); 800992e: 2120 movs r1, #32 8009930: f640 1011 movw r0, #2321 @ 0x911 8009934: f000 feea bl 800a70c SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE ); 8009938: 2120 movs r1, #32 800993a: f640 1012 movw r0, #2322 @ 0x912 800993e: f000 fee5 bl 800a70c } /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); 8009942: 210e movs r1, #14 8009944: f640 101f movw r0, #2335 @ 0x91f 8009948: f000 fee0 bl 800a70c /* Init RF Switch */ RBI_Init(); 800994c: f003 fb90 bl 800d070 OperatingMode = MODE_STDBY_RC; 8009950: 4b05 ldr r3, [pc, #20] @ (8009968 ) 8009952: 2201 movs r2, #1 8009954: 701a strb r2, [r3, #0] } 8009956: bf00 nop 8009958: 3710 adds r7, #16 800995a: 46bd mov sp, r7 800995c: bd80 pop {r7, pc} 800995e: bf00 nop 8009960: 20000398 .word 0x20000398 8009964: 20000394 .word 0x20000394 8009968: 2000038c .word 0x2000038c 0800996c : RadioOperatingModes_t SUBGRF_GetOperatingMode( void ) { 800996c: b480 push {r7} 800996e: af00 add r7, sp, #0 return OperatingMode; 8009970: 4b02 ldr r3, [pc, #8] @ (800997c ) 8009972: 781b ldrb r3, [r3, #0] } 8009974: 4618 mov r0, r3 8009976: 46bd mov sp, r7 8009978: bc80 pop {r7} 800997a: 4770 bx lr 800997c: 2000038c .word 0x2000038c 08009980 : void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ) { 8009980: b580 push {r7, lr} 8009982: b082 sub sp, #8 8009984: af00 add r7, sp, #0 8009986: 6078 str r0, [r7, #4] 8009988: 460b mov r3, r1 800998a: 70fb strb r3, [r7, #3] SUBGRF_WriteBuffer( 0x00, payload, size ); 800998c: 78fb ldrb r3, [r7, #3] 800998e: 461a mov r2, r3 8009990: 6879 ldr r1, [r7, #4] 8009992: 2000 movs r0, #0 8009994: f000 ff40 bl 800a818 } 8009998: bf00 nop 800999a: 3708 adds r7, #8 800999c: 46bd mov sp, r7 800999e: bd80 pop {r7, pc} 080099a0 : uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) { 80099a0: b580 push {r7, lr} 80099a2: b086 sub sp, #24 80099a4: af00 add r7, sp, #0 80099a6: 60f8 str r0, [r7, #12] 80099a8: 60b9 str r1, [r7, #8] 80099aa: 4613 mov r3, r2 80099ac: 71fb strb r3, [r7, #7] uint8_t offset = 0; 80099ae: 2300 movs r3, #0 80099b0: 75fb strb r3, [r7, #23] SUBGRF_GetRxBufferStatus( size, &offset ); 80099b2: f107 0317 add.w r3, r7, #23 80099b6: 4619 mov r1, r3 80099b8: 68b8 ldr r0, [r7, #8] 80099ba: f000 fe29 bl 800a610 if( *size > maxSize ) 80099be: 68bb ldr r3, [r7, #8] 80099c0: 781b ldrb r3, [r3, #0] 80099c2: 79fa ldrb r2, [r7, #7] 80099c4: 429a cmp r2, r3 80099c6: d201 bcs.n 80099cc { return 1; 80099c8: 2301 movs r3, #1 80099ca: e007 b.n 80099dc } SUBGRF_ReadBuffer( offset, buffer, *size ); 80099cc: 7df8 ldrb r0, [r7, #23] 80099ce: 68bb ldr r3, [r7, #8] 80099d0: 781b ldrb r3, [r3, #0] 80099d2: 461a mov r2, r3 80099d4: 68f9 ldr r1, [r7, #12] 80099d6: f000 ff41 bl 800a85c return 0; 80099da: 2300 movs r3, #0 } 80099dc: 4618 mov r0, r3 80099de: 3718 adds r7, #24 80099e0: 46bd mov sp, r7 80099e2: bd80 pop {r7, pc} 080099e4 : void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout) { 80099e4: b580 push {r7, lr} 80099e6: b084 sub sp, #16 80099e8: af00 add r7, sp, #0 80099ea: 60f8 str r0, [r7, #12] 80099ec: 460b mov r3, r1 80099ee: 607a str r2, [r7, #4] 80099f0: 72fb strb r3, [r7, #11] SUBGRF_SetPayload( payload, size ); 80099f2: 7afb ldrb r3, [r7, #11] 80099f4: 4619 mov r1, r3 80099f6: 68f8 ldr r0, [r7, #12] 80099f8: f7ff ffc2 bl 8009980 SUBGRF_SetTx( timeout ); 80099fc: 6878 ldr r0, [r7, #4] 80099fe: f000 f91d bl 8009c3c } 8009a02: bf00 nop 8009a04: 3710 adds r7, #16 8009a06: 46bd mov sp, r7 8009a08: bd80 pop {r7, pc} 08009a0a : uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ) { 8009a0a: b580 push {r7, lr} 8009a0c: b082 sub sp, #8 8009a0e: af00 add r7, sp, #0 8009a10: 6078 str r0, [r7, #4] SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 ); 8009a12: 2208 movs r2, #8 8009a14: 6879 ldr r1, [r7, #4] 8009a16: f44f 60d8 mov.w r0, #1728 @ 0x6c0 8009a1a: f000 feb9 bl 800a790 return 0; 8009a1e: 2300 movs r3, #0 } 8009a20: 4618 mov r0, r3 8009a22: 3708 adds r7, #8 8009a24: 46bd mov sp, r7 8009a26: bd80 pop {r7, pc} 08009a28 : void SUBGRF_SetCrcSeed( uint16_t seed ) { 8009a28: b580 push {r7, lr} 8009a2a: b084 sub sp, #16 8009a2c: af00 add r7, sp, #0 8009a2e: 4603 mov r3, r0 8009a30: 80fb strh r3, [r7, #6] uint8_t buf[2]; buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); 8009a32: 88fb ldrh r3, [r7, #6] 8009a34: 0a1b lsrs r3, r3, #8 8009a36: b29b uxth r3, r3 8009a38: b2db uxtb r3, r3 8009a3a: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( seed & 0xFF ); 8009a3c: 88fb ldrh r3, [r7, #6] 8009a3e: b2db uxtb r3, r3 8009a40: 737b strb r3, [r7, #13] switch( SUBGRF_GetPacketType( ) ) 8009a42: f000 fb77 bl 800a134 8009a46: 4603 mov r3, r0 8009a48: 2b00 cmp r3, #0 8009a4a: d108 bne.n 8009a5e { case PACKET_TYPE_GFSK: SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); 8009a4c: f107 030c add.w r3, r7, #12 8009a50: 2202 movs r2, #2 8009a52: 4619 mov r1, r3 8009a54: f240 60bc movw r0, #1724 @ 0x6bc 8009a58: f000 fe9a bl 800a790 break; 8009a5c: e000 b.n 8009a60 default: break; 8009a5e: bf00 nop } } 8009a60: bf00 nop 8009a62: 3710 adds r7, #16 8009a64: 46bd mov sp, r7 8009a66: bd80 pop {r7, pc} 08009a68 : void SUBGRF_SetCrcPolynomial( uint16_t polynomial ) { 8009a68: b580 push {r7, lr} 8009a6a: b084 sub sp, #16 8009a6c: af00 add r7, sp, #0 8009a6e: 4603 mov r3, r0 8009a70: 80fb strh r3, [r7, #6] uint8_t buf[2]; buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); 8009a72: 88fb ldrh r3, [r7, #6] 8009a74: 0a1b lsrs r3, r3, #8 8009a76: b29b uxth r3, r3 8009a78: b2db uxtb r3, r3 8009a7a: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( polynomial & 0xFF ); 8009a7c: 88fb ldrh r3, [r7, #6] 8009a7e: b2db uxtb r3, r3 8009a80: 737b strb r3, [r7, #13] switch( SUBGRF_GetPacketType( ) ) 8009a82: f000 fb57 bl 800a134 8009a86: 4603 mov r3, r0 8009a88: 2b00 cmp r3, #0 8009a8a: d108 bne.n 8009a9e { case PACKET_TYPE_GFSK: SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); 8009a8c: f107 030c add.w r3, r7, #12 8009a90: 2202 movs r2, #2 8009a92: 4619 mov r1, r3 8009a94: f240 60be movw r0, #1726 @ 0x6be 8009a98: f000 fe7a bl 800a790 break; 8009a9c: e000 b.n 8009aa0 default: break; 8009a9e: bf00 nop } } 8009aa0: bf00 nop 8009aa2: 3710 adds r7, #16 8009aa4: 46bd mov sp, r7 8009aa6: bd80 pop {r7, pc} 08009aa8 : void SUBGRF_SetWhiteningSeed( uint16_t seed ) { 8009aa8: b580 push {r7, lr} 8009aaa: b084 sub sp, #16 8009aac: af00 add r7, sp, #0 8009aae: 4603 mov r3, r0 8009ab0: 80fb strh r3, [r7, #6] uint8_t regValue = 0; 8009ab2: 2300 movs r3, #0 8009ab4: 73fb strb r3, [r7, #15] switch( SUBGRF_GetPacketType( ) ) 8009ab6: f000 fb3d bl 800a134 8009aba: 4603 mov r3, r0 8009abc: 2b00 cmp r3, #0 8009abe: d121 bne.n 8009b04 { case PACKET_TYPE_GFSK: regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; 8009ac0: f44f 60d7 mov.w r0, #1720 @ 0x6b8 8009ac4: f000 fe44 bl 800a750 8009ac8: 4603 mov r3, r0 8009aca: f023 0301 bic.w r3, r3, #1 8009ace: 73fb strb r3, [r7, #15] regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; 8009ad0: 88fb ldrh r3, [r7, #6] 8009ad2: 0a1b lsrs r3, r3, #8 8009ad4: b29b uxth r3, r3 8009ad6: b25b sxtb r3, r3 8009ad8: f003 0301 and.w r3, r3, #1 8009adc: b25a sxtb r2, r3 8009ade: f997 300f ldrsb.w r3, [r7, #15] 8009ae2: 4313 orrs r3, r2 8009ae4: b25b sxtb r3, r3 8009ae6: 73fb strb r3, [r7, #15] SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. 8009ae8: 7bfb ldrb r3, [r7, #15] 8009aea: 4619 mov r1, r3 8009aec: f44f 60d7 mov.w r0, #1720 @ 0x6b8 8009af0: f000 fe0c bl 800a70c SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed ); 8009af4: 88fb ldrh r3, [r7, #6] 8009af6: b2db uxtb r3, r3 8009af8: 4619 mov r1, r3 8009afa: f240 60b9 movw r0, #1721 @ 0x6b9 8009afe: f000 fe05 bl 800a70c break; 8009b02: e000 b.n 8009b06 default: break; 8009b04: bf00 nop } } 8009b06: bf00 nop 8009b08: 3710 adds r7, #16 8009b0a: 46bd mov sp, r7 8009b0c: bd80 pop {r7, pc} 08009b0e : uint32_t SUBGRF_GetRandom( void ) { 8009b0e: b580 push {r7, lr} 8009b10: b082 sub sp, #8 8009b12: af00 add r7, sp, #0 uint32_t number = 0; 8009b14: 2300 movs r3, #0 8009b16: 603b str r3, [r7, #0] uint8_t regAnaLna = 0; 8009b18: 2300 movs r3, #0 8009b1a: 71fb strb r3, [r7, #7] uint8_t regAnaMixer = 0; 8009b1c: 2300 movs r3, #0 8009b1e: 71bb strb r3, [r7, #6] regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA ); 8009b20: f640 00e2 movw r0, #2274 @ 0x8e2 8009b24: f000 fe14 bl 800a750 8009b28: 4603 mov r3, r0 8009b2a: 71fb strb r3, [r7, #7] SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) ); 8009b2c: 79fb ldrb r3, [r7, #7] 8009b2e: f023 0301 bic.w r3, r3, #1 8009b32: b2db uxtb r3, r3 8009b34: 4619 mov r1, r3 8009b36: f640 00e2 movw r0, #2274 @ 0x8e2 8009b3a: f000 fde7 bl 800a70c regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER ); 8009b3e: f640 00e5 movw r0, #2277 @ 0x8e5 8009b42: f000 fe05 bl 800a750 8009b46: 4603 mov r3, r0 8009b48: 71bb strb r3, [r7, #6] SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) ); 8009b4a: 79bb ldrb r3, [r7, #6] 8009b4c: f003 037f and.w r3, r3, #127 @ 0x7f 8009b50: b2db uxtb r3, r3 8009b52: 4619 mov r1, r3 8009b54: f640 00e5 movw r0, #2277 @ 0x8e5 8009b58: f000 fdd8 bl 800a70c // Set radio in continuous reception SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous 8009b5c: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 8009b60: f000 f88c bl 8009c7c SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 ); 8009b64: 463b mov r3, r7 8009b66: 2204 movs r2, #4 8009b68: 4619 mov r1, r3 8009b6a: f640 0019 movw r0, #2073 @ 0x819 8009b6e: f000 fe31 bl 800a7d4 SUBGRF_SetStandby( STDBY_RC ); 8009b72: 2000 movs r0, #0 8009b74: f000 f846 bl 8009c04 SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna ); 8009b78: 79fb ldrb r3, [r7, #7] 8009b7a: 4619 mov r1, r3 8009b7c: f640 00e2 movw r0, #2274 @ 0x8e2 8009b80: f000 fdc4 bl 800a70c SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer ); 8009b84: 79bb ldrb r3, [r7, #6] 8009b86: 4619 mov r1, r3 8009b88: f640 00e5 movw r0, #2277 @ 0x8e5 8009b8c: f000 fdbe bl 800a70c return number; 8009b90: 683b ldr r3, [r7, #0] } 8009b92: 4618 mov r0, r3 8009b94: 3708 adds r7, #8 8009b96: 46bd mov sp, r7 8009b98: bd80 pop {r7, pc} ... 08009b9c : void SUBGRF_SetSleep( SleepParams_t sleepConfig ) { 8009b9c: b580 push {r7, lr} 8009b9e: b084 sub sp, #16 8009ba0: af00 add r7, sp, #0 8009ba2: 7138 strb r0, [r7, #4] /* switch the antenna OFF by SW */ RBI_ConfigRFSwitch(RBI_SWITCH_OFF); 8009ba4: 2000 movs r0, #0 8009ba6: f003 fa6a bl 800d07e Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); 8009baa: 2002 movs r0, #2 8009bac: f000 ffc0 bl 800ab30 uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | 8009bb0: 793b ldrb r3, [r7, #4] 8009bb2: f3c3 0380 ubfx r3, r3, #2, #1 8009bb6: b2db uxtb r3, r3 8009bb8: b25b sxtb r3, r3 8009bba: 009b lsls r3, r3, #2 8009bbc: b25a sxtb r2, r3 ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | 8009bbe: 793b ldrb r3, [r7, #4] 8009bc0: f3c3 0340 ubfx r3, r3, #1, #1 8009bc4: b2db uxtb r3, r3 uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | 8009bc6: b25b sxtb r3, r3 8009bc8: 005b lsls r3, r3, #1 8009bca: b25b sxtb r3, r3 8009bcc: 4313 orrs r3, r2 8009bce: b25a sxtb r2, r3 ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) ); 8009bd0: 793b ldrb r3, [r7, #4] 8009bd2: f3c3 0300 ubfx r3, r3, #0, #1 8009bd6: b2db uxtb r3, r3 8009bd8: b25b sxtb r3, r3 ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | 8009bda: 4313 orrs r3, r2 8009bdc: b25b sxtb r3, r3 8009bde: b2db uxtb r3, r3 uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | 8009be0: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 ); 8009be2: f107 030f add.w r3, r7, #15 8009be6: 2201 movs r2, #1 8009be8: 4619 mov r1, r3 8009bea: 2084 movs r0, #132 @ 0x84 8009bec: f000 fe58 bl 800a8a0 OperatingMode = MODE_SLEEP; 8009bf0: 4b03 ldr r3, [pc, #12] @ (8009c00 ) 8009bf2: 2200 movs r2, #0 8009bf4: 701a strb r2, [r3, #0] } 8009bf6: bf00 nop 8009bf8: 3710 adds r7, #16 8009bfa: 46bd mov sp, r7 8009bfc: bd80 pop {r7, pc} 8009bfe: bf00 nop 8009c00: 2000038c .word 0x2000038c 08009c04 : void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig ) { 8009c04: b580 push {r7, lr} 8009c06: b082 sub sp, #8 8009c08: af00 add r7, sp, #0 8009c0a: 4603 mov r3, r0 8009c0c: 71fb strb r3, [r7, #7] SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); 8009c0e: 1dfb adds r3, r7, #7 8009c10: 2201 movs r2, #1 8009c12: 4619 mov r1, r3 8009c14: 2080 movs r0, #128 @ 0x80 8009c16: f000 fe43 bl 800a8a0 if( standbyConfig == STDBY_RC ) 8009c1a: 79fb ldrb r3, [r7, #7] 8009c1c: 2b00 cmp r3, #0 8009c1e: d103 bne.n 8009c28 { OperatingMode = MODE_STDBY_RC; 8009c20: 4b05 ldr r3, [pc, #20] @ (8009c38 ) 8009c22: 2201 movs r2, #1 8009c24: 701a strb r2, [r3, #0] } else { OperatingMode = MODE_STDBY_XOSC; } } 8009c26: e002 b.n 8009c2e OperatingMode = MODE_STDBY_XOSC; 8009c28: 4b03 ldr r3, [pc, #12] @ (8009c38 ) 8009c2a: 2202 movs r2, #2 8009c2c: 701a strb r2, [r3, #0] } 8009c2e: bf00 nop 8009c30: 3708 adds r7, #8 8009c32: 46bd mov sp, r7 8009c34: bd80 pop {r7, pc} 8009c36: bf00 nop 8009c38: 2000038c .word 0x2000038c 08009c3c : SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 ); OperatingMode = MODE_FS; } void SUBGRF_SetTx( uint32_t timeout ) { 8009c3c: b580 push {r7, lr} 8009c3e: b084 sub sp, #16 8009c40: af00 add r7, sp, #0 8009c42: 6078 str r0, [r7, #4] uint8_t buf[3]; OperatingMode = MODE_TX; 8009c44: 4b0c ldr r3, [pc, #48] @ (8009c78 ) 8009c46: 2204 movs r2, #4 8009c48: 701a strb r2, [r3, #0] buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); 8009c4a: 687b ldr r3, [r7, #4] 8009c4c: 0c1b lsrs r3, r3, #16 8009c4e: b2db uxtb r3, r3 8009c50: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); 8009c52: 687b ldr r3, [r7, #4] 8009c54: 0a1b lsrs r3, r3, #8 8009c56: b2db uxtb r3, r3 8009c58: 737b strb r3, [r7, #13] buf[2] = ( uint8_t )( timeout & 0xFF ); 8009c5a: 687b ldr r3, [r7, #4] 8009c5c: b2db uxtb r3, r3 8009c5e: 73bb strb r3, [r7, #14] SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 ); 8009c60: f107 030c add.w r3, r7, #12 8009c64: 2203 movs r2, #3 8009c66: 4619 mov r1, r3 8009c68: 2083 movs r0, #131 @ 0x83 8009c6a: f000 fe19 bl 800a8a0 } 8009c6e: bf00 nop 8009c70: 3710 adds r7, #16 8009c72: 46bd mov sp, r7 8009c74: bd80 pop {r7, pc} 8009c76: bf00 nop 8009c78: 2000038c .word 0x2000038c 08009c7c : void SUBGRF_SetRx( uint32_t timeout ) { 8009c7c: b580 push {r7, lr} 8009c7e: b084 sub sp, #16 8009c80: af00 add r7, sp, #0 8009c82: 6078 str r0, [r7, #4] uint8_t buf[3]; OperatingMode = MODE_RX; 8009c84: 4b0c ldr r3, [pc, #48] @ (8009cb8 ) 8009c86: 2205 movs r2, #5 8009c88: 701a strb r2, [r3, #0] buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); 8009c8a: 687b ldr r3, [r7, #4] 8009c8c: 0c1b lsrs r3, r3, #16 8009c8e: b2db uxtb r3, r3 8009c90: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); 8009c92: 687b ldr r3, [r7, #4] 8009c94: 0a1b lsrs r3, r3, #8 8009c96: b2db uxtb r3, r3 8009c98: 737b strb r3, [r7, #13] buf[2] = ( uint8_t )( timeout & 0xFF ); 8009c9a: 687b ldr r3, [r7, #4] 8009c9c: b2db uxtb r3, r3 8009c9e: 73bb strb r3, [r7, #14] SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); 8009ca0: f107 030c add.w r3, r7, #12 8009ca4: 2203 movs r2, #3 8009ca6: 4619 mov r1, r3 8009ca8: 2082 movs r0, #130 @ 0x82 8009caa: f000 fdf9 bl 800a8a0 } 8009cae: bf00 nop 8009cb0: 3710 adds r7, #16 8009cb2: 46bd mov sp, r7 8009cb4: bd80 pop {r7, pc} 8009cb6: bf00 nop 8009cb8: 2000038c .word 0x2000038c 08009cbc : void SUBGRF_SetRxBoosted( uint32_t timeout ) { 8009cbc: b580 push {r7, lr} 8009cbe: b084 sub sp, #16 8009cc0: af00 add r7, sp, #0 8009cc2: 6078 str r0, [r7, #4] uint8_t buf[3]; OperatingMode = MODE_RX; 8009cc4: 4b0e ldr r3, [pc, #56] @ (8009d00 ) 8009cc6: 2205 movs r2, #5 8009cc8: 701a strb r2, [r3, #0] SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity 8009cca: 2197 movs r1, #151 @ 0x97 8009ccc: f640 00ac movw r0, #2220 @ 0x8ac 8009cd0: f000 fd1c bl 800a70c buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); 8009cd4: 687b ldr r3, [r7, #4] 8009cd6: 0c1b lsrs r3, r3, #16 8009cd8: b2db uxtb r3, r3 8009cda: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); 8009cdc: 687b ldr r3, [r7, #4] 8009cde: 0a1b lsrs r3, r3, #8 8009ce0: b2db uxtb r3, r3 8009ce2: 737b strb r3, [r7, #13] buf[2] = ( uint8_t )( timeout & 0xFF ); 8009ce4: 687b ldr r3, [r7, #4] 8009ce6: b2db uxtb r3, r3 8009ce8: 73bb strb r3, [r7, #14] SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); 8009cea: f107 030c add.w r3, r7, #12 8009cee: 2203 movs r2, #3 8009cf0: 4619 mov r1, r3 8009cf2: 2082 movs r0, #130 @ 0x82 8009cf4: f000 fdd4 bl 800a8a0 } 8009cf8: bf00 nop 8009cfa: 3710 adds r7, #16 8009cfc: 46bd mov sp, r7 8009cfe: bd80 pop {r7, pc} 8009d00: 2000038c .word 0x2000038c 08009d04 : void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) { 8009d04: b580 push {r7, lr} 8009d06: b084 sub sp, #16 8009d08: af00 add r7, sp, #0 8009d0a: 6078 str r0, [r7, #4] 8009d0c: 6039 str r1, [r7, #0] uint8_t buf[6]; buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); 8009d0e: 687b ldr r3, [r7, #4] 8009d10: 0c1b lsrs r3, r3, #16 8009d12: b2db uxtb r3, r3 8009d14: 723b strb r3, [r7, #8] buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); 8009d16: 687b ldr r3, [r7, #4] 8009d18: 0a1b lsrs r3, r3, #8 8009d1a: b2db uxtb r3, r3 8009d1c: 727b strb r3, [r7, #9] buf[2] = ( uint8_t )( rxTime & 0xFF ); 8009d1e: 687b ldr r3, [r7, #4] 8009d20: b2db uxtb r3, r3 8009d22: 72bb strb r3, [r7, #10] buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); 8009d24: 683b ldr r3, [r7, #0] 8009d26: 0c1b lsrs r3, r3, #16 8009d28: b2db uxtb r3, r3 8009d2a: 72fb strb r3, [r7, #11] buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); 8009d2c: 683b ldr r3, [r7, #0] 8009d2e: 0a1b lsrs r3, r3, #8 8009d30: b2db uxtb r3, r3 8009d32: 733b strb r3, [r7, #12] buf[5] = ( uint8_t )( sleepTime & 0xFF ); 8009d34: 683b ldr r3, [r7, #0] 8009d36: b2db uxtb r3, r3 8009d38: 737b strb r3, [r7, #13] SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); 8009d3a: f107 0308 add.w r3, r7, #8 8009d3e: 2206 movs r2, #6 8009d40: 4619 mov r1, r3 8009d42: 2094 movs r0, #148 @ 0x94 8009d44: f000 fdac bl 800a8a0 OperatingMode = MODE_RX_DC; 8009d48: 4b03 ldr r3, [pc, #12] @ (8009d58 ) 8009d4a: 2206 movs r2, #6 8009d4c: 701a strb r2, [r3, #0] } 8009d4e: bf00 nop 8009d50: 3710 adds r7, #16 8009d52: 46bd mov sp, r7 8009d54: bd80 pop {r7, pc} 8009d56: bf00 nop 8009d58: 2000038c .word 0x2000038c 08009d5c : void SUBGRF_SetCad( void ) { 8009d5c: b580 push {r7, lr} 8009d5e: af00 add r7, sp, #0 SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 ); 8009d60: 2200 movs r2, #0 8009d62: 2100 movs r1, #0 8009d64: 20c5 movs r0, #197 @ 0xc5 8009d66: f000 fd9b bl 800a8a0 OperatingMode = MODE_CAD; 8009d6a: 4b02 ldr r3, [pc, #8] @ (8009d74 ) 8009d6c: 2207 movs r2, #7 8009d6e: 701a strb r2, [r3, #0] } 8009d70: bf00 nop 8009d72: bd80 pop {r7, pc} 8009d74: 2000038c .word 0x2000038c 08009d78 : void SUBGRF_SetTxContinuousWave( void ) { 8009d78: b580 push {r7, lr} 8009d7a: af00 add r7, sp, #0 SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); 8009d7c: 2200 movs r2, #0 8009d7e: 2100 movs r1, #0 8009d80: 20d1 movs r0, #209 @ 0xd1 8009d82: f000 fd8d bl 800a8a0 } 8009d86: bf00 nop 8009d88: bd80 pop {r7, pc} 08009d8a : void SUBGRF_SetTxInfinitePreamble( void ) { 8009d8a: b580 push {r7, lr} 8009d8c: af00 add r7, sp, #0 SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); 8009d8e: 2200 movs r2, #0 8009d90: 2100 movs r1, #0 8009d92: 20d2 movs r0, #210 @ 0xd2 8009d94: f000 fd84 bl 800a8a0 } 8009d98: bf00 nop 8009d9a: bd80 pop {r7, pc} 08009d9c : void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ) { 8009d9c: b580 push {r7, lr} 8009d9e: b082 sub sp, #8 8009da0: af00 add r7, sp, #0 8009da2: 4603 mov r3, r0 8009da4: 71fb strb r3, [r7, #7] SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); 8009da6: 1dfb adds r3, r7, #7 8009da8: 2201 movs r2, #1 8009daa: 4619 mov r1, r3 8009dac: 209f movs r0, #159 @ 0x9f 8009dae: f000 fd77 bl 800a8a0 } 8009db2: bf00 nop 8009db4: 3708 adds r7, #8 8009db6: 46bd mov sp, r7 8009db8: bd80 pop {r7, pc} 08009dba : void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ) { 8009dba: b580 push {r7, lr} 8009dbc: b084 sub sp, #16 8009dbe: af00 add r7, sp, #0 8009dc0: 4603 mov r3, r0 8009dc2: 71fb strb r3, [r7, #7] SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 ); 8009dc4: 1dfb adds r3, r7, #7 8009dc6: 2201 movs r2, #1 8009dc8: 4619 mov r1, r3 8009dca: 20a0 movs r0, #160 @ 0xa0 8009dcc: f000 fd68 bl 800a8a0 if( symbNum >= 64 ) 8009dd0: 79fb ldrb r3, [r7, #7] 8009dd2: 2b3f cmp r3, #63 @ 0x3f 8009dd4: d91c bls.n 8009e10 { uint8_t mant = symbNum >> 1; 8009dd6: 79fb ldrb r3, [r7, #7] 8009dd8: 085b lsrs r3, r3, #1 8009dda: 73fb strb r3, [r7, #15] uint8_t exp = 0; 8009ddc: 2300 movs r3, #0 8009dde: 73bb strb r3, [r7, #14] uint8_t reg = 0; 8009de0: 2300 movs r3, #0 8009de2: 737b strb r3, [r7, #13] while( mant > 31 ) 8009de4: e005 b.n 8009df2 { mant >>= 2; 8009de6: 7bfb ldrb r3, [r7, #15] 8009de8: 089b lsrs r3, r3, #2 8009dea: 73fb strb r3, [r7, #15] exp++; 8009dec: 7bbb ldrb r3, [r7, #14] 8009dee: 3301 adds r3, #1 8009df0: 73bb strb r3, [r7, #14] while( mant > 31 ) 8009df2: 7bfb ldrb r3, [r7, #15] 8009df4: 2b1f cmp r3, #31 8009df6: d8f6 bhi.n 8009de6 } reg = exp + ( mant << 3 ); 8009df8: 7bfb ldrb r3, [r7, #15] 8009dfa: 00db lsls r3, r3, #3 8009dfc: b2da uxtb r2, r3 8009dfe: 7bbb ldrb r3, [r7, #14] 8009e00: 4413 add r3, r2 8009e02: 737b strb r3, [r7, #13] SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg ); 8009e04: 7b7b ldrb r3, [r7, #13] 8009e06: 4619 mov r1, r3 8009e08: f240 7006 movw r0, #1798 @ 0x706 8009e0c: f000 fc7e bl 800a70c } } 8009e10: bf00 nop 8009e12: 3710 adds r7, #16 8009e14: 46bd mov sp, r7 8009e16: bd80 pop {r7, pc} 08009e18 : void SUBGRF_SetRegulatorMode( void ) { 8009e18: b580 push {r7, lr} 8009e1a: b082 sub sp, #8 8009e1c: af00 add r7, sp, #0 RadioRegulatorMode_t mode; if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) ) 8009e1e: f003 f94a bl 800d0b6 8009e22: 4603 mov r3, r0 8009e24: 2b01 cmp r3, #1 8009e26: d102 bne.n 8009e2e { mode = USE_DCDC ; 8009e28: 2301 movs r3, #1 8009e2a: 71fb strb r3, [r7, #7] 8009e2c: e001 b.n 8009e32 } else { mode = USE_LDO ; 8009e2e: 2300 movs r3, #0 8009e30: 71fb strb r3, [r7, #7] } SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); 8009e32: 1dfb adds r3, r7, #7 8009e34: 2201 movs r2, #1 8009e36: 4619 mov r1, r3 8009e38: 2096 movs r0, #150 @ 0x96 8009e3a: f000 fd31 bl 800a8a0 } 8009e3e: bf00 nop 8009e40: 3708 adds r7, #8 8009e42: 46bd mov sp, r7 8009e44: bd80 pop {r7, pc} 08009e46 : void SUBGRF_Calibrate( CalibrationParams_t calibParam ) { 8009e46: b580 push {r7, lr} 8009e48: b084 sub sp, #16 8009e4a: af00 add r7, sp, #0 8009e4c: 7138 strb r0, [r7, #4] uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | 8009e4e: 793b ldrb r3, [r7, #4] 8009e50: f3c3 1380 ubfx r3, r3, #6, #1 8009e54: b2db uxtb r3, r3 8009e56: b25b sxtb r3, r3 8009e58: 019b lsls r3, r3, #6 8009e5a: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | 8009e5c: 793b ldrb r3, [r7, #4] 8009e5e: f3c3 1340 ubfx r3, r3, #5, #1 8009e62: b2db uxtb r3, r3 uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | 8009e64: b25b sxtb r3, r3 8009e66: 015b lsls r3, r3, #5 8009e68: b25b sxtb r3, r3 8009e6a: 4313 orrs r3, r2 8009e6c: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | 8009e6e: 793b ldrb r3, [r7, #4] 8009e70: f3c3 1300 ubfx r3, r3, #4, #1 8009e74: b2db uxtb r3, r3 ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | 8009e76: b25b sxtb r3, r3 8009e78: 011b lsls r3, r3, #4 8009e7a: b25b sxtb r3, r3 8009e7c: 4313 orrs r3, r2 8009e7e: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | 8009e80: 793b ldrb r3, [r7, #4] 8009e82: f3c3 03c0 ubfx r3, r3, #3, #1 8009e86: b2db uxtb r3, r3 ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | 8009e88: b25b sxtb r3, r3 8009e8a: 00db lsls r3, r3, #3 8009e8c: b25b sxtb r3, r3 8009e8e: 4313 orrs r3, r2 8009e90: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | 8009e92: 793b ldrb r3, [r7, #4] 8009e94: f3c3 0380 ubfx r3, r3, #2, #1 8009e98: b2db uxtb r3, r3 ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | 8009e9a: b25b sxtb r3, r3 8009e9c: 009b lsls r3, r3, #2 8009e9e: b25b sxtb r3, r3 8009ea0: 4313 orrs r3, r2 8009ea2: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | 8009ea4: 793b ldrb r3, [r7, #4] 8009ea6: f3c3 0340 ubfx r3, r3, #1, #1 8009eaa: b2db uxtb r3, r3 ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | 8009eac: b25b sxtb r3, r3 8009eae: 005b lsls r3, r3, #1 8009eb0: b25b sxtb r3, r3 8009eb2: 4313 orrs r3, r2 8009eb4: b25a sxtb r2, r3 ( ( uint8_t )calibParam.Fields.RC64KEnable ) ); 8009eb6: 793b ldrb r3, [r7, #4] 8009eb8: f3c3 0300 ubfx r3, r3, #0, #1 8009ebc: b2db uxtb r3, r3 8009ebe: b25b sxtb r3, r3 ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | 8009ec0: 4313 orrs r3, r2 8009ec2: b25b sxtb r3, r3 8009ec4: b2db uxtb r3, r3 uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | 8009ec6: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 ); 8009ec8: f107 030f add.w r3, r7, #15 8009ecc: 2201 movs r2, #1 8009ece: 4619 mov r1, r3 8009ed0: 2089 movs r0, #137 @ 0x89 8009ed2: f000 fce5 bl 800a8a0 } 8009ed6: bf00 nop 8009ed8: 3710 adds r7, #16 8009eda: 46bd mov sp, r7 8009edc: bd80 pop {r7, pc} ... 08009ee0 : void SUBGRF_CalibrateImage( uint32_t freq ) { 8009ee0: b580 push {r7, lr} 8009ee2: b084 sub sp, #16 8009ee4: af00 add r7, sp, #0 8009ee6: 6078 str r0, [r7, #4] uint8_t calFreq[2]; if( freq > 900000000 ) 8009ee8: 687b ldr r3, [r7, #4] 8009eea: 4a1d ldr r2, [pc, #116] @ (8009f60 ) 8009eec: 4293 cmp r3, r2 8009eee: d904 bls.n 8009efa { calFreq[0] = 0xE1; 8009ef0: 23e1 movs r3, #225 @ 0xe1 8009ef2: 733b strb r3, [r7, #12] calFreq[1] = 0xE9; 8009ef4: 23e9 movs r3, #233 @ 0xe9 8009ef6: 737b strb r3, [r7, #13] 8009ef8: e027 b.n 8009f4a } else if( freq > 850000000 ) 8009efa: 687b ldr r3, [r7, #4] 8009efc: 4a19 ldr r2, [pc, #100] @ (8009f64 ) 8009efe: 4293 cmp r3, r2 8009f00: d904 bls.n 8009f0c { calFreq[0] = 0xD7; 8009f02: 23d7 movs r3, #215 @ 0xd7 8009f04: 733b strb r3, [r7, #12] calFreq[1] = 0xDB; 8009f06: 23db movs r3, #219 @ 0xdb 8009f08: 737b strb r3, [r7, #13] 8009f0a: e01e b.n 8009f4a } else if( freq > 770000000 ) 8009f0c: 687b ldr r3, [r7, #4] 8009f0e: 4a16 ldr r2, [pc, #88] @ (8009f68 ) 8009f10: 4293 cmp r3, r2 8009f12: d904 bls.n 8009f1e { calFreq[0] = 0xC1; 8009f14: 23c1 movs r3, #193 @ 0xc1 8009f16: 733b strb r3, [r7, #12] calFreq[1] = 0xC5; 8009f18: 23c5 movs r3, #197 @ 0xc5 8009f1a: 737b strb r3, [r7, #13] 8009f1c: e015 b.n 8009f4a } else if( freq > 460000000 ) 8009f1e: 687b ldr r3, [r7, #4] 8009f20: 4a12 ldr r2, [pc, #72] @ (8009f6c ) 8009f22: 4293 cmp r3, r2 8009f24: d904 bls.n 8009f30 { calFreq[0] = 0x75; 8009f26: 2375 movs r3, #117 @ 0x75 8009f28: 733b strb r3, [r7, #12] calFreq[1] = 0x81; 8009f2a: 2381 movs r3, #129 @ 0x81 8009f2c: 737b strb r3, [r7, #13] 8009f2e: e00c b.n 8009f4a } else if( freq > 425000000 ) 8009f30: 687b ldr r3, [r7, #4] 8009f32: 4a0f ldr r2, [pc, #60] @ (8009f70 ) 8009f34: 4293 cmp r3, r2 8009f36: d904 bls.n 8009f42 { calFreq[0] = 0x6B; 8009f38: 236b movs r3, #107 @ 0x6b 8009f3a: 733b strb r3, [r7, #12] calFreq[1] = 0x6F; 8009f3c: 236f movs r3, #111 @ 0x6f 8009f3e: 737b strb r3, [r7, #13] 8009f40: e003 b.n 8009f4a } else /* freq <= 425000000*/ { /* [ 156MHz - 171MHz ] */ calFreq[0] = 0x29; 8009f42: 2329 movs r3, #41 @ 0x29 8009f44: 733b strb r3, [r7, #12] calFreq[1] = 0x2B ; 8009f46: 232b movs r3, #43 @ 0x2b 8009f48: 737b strb r3, [r7, #13] } SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); 8009f4a: f107 030c add.w r3, r7, #12 8009f4e: 2202 movs r2, #2 8009f50: 4619 mov r1, r3 8009f52: 2098 movs r0, #152 @ 0x98 8009f54: f000 fca4 bl 800a8a0 } 8009f58: bf00 nop 8009f5a: 3710 adds r7, #16 8009f5c: 46bd mov sp, r7 8009f5e: bd80 pop {r7, pc} 8009f60: 35a4e900 .word 0x35a4e900 8009f64: 32a9f880 .word 0x32a9f880 8009f68: 2de54480 .word 0x2de54480 8009f6c: 1b6b0b00 .word 0x1b6b0b00 8009f70: 1954fc40 .word 0x1954fc40 08009f74 : void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) { 8009f74: b590 push {r4, r7, lr} 8009f76: b085 sub sp, #20 8009f78: af00 add r7, sp, #0 8009f7a: 4604 mov r4, r0 8009f7c: 4608 mov r0, r1 8009f7e: 4611 mov r1, r2 8009f80: 461a mov r2, r3 8009f82: 4623 mov r3, r4 8009f84: 71fb strb r3, [r7, #7] 8009f86: 4603 mov r3, r0 8009f88: 71bb strb r3, [r7, #6] 8009f8a: 460b mov r3, r1 8009f8c: 717b strb r3, [r7, #5] 8009f8e: 4613 mov r3, r2 8009f90: 713b strb r3, [r7, #4] uint8_t buf[4]; buf[0] = paDutyCycle; 8009f92: 79fb ldrb r3, [r7, #7] 8009f94: 733b strb r3, [r7, #12] buf[1] = hpMax; 8009f96: 79bb ldrb r3, [r7, #6] 8009f98: 737b strb r3, [r7, #13] buf[2] = deviceSel; 8009f9a: 797b ldrb r3, [r7, #5] 8009f9c: 73bb strb r3, [r7, #14] buf[3] = paLut; 8009f9e: 793b ldrb r3, [r7, #4] 8009fa0: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 ); 8009fa2: f107 030c add.w r3, r7, #12 8009fa6: 2204 movs r2, #4 8009fa8: 4619 mov r1, r3 8009faa: 2095 movs r0, #149 @ 0x95 8009fac: f000 fc78 bl 800a8a0 } 8009fb0: bf00 nop 8009fb2: 3714 adds r7, #20 8009fb4: 46bd mov sp, r7 8009fb6: bd90 pop {r4, r7, pc} 08009fb8 : { SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); } void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) { 8009fb8: b590 push {r4, r7, lr} 8009fba: b085 sub sp, #20 8009fbc: af00 add r7, sp, #0 8009fbe: 4604 mov r4, r0 8009fc0: 4608 mov r0, r1 8009fc2: 4611 mov r1, r2 8009fc4: 461a mov r2, r3 8009fc6: 4623 mov r3, r4 8009fc8: 80fb strh r3, [r7, #6] 8009fca: 4603 mov r3, r0 8009fcc: 80bb strh r3, [r7, #4] 8009fce: 460b mov r3, r1 8009fd0: 807b strh r3, [r7, #2] 8009fd2: 4613 mov r3, r2 8009fd4: 803b strh r3, [r7, #0] uint8_t buf[8]; buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); 8009fd6: 88fb ldrh r3, [r7, #6] 8009fd8: 0a1b lsrs r3, r3, #8 8009fda: b29b uxth r3, r3 8009fdc: b2db uxtb r3, r3 8009fde: 723b strb r3, [r7, #8] buf[1] = ( uint8_t )( irqMask & 0x00FF ); 8009fe0: 88fb ldrh r3, [r7, #6] 8009fe2: b2db uxtb r3, r3 8009fe4: 727b strb r3, [r7, #9] buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); 8009fe6: 88bb ldrh r3, [r7, #4] 8009fe8: 0a1b lsrs r3, r3, #8 8009fea: b29b uxth r3, r3 8009fec: b2db uxtb r3, r3 8009fee: 72bb strb r3, [r7, #10] buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); 8009ff0: 88bb ldrh r3, [r7, #4] 8009ff2: b2db uxtb r3, r3 8009ff4: 72fb strb r3, [r7, #11] buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); 8009ff6: 887b ldrh r3, [r7, #2] 8009ff8: 0a1b lsrs r3, r3, #8 8009ffa: b29b uxth r3, r3 8009ffc: b2db uxtb r3, r3 8009ffe: 733b strb r3, [r7, #12] buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); 800a000: 887b ldrh r3, [r7, #2] 800a002: b2db uxtb r3, r3 800a004: 737b strb r3, [r7, #13] buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); 800a006: 883b ldrh r3, [r7, #0] 800a008: 0a1b lsrs r3, r3, #8 800a00a: b29b uxth r3, r3 800a00c: b2db uxtb r3, r3 800a00e: 73bb strb r3, [r7, #14] buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); 800a010: 883b ldrh r3, [r7, #0] 800a012: b2db uxtb r3, r3 800a014: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); 800a016: f107 0308 add.w r3, r7, #8 800a01a: 2208 movs r2, #8 800a01c: 4619 mov r1, r3 800a01e: 2008 movs r0, #8 800a020: f000 fc3e bl 800a8a0 } 800a024: bf00 nop 800a026: 3714 adds r7, #20 800a028: 46bd mov sp, r7 800a02a: bd90 pop {r4, r7, pc} 0800a02c : SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); return ( irqStatus[0] << 8 ) | irqStatus[1]; } void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) { 800a02c: b580 push {r7, lr} 800a02e: b084 sub sp, #16 800a030: af00 add r7, sp, #0 800a032: 4603 mov r3, r0 800a034: 6039 str r1, [r7, #0] 800a036: 71fb strb r3, [r7, #7] uint8_t buf[4]; buf[0] = tcxoVoltage & 0x07; 800a038: 79fb ldrb r3, [r7, #7] 800a03a: f003 0307 and.w r3, r3, #7 800a03e: b2db uxtb r3, r3 800a040: 733b strb r3, [r7, #12] buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); 800a042: 683b ldr r3, [r7, #0] 800a044: 0c1b lsrs r3, r3, #16 800a046: b2db uxtb r3, r3 800a048: 737b strb r3, [r7, #13] buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); 800a04a: 683b ldr r3, [r7, #0] 800a04c: 0a1b lsrs r3, r3, #8 800a04e: b2db uxtb r3, r3 800a050: 73bb strb r3, [r7, #14] buf[3] = ( uint8_t )( timeout & 0xFF ); 800a052: 683b ldr r3, [r7, #0] 800a054: b2db uxtb r3, r3 800a056: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); 800a058: f107 030c add.w r3, r7, #12 800a05c: 2204 movs r2, #4 800a05e: 4619 mov r1, r3 800a060: 2097 movs r0, #151 @ 0x97 800a062: f000 fc1d bl 800a8a0 } 800a066: bf00 nop 800a068: 3710 adds r7, #16 800a06a: 46bd mov sp, r7 800a06c: bd80 pop {r7, pc} ... 0800a070 : void SUBGRF_SetRfFrequency( uint32_t frequency ) { 800a070: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800a074: b084 sub sp, #16 800a076: af00 add r7, sp, #0 800a078: 6078 str r0, [r7, #4] uint8_t buf[4]; uint32_t chan = 0; 800a07a: 2300 movs r3, #0 800a07c: 60fb str r3, [r7, #12] if( ImageCalibrated == false ) 800a07e: 4b1d ldr r3, [pc, #116] @ (800a0f4 ) 800a080: 781b ldrb r3, [r3, #0] 800a082: f083 0301 eor.w r3, r3, #1 800a086: b2db uxtb r3, r3 800a088: 2b00 cmp r3, #0 800a08a: d005 beq.n 800a098 { SUBGRF_CalibrateImage( frequency ); 800a08c: 6878 ldr r0, [r7, #4] 800a08e: f7ff ff27 bl 8009ee0 ImageCalibrated = true; 800a092: 4b18 ldr r3, [pc, #96] @ (800a0f4 ) 800a094: 2201 movs r2, #1 800a096: 701a strb r2, [r3, #0] } SX_FREQ_TO_CHANNEL(chan, frequency); 800a098: 687b ldr r3, [r7, #4] 800a09a: 2200 movs r2, #0 800a09c: 461c mov r4, r3 800a09e: 4615 mov r5, r2 800a0a0: ea4f 19d4 mov.w r9, r4, lsr #7 800a0a4: ea4f 6844 mov.w r8, r4, lsl #25 800a0a8: 4a13 ldr r2, [pc, #76] @ (800a0f8 ) 800a0aa: f04f 0300 mov.w r3, #0 800a0ae: 4640 mov r0, r8 800a0b0: 4649 mov r1, r9 800a0b2: f7f6 f8cd bl 8000250 <__aeabi_uldivmod> 800a0b6: 4602 mov r2, r0 800a0b8: 460b mov r3, r1 800a0ba: 4613 mov r3, r2 800a0bc: 60fb str r3, [r7, #12] buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF ); 800a0be: 68fb ldr r3, [r7, #12] 800a0c0: 0e1b lsrs r3, r3, #24 800a0c2: b2db uxtb r3, r3 800a0c4: 723b strb r3, [r7, #8] buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF ); 800a0c6: 68fb ldr r3, [r7, #12] 800a0c8: 0c1b lsrs r3, r3, #16 800a0ca: b2db uxtb r3, r3 800a0cc: 727b strb r3, [r7, #9] buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF ); 800a0ce: 68fb ldr r3, [r7, #12] 800a0d0: 0a1b lsrs r3, r3, #8 800a0d2: b2db uxtb r3, r3 800a0d4: 72bb strb r3, [r7, #10] buf[3] = ( uint8_t )( chan & 0xFF ); 800a0d6: 68fb ldr r3, [r7, #12] 800a0d8: b2db uxtb r3, r3 800a0da: 72fb strb r3, [r7, #11] SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); 800a0dc: f107 0308 add.w r3, r7, #8 800a0e0: 2204 movs r2, #4 800a0e2: 4619 mov r1, r3 800a0e4: 2086 movs r0, #134 @ 0x86 800a0e6: f000 fbdb bl 800a8a0 } 800a0ea: bf00 nop 800a0ec: 3710 adds r7, #16 800a0ee: 46bd mov sp, r7 800a0f0: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800a0f4: 20000394 .word 0x20000394 800a0f8: 01e84800 .word 0x01e84800 0800a0fc : void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ) { 800a0fc: b580 push {r7, lr} 800a0fe: b082 sub sp, #8 800a100: af00 add r7, sp, #0 800a102: 4603 mov r3, r0 800a104: 71fb strb r3, [r7, #7] // Save packet type internally to avoid questioning the radio PacketType = packetType; 800a106: 79fa ldrb r2, [r7, #7] 800a108: 4b09 ldr r3, [pc, #36] @ (800a130 ) 800a10a: 701a strb r2, [r3, #0] if( packetType == PACKET_TYPE_GFSK ) 800a10c: 79fb ldrb r3, [r7, #7] 800a10e: 2b00 cmp r3, #0 800a110: d104 bne.n 800a11c { SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 ); 800a112: 2100 movs r1, #0 800a114: f240 60ac movw r0, #1708 @ 0x6ac 800a118: f000 faf8 bl 800a70c } SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); 800a11c: 1dfb adds r3, r7, #7 800a11e: 2201 movs r2, #1 800a120: 4619 mov r1, r3 800a122: 208a movs r0, #138 @ 0x8a 800a124: f000 fbbc bl 800a8a0 } 800a128: bf00 nop 800a12a: 3708 adds r7, #8 800a12c: 46bd mov sp, r7 800a12e: bd80 pop {r7, pc} 800a130: 2000038d .word 0x2000038d 0800a134 : RadioPacketTypes_t SUBGRF_GetPacketType( void ) { 800a134: b480 push {r7} 800a136: af00 add r7, sp, #0 return PacketType; 800a138: 4b02 ldr r3, [pc, #8] @ (800a144 ) 800a13a: 781b ldrb r3, [r3, #0] } 800a13c: 4618 mov r0, r3 800a13e: 46bd mov sp, r7 800a140: bc80 pop {r7} 800a142: 4770 bx lr 800a144: 2000038d .word 0x2000038d 0800a148 : void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ) { 800a148: b580 push {r7, lr} 800a14a: b084 sub sp, #16 800a14c: af00 add r7, sp, #0 800a14e: 4603 mov r3, r0 800a150: 71fb strb r3, [r7, #7] 800a152: 460b mov r3, r1 800a154: 71bb strb r3, [r7, #6] 800a156: 4613 mov r3, r2 800a158: 717b strb r3, [r7, #5] uint8_t buf[2]; int32_t max_power; if (paSelect == RFO_LP) 800a15a: 79fb ldrb r3, [r7, #7] 800a15c: 2b01 cmp r3, #1 800a15e: d149 bne.n 800a1f4 { max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER); 800a160: 2000 movs r0, #0 800a162: f002 ffaf bl 800d0c4 800a166: 60f8 str r0, [r7, #12] if (power > max_power) 800a168: f997 3006 ldrsb.w r3, [r7, #6] 800a16c: 68fa ldr r2, [r7, #12] 800a16e: 429a cmp r2, r3 800a170: da01 bge.n 800a176 { power = max_power; 800a172: 68fb ldr r3, [r7, #12] 800a174: 71bb strb r3, [r7, #6] } if (max_power == 14) 800a176: 68fb ldr r3, [r7, #12] 800a178: 2b0e cmp r3, #14 800a17a: d10e bne.n 800a19a { SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01); 800a17c: 2301 movs r3, #1 800a17e: 2201 movs r2, #1 800a180: 2100 movs r1, #0 800a182: 2004 movs r0, #4 800a184: f7ff fef6 bl 8009f74 power = 0x0E - (max_power - power); 800a188: 79ba ldrb r2, [r7, #6] 800a18a: 68fb ldr r3, [r7, #12] 800a18c: b2db uxtb r3, r3 800a18e: 1ad3 subs r3, r2, r3 800a190: b2db uxtb r3, r3 800a192: 330e adds r3, #14 800a194: b2db uxtb r3, r3 800a196: 71bb strb r3, [r7, #6] 800a198: e01f b.n 800a1da } else if (max_power == 10) 800a19a: 68fb ldr r3, [r7, #12] 800a19c: 2b0a cmp r3, #10 800a19e: d10e bne.n 800a1be { SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01); 800a1a0: 2301 movs r3, #1 800a1a2: 2201 movs r2, #1 800a1a4: 2100 movs r1, #0 800a1a6: 2001 movs r0, #1 800a1a8: f7ff fee4 bl 8009f74 power = 0x0D - (max_power - power); 800a1ac: 79ba ldrb r2, [r7, #6] 800a1ae: 68fb ldr r3, [r7, #12] 800a1b0: b2db uxtb r3, r3 800a1b2: 1ad3 subs r3, r2, r3 800a1b4: b2db uxtb r3, r3 800a1b6: 330d adds r3, #13 800a1b8: b2db uxtb r3, r3 800a1ba: 71bb strb r3, [r7, #6] 800a1bc: e00d b.n 800a1da } else /*default 15dBm*/ { SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01); 800a1be: 2301 movs r3, #1 800a1c0: 2201 movs r2, #1 800a1c2: 2100 movs r1, #0 800a1c4: 2007 movs r0, #7 800a1c6: f7ff fed5 bl 8009f74 power = 0x0E - (max_power - power); 800a1ca: 79ba ldrb r2, [r7, #6] 800a1cc: 68fb ldr r3, [r7, #12] 800a1ce: b2db uxtb r3, r3 800a1d0: 1ad3 subs r3, r2, r3 800a1d2: b2db uxtb r3, r3 800a1d4: 330e adds r3, #14 800a1d6: b2db uxtb r3, r3 800a1d8: 71bb strb r3, [r7, #6] } if (power < -17) 800a1da: f997 3006 ldrsb.w r3, [r7, #6] 800a1de: f113 0f11 cmn.w r3, #17 800a1e2: da01 bge.n 800a1e8 { power = -17; 800a1e4: 23ef movs r3, #239 @ 0xef 800a1e6: 71bb strb r3, [r7, #6] } SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/ 800a1e8: 2118 movs r1, #24 800a1ea: f640 00e7 movw r0, #2279 @ 0x8e7 800a1ee: f000 fa8d bl 800a70c 800a1f2: e067 b.n 800a2c4 } else /* rfo_hp*/ { /* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/ SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1)); 800a1f4: f640 00d8 movw r0, #2264 @ 0x8d8 800a1f8: f000 faaa bl 800a750 800a1fc: 4603 mov r3, r0 800a1fe: f043 031e orr.w r3, r3, #30 800a202: b2db uxtb r3, r3 800a204: 4619 mov r1, r3 800a206: f640 00d8 movw r0, #2264 @ 0x8d8 800a20a: f000 fa7f bl 800a70c /* WORKAROUND END*/ max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER); 800a20e: 2001 movs r0, #1 800a210: f002 ff58 bl 800d0c4 800a214: 60f8 str r0, [r7, #12] if (power > max_power) 800a216: f997 3006 ldrsb.w r3, [r7, #6] 800a21a: 68fa ldr r2, [r7, #12] 800a21c: 429a cmp r2, r3 800a21e: da01 bge.n 800a224 { power = max_power; 800a220: 68fb ldr r3, [r7, #12] 800a222: 71bb strb r3, [r7, #6] } if (max_power == 20) 800a224: 68fb ldr r3, [r7, #12] 800a226: 2b14 cmp r3, #20 800a228: d10e bne.n 800a248 { SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01); 800a22a: 2301 movs r3, #1 800a22c: 2200 movs r2, #0 800a22e: 2105 movs r1, #5 800a230: 2003 movs r0, #3 800a232: f7ff fe9f bl 8009f74 power = 0x16 - (max_power - power); 800a236: 79ba ldrb r2, [r7, #6] 800a238: 68fb ldr r3, [r7, #12] 800a23a: b2db uxtb r3, r3 800a23c: 1ad3 subs r3, r2, r3 800a23e: b2db uxtb r3, r3 800a240: 3316 adds r3, #22 800a242: b2db uxtb r3, r3 800a244: 71bb strb r3, [r7, #6] 800a246: e031 b.n 800a2ac } else if (max_power == 17) 800a248: 68fb ldr r3, [r7, #12] 800a24a: 2b11 cmp r3, #17 800a24c: d10e bne.n 800a26c { SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01); 800a24e: 2301 movs r3, #1 800a250: 2200 movs r2, #0 800a252: 2103 movs r1, #3 800a254: 2002 movs r0, #2 800a256: f7ff fe8d bl 8009f74 power = 0x16 - (max_power - power); 800a25a: 79ba ldrb r2, [r7, #6] 800a25c: 68fb ldr r3, [r7, #12] 800a25e: b2db uxtb r3, r3 800a260: 1ad3 subs r3, r2, r3 800a262: b2db uxtb r3, r3 800a264: 3316 adds r3, #22 800a266: b2db uxtb r3, r3 800a268: 71bb strb r3, [r7, #6] 800a26a: e01f b.n 800a2ac } else if (max_power == 14) 800a26c: 68fb ldr r3, [r7, #12] 800a26e: 2b0e cmp r3, #14 800a270: d10e bne.n 800a290 { SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01); 800a272: 2301 movs r3, #1 800a274: 2200 movs r2, #0 800a276: 2102 movs r1, #2 800a278: 2002 movs r0, #2 800a27a: f7ff fe7b bl 8009f74 power = 0x0E - (max_power - power); 800a27e: 79ba ldrb r2, [r7, #6] 800a280: 68fb ldr r3, [r7, #12] 800a282: b2db uxtb r3, r3 800a284: 1ad3 subs r3, r2, r3 800a286: b2db uxtb r3, r3 800a288: 330e adds r3, #14 800a28a: b2db uxtb r3, r3 800a28c: 71bb strb r3, [r7, #6] 800a28e: e00d b.n 800a2ac } else /*22dBm*/ { SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01); 800a290: 2301 movs r3, #1 800a292: 2200 movs r2, #0 800a294: 2107 movs r1, #7 800a296: 2004 movs r0, #4 800a298: f7ff fe6c bl 8009f74 power = 0x16 - (max_power - power); 800a29c: 79ba ldrb r2, [r7, #6] 800a29e: 68fb ldr r3, [r7, #12] 800a2a0: b2db uxtb r3, r3 800a2a2: 1ad3 subs r3, r2, r3 800a2a4: b2db uxtb r3, r3 800a2a6: 3316 adds r3, #22 800a2a8: b2db uxtb r3, r3 800a2aa: 71bb strb r3, [r7, #6] } if (power < -9) 800a2ac: f997 3006 ldrsb.w r3, [r7, #6] 800a2b0: f113 0f09 cmn.w r3, #9 800a2b4: da01 bge.n 800a2ba { power = -9; 800a2b6: 23f7 movs r3, #247 @ 0xf7 800a2b8: 71bb strb r3, [r7, #6] } SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/ 800a2ba: 2138 movs r1, #56 @ 0x38 800a2bc: f640 00e7 movw r0, #2279 @ 0x8e7 800a2c0: f000 fa24 bl 800a70c } buf[0] = power; 800a2c4: 79bb ldrb r3, [r7, #6] 800a2c6: 723b strb r3, [r7, #8] buf[1] = (uint8_t)rampTime; 800a2c8: 797b ldrb r3, [r7, #5] 800a2ca: 727b strb r3, [r7, #9] SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2); 800a2cc: f107 0308 add.w r3, r7, #8 800a2d0: 2202 movs r2, #2 800a2d2: 4619 mov r1, r3 800a2d4: 208e movs r0, #142 @ 0x8e 800a2d6: f000 fae3 bl 800a8a0 } 800a2da: bf00 nop 800a2dc: 3710 adds r7, #16 800a2de: 46bd mov sp, r7 800a2e0: bd80 pop {r7, pc} ... 0800a2e4 : void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams ) { 800a2e4: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800a2e8: b086 sub sp, #24 800a2ea: af00 add r7, sp, #0 800a2ec: 6078 str r0, [r7, #4] uint8_t n; uint32_t tempVal = 0; 800a2ee: 2300 movs r3, #0 800a2f0: 617b str r3, [r7, #20] uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; 800a2f2: f107 0308 add.w r3, r7, #8 800a2f6: 2200 movs r2, #0 800a2f8: 601a str r2, [r3, #0] 800a2fa: 605a str r2, [r3, #4] // Check if required configuration corresponds to the stored packet type // If not, silently update radio packet type if( PacketType != modulationParams->PacketType ) 800a2fc: 687b ldr r3, [r7, #4] 800a2fe: 781a ldrb r2, [r3, #0] 800a300: 4b5c ldr r3, [pc, #368] @ (800a474 ) 800a302: 781b ldrb r3, [r3, #0] 800a304: 429a cmp r2, r3 800a306: d004 beq.n 800a312 { SUBGRF_SetPacketType( modulationParams->PacketType ); 800a308: 687b ldr r3, [r7, #4] 800a30a: 781b ldrb r3, [r3, #0] 800a30c: 4618 mov r0, r3 800a30e: f7ff fef5 bl 800a0fc } switch( modulationParams->PacketType ) 800a312: 687b ldr r3, [r7, #4] 800a314: 781b ldrb r3, [r3, #0] 800a316: 2b03 cmp r3, #3 800a318: f200 80a5 bhi.w 800a466 800a31c: a201 add r2, pc, #4 @ (adr r2, 800a324 ) 800a31e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a322: bf00 nop 800a324: 0800a335 .word 0x0800a335 800a328: 0800a3f5 .word 0x0800a3f5 800a32c: 0800a3b7 .word 0x0800a3b7 800a330: 0800a423 .word 0x0800a423 { case PACKET_TYPE_GFSK: n = 8; 800a334: 2308 movs r3, #8 800a336: 74fb strb r3, [r7, #19] tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate ); 800a338: 687b ldr r3, [r7, #4] 800a33a: 685b ldr r3, [r3, #4] 800a33c: 4a4e ldr r2, [pc, #312] @ (800a478 ) 800a33e: fbb2 f3f3 udiv r3, r2, r3 800a342: 617b str r3, [r7, #20] buf[0] = ( tempVal >> 16 ) & 0xFF; 800a344: 697b ldr r3, [r7, #20] 800a346: 0c1b lsrs r3, r3, #16 800a348: b2db uxtb r3, r3 800a34a: 723b strb r3, [r7, #8] buf[1] = ( tempVal >> 8 ) & 0xFF; 800a34c: 697b ldr r3, [r7, #20] 800a34e: 0a1b lsrs r3, r3, #8 800a350: b2db uxtb r3, r3 800a352: 727b strb r3, [r7, #9] buf[2] = tempVal & 0xFF; 800a354: 697b ldr r3, [r7, #20] 800a356: b2db uxtb r3, r3 800a358: 72bb strb r3, [r7, #10] buf[3] = modulationParams->Params.Gfsk.ModulationShaping; 800a35a: 687b ldr r3, [r7, #4] 800a35c: 7b1b ldrb r3, [r3, #12] 800a35e: 72fb strb r3, [r7, #11] buf[4] = modulationParams->Params.Gfsk.Bandwidth; 800a360: 687b ldr r3, [r7, #4] 800a362: 7b5b ldrb r3, [r3, #13] 800a364: 733b strb r3, [r7, #12] SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev); 800a366: 687b ldr r3, [r7, #4] 800a368: 689b ldr r3, [r3, #8] 800a36a: 2200 movs r2, #0 800a36c: 461c mov r4, r3 800a36e: 4615 mov r5, r2 800a370: ea4f 19d4 mov.w r9, r4, lsr #7 800a374: ea4f 6844 mov.w r8, r4, lsl #25 800a378: 4a40 ldr r2, [pc, #256] @ (800a47c ) 800a37a: f04f 0300 mov.w r3, #0 800a37e: 4640 mov r0, r8 800a380: 4649 mov r1, r9 800a382: f7f5 ff65 bl 8000250 <__aeabi_uldivmod> 800a386: 4602 mov r2, r0 800a388: 460b mov r3, r1 800a38a: 4613 mov r3, r2 800a38c: 617b str r3, [r7, #20] buf[5] = ( tempVal >> 16 ) & 0xFF; 800a38e: 697b ldr r3, [r7, #20] 800a390: 0c1b lsrs r3, r3, #16 800a392: b2db uxtb r3, r3 800a394: 737b strb r3, [r7, #13] buf[6] = ( tempVal >> 8 ) & 0xFF; 800a396: 697b ldr r3, [r7, #20] 800a398: 0a1b lsrs r3, r3, #8 800a39a: b2db uxtb r3, r3 800a39c: 73bb strb r3, [r7, #14] buf[7] = ( tempVal& 0xFF ); 800a39e: 697b ldr r3, [r7, #20] 800a3a0: b2db uxtb r3, r3 800a3a2: 73fb strb r3, [r7, #15] SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); 800a3a4: 7cfb ldrb r3, [r7, #19] 800a3a6: b29a uxth r2, r3 800a3a8: f107 0308 add.w r3, r7, #8 800a3ac: 4619 mov r1, r3 800a3ae: 208b movs r0, #139 @ 0x8b 800a3b0: f000 fa76 bl 800a8a0 break; 800a3b4: e058 b.n 800a468 case PACKET_TYPE_BPSK: n = 4; 800a3b6: 2304 movs r3, #4 800a3b8: 74fb strb r3, [r7, #19] tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate ); 800a3ba: 687b ldr r3, [r7, #4] 800a3bc: 691b ldr r3, [r3, #16] 800a3be: 4a2e ldr r2, [pc, #184] @ (800a478 ) 800a3c0: fbb2 f3f3 udiv r3, r2, r3 800a3c4: 617b str r3, [r7, #20] buf[0] = ( tempVal >> 16 ) & 0xFF; 800a3c6: 697b ldr r3, [r7, #20] 800a3c8: 0c1b lsrs r3, r3, #16 800a3ca: b2db uxtb r3, r3 800a3cc: 723b strb r3, [r7, #8] buf[1] = ( tempVal >> 8 ) & 0xFF; 800a3ce: 697b ldr r3, [r7, #20] 800a3d0: 0a1b lsrs r3, r3, #8 800a3d2: b2db uxtb r3, r3 800a3d4: 727b strb r3, [r7, #9] buf[2] = tempVal & 0xFF; 800a3d6: 697b ldr r3, [r7, #20] 800a3d8: b2db uxtb r3, r3 800a3da: 72bb strb r3, [r7, #10] buf[3] = modulationParams->Params.Bpsk.ModulationShaping; 800a3dc: 687b ldr r3, [r7, #4] 800a3de: 7d1b ldrb r3, [r3, #20] 800a3e0: 72fb strb r3, [r7, #11] SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); 800a3e2: 7cfb ldrb r3, [r7, #19] 800a3e4: b29a uxth r2, r3 800a3e6: f107 0308 add.w r3, r7, #8 800a3ea: 4619 mov r1, r3 800a3ec: 208b movs r0, #139 @ 0x8b 800a3ee: f000 fa57 bl 800a8a0 break; 800a3f2: e039 b.n 800a468 case PACKET_TYPE_LORA: n = 4; 800a3f4: 2304 movs r3, #4 800a3f6: 74fb strb r3, [r7, #19] buf[0] = modulationParams->Params.LoRa.SpreadingFactor; 800a3f8: 687b ldr r3, [r7, #4] 800a3fa: 7e1b ldrb r3, [r3, #24] 800a3fc: 723b strb r3, [r7, #8] buf[1] = modulationParams->Params.LoRa.Bandwidth; 800a3fe: 687b ldr r3, [r7, #4] 800a400: 7e5b ldrb r3, [r3, #25] 800a402: 727b strb r3, [r7, #9] buf[2] = modulationParams->Params.LoRa.CodingRate; 800a404: 687b ldr r3, [r7, #4] 800a406: 7e9b ldrb r3, [r3, #26] 800a408: 72bb strb r3, [r7, #10] buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; 800a40a: 687b ldr r3, [r7, #4] 800a40c: 7edb ldrb r3, [r3, #27] 800a40e: 72fb strb r3, [r7, #11] SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); 800a410: 7cfb ldrb r3, [r7, #19] 800a412: b29a uxth r2, r3 800a414: f107 0308 add.w r3, r7, #8 800a418: 4619 mov r1, r3 800a41a: 208b movs r0, #139 @ 0x8b 800a41c: f000 fa40 bl 800a8a0 break; 800a420: e022 b.n 800a468 case PACKET_TYPE_GMSK: n = 5; 800a422: 2305 movs r3, #5 800a424: 74fb strb r3, [r7, #19] tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate ); 800a426: 687b ldr r3, [r7, #4] 800a428: 685b ldr r3, [r3, #4] 800a42a: 4a13 ldr r2, [pc, #76] @ (800a478 ) 800a42c: fbb2 f3f3 udiv r3, r2, r3 800a430: 617b str r3, [r7, #20] buf[0] = ( tempVal >> 16 ) & 0xFF; 800a432: 697b ldr r3, [r7, #20] 800a434: 0c1b lsrs r3, r3, #16 800a436: b2db uxtb r3, r3 800a438: 723b strb r3, [r7, #8] buf[1] = ( tempVal >> 8 ) & 0xFF; 800a43a: 697b ldr r3, [r7, #20] 800a43c: 0a1b lsrs r3, r3, #8 800a43e: b2db uxtb r3, r3 800a440: 727b strb r3, [r7, #9] buf[2] = tempVal & 0xFF; 800a442: 697b ldr r3, [r7, #20] 800a444: b2db uxtb r3, r3 800a446: 72bb strb r3, [r7, #10] buf[3] = modulationParams->Params.Gfsk.ModulationShaping; 800a448: 687b ldr r3, [r7, #4] 800a44a: 7b1b ldrb r3, [r3, #12] 800a44c: 72fb strb r3, [r7, #11] buf[4] = modulationParams->Params.Gfsk.Bandwidth; 800a44e: 687b ldr r3, [r7, #4] 800a450: 7b5b ldrb r3, [r3, #13] 800a452: 733b strb r3, [r7, #12] SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); 800a454: 7cfb ldrb r3, [r7, #19] 800a456: b29a uxth r2, r3 800a458: f107 0308 add.w r3, r7, #8 800a45c: 4619 mov r1, r3 800a45e: 208b movs r0, #139 @ 0x8b 800a460: f000 fa1e bl 800a8a0 break; 800a464: e000 b.n 800a468 default: case PACKET_TYPE_NONE: break; 800a466: bf00 nop } } 800a468: bf00 nop 800a46a: 3718 adds r7, #24 800a46c: 46bd mov sp, r7 800a46e: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800a472: bf00 nop 800a474: 2000038d .word 0x2000038d 800a478: 3d090000 .word 0x3d090000 800a47c: 01e84800 .word 0x01e84800 0800a480 : void SUBGRF_SetPacketParams( PacketParams_t *packetParams ) { 800a480: b580 push {r7, lr} 800a482: b086 sub sp, #24 800a484: af00 add r7, sp, #0 800a486: 6078 str r0, [r7, #4] uint8_t n; uint8_t crcVal = 0; 800a488: 2300 movs r3, #0 800a48a: 75bb strb r3, [r7, #22] uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; 800a48c: f107 030c add.w r3, r7, #12 800a490: 2200 movs r2, #0 800a492: 601a str r2, [r3, #0] 800a494: 605a str r2, [r3, #4] 800a496: 721a strb r2, [r3, #8] // Check if required configuration corresponds to the stored packet type // If not, silently update radio packet type if( PacketType != packetParams->PacketType ) 800a498: 687b ldr r3, [r7, #4] 800a49a: 781a ldrb r2, [r3, #0] 800a49c: 4b44 ldr r3, [pc, #272] @ (800a5b0 ) 800a49e: 781b ldrb r3, [r3, #0] 800a4a0: 429a cmp r2, r3 800a4a2: d004 beq.n 800a4ae { SUBGRF_SetPacketType( packetParams->PacketType ); 800a4a4: 687b ldr r3, [r7, #4] 800a4a6: 781b ldrb r3, [r3, #0] 800a4a8: 4618 mov r0, r3 800a4aa: f7ff fe27 bl 800a0fc } switch( packetParams->PacketType ) 800a4ae: 687b ldr r3, [r7, #4] 800a4b0: 781b ldrb r3, [r3, #0] 800a4b2: 2b03 cmp r3, #3 800a4b4: d878 bhi.n 800a5a8 800a4b6: a201 add r2, pc, #4 @ (adr r2, 800a4bc ) 800a4b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a4bc: 0800a4cd .word 0x0800a4cd 800a4c0: 0800a55d .word 0x0800a55d 800a4c4: 0800a551 .word 0x0800a551 800a4c8: 0800a4cd .word 0x0800a4cd { case PACKET_TYPE_GMSK: case PACKET_TYPE_GFSK: if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) 800a4cc: 687b ldr r3, [r7, #4] 800a4ce: 7a5b ldrb r3, [r3, #9] 800a4d0: 2bf1 cmp r3, #241 @ 0xf1 800a4d2: d10a bne.n 800a4ea { SUBGRF_SetCrcSeed( CRC_IBM_SEED ); 800a4d4: f64f 70ff movw r0, #65535 @ 0xffff 800a4d8: f7ff faa6 bl 8009a28 SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM ); 800a4dc: f248 0005 movw r0, #32773 @ 0x8005 800a4e0: f7ff fac2 bl 8009a68 crcVal = RADIO_CRC_2_BYTES; 800a4e4: 2302 movs r3, #2 800a4e6: 75bb strb r3, [r7, #22] 800a4e8: e011 b.n 800a50e } else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) 800a4ea: 687b ldr r3, [r7, #4] 800a4ec: 7a5b ldrb r3, [r3, #9] 800a4ee: 2bf2 cmp r3, #242 @ 0xf2 800a4f0: d10a bne.n 800a508 { SUBGRF_SetCrcSeed( CRC_CCITT_SEED ); 800a4f2: f641 500f movw r0, #7439 @ 0x1d0f 800a4f6: f7ff fa97 bl 8009a28 SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); 800a4fa: f241 0021 movw r0, #4129 @ 0x1021 800a4fe: f7ff fab3 bl 8009a68 crcVal = RADIO_CRC_2_BYTES_INV; 800a502: 2306 movs r3, #6 800a504: 75bb strb r3, [r7, #22] 800a506: e002 b.n 800a50e } else { crcVal = packetParams->Params.Gfsk.CrcLength; 800a508: 687b ldr r3, [r7, #4] 800a50a: 7a5b ldrb r3, [r3, #9] 800a50c: 75bb strb r3, [r7, #22] } n = 9; 800a50e: 2309 movs r3, #9 800a510: 75fb strb r3, [r7, #23] buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; 800a512: 687b ldr r3, [r7, #4] 800a514: 885b ldrh r3, [r3, #2] 800a516: 0a1b lsrs r3, r3, #8 800a518: b29b uxth r3, r3 800a51a: b2db uxtb r3, r3 800a51c: 733b strb r3, [r7, #12] buf[1] = packetParams->Params.Gfsk.PreambleLength; 800a51e: 687b ldr r3, [r7, #4] 800a520: 885b ldrh r3, [r3, #2] 800a522: b2db uxtb r3, r3 800a524: 737b strb r3, [r7, #13] buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; 800a526: 687b ldr r3, [r7, #4] 800a528: 791b ldrb r3, [r3, #4] 800a52a: 73bb strb r3, [r7, #14] buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit 800a52c: 687b ldr r3, [r7, #4] 800a52e: 795b ldrb r3, [r3, #5] 800a530: 73fb strb r3, [r7, #15] buf[4] = packetParams->Params.Gfsk.AddrComp; 800a532: 687b ldr r3, [r7, #4] 800a534: 799b ldrb r3, [r3, #6] 800a536: 743b strb r3, [r7, #16] buf[5] = packetParams->Params.Gfsk.HeaderType; 800a538: 687b ldr r3, [r7, #4] 800a53a: 79db ldrb r3, [r3, #7] 800a53c: 747b strb r3, [r7, #17] buf[6] = packetParams->Params.Gfsk.PayloadLength; 800a53e: 687b ldr r3, [r7, #4] 800a540: 7a1b ldrb r3, [r3, #8] 800a542: 74bb strb r3, [r7, #18] buf[7] = crcVal; 800a544: 7dbb ldrb r3, [r7, #22] 800a546: 74fb strb r3, [r7, #19] buf[8] = packetParams->Params.Gfsk.DcFree; 800a548: 687b ldr r3, [r7, #4] 800a54a: 7a9b ldrb r3, [r3, #10] 800a54c: 753b strb r3, [r7, #20] break; 800a54e: e022 b.n 800a596 case PACKET_TYPE_BPSK: n = 1; 800a550: 2301 movs r3, #1 800a552: 75fb strb r3, [r7, #23] buf[0] = packetParams->Params.Bpsk.PayloadLength; 800a554: 687b ldr r3, [r7, #4] 800a556: 7b1b ldrb r3, [r3, #12] 800a558: 733b strb r3, [r7, #12] break; 800a55a: e01c b.n 800a596 case PACKET_TYPE_LORA: n = 6; 800a55c: 2306 movs r3, #6 800a55e: 75fb strb r3, [r7, #23] buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; 800a560: 687b ldr r3, [r7, #4] 800a562: 89db ldrh r3, [r3, #14] 800a564: 0a1b lsrs r3, r3, #8 800a566: b29b uxth r3, r3 800a568: b2db uxtb r3, r3 800a56a: 733b strb r3, [r7, #12] buf[1] = packetParams->Params.LoRa.PreambleLength; 800a56c: 687b ldr r3, [r7, #4] 800a56e: 89db ldrh r3, [r3, #14] 800a570: b2db uxtb r3, r3 800a572: 737b strb r3, [r7, #13] buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType; 800a574: 687b ldr r3, [r7, #4] 800a576: 7c1a ldrb r2, [r3, #16] 800a578: 4b0e ldr r3, [pc, #56] @ (800a5b4 ) 800a57a: 4611 mov r1, r2 800a57c: 7019 strb r1, [r3, #0] 800a57e: 4613 mov r3, r2 800a580: 73bb strb r3, [r7, #14] buf[3] = packetParams->Params.LoRa.PayloadLength; 800a582: 687b ldr r3, [r7, #4] 800a584: 7c5b ldrb r3, [r3, #17] 800a586: 73fb strb r3, [r7, #15] buf[4] = packetParams->Params.LoRa.CrcMode; 800a588: 687b ldr r3, [r7, #4] 800a58a: 7c9b ldrb r3, [r3, #18] 800a58c: 743b strb r3, [r7, #16] buf[5] = packetParams->Params.LoRa.InvertIQ; 800a58e: 687b ldr r3, [r7, #4] 800a590: 7cdb ldrb r3, [r3, #19] 800a592: 747b strb r3, [r7, #17] break; 800a594: bf00 nop default: case PACKET_TYPE_NONE: return; } SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); 800a596: 7dfb ldrb r3, [r7, #23] 800a598: b29a uxth r2, r3 800a59a: f107 030c add.w r3, r7, #12 800a59e: 4619 mov r1, r3 800a5a0: 208c movs r0, #140 @ 0x8c 800a5a2: f000 f97d bl 800a8a0 800a5a6: e000 b.n 800a5aa return; 800a5a8: bf00 nop } 800a5aa: 3718 adds r7, #24 800a5ac: 46bd mov sp, r7 800a5ae: bd80 pop {r7, pc} 800a5b0: 2000038d .word 0x2000038d 800a5b4: 2000038e .word 0x2000038e 0800a5b8 : SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 ); OperatingMode = MODE_CAD; } void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) { 800a5b8: b580 push {r7, lr} 800a5ba: b084 sub sp, #16 800a5bc: af00 add r7, sp, #0 800a5be: 4603 mov r3, r0 800a5c0: 460a mov r2, r1 800a5c2: 71fb strb r3, [r7, #7] 800a5c4: 4613 mov r3, r2 800a5c6: 71bb strb r3, [r7, #6] uint8_t buf[2]; buf[0] = txBaseAddress; 800a5c8: 79fb ldrb r3, [r7, #7] 800a5ca: 733b strb r3, [r7, #12] buf[1] = rxBaseAddress; 800a5cc: 79bb ldrb r3, [r7, #6] 800a5ce: 737b strb r3, [r7, #13] SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); 800a5d0: f107 030c add.w r3, r7, #12 800a5d4: 2202 movs r2, #2 800a5d6: 4619 mov r1, r3 800a5d8: 208f movs r0, #143 @ 0x8f 800a5da: f000 f961 bl 800a8a0 } 800a5de: bf00 nop 800a5e0: 3710 adds r7, #16 800a5e2: 46bd mov sp, r7 800a5e4: bd80 pop {r7, pc} 0800a5e6 : status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4; return status; } int8_t SUBGRF_GetRssiInst( void ) { 800a5e6: b580 push {r7, lr} 800a5e8: b082 sub sp, #8 800a5ea: af00 add r7, sp, #0 uint8_t buf[1]; int8_t rssi = 0; 800a5ec: 2300 movs r3, #0 800a5ee: 71fb strb r3, [r7, #7] SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 ); 800a5f0: 1d3b adds r3, r7, #4 800a5f2: 2201 movs r2, #1 800a5f4: 4619 mov r1, r3 800a5f6: 2015 movs r0, #21 800a5f8: f000 f974 bl 800a8e4 rssi = -buf[0] >> 1; 800a5fc: 793b ldrb r3, [r7, #4] 800a5fe: 425b negs r3, r3 800a600: 105b asrs r3, r3, #1 800a602: 71fb strb r3, [r7, #7] return rssi; 800a604: f997 3007 ldrsb.w r3, [r7, #7] } 800a608: 4618 mov r0, r3 800a60a: 3708 adds r7, #8 800a60c: 46bd mov sp, r7 800a60e: bd80 pop {r7, pc} 0800a610 : void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) { 800a610: b580 push {r7, lr} 800a612: b084 sub sp, #16 800a614: af00 add r7, sp, #0 800a616: 6078 str r0, [r7, #4] 800a618: 6039 str r1, [r7, #0] uint8_t status[2]; SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); 800a61a: f107 030c add.w r3, r7, #12 800a61e: 2202 movs r2, #2 800a620: 4619 mov r1, r3 800a622: 2013 movs r0, #19 800a624: f000 f95e bl 800a8e4 // In case of LORA fixed header, the payloadLength is obtained by reading // the register REG_LR_PAYLOADLENGTH if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) ) 800a628: f7ff fd84 bl 800a134 800a62c: 4603 mov r3, r0 800a62e: 2b01 cmp r3, #1 800a630: d10d bne.n 800a64e 800a632: 4b0c ldr r3, [pc, #48] @ (800a664 ) 800a634: 781b ldrb r3, [r3, #0] 800a636: b2db uxtb r3, r3 800a638: 2b01 cmp r3, #1 800a63a: d108 bne.n 800a64e { *payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH ); 800a63c: f240 7002 movw r0, #1794 @ 0x702 800a640: f000 f886 bl 800a750 800a644: 4603 mov r3, r0 800a646: 461a mov r2, r3 800a648: 687b ldr r3, [r7, #4] 800a64a: 701a strb r2, [r3, #0] 800a64c: e002 b.n 800a654 } else { *payloadLength = status[0]; 800a64e: 7b3a ldrb r2, [r7, #12] 800a650: 687b ldr r3, [r7, #4] 800a652: 701a strb r2, [r3, #0] } *rxStartBufferPointer = status[1]; 800a654: 7b7a ldrb r2, [r7, #13] 800a656: 683b ldr r3, [r7, #0] 800a658: 701a strb r2, [r3, #0] } 800a65a: bf00 nop 800a65c: 3710 adds r7, #16 800a65e: 46bd mov sp, r7 800a660: bd80 pop {r7, pc} 800a662: bf00 nop 800a664: 2000038e .word 0x2000038e 0800a668 : void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ) { 800a668: b580 push {r7, lr} 800a66a: b084 sub sp, #16 800a66c: af00 add r7, sp, #0 800a66e: 6078 str r0, [r7, #4] uint8_t status[3]; SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); 800a670: f107 030c add.w r3, r7, #12 800a674: 2203 movs r2, #3 800a676: 4619 mov r1, r3 800a678: 2014 movs r0, #20 800a67a: f000 f933 bl 800a8e4 pktStatus->packetType = SUBGRF_GetPacketType( ); 800a67e: f7ff fd59 bl 800a134 800a682: 4603 mov r3, r0 800a684: 461a mov r2, r3 800a686: 687b ldr r3, [r7, #4] 800a688: 701a strb r2, [r3, #0] switch( pktStatus->packetType ) 800a68a: 687b ldr r3, [r7, #4] 800a68c: 781b ldrb r3, [r3, #0] 800a68e: 2b00 cmp r3, #0 800a690: d002 beq.n 800a698 800a692: 2b01 cmp r3, #1 800a694: d013 beq.n 800a6be 800a696: e02a b.n 800a6ee { case PACKET_TYPE_GFSK: pktStatus->Params.Gfsk.RxStatus = status[0]; 800a698: 7b3a ldrb r2, [r7, #12] 800a69a: 687b ldr r3, [r7, #4] 800a69c: 711a strb r2, [r3, #4] pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; 800a69e: 7b7b ldrb r3, [r7, #13] 800a6a0: 425b negs r3, r3 800a6a2: 105b asrs r3, r3, #1 800a6a4: b25a sxtb r2, r3 800a6a6: 687b ldr r3, [r7, #4] 800a6a8: 719a strb r2, [r3, #6] pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; 800a6aa: 7bbb ldrb r3, [r7, #14] 800a6ac: 425b negs r3, r3 800a6ae: 105b asrs r3, r3, #1 800a6b0: b25a sxtb r2, r3 800a6b2: 687b ldr r3, [r7, #4] 800a6b4: 715a strb r2, [r3, #5] pktStatus->Params.Gfsk.FreqError = 0; 800a6b6: 687b ldr r3, [r7, #4] 800a6b8: 2200 movs r2, #0 800a6ba: 609a str r2, [r3, #8] break; 800a6bc: e020 b.n 800a700 case PACKET_TYPE_LORA: pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; 800a6be: 7b3b ldrb r3, [r7, #12] 800a6c0: 425b negs r3, r3 800a6c2: 105b asrs r3, r3, #1 800a6c4: b25a sxtb r2, r3 800a6c6: 687b ldr r3, [r7, #4] 800a6c8: 731a strb r2, [r3, #12] // Returns SNR value [dB] rounded to the nearest integer value pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2; 800a6ca: 7b7b ldrb r3, [r7, #13] 800a6cc: b25b sxtb r3, r3 800a6ce: 3302 adds r3, #2 800a6d0: 109b asrs r3, r3, #2 800a6d2: b25a sxtb r2, r3 800a6d4: 687b ldr r3, [r7, #4] 800a6d6: 735a strb r2, [r3, #13] pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; 800a6d8: 7bbb ldrb r3, [r7, #14] 800a6da: 425b negs r3, r3 800a6dc: 105b asrs r3, r3, #1 800a6de: b25a sxtb r2, r3 800a6e0: 687b ldr r3, [r7, #4] 800a6e2: 739a strb r2, [r3, #14] pktStatus->Params.LoRa.FreqError = FrequencyError; 800a6e4: 4b08 ldr r3, [pc, #32] @ (800a708 ) 800a6e6: 681a ldr r2, [r3, #0] 800a6e8: 687b ldr r3, [r7, #4] 800a6ea: 611a str r2, [r3, #16] break; 800a6ec: e008 b.n 800a700 default: case PACKET_TYPE_NONE: // In that specific case, we set everything in the pktStatus to zeros // and reset the packet type accordingly RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) ); 800a6ee: 2214 movs r2, #20 800a6f0: 2100 movs r1, #0 800a6f2: 6878 ldr r0, [r7, #4] 800a6f4: f002 fdb9 bl 800d26a pktStatus->packetType = PACKET_TYPE_NONE; 800a6f8: 687b ldr r3, [r7, #4] 800a6fa: 220f movs r2, #15 800a6fc: 701a strb r2, [r3, #0] break; 800a6fe: bf00 nop } } 800a700: bf00 nop 800a702: 3710 adds r7, #16 800a704: 46bd mov sp, r7 800a706: bd80 pop {r7, pc} 800a708: 20000390 .word 0x20000390 0800a70c : buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); } void SUBGRF_WriteRegister( uint16_t addr, uint8_t data ) { 800a70c: b580 push {r7, lr} 800a70e: b086 sub sp, #24 800a710: af00 add r7, sp, #0 800a712: 4603 mov r3, r0 800a714: 460a mov r2, r1 800a716: 80fb strh r3, [r7, #6] 800a718: 4613 mov r3, r2 800a71a: 717b strb r3, [r7, #5] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a71c: f3ef 8310 mrs r3, PRIMASK 800a720: 60fb str r3, [r7, #12] return(result); 800a722: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a724: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a726: b672 cpsid i } 800a728: bf00 nop HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 ); 800a72a: 1d7a adds r2, r7, #5 800a72c: 88f9 ldrh r1, [r7, #6] 800a72e: 2301 movs r3, #1 800a730: 4806 ldr r0, [pc, #24] @ (800a74c ) 800a732: f7fa f94b bl 80049cc 800a736: 697b ldr r3, [r7, #20] 800a738: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a73a: 693b ldr r3, [r7, #16] 800a73c: f383 8810 msr PRIMASK, r3 } 800a740: bf00 nop CRITICAL_SECTION_END(); } 800a742: bf00 nop 800a744: 3718 adds r7, #24 800a746: 46bd mov sp, r7 800a748: bd80 pop {r7, pc} 800a74a: bf00 nop 800a74c: 200000e0 .word 0x200000e0 0800a750 : uint8_t SUBGRF_ReadRegister( uint16_t addr ) { 800a750: b580 push {r7, lr} 800a752: b086 sub sp, #24 800a754: af00 add r7, sp, #0 800a756: 4603 mov r3, r0 800a758: 80fb strh r3, [r7, #6] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a75a: f3ef 8310 mrs r3, PRIMASK 800a75e: 60fb str r3, [r7, #12] return(result); 800a760: 68fb ldr r3, [r7, #12] uint8_t data; CRITICAL_SECTION_BEGIN(); 800a762: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a764: b672 cpsid i } 800a766: bf00 nop HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 ); 800a768: f107 020b add.w r2, r7, #11 800a76c: 88f9 ldrh r1, [r7, #6] 800a76e: 2301 movs r3, #1 800a770: 4806 ldr r0, [pc, #24] @ (800a78c ) 800a772: f7fa f98a bl 8004a8a 800a776: 697b ldr r3, [r7, #20] 800a778: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a77a: 693b ldr r3, [r7, #16] 800a77c: f383 8810 msr PRIMASK, r3 } 800a780: bf00 nop CRITICAL_SECTION_END(); return data; 800a782: 7afb ldrb r3, [r7, #11] } 800a784: 4618 mov r0, r3 800a786: 3718 adds r7, #24 800a788: 46bd mov sp, r7 800a78a: bd80 pop {r7, pc} 800a78c: 200000e0 .word 0x200000e0 0800a790 : void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) { 800a790: b580 push {r7, lr} 800a792: b086 sub sp, #24 800a794: af00 add r7, sp, #0 800a796: 4603 mov r3, r0 800a798: 6039 str r1, [r7, #0] 800a79a: 80fb strh r3, [r7, #6] 800a79c: 4613 mov r3, r2 800a79e: 80bb strh r3, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a7a0: f3ef 8310 mrs r3, PRIMASK 800a7a4: 60fb str r3, [r7, #12] return(result); 800a7a6: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a7a8: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a7aa: b672 cpsid i } 800a7ac: bf00 nop HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size ); 800a7ae: 88bb ldrh r3, [r7, #4] 800a7b0: 88f9 ldrh r1, [r7, #6] 800a7b2: 683a ldr r2, [r7, #0] 800a7b4: 4806 ldr r0, [pc, #24] @ (800a7d0 ) 800a7b6: f7fa f909 bl 80049cc 800a7ba: 697b ldr r3, [r7, #20] 800a7bc: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a7be: 693b ldr r3, [r7, #16] 800a7c0: f383 8810 msr PRIMASK, r3 } 800a7c4: bf00 nop CRITICAL_SECTION_END(); } 800a7c6: bf00 nop 800a7c8: 3718 adds r7, #24 800a7ca: 46bd mov sp, r7 800a7cc: bd80 pop {r7, pc} 800a7ce: bf00 nop 800a7d0: 200000e0 .word 0x200000e0 0800a7d4 : void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) { 800a7d4: b580 push {r7, lr} 800a7d6: b086 sub sp, #24 800a7d8: af00 add r7, sp, #0 800a7da: 4603 mov r3, r0 800a7dc: 6039 str r1, [r7, #0] 800a7de: 80fb strh r3, [r7, #6] 800a7e0: 4613 mov r3, r2 800a7e2: 80bb strh r3, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a7e4: f3ef 8310 mrs r3, PRIMASK 800a7e8: 60fb str r3, [r7, #12] return(result); 800a7ea: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a7ec: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a7ee: b672 cpsid i } 800a7f0: bf00 nop HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size ); 800a7f2: 88bb ldrh r3, [r7, #4] 800a7f4: 88f9 ldrh r1, [r7, #6] 800a7f6: 683a ldr r2, [r7, #0] 800a7f8: 4806 ldr r0, [pc, #24] @ (800a814 ) 800a7fa: f7fa f946 bl 8004a8a 800a7fe: 697b ldr r3, [r7, #20] 800a800: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a802: 693b ldr r3, [r7, #16] 800a804: f383 8810 msr PRIMASK, r3 } 800a808: bf00 nop CRITICAL_SECTION_END(); } 800a80a: bf00 nop 800a80c: 3718 adds r7, #24 800a80e: 46bd mov sp, r7 800a810: bd80 pop {r7, pc} 800a812: bf00 nop 800a814: 200000e0 .word 0x200000e0 0800a818 : void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) { 800a818: b580 push {r7, lr} 800a81a: b086 sub sp, #24 800a81c: af00 add r7, sp, #0 800a81e: 4603 mov r3, r0 800a820: 6039 str r1, [r7, #0] 800a822: 71fb strb r3, [r7, #7] 800a824: 4613 mov r3, r2 800a826: 71bb strb r3, [r7, #6] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a828: f3ef 8310 mrs r3, PRIMASK 800a82c: 60fb str r3, [r7, #12] return(result); 800a82e: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a830: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a832: b672 cpsid i } 800a834: bf00 nop HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size ); 800a836: 79bb ldrb r3, [r7, #6] 800a838: b29b uxth r3, r3 800a83a: 79f9 ldrb r1, [r7, #7] 800a83c: 683a ldr r2, [r7, #0] 800a83e: 4806 ldr r0, [pc, #24] @ (800a858 ) 800a840: f7fa fa37 bl 8004cb2 800a844: 697b ldr r3, [r7, #20] 800a846: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a848: 693b ldr r3, [r7, #16] 800a84a: f383 8810 msr PRIMASK, r3 } 800a84e: bf00 nop CRITICAL_SECTION_END(); } 800a850: bf00 nop 800a852: 3718 adds r7, #24 800a854: 46bd mov sp, r7 800a856: bd80 pop {r7, pc} 800a858: 200000e0 .word 0x200000e0 0800a85c : void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) { 800a85c: b580 push {r7, lr} 800a85e: b086 sub sp, #24 800a860: af00 add r7, sp, #0 800a862: 4603 mov r3, r0 800a864: 6039 str r1, [r7, #0] 800a866: 71fb strb r3, [r7, #7] 800a868: 4613 mov r3, r2 800a86a: 71bb strb r3, [r7, #6] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a86c: f3ef 8310 mrs r3, PRIMASK 800a870: 60fb str r3, [r7, #12] return(result); 800a872: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a874: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a876: b672 cpsid i } 800a878: bf00 nop HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size ); 800a87a: 79bb ldrb r3, [r7, #6] 800a87c: b29b uxth r3, r3 800a87e: 79f9 ldrb r1, [r7, #7] 800a880: 683a ldr r2, [r7, #0] 800a882: 4806 ldr r0, [pc, #24] @ (800a89c ) 800a884: f7fa fa68 bl 8004d58 800a888: 697b ldr r3, [r7, #20] 800a88a: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a88c: 693b ldr r3, [r7, #16] 800a88e: f383 8810 msr PRIMASK, r3 } 800a892: bf00 nop CRITICAL_SECTION_END(); } 800a894: bf00 nop 800a896: 3718 adds r7, #24 800a898: 46bd mov sp, r7 800a89a: bd80 pop {r7, pc} 800a89c: 200000e0 .word 0x200000e0 0800a8a0 : void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, uint16_t Size ) { 800a8a0: b580 push {r7, lr} 800a8a2: b086 sub sp, #24 800a8a4: af00 add r7, sp, #0 800a8a6: 4603 mov r3, r0 800a8a8: 6039 str r1, [r7, #0] 800a8aa: 71fb strb r3, [r7, #7] 800a8ac: 4613 mov r3, r2 800a8ae: 80bb strh r3, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a8b0: f3ef 8310 mrs r3, PRIMASK 800a8b4: 60fb str r3, [r7, #12] return(result); 800a8b6: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a8b8: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a8ba: b672 cpsid i } 800a8bc: bf00 nop HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size ); 800a8be: 88bb ldrh r3, [r7, #4] 800a8c0: 79f9 ldrb r1, [r7, #7] 800a8c2: 683a ldr r2, [r7, #0] 800a8c4: 4806 ldr r0, [pc, #24] @ (800a8e0 ) 800a8c6: f7fa f941 bl 8004b4c 800a8ca: 697b ldr r3, [r7, #20] 800a8cc: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a8ce: 693b ldr r3, [r7, #16] 800a8d0: f383 8810 msr PRIMASK, r3 } 800a8d4: bf00 nop CRITICAL_SECTION_END(); } 800a8d6: bf00 nop 800a8d8: 3718 adds r7, #24 800a8da: 46bd mov sp, r7 800a8dc: bd80 pop {r7, pc} 800a8de: bf00 nop 800a8e0: 200000e0 .word 0x200000e0 0800a8e4 : void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, uint16_t Size ) { 800a8e4: b580 push {r7, lr} 800a8e6: b086 sub sp, #24 800a8e8: af00 add r7, sp, #0 800a8ea: 4603 mov r3, r0 800a8ec: 6039 str r1, [r7, #0] 800a8ee: 71fb strb r3, [r7, #7] 800a8f0: 4613 mov r3, r2 800a8f2: 80bb strh r3, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800a8f4: f3ef 8310 mrs r3, PRIMASK 800a8f8: 60fb str r3, [r7, #12] return(result); 800a8fa: 68fb ldr r3, [r7, #12] CRITICAL_SECTION_BEGIN(); 800a8fc: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800a8fe: b672 cpsid i } 800a900: bf00 nop HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size ); 800a902: 88bb ldrh r3, [r7, #4] 800a904: 79f9 ldrb r1, [r7, #7] 800a906: 683a ldr r2, [r7, #0] 800a908: 4806 ldr r0, [pc, #24] @ (800a924 ) 800a90a: f7fa f97e bl 8004c0a 800a90e: 697b ldr r3, [r7, #20] 800a910: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800a912: 693b ldr r3, [r7, #16] 800a914: f383 8810 msr PRIMASK, r3 } 800a918: bf00 nop CRITICAL_SECTION_END(); } 800a91a: bf00 nop 800a91c: 3718 adds r7, #24 800a91e: 46bd mov sp, r7 800a920: bd80 pop {r7, pc} 800a922: bf00 nop 800a924: 200000e0 .word 0x200000e0 0800a928 : void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx ) { 800a928: b580 push {r7, lr} 800a92a: b084 sub sp, #16 800a92c: af00 add r7, sp, #0 800a92e: 4603 mov r3, r0 800a930: 460a mov r2, r1 800a932: 71fb strb r3, [r7, #7] 800a934: 4613 mov r3, r2 800a936: 71bb strb r3, [r7, #6] RBI_Switch_TypeDef state = RBI_SWITCH_RX; 800a938: 2301 movs r3, #1 800a93a: 73fb strb r3, [r7, #15] if (rxtx == RFSWITCH_TX) 800a93c: 79bb ldrb r3, [r7, #6] 800a93e: 2b01 cmp r3, #1 800a940: d10d bne.n 800a95e { if (paSelect == RFO_LP) 800a942: 79fb ldrb r3, [r7, #7] 800a944: 2b01 cmp r3, #1 800a946: d104 bne.n 800a952 { state = RBI_SWITCH_RFO_LP; 800a948: 2302 movs r3, #2 800a94a: 73fb strb r3, [r7, #15] Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX); 800a94c: 2004 movs r0, #4 800a94e: f000 f8ef bl 800ab30 } if (paSelect == RFO_HP) 800a952: 79fb ldrb r3, [r7, #7] 800a954: 2b02 cmp r3, #2 800a956: d107 bne.n 800a968 { state = RBI_SWITCH_RFO_HP; 800a958: 2303 movs r3, #3 800a95a: 73fb strb r3, [r7, #15] 800a95c: e004 b.n 800a968 } } else { if (rxtx == RFSWITCH_RX) 800a95e: 79bb ldrb r3, [r7, #6] 800a960: 2b00 cmp r3, #0 800a962: d101 bne.n 800a968 { state = RBI_SWITCH_RX; 800a964: 2301 movs r3, #1 800a966: 73fb strb r3, [r7, #15] } } RBI_ConfigRFSwitch(state); 800a968: 7bfb ldrb r3, [r7, #15] 800a96a: 4618 mov r0, r3 800a96c: f002 fb87 bl 800d07e } 800a970: bf00 nop 800a972: 3710 adds r7, #16 800a974: 46bd mov sp, r7 800a976: bd80 pop {r7, pc} 0800a978 : uint8_t SUBGRF_SetRfTxPower( int8_t power ) { 800a978: b580 push {r7, lr} 800a97a: b084 sub sp, #16 800a97c: af00 add r7, sp, #0 800a97e: 4603 mov r3, r0 800a980: 71fb strb r3, [r7, #7] uint8_t paSelect= RFO_LP; 800a982: 2301 movs r3, #1 800a984: 73fb strb r3, [r7, #15] int32_t TxConfig = RBI_GetTxConfig(); 800a986: f002 fb88 bl 800d09a 800a98a: 60b8 str r0, [r7, #8] switch (TxConfig) 800a98c: 68bb ldr r3, [r7, #8] 800a98e: 2b02 cmp r3, #2 800a990: d016 beq.n 800a9c0 800a992: 68bb ldr r3, [r7, #8] 800a994: 2b02 cmp r3, #2 800a996: dc16 bgt.n 800a9c6 800a998: 68bb ldr r3, [r7, #8] 800a99a: 2b00 cmp r3, #0 800a99c: d003 beq.n 800a9a6 800a99e: 68bb ldr r3, [r7, #8] 800a9a0: 2b01 cmp r3, #1 800a9a2: d00a beq.n 800a9ba { paSelect = RFO_HP; break; } default: break; 800a9a4: e00f b.n 800a9c6 if (power > 15) 800a9a6: f997 3007 ldrsb.w r3, [r7, #7] 800a9aa: 2b0f cmp r3, #15 800a9ac: dd02 ble.n 800a9b4 paSelect = RFO_HP; 800a9ae: 2302 movs r3, #2 800a9b0: 73fb strb r3, [r7, #15] break; 800a9b2: e009 b.n 800a9c8 paSelect = RFO_LP; 800a9b4: 2301 movs r3, #1 800a9b6: 73fb strb r3, [r7, #15] break; 800a9b8: e006 b.n 800a9c8 paSelect = RFO_LP; 800a9ba: 2301 movs r3, #1 800a9bc: 73fb strb r3, [r7, #15] break; 800a9be: e003 b.n 800a9c8 paSelect = RFO_HP; 800a9c0: 2302 movs r3, #2 800a9c2: 73fb strb r3, [r7, #15] break; 800a9c4: e000 b.n 800a9c8 break; 800a9c6: bf00 nop } SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US ); 800a9c8: f997 1007 ldrsb.w r1, [r7, #7] 800a9cc: 7bfb ldrb r3, [r7, #15] 800a9ce: 2202 movs r2, #2 800a9d0: 4618 mov r0, r3 800a9d2: f7ff fbb9 bl 800a148 return paSelect; 800a9d6: 7bfb ldrb r3, [r7, #15] } 800a9d8: 4618 mov r0, r3 800a9da: 3710 adds r7, #16 800a9dc: 46bd mov sp, r7 800a9de: bd80 pop {r7, pc} 0800a9e0 : uint32_t SUBGRF_GetRadioWakeUpTime( void ) { 800a9e0: b480 push {r7} 800a9e2: af00 add r7, sp, #0 return RF_WAKEUP_TIME; 800a9e4: 2301 movs r3, #1 } 800a9e6: 4618 mov r0, r3 800a9e8: 46bd mov sp, r7 800a9ea: bc80 pop {r7} 800a9ec: 4770 bx lr ... 0800a9f0 : /* HAL_SUBGHz Callbacks definitions */ void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800a9f0: b580 push {r7, lr} 800a9f2: b082 sub sp, #8 800a9f4: af00 add r7, sp, #0 800a9f6: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_TX_DONE ); 800a9f8: 4b03 ldr r3, [pc, #12] @ (800aa08 ) 800a9fa: 681b ldr r3, [r3, #0] 800a9fc: 2001 movs r0, #1 800a9fe: 4798 blx r3 } 800aa00: bf00 nop 800aa02: 3708 adds r7, #8 800aa04: 46bd mov sp, r7 800aa06: bd80 pop {r7, pc} 800aa08: 20000398 .word 0x20000398 0800aa0c : void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aa0c: b580 push {r7, lr} 800aa0e: b082 sub sp, #8 800aa10: af00 add r7, sp, #0 800aa12: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_RX_DONE ); 800aa14: 4b03 ldr r3, [pc, #12] @ (800aa24 ) 800aa16: 681b ldr r3, [r3, #0] 800aa18: 2002 movs r0, #2 800aa1a: 4798 blx r3 } 800aa1c: bf00 nop 800aa1e: 3708 adds r7, #8 800aa20: 46bd mov sp, r7 800aa22: bd80 pop {r7, pc} 800aa24: 20000398 .word 0x20000398 0800aa28 : void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz) { 800aa28: b580 push {r7, lr} 800aa2a: b082 sub sp, #8 800aa2c: af00 add r7, sp, #0 800aa2e: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_CRC_ERROR); 800aa30: 4b03 ldr r3, [pc, #12] @ (800aa40 ) 800aa32: 681b ldr r3, [r3, #0] 800aa34: 2040 movs r0, #64 @ 0x40 800aa36: 4798 blx r3 } 800aa38: bf00 nop 800aa3a: 3708 adds r7, #8 800aa3c: 46bd mov sp, r7 800aa3e: bd80 pop {r7, pc} 800aa40: 20000398 .word 0x20000398 0800aa44 : void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus) { 800aa44: b580 push {r7, lr} 800aa46: b082 sub sp, #8 800aa48: af00 add r7, sp, #0 800aa4a: 6078 str r0, [r7, #4] 800aa4c: 460b mov r3, r1 800aa4e: 70fb strb r3, [r7, #3] switch (cadstatus) 800aa50: 78fb ldrb r3, [r7, #3] 800aa52: 2b00 cmp r3, #0 800aa54: d002 beq.n 800aa5c 800aa56: 2b01 cmp r3, #1 800aa58: d005 beq.n 800aa66 break; case HAL_SUBGHZ_CAD_DETECTED: RadioOnDioIrqCb( IRQ_CAD_DETECTED); break; default: break; 800aa5a: e00a b.n 800aa72 RadioOnDioIrqCb( IRQ_CAD_CLEAR); 800aa5c: 4b07 ldr r3, [pc, #28] @ (800aa7c ) 800aa5e: 681b ldr r3, [r3, #0] 800aa60: 2080 movs r0, #128 @ 0x80 800aa62: 4798 blx r3 break; 800aa64: e005 b.n 800aa72 RadioOnDioIrqCb( IRQ_CAD_DETECTED); 800aa66: 4b05 ldr r3, [pc, #20] @ (800aa7c ) 800aa68: 681b ldr r3, [r3, #0] 800aa6a: f44f 7080 mov.w r0, #256 @ 0x100 800aa6e: 4798 blx r3 break; 800aa70: bf00 nop } } 800aa72: bf00 nop 800aa74: 3708 adds r7, #8 800aa76: 46bd mov sp, r7 800aa78: bd80 pop {r7, pc} 800aa7a: bf00 nop 800aa7c: 20000398 .word 0x20000398 0800aa80 : void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aa80: b580 push {r7, lr} 800aa82: b082 sub sp, #8 800aa84: af00 add r7, sp, #0 800aa86: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT ); 800aa88: 4b04 ldr r3, [pc, #16] @ (800aa9c ) 800aa8a: 681b ldr r3, [r3, #0] 800aa8c: f44f 7000 mov.w r0, #512 @ 0x200 800aa90: 4798 blx r3 } 800aa92: bf00 nop 800aa94: 3708 adds r7, #8 800aa96: 46bd mov sp, r7 800aa98: bd80 pop {r7, pc} 800aa9a: bf00 nop 800aa9c: 20000398 .word 0x20000398 0800aaa0 : void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aaa0: b580 push {r7, lr} 800aaa2: b082 sub sp, #8 800aaa4: af00 add r7, sp, #0 800aaa6: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_HEADER_ERROR ); 800aaa8: 4b03 ldr r3, [pc, #12] @ (800aab8 ) 800aaaa: 681b ldr r3, [r3, #0] 800aaac: 2020 movs r0, #32 800aaae: 4798 blx r3 } 800aab0: bf00 nop 800aab2: 3708 adds r7, #8 800aab4: 46bd mov sp, r7 800aab6: bd80 pop {r7, pc} 800aab8: 20000398 .word 0x20000398 0800aabc : void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aabc: b580 push {r7, lr} 800aabe: b082 sub sp, #8 800aac0: af00 add r7, sp, #0 800aac2: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED ); 800aac4: 4b03 ldr r3, [pc, #12] @ (800aad4 ) 800aac6: 681b ldr r3, [r3, #0] 800aac8: 2004 movs r0, #4 800aaca: 4798 blx r3 } 800aacc: bf00 nop 800aace: 3708 adds r7, #8 800aad0: 46bd mov sp, r7 800aad2: bd80 pop {r7, pc} 800aad4: 20000398 .word 0x20000398 0800aad8 : void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aad8: b580 push {r7, lr} 800aada: b082 sub sp, #8 800aadc: af00 add r7, sp, #0 800aade: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_SYNCWORD_VALID ); 800aae0: 4b03 ldr r3, [pc, #12] @ (800aaf0 ) 800aae2: 681b ldr r3, [r3, #0] 800aae4: 2008 movs r0, #8 800aae6: 4798 blx r3 } 800aae8: bf00 nop 800aaea: 3708 adds r7, #8 800aaec: 46bd mov sp, r7 800aaee: bd80 pop {r7, pc} 800aaf0: 20000398 .word 0x20000398 0800aaf4 : void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800aaf4: b580 push {r7, lr} 800aaf6: b082 sub sp, #8 800aaf8: af00 add r7, sp, #0 800aafa: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_HEADER_VALID ); 800aafc: 4b03 ldr r3, [pc, #12] @ (800ab0c ) 800aafe: 681b ldr r3, [r3, #0] 800ab00: 2010 movs r0, #16 800ab02: 4798 blx r3 } 800ab04: bf00 nop 800ab06: 3708 adds r7, #8 800ab08: 46bd mov sp, r7 800ab0a: bd80 pop {r7, pc} 800ab0c: 20000398 .word 0x20000398 0800ab10 : void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) { 800ab10: b580 push {r7, lr} 800ab12: b082 sub sp, #8 800ab14: af00 add r7, sp, #0 800ab16: 6078 str r0, [r7, #4] RadioOnDioIrqCb( IRQ_LR_FHSS_HOP ); 800ab18: 4b04 ldr r3, [pc, #16] @ (800ab2c ) 800ab1a: 681b ldr r3, [r3, #0] 800ab1c: f44f 4080 mov.w r0, #16384 @ 0x4000 800ab20: 4798 blx r3 } 800ab22: bf00 nop 800ab24: 3708 adds r7, #8 800ab26: 46bd mov sp, r7 800ab28: bd80 pop {r7, pc} 800ab2a: bf00 nop 800ab2c: 20000398 .word 0x20000398 0800ab30 : static void Radio_SMPS_Set(uint8_t level) { 800ab30: b580 push {r7, lr} 800ab32: b084 sub sp, #16 800ab34: af00 add r7, sp, #0 800ab36: 4603 mov r3, r0 800ab38: 71fb strb r3, [r7, #7] if ( 1U == RBI_IsDCDC() ) 800ab3a: f002 fabc bl 800d0b6 800ab3e: 4603 mov r3, r0 800ab40: 2b01 cmp r3, #1 800ab42: d112 bne.n 800ab6a { uint8_t modReg; modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R); 800ab44: f640 1023 movw r0, #2339 @ 0x923 800ab48: f7ff fe02 bl 800a750 800ab4c: 4603 mov r3, r0 800ab4e: 73fb strb r3, [r7, #15] modReg&= (~SMPS_DRV_MASK); 800ab50: 7bfb ldrb r3, [r7, #15] 800ab52: f023 0306 bic.w r3, r3, #6 800ab56: 73fb strb r3, [r7, #15] SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level); 800ab58: 7bfa ldrb r2, [r7, #15] 800ab5a: 79fb ldrb r3, [r7, #7] 800ab5c: 4313 orrs r3, r2 800ab5e: b2db uxtb r3, r3 800ab60: 4619 mov r1, r3 800ab62: f640 1023 movw r0, #2339 @ 0x923 800ab66: f7ff fdd1 bl 800a70c } } 800ab6a: bf00 nop 800ab6c: 3710 adds r7, #16 800ab6e: 46bd mov sp, r7 800ab70: bd80 pop {r7, pc} ... 0800ab74 : uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ) { 800ab74: b480 push {r7} 800ab76: b085 sub sp, #20 800ab78: af00 add r7, sp, #0 800ab7a: 6078 str r0, [r7, #4] uint8_t i; if( bandwidth == 0 ) 800ab7c: 687b ldr r3, [r7, #4] 800ab7e: 2b00 cmp r3, #0 800ab80: d101 bne.n 800ab86 { return( 0x1F ); 800ab82: 231f movs r3, #31 800ab84: e017 b.n 800abb6 } for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) 800ab86: 2300 movs r3, #0 800ab88: 73fb strb r3, [r7, #15] 800ab8a: e00f b.n 800abac { if ( bandwidth < FskBandwidths[i].bandwidth ) 800ab8c: 7bfb ldrb r3, [r7, #15] 800ab8e: 4a0c ldr r2, [pc, #48] @ (800abc0 ) 800ab90: f852 3033 ldr.w r3, [r2, r3, lsl #3] 800ab94: 687a ldr r2, [r7, #4] 800ab96: 429a cmp r2, r3 800ab98: d205 bcs.n 800aba6 { return FskBandwidths[i].RegValue; 800ab9a: 7bfb ldrb r3, [r7, #15] 800ab9c: 4a08 ldr r2, [pc, #32] @ (800abc0 ) 800ab9e: 00db lsls r3, r3, #3 800aba0: 4413 add r3, r2 800aba2: 791b ldrb r3, [r3, #4] 800aba4: e007 b.n 800abb6 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) 800aba6: 7bfb ldrb r3, [r7, #15] 800aba8: 3301 adds r3, #1 800abaa: 73fb strb r3, [r7, #15] 800abac: 7bfb ldrb r3, [r7, #15] 800abae: 2b15 cmp r3, #21 800abb0: d9ec bls.n 800ab8c } } // ERROR: Value not found while( 1 ); 800abb2: bf00 nop 800abb4: e7fd b.n 800abb2 } 800abb6: 4618 mov r0, r3 800abb8: 3714 adds r7, #20 800abba: 46bd mov sp, r7 800abbc: bc80 pop {r7} 800abbe: 4770 bx lr 800abc0: 0800fc0c .word 0x0800fc0c 0800abc4 : void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo) { 800abc4: b580 push {r7, lr} 800abc6: b08a sub sp, #40 @ 0x28 800abc8: af00 add r7, sp, #0 800abca: 6078 str r0, [r7, #4] 800abcc: 6039 str r1, [r7, #0] uint8_t BwMant[] = {4, 8, 10, 12}; 800abce: 4b35 ldr r3, [pc, #212] @ (800aca4 ) 800abd0: 60fb str r3, [r7, #12] /* read demod bandwidth: mant bit4:3, exp bits 2:0 */ uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR )); 800abd2: f640 0007 movw r0, #2055 @ 0x807 800abd6: f7ff fdbb bl 800a750 800abda: 4603 mov r3, r0 800abdc: 77fb strb r3, [r7, #31] uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3]; 800abde: 7ffb ldrb r3, [r7, #31] 800abe0: 08db lsrs r3, r3, #3 800abe2: b2db uxtb r3, r3 800abe4: f003 0303 and.w r3, r3, #3 800abe8: 3328 adds r3, #40 @ 0x28 800abea: 443b add r3, r7 800abec: f813 3c1c ldrb.w r3, [r3, #-28] 800abf0: 77bb strb r3, [r7, #30] uint8_t bandwidth_exp = reg & 0x7; 800abf2: 7ffb ldrb r3, [r7, #31] 800abf4: f003 0307 and.w r3, r3, #7 800abf8: 777b strb r3, [r7, #29] uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 ))); 800abfa: 7fba ldrb r2, [r7, #30] 800abfc: 7f7b ldrb r3, [r7, #29] 800abfe: 3301 adds r3, #1 800ac00: fa02 f303 lsl.w r3, r2, r3 800ac04: 461a mov r2, r3 800ac06: 4b28 ldr r3, [pc, #160] @ (800aca8 ) 800ac08: fbb3 f3f2 udiv r3, r3, r2 800ac0c: 61bb str r3, [r7, #24] uint32_t cf_osr = cf_fs / bitRate; 800ac0e: 69ba ldr r2, [r7, #24] 800ac10: 687b ldr r3, [r7, #4] 800ac12: fbb2 f3f3 udiv r3, r2, r3 800ac16: 617b str r3, [r7, #20] uint8_t interp = 1; 800ac18: 2301 movs r3, #1 800ac1a: f887 3027 strb.w r3, [r7, #39] @ 0x27 /* calculate demod interpolation factor */ if (cf_osr * interp < 8) 800ac1e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800ac22: 697a ldr r2, [r7, #20] 800ac24: fb02 f303 mul.w r3, r2, r3 800ac28: 2b07 cmp r3, #7 800ac2a: d802 bhi.n 800ac32 { interp = 2; 800ac2c: 2302 movs r3, #2 800ac2e: f887 3027 strb.w r3, [r7, #39] @ 0x27 } if (cf_osr * interp < 4) 800ac32: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800ac36: 697a ldr r2, [r7, #20] 800ac38: fb02 f303 mul.w r3, r2, r3 800ac3c: 2b03 cmp r3, #3 800ac3e: d802 bhi.n 800ac46 { interp = 4; 800ac40: 2304 movs r3, #4 800ac42: f887 3027 strb.w r3, [r7, #39] @ 0x27 } /* calculate demod sampling frequency */ uint32_t fs = cf_fs* interp; 800ac46: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 800ac4a: 69bb ldr r3, [r7, #24] 800ac4c: fb02 f303 mul.w r3, r2, r3 800ac50: 613b str r3, [r7, #16] /* get the cfo registers */ int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8; 800ac52: f44f 60d6 mov.w r0, #1712 @ 0x6b0 800ac56: f7ff fd7b bl 800a750 800ac5a: 4603 mov r3, r0 800ac5c: 021b lsls r3, r3, #8 800ac5e: f403 6370 and.w r3, r3, #3840 @ 0xf00 800ac62: 623b str r3, [r7, #32] cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL ); 800ac64: f240 60b1 movw r0, #1713 @ 0x6b1 800ac68: f7ff fd72 bl 800a750 800ac6c: 4603 mov r3, r0 800ac6e: 461a mov r2, r3 800ac70: 6a3b ldr r3, [r7, #32] 800ac72: 4313 orrs r3, r2 800ac74: 623b str r3, [r7, #32] /* negate if 12 bits sign bit is 1 */ if (( cfo_bin & 0x800 ) == 0x800 ) 800ac76: 6a3b ldr r3, [r7, #32] 800ac78: f403 6300 and.w r3, r3, #2048 @ 0x800 800ac7c: 2b00 cmp r3, #0 800ac7e: d005 beq.n 800ac8c { cfo_bin |= 0xFFFFF000; 800ac80: 6a3b ldr r3, [r7, #32] 800ac82: ea6f 5303 mvn.w r3, r3, lsl #20 800ac86: ea6f 5313 mvn.w r3, r3, lsr #20 800ac8a: 623b str r3, [r7, #32] } /* calculate cfo in Hz */ /* shift by 5 first to not saturate, cfo_bin on 12bits */ *cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 ); 800ac8c: 693b ldr r3, [r7, #16] 800ac8e: 095b lsrs r3, r3, #5 800ac90: 6a3a ldr r2, [r7, #32] 800ac92: fb02 f303 mul.w r3, r2, r3 800ac96: 11da asrs r2, r3, #7 800ac98: 683b ldr r3, [r7, #0] 800ac9a: 601a str r2, [r3, #0] } 800ac9c: bf00 nop 800ac9e: 3728 adds r7, #40 @ 0x28 800aca0: 46bd mov sp, r7 800aca2: bd80 pop {r7, pc} 800aca4: 0c0a0804 .word 0x0c0a0804 800aca8: 01e84800 .word 0x01e84800 0800acac : { 800acac: b480 push {r7} 800acae: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 800acb0: 4b03 ldr r3, [pc, #12] @ (800acc0 ) 800acb2: 681b ldr r3, [r3, #0] 800acb4: 0c1b lsrs r3, r3, #16 800acb6: b29b uxth r3, r3 } 800acb8: 4618 mov r0, r3 800acba: 46bd mov sp, r7 800acbc: bc80 pop {r7} 800acbe: 4770 bx lr 800acc0: e0042000 .word 0xe0042000 0800acc4 : { 800acc4: b480 push {r7} 800acc6: b083 sub sp, #12 800acc8: af00 add r7, sp, #0 800acca: 6078 str r0, [r7, #4] 800accc: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BSRR, PinMask); 800acce: 687b ldr r3, [r7, #4] 800acd0: 683a ldr r2, [r7, #0] 800acd2: 619a str r2, [r3, #24] } 800acd4: bf00 nop 800acd6: 370c adds r7, #12 800acd8: 46bd mov sp, r7 800acda: bc80 pop {r7} 800acdc: 4770 bx lr 0800acde : { 800acde: b480 push {r7} 800ace0: b083 sub sp, #12 800ace2: af00 add r7, sp, #0 800ace4: 6078 str r0, [r7, #4] 800ace6: 6039 str r1, [r7, #0] WRITE_REG(GPIOx->BRR, PinMask); 800ace8: 687b ldr r3, [r7, #4] 800acea: 683a ldr r2, [r7, #0] 800acec: 629a str r2, [r3, #40] @ 0x28 } 800acee: bf00 nop 800acf0: 370c adds r7, #12 800acf2: 46bd mov sp, r7 800acf4: bc80 pop {r7} 800acf6: 4770 bx lr 0800acf8 : #endif /* RFW_ENABLE == 1 */ /* Exported functions --------------------------------------------------------*/ int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ) { 800acf8: b580 push {r7, lr} 800acfa: b08e sub sp, #56 @ 0x38 800acfc: af02 add r7, sp, #8 800acfe: 4603 mov r3, r0 800ad00: 60b9 str r1, [r7, #8] 800ad02: 607a str r2, [r7, #4] 800ad04: 81fb strh r3, [r7, #14] int32_t status = 0; 800ad06: 2300 movs r3, #0 800ad08: 62fb str r3, [r7, #44] @ 0x2c #if (RFW_LONGPACKET_ENABLE == 1 ) uint32_t total_size = payload_size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; 800ad0a: 89fb ldrh r3, [r7, #14] 800ad0c: 4ab0 ldr r2, [pc, #704] @ (800afd0 ) 800ad0e: 7852 ldrb r2, [r2, #1] 800ad10: 4413 add r3, r2 800ad12: 4aaf ldr r2, [pc, #700] @ (800afd0 ) 800ad14: 78d2 ldrb r2, [r2, #3] 800ad16: 4413 add r3, r2 800ad18: 627b str r3, [r7, #36] @ 0x24 RFW_MW_LOG( TS_ON, VLEVEL_M, "RevID=%04X\r\n", LL_DBGMCU_GetRevisionID() ); 800ad1a: f7ff ffc7 bl 800acac 800ad1e: 4603 mov r3, r0 800ad20: 9300 str r3, [sp, #0] 800ad22: 4bac ldr r3, [pc, #688] @ (800afd4 ) 800ad24: 2201 movs r2, #1 800ad26: 2100 movs r1, #0 800ad28: 2002 movs r0, #2 800ad2a: f003 f97d bl 800e028 if( ( TxLongPacketGetNextChunkCb == NULL ) || 800ad2e: 687b ldr r3, [r7, #4] 800ad30: 2b00 cmp r3, #0 800ad32: d012 beq.n 800ad5a ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ 800ad34: 4ba6 ldr r3, [pc, #664] @ (800afd0 ) 800ad36: 785b ldrb r3, [r3, #1] 800ad38: 00db lsls r3, r3, #3 800ad3a: 2201 movs r2, #1 800ad3c: 409a lsls r2, r3 800ad3e: 89fb ldrh r3, [r7, #14] if( ( TxLongPacketGetNextChunkCb == NULL ) || 800ad40: 429a cmp r2, r3 800ad42: dd0a ble.n 800ad5a ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ 800ad44: 4ba2 ldr r3, [pc, #648] @ (800afd0 ) 800ad46: 781b ldrb r3, [r3, #0] ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ 800ad48: 2b00 cmp r3, #0 800ad4a: d006 beq.n 800ad5a ( LL_DBGMCU_GetRevisionID() < 0x1003 ) ) /* Only available from stm32wl revision Y*/ 800ad4c: f7ff ffae bl 800acac 800ad50: 4603 mov r3, r0 ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ 800ad52: f241 0202 movw r2, #4098 @ 0x1002 800ad56: 4293 cmp r3, r2 800ad58: d803 bhi.n 800ad62 { status = -1; 800ad5a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800ad5e: 62fb str r3, [r7, #44] @ 0x2c 800ad60: e130 b.n 800afc4 } else { /*chunk buffer pointer fed by the application*/ uint8_t *app_chunk_buffer_ptr = NULL; 800ad62: 2300 movs r3, #0 800ad64: 61bb str r3, [r7, #24] uint8_t chunk_size; uint8_t crc_size; /*timeout for next chunk*/ uint32_t chunk_timeout; /*Records call back*/ RFWPacket.TxLongPacketGetNextChunkCb = TxLongPacketGetNextChunkCb; 800ad66: 4a9a ldr r2, [pc, #616] @ (800afd0 ) 800ad68: 687b ldr r3, [r7, #4] 800ad6a: 6413 str r3, [r2, #64] @ 0x40 /* Radio IRQ is set to DIO1 by default */ SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, 800ad6c: 2300 movs r3, #0 800ad6e: 2200 movs r2, #0 800ad70: f240 2101 movw r1, #513 @ 0x201 800ad74: f240 2001 movw r0, #513 @ 0x201 800ad78: f7ff f91e bl 8009fb8 IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); /* Set DBG pin */ DBG_GPIO_RADIO_TX( SET ); 800ad7c: f44f 5100 mov.w r1, #8192 @ 0x2000 800ad80: 4895 ldr r0, [pc, #596] @ (800afd8 ) 800ad82: f7ff ff9f bl 800acc4 /* Set RF switch */ SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_TX ); 800ad86: 4b92 ldr r3, [pc, #584] @ (800afd0 ) 800ad88: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800ad8c: 2101 movs r1, #1 800ad8e: 4618 mov r0, r3 800ad90: f7ff fdca bl 800a928 switch( RFWPacket.Init.Modem ) 800ad94: 4b8e ldr r3, [pc, #568] @ (800afd0 ) 800ad96: 7b9b ldrb r3, [r3, #14] 800ad98: 2b04 cmp r3, #4 800ad9a: f200 8110 bhi.w 800afbe 800ad9e: a201 add r2, pc, #4 @ (adr r2, 800ada4 ) 800ada0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ada4: 0800adb9 .word 0x0800adb9 800ada8: 0800afa7 .word 0x0800afa7 800adac: 0800adb9 .word 0x0800adb9 800adb0: 0800afaf .word 0x0800afaf 800adb4: 0800afb7 .word 0x0800afb7 { case MODEM_FSK: case MODEM_MSK: { if( RFWPacket.Init.Enable == 1 ) 800adb8: 4b85 ldr r3, [pc, #532] @ (800afd0 ) 800adba: 781b ldrb r3, [r3, #0] 800adbc: 2b01 cmp r3, #1 800adbe: f040 80ee bne.w 800af9e { /*crc will be calculated on the fly along with packet chunk transmission*/ uint8_t crc_result[2]; /*init radio buffer offset*/ RFWPacket.RadioBufferOffset = 0; 800adc2: 4b83 ldr r3, [pc, #524] @ (800afd0 ) 800adc4: 2200 movs r2, #0 800adc6: f883 2036 strb.w r2, [r3, #54] @ 0x36 /*long packet mode enable*/ RFWPacket.LongPacketModeEnable = 1; 800adca: 4b81 ldr r3, [pc, #516] @ (800afd0 ) 800adcc: 2201 movs r2, #1 800adce: 769a strb r2, [r3, #26] /*Remaining bytes to transmit*/ RFWPacket.LongPacketRemainingBytes = total_size; 800add0: 6a7b ldr r3, [r7, #36] @ 0x24 800add2: b29a uxth r2, r3 800add4: 4b7e ldr r3, [pc, #504] @ (800afd0 ) 800add6: 869a strh r2, [r3, #52] @ 0x34 /*Records total payload bytes to transmit*/ RFWPacket.PayloadLength = total_size; 800add8: 6a7b ldr r3, [r7, #36] @ 0x24 800adda: b29a uxth r2, r3 800addc: 4b7c ldr r3, [pc, #496] @ (800afd0 ) 800adde: 831a strh r2, [r3, #24] if( total_size > RADIO_BUF_SIZE ) 800ade0: 6a7b ldr r3, [r7, #36] @ 0x24 800ade2: 2bff cmp r3, #255 @ 0xff 800ade4: d919 bls.n 800ae1a { /*cut in chunk*/ if( total_size < RADIO_BUF_SIZE + RFWPacket.Init.CrcFieldSize ) 800ade6: 4b7a ldr r3, [pc, #488] @ (800afd0 ) 800ade8: 78db ldrb r3, [r3, #3] 800adea: 33ff adds r3, #255 @ 0xff 800adec: 461a mov r2, r3 800adee: 6a7b ldr r3, [r7, #36] @ 0x24 800adf0: 4293 cmp r3, r2 800adf2: d209 bcs.n 800ae08 { /*reduce chunk so that crc is treated in the next chunk*/ chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize - RFWPacket.Init.CrcFieldSize; 800adf4: 4b76 ldr r3, [pc, #472] @ (800afd0 ) 800adf6: 785b ldrb r3, [r3, #1] 800adf8: 43db mvns r3, r3 800adfa: b2da uxtb r2, r3 800adfc: 4b74 ldr r3, [pc, #464] @ (800afd0 ) 800adfe: 78db ldrb r3, [r3, #3] 800ae00: 1ad3 subs r3, r2, r3 800ae02: f887 302b strb.w r3, [r7, #43] @ 0x2b 800ae06: e004 b.n 800ae12 } else { chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize; 800ae08: 4b71 ldr r3, [pc, #452] @ (800afd0 ) 800ae0a: 785b ldrb r3, [r3, #1] 800ae0c: 43db mvns r3, r3 800ae0e: f887 302b strb.w r3, [r7, #43] @ 0x2b } /*Set crc size for the crc calculation: no crc here because it is not the end of the packet*/ crc_size = 0; 800ae12: 2300 movs r3, #0 800ae14: f887 302a strb.w r3, [r7, #42] @ 0x2a 800ae18: e006 b.n 800ae28 } else { chunk_size = payload_size; 800ae1a: 89fb ldrh r3, [r7, #14] 800ae1c: f887 302b strb.w r3, [r7, #43] @ 0x2b /*Set crc size for the crc calculation*/ crc_size = RFWPacket.Init.CrcFieldSize; 800ae20: 4b6b ldr r3, [pc, #428] @ (800afd0 ) 800ae22: 78db ldrb r3, [r3, #3] 800ae24: f887 302a strb.w r3, [r7, #42] @ 0x2a } /* Prepend payload size before Payload*/ if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) 800ae28: 4b69 ldr r3, [pc, #420] @ (800afd0 ) 800ae2a: 785b ldrb r3, [r3, #1] 800ae2c: 2b01 cmp r3, #1 800ae2e: d104 bne.n 800ae3a { ChunkBuffer[0] = payload_size; 800ae30: 89fb ldrh r3, [r7, #14] 800ae32: b2da uxtb r2, r3 800ae34: 4b69 ldr r3, [pc, #420] @ (800afdc ) 800ae36: 701a strb r2, [r3, #0] 800ae38: e009 b.n 800ae4e } else { ChunkBuffer[0] = ( uint8_t )( ( payload_size ) >> 8 ); 800ae3a: 89fb ldrh r3, [r7, #14] 800ae3c: 0a1b lsrs r3, r3, #8 800ae3e: b29b uxth r3, r3 800ae40: b2da uxtb r2, r3 800ae42: 4b66 ldr r3, [pc, #408] @ (800afdc ) 800ae44: 701a strb r2, [r3, #0] ChunkBuffer[1] = ( uint8_t )( ( payload_size ) & 0xFF ); 800ae46: 89fb ldrh r3, [r7, #14] 800ae48: b2da uxtb r2, r3 800ae4a: 4b64 ldr r3, [pc, #400] @ (800afdc ) 800ae4c: 705a strb r2, [r3, #1] } /* Get Tx chunk from app*/ TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size ); 800ae4e: f897 102b ldrb.w r1, [r7, #43] @ 0x2b 800ae52: f107 0218 add.w r2, r7, #24 800ae56: 687b ldr r3, [r7, #4] 800ae58: 4610 mov r0, r2 800ae5a: 4798 blx r3 /* Copy first chunk in ChunkBuffer Buffer*/ RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], app_chunk_buffer_ptr, chunk_size ); 800ae5c: 4b5c ldr r3, [pc, #368] @ (800afd0 ) 800ae5e: 785b ldrb r3, [r3, #1] 800ae60: 461a mov r2, r3 800ae62: 4b5e ldr r3, [pc, #376] @ (800afdc ) 800ae64: 4413 add r3, r2 800ae66: 69b9 ldr r1, [r7, #24] 800ae68: f897 202b ldrb.w r2, [r7, #43] @ 0x2b 800ae6c: b292 uxth r2, r2 800ae6e: 4618 mov r0, r3 800ae70: f002 f9dc bl 800d22c if( RFWPacket.Init.CrcEnable == 1 ) 800ae74: 4b56 ldr r3, [pc, #344] @ (800afd0 ) 800ae76: 789b ldrb r3, [r3, #2] 800ae78: 2b01 cmp r3, #1 800ae7a: d11f bne.n 800aebc { /* Set the state of the Crc to crc_seed*/ RFW_CrcSetState( &RFWPacket ); 800ae7c: 4854 ldr r0, [pc, #336] @ (800afd0 ) 800ae7e: f000 fc57 bl 800b730 /* Run the crc calculation on payload length and payload*/ RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size, crc_result ); 800ae82: 4b53 ldr r3, [pc, #332] @ (800afd0 ) 800ae84: 785b ldrb r3, [r3, #1] 800ae86: 461a mov r2, r3 800ae88: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800ae8c: 4413 add r3, r2 800ae8e: 461a mov r2, r3 800ae90: f107 0314 add.w r3, r7, #20 800ae94: 4951 ldr r1, [pc, #324] @ (800afdc ) 800ae96: 484e ldr r0, [pc, #312] @ (800afd0 ) 800ae98: f000 fc9f bl 800b7da /* Append the crc result after the payload if total_size<= RADIO_BUF_SIZE*/ RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize + chunk_size], crc_result, crc_size ); 800ae9c: 4b4c ldr r3, [pc, #304] @ (800afd0 ) 800ae9e: 785b ldrb r3, [r3, #1] 800aea0: 461a mov r2, r3 800aea2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800aea6: 4413 add r3, r2 800aea8: 4a4c ldr r2, [pc, #304] @ (800afdc ) 800aeaa: 4413 add r3, r2 800aeac: f897 202a ldrb.w r2, [r7, #42] @ 0x2a 800aeb0: b292 uxth r2, r2 800aeb2: f107 0114 add.w r1, r7, #20 800aeb6: 4618 mov r0, r3 800aeb8: f002 f9b8 bl 800d22c } /* Init whitening at beginning of the packet*/ RFW_WhiteSetState( &RFWPacket ); 800aebc: 4844 ldr r0, [pc, #272] @ (800afd0 ) 800aebe: f000 fc0f bl 800b6e0 /* Run the whitening calculation on payload length, payload and crc if crc fits inside 1st chunk*/ RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); 800aec2: 4b43 ldr r3, [pc, #268] @ (800afd0 ) 800aec4: 785b ldrb r3, [r3, #1] 800aec6: 461a mov r2, r3 800aec8: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800aecc: 441a add r2, r3 800aece: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800aed2: 4413 add r3, r2 800aed4: 461a mov r2, r3 800aed6: 4941 ldr r1, [pc, #260] @ (800afdc ) 800aed8: 483d ldr r0, [pc, #244] @ (800afd0 ) 800aeda: f000 fc36 bl 800b74a /* Configure the Transmitter to send all*/ /* Init radio buffer */ SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); 800aede: 4b3c ldr r3, [pc, #240] @ (800afd0 ) 800aee0: 785a ldrb r2, [r3, #1] 800aee2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800aee6: 4413 add r3, r2 800aee8: b2da uxtb r2, r3 800aeea: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800aeee: 4413 add r3, r2 800aef0: b2db uxtb r3, r3 800aef2: 4619 mov r1, r3 800aef4: f240 60bb movw r0, #1723 @ 0x6bb 800aef8: f7ff fc08 bl 800a70c SUBGRF_WriteRegister( SUBGHZ_TXADRPTR, 0 ); 800aefc: 2100 movs r1, #0 800aefe: f640 0002 movw r0, #2050 @ 0x802 800af02: f7ff fc03 bl 800a70c /* Send*/ SUBGRF_SendPayload( ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size, 0 ); 800af06: 4b32 ldr r3, [pc, #200] @ (800afd0 ) 800af08: 785a ldrb r2, [r3, #1] 800af0a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800af0e: 4413 add r3, r2 800af10: b2da uxtb r2, r3 800af12: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800af16: 4413 add r3, r2 800af18: b2db uxtb r3, r3 800af1a: 2200 movs r2, #0 800af1c: 4619 mov r1, r3 800af1e: 482f ldr r0, [pc, #188] @ (800afdc ) 800af20: f7fe fd60 bl 80099e4 if( total_size > RADIO_BUF_SIZE ) 800af24: 6a7b ldr r3, [r7, #36] @ 0x24 800af26: 2bff cmp r3, #255 @ 0xff 800af28: d94b bls.n 800afc2 { /*in case total size is greater than RADIO_BUF_SIZE, need to program a timer to get next chunk*/ /*RFWPacket.LongPacketRemainingBytes-= RFWPacket.Init.PayloadLengthFieldSize+ chunk_size+ crc_size;*/ /*Initialize Timer to get new chunk and update radio ptr*/ chunk_timeout = ( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000 ) / RFWPacket.BitRate; 800af2a: 4b29 ldr r3, [pc, #164] @ (800afd0 ) 800af2c: 6c9b ldr r3, [r3, #72] @ 0x48 800af2e: f44f 227a mov.w r2, #1024000 @ 0xfa000 800af32: fbb2 f3f3 udiv r3, r2, r3 800af36: 623b str r3, [r7, #32] RFW_MW_LOG( TS_ON, VLEVEL_M, "Timeout=%d,\r\n", chunk_timeout ); 800af38: 6a3b ldr r3, [r7, #32] 800af3a: 9300 str r3, [sp, #0] 800af3c: 4b28 ldr r3, [pc, #160] @ (800afe0 ) 800af3e: 2201 movs r2, #1 800af40: 2100 movs r1, #0 800af42: 2002 movs r0, #2 800af44: f003 f870 bl 800e028 TimerInit( &RFWPacket.Timer, RFW_TransmitLongPacket_NewTxChunkTimerEvent ); 800af48: 2300 movs r3, #0 800af4a: 9300 str r3, [sp, #0] 800af4c: 4b25 ldr r3, [pc, #148] @ (800afe4 ) 800af4e: 2200 movs r2, #0 800af50: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800af54: 4824 ldr r0, [pc, #144] @ (800afe8 ) 800af56: f002 fdcb bl 800daf0 TimerSetValue( &RFWPacket.Timer, chunk_timeout ); 800af5a: 6a39 ldr r1, [r7, #32] 800af5c: 4822 ldr r0, [pc, #136] @ (800afe8 ) 800af5e: f002 fedb bl 800dd18 TimerStart( &RFWPacket.Timer ); 800af62: 4821 ldr r0, [pc, #132] @ (800afe8 ) 800af64: f002 fdfa bl 800db5c /*Write bit infinite_sequence = 1, required for long packet*/ uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); 800af68: f44f 60d7 mov.w r0, #1720 @ 0x6b8 800af6c: f7ff fbf0 bl 800a750 800af70: 4603 mov r3, r0 800af72: 77fb strb r3, [r7, #31] SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg | 0x02 ); 800af74: 7ffb ldrb r3, [r7, #31] 800af76: f043 0302 orr.w r3, r3, #2 800af7a: b2db uxtb r3, r3 800af7c: 4619 mov r1, r3 800af7e: f44f 60d7 mov.w r0, #1720 @ 0x6b8 800af82: f7ff fbc3 bl 800a70c TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); 800af86: 4b12 ldr r3, [pc, #72] @ (800afd0 ) 800af88: 6cdb ldr r3, [r3, #76] @ 0x4c 800af8a: 68b9 ldr r1, [r7, #8] 800af8c: 4618 mov r0, r3 800af8e: f002 fec3 bl 800dd18 TimerStart( RFWPacket.RxTimeoutTimer ); 800af92: 4b0f ldr r3, [pc, #60] @ (800afd0 ) 800af94: 6cdb ldr r3, [r3, #76] @ 0x4c 800af96: 4618 mov r0, r3 800af98: f002 fde0 bl 800db5c else { /* error*/ status = -1; } break; 800af9c: e011 b.n 800afc2 status = -1; 800af9e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800afa2: 62fb str r3, [r7, #44] @ 0x2c break; 800afa4: e00d b.n 800afc2 } case MODEM_LORA: { /* not supported by the radio Ip*/ status = -2; 800afa6: f06f 0301 mvn.w r3, #1 800afaa: 62fb str r3, [r7, #44] @ 0x2c break; 800afac: e00a b.n 800afc4 } case MODEM_BPSK: { /* not supported by the FW*/ status = -2; 800afae: f06f 0301 mvn.w r3, #1 800afb2: 62fb str r3, [r7, #44] @ 0x2c break; 800afb4: e006 b.n 800afc4 } case MODEM_SIGFOX_TX: { /* not supported by the FW*/ status = -2; 800afb6: f06f 0301 mvn.w r3, #1 800afba: 62fb str r3, [r7, #44] @ 0x2c break; 800afbc: e002 b.n 800afc4 } default: break; 800afbe: bf00 nop 800afc0: e000 b.n 800afc4 break; 800afc2: bf00 nop } } #else status = -1; #endif /* RFW_LONGPACKET_ENABLE == 1 */ return status; 800afc4: 6afb ldr r3, [r7, #44] @ 0x2c } 800afc6: 4618 mov r0, r3 800afc8: 3730 adds r7, #48 @ 0x30 800afca: 46bd mov sp, r7 800afcc: bd80 pop {r7, pc} 800afce: bf00 nop 800afd0: 2000039c .word 0x2000039c 800afd4: 0800f164 .word 0x0800f164 800afd8: 48000400 .word 0x48000400 800afdc: 200003f0 .word 0x200003f0 800afe0: 0800f174 .word 0x0800f174 800afe4: 0800b4e1 .word 0x0800b4e1 800afe8: 200003b8 .word 0x200003b8 0800afec : int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ) { 800afec: b580 push {r7, lr} 800afee: b086 sub sp, #24 800aff0: af00 add r7, sp, #0 800aff2: 4603 mov r3, r0 800aff4: 60b9 str r1, [r7, #8] 800aff6: 607a str r2, [r7, #4] 800aff8: 73fb strb r3, [r7, #15] int32_t status = 0; 800affa: 2300 movs r3, #0 800affc: 617b str r3, [r7, #20] #if (RFW_LONGPACKET_ENABLE == 1 ) if( ( RxLongPacketStoreChunkCb == NULL ) || 800affe: 687b ldr r3, [r7, #4] 800b000: 2b00 cmp r3, #0 800b002: d003 beq.n 800b00c ( RFWPacket.Init.Enable == 0 ) ) /* Can only be used when after RadioSetRxGenericConfig*/ 800b004: 4b2a ldr r3, [pc, #168] @ (800b0b0 ) 800b006: 781b ldrb r3, [r3, #0] if( ( RxLongPacketStoreChunkCb == NULL ) || 800b008: 2b00 cmp r3, #0 800b00a: d103 bne.n 800b014 { status = -1; 800b00c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b010: 617b str r3, [r7, #20] 800b012: e047 b.n 800b0a4 } else { /*Records call back*/ RFWPacket.RxLongPacketStoreChunkCb = RxLongPacketStoreChunkCb; 800b014: 4a26 ldr r2, [pc, #152] @ (800b0b0 ) 800b016: 687b ldr r3, [r7, #4] 800b018: 63d3 str r3, [r2, #60] @ 0x3c SUBGRF_SetDioIrqParams( IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, 800b01a: 2300 movs r3, #0 800b01c: 2200 movs r2, #0 800b01e: f44f 7102 mov.w r1, #520 @ 0x208 800b022: f44f 7002 mov.w r0, #520 @ 0x208 800b026: f7fe ffc7 bl 8009fb8 IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_RX ); 800b02a: 4b21 ldr r3, [pc, #132] @ (800b0b0 ) 800b02c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800b030: 2100 movs r1, #0 800b032: 4618 mov r0, r3 800b034: f7ff fc78 bl 800a928 /*init radio buffer offset*/ RFWPacket.RadioBufferOffset = 0; 800b038: 4b1d ldr r3, [pc, #116] @ (800b0b0 ) 800b03a: 2200 movs r2, #0 800b03c: f883 2036 strb.w r2, [r3, #54] @ 0x36 /* Init whitening at beginning of the packet*/ RFW_WhiteSetState( &RFWPacket ); 800b040: 481b ldr r0, [pc, #108] @ (800b0b0 ) 800b042: f000 fb4d bl 800b6e0 /* Set the state of the Crc to crc_seed*/ RFW_CrcSetState( &RFWPacket ); 800b046: 481a ldr r0, [pc, #104] @ (800b0b0 ) 800b048: f000 fb72 bl 800b730 /* Init radio buffer */ SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 255 ); 800b04c: 21ff movs r1, #255 @ 0xff 800b04e: f240 60bb movw r0, #1723 @ 0x6bb 800b052: f7ff fb5b bl 800a70c SUBGRF_WriteRegister( SUBGHZ_RXADRPTR, 0 ); 800b056: 2100 movs r1, #0 800b058: f640 0003 movw r0, #2051 @ 0x803 800b05c: f7ff fb56 bl 800a70c /*enable long packet*/ RFWPacket.LongPacketModeEnable = 1; 800b060: 4b13 ldr r3, [pc, #76] @ (800b0b0 ) 800b062: 2201 movs r2, #1 800b064: 769a strb r2, [r3, #26] if( timeout != 0 ) 800b066: 68bb ldr r3, [r7, #8] 800b068: 2b00 cmp r3, #0 800b06a: d00a beq.n 800b082 { TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); 800b06c: 4b10 ldr r3, [pc, #64] @ (800b0b0 ) 800b06e: 6cdb ldr r3, [r3, #76] @ 0x4c 800b070: 68b9 ldr r1, [r7, #8] 800b072: 4618 mov r0, r3 800b074: f002 fe50 bl 800dd18 TimerStart( RFWPacket.RxTimeoutTimer ); 800b078: 4b0d ldr r3, [pc, #52] @ (800b0b0 ) 800b07a: 6cdb ldr r3, [r3, #76] @ 0x4c 800b07c: 4618 mov r0, r3 800b07e: f002 fd6d bl 800db5c } DBG_GPIO_RADIO_RX( SET ); 800b082: f44f 5180 mov.w r1, #4096 @ 0x1000 800b086: 480b ldr r0, [pc, #44] @ (800b0b4 ) 800b088: f7ff fe1c bl 800acc4 if( boosted_mode == 1 ) 800b08c: 7bfb ldrb r3, [r7, #15] 800b08e: 2b01 cmp r3, #1 800b090: d104 bne.n 800b09c { SUBGRF_SetRxBoosted( 0xFFFFFF ); /* Rx Continuous */ 800b092: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 800b096: f7fe fe11 bl 8009cbc 800b09a: e003 b.n 800b0a4 } else { SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */ 800b09c: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 800b0a0: f7fe fdec bl 8009c7c } } #else status = -1; #endif /* RFW_LONGPACKET_ENABLE == 1 */ return status; 800b0a4: 697b ldr r3, [r7, #20] } 800b0a6: 4618 mov r0, r3 800b0a8: 3718 adds r7, #24 800b0aa: 46bd mov sp, r7 800b0ac: bd80 pop {r7, pc} 800b0ae: bf00 nop 800b0b0: 2000039c .word 0x2000039c 800b0b4: 48000400 .word 0x48000400 0800b0b8 : int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ) { 800b0b8: b580 push {r7, lr} 800b0ba: b08a sub sp, #40 @ 0x28 800b0bc: af02 add r7, sp, #8 800b0be: 60f8 str r0, [r7, #12] 800b0c0: 60b9 str r1, [r7, #8] 800b0c2: 607a str r2, [r7, #4] #if (RFW_ENABLE == 1 ) RADIO_FSK_PacketLengthModes_t HeaderType; uint32_t RxMaxPayloadLength = 0; 800b0c4: 2300 movs r3, #0 800b0c6: 61bb str r3, [r7, #24] RADIO_FSK_CrcTypes_t CrcLength; uint16_t whiteSeed; uint16_t CrcPolynomial; uint16_t CrcSeed; if( config->rtx == CONFIG_TX ) 800b0c8: 68fb ldr r3, [r7, #12] 800b0ca: 7a1b ldrb r3, [r3, #8] 800b0cc: 2b01 cmp r3, #1 800b0ce: d11c bne.n 800b10a { HeaderType = config->TxConfig->fsk.HeaderType; 800b0d0: 68fb ldr r3, [r7, #12] 800b0d2: 681b ldr r3, [r3, #0] 800b0d4: 7d1b ldrb r3, [r3, #20] 800b0d6: 77fb strb r3, [r7, #31] CrcLength = config->TxConfig->fsk.CrcLength; 800b0d8: 68fb ldr r3, [r7, #12] 800b0da: 681b ldr r3, [r3, #0] 800b0dc: 7d5b ldrb r3, [r3, #21] 800b0de: 75fb strb r3, [r7, #23] whiteSeed = config->TxConfig->fsk.whiteSeed; 800b0e0: 68fb ldr r3, [r7, #12] 800b0e2: 681b ldr r3, [r3, #0] 800b0e4: 8a1b ldrh r3, [r3, #16] 800b0e6: 82bb strh r3, [r7, #20] CrcPolynomial = config->TxConfig->fsk.CrcPolynomial; 800b0e8: 68fb ldr r3, [r7, #12] 800b0ea: 681b ldr r3, [r3, #0] 800b0ec: 899b ldrh r3, [r3, #12] 800b0ee: 827b strh r3, [r7, #18] CrcSeed = config->TxConfig->fsk.CrcSeed; 800b0f0: 68fb ldr r3, [r7, #12] 800b0f2: 681b ldr r3, [r3, #0] 800b0f4: 89db ldrh r3, [r3, #14] 800b0f6: 823b strh r3, [r7, #16] RFWPacket.BitRate = config->TxConfig->fsk.BitRate; 800b0f8: 68fb ldr r3, [r7, #12] 800b0fa: 681b ldr r3, [r3, #0] 800b0fc: 681b ldr r3, [r3, #0] 800b0fe: 4a38 ldr r2, [pc, #224] @ (800b1e0 ) 800b100: 6493 str r3, [r2, #72] @ 0x48 RFWPacket.TxTimeoutTimer = TimeoutTimerEvent; 800b102: 4a37 ldr r2, [pc, #220] @ (800b1e0 ) 800b104: 687b ldr r3, [r7, #4] 800b106: 6513 str r3, [r2, #80] @ 0x50 800b108: e021 b.n 800b14e } else { HeaderType = config->RxConfig->fsk.LengthMode; 800b10a: 68fb ldr r3, [r7, #12] 800b10c: 685b ldr r3, [r3, #4] 800b10e: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 800b112: 77fb strb r3, [r7, #31] CrcLength = config->RxConfig->fsk.CrcLength; 800b114: 68fb ldr r3, [r7, #12] 800b116: 685b ldr r3, [r3, #4] 800b118: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 800b11c: 75fb strb r3, [r7, #23] RxMaxPayloadLength = config->RxConfig->fsk.MaxPayloadLength; 800b11e: 68fb ldr r3, [r7, #12] 800b120: 685b ldr r3, [r3, #4] 800b122: 695b ldr r3, [r3, #20] 800b124: 61bb str r3, [r7, #24] whiteSeed = config->RxConfig->fsk.whiteSeed; 800b126: 68fb ldr r3, [r7, #12] 800b128: 685b ldr r3, [r3, #4] 800b12a: 8b9b ldrh r3, [r3, #28] 800b12c: 82bb strh r3, [r7, #20] CrcPolynomial = config->RxConfig->fsk.CrcPolynomial; 800b12e: 68fb ldr r3, [r7, #12] 800b130: 685b ldr r3, [r3, #4] 800b132: 8b1b ldrh r3, [r3, #24] 800b134: 827b strh r3, [r7, #18] CrcSeed = config->RxConfig->fsk.CrcSeed; 800b136: 68fb ldr r3, [r7, #12] 800b138: 685b ldr r3, [r3, #4] 800b13a: 8b5b ldrh r3, [r3, #26] 800b13c: 823b strh r3, [r7, #16] RFWPacket.BitRate = config->RxConfig->fsk.BitRate; 800b13e: 68fb ldr r3, [r7, #12] 800b140: 685b ldr r3, [r3, #4] 800b142: 689b ldr r3, [r3, #8] 800b144: 4a26 ldr r2, [pc, #152] @ (800b1e0 ) 800b146: 6493 str r3, [r2, #72] @ 0x48 RFWPacket.RxTimeoutTimer = TimeoutTimerEvent; 800b148: 4a25 ldr r2, [pc, #148] @ (800b1e0 ) 800b14a: 687b ldr r3, [r7, #4] 800b14c: 64d3 str r3, [r2, #76] @ 0x4c } if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) 800b14e: 68bb ldr r3, [r7, #8] 800b150: 2b00 cmp r3, #0 800b152: d00a beq.n 800b16a 800b154: 68bb ldr r3, [r7, #8] 800b156: 691b ldr r3, [r3, #16] 800b158: 2b00 cmp r3, #0 800b15a: d006 beq.n 800b16a { RFWPacket.Init.RadioEvents = RadioEvents; 800b15c: 4a20 ldr r2, [pc, #128] @ (800b1e0 ) 800b15e: 68bb ldr r3, [r7, #8] 800b160: 6113 str r3, [r2, #16] } else { return -1; } if( HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) 800b162: 7ffb ldrb r3, [r7, #31] 800b164: 2b02 cmp r3, #2 800b166: d003 beq.n 800b170 800b168: e006 b.n 800b178 return -1; 800b16a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b16e: e032 b.n 800b1d6 { #if (RFW_LONGPACKET_ENABLE == 1 ) RFWPacket.Init.PayloadLengthFieldSize = 2; 800b170: 4b1b ldr r3, [pc, #108] @ (800b1e0 ) 800b172: 2202 movs r2, #2 800b174: 705a strb r2, [r3, #1] 800b176: e002 b.n 800b17e return -1; #endif /* RFW_LONGPACKET_ENABLE == 1 */ } else { RFWPacket.Init.PayloadLengthFieldSize = 1; 800b178: 4b19 ldr r3, [pc, #100] @ (800b1e0 ) 800b17a: 2201 movs r2, #1 800b17c: 705a strb r2, [r3, #1] } /*record, used to reject packet in length decoded at sync time out greater than LongPacketMaxRxLength*/ RFWPacket.Init.LongPacketMaxRxLength = RxMaxPayloadLength; 800b17e: 69bb ldr r3, [r7, #24] 800b180: b29a uxth r2, r3 800b182: 4b17 ldr r3, [pc, #92] @ (800b1e0 ) 800b184: 819a strh r2, [r3, #12] if( CrcLength == RADIO_FSK_CRC_OFF ) 800b186: 7dfb ldrb r3, [r7, #23] 800b188: 2b01 cmp r3, #1 800b18a: d106 bne.n 800b19a { RFWPacket.Init.CrcEnable = 0; 800b18c: 4b14 ldr r3, [pc, #80] @ (800b1e0 ) 800b18e: 2200 movs r2, #0 800b190: 709a strb r2, [r3, #2] RFWPacket.Init.CrcFieldSize = 0; 800b192: 4b13 ldr r3, [pc, #76] @ (800b1e0 ) 800b194: 2200 movs r2, #0 800b196: 70da strb r2, [r3, #3] 800b198: e005 b.n 800b1a6 } else { RFWPacket.Init.CrcEnable = 1; 800b19a: 4b11 ldr r3, [pc, #68] @ (800b1e0 ) 800b19c: 2201 movs r2, #1 800b19e: 709a strb r2, [r3, #2] RFWPacket.Init.CrcFieldSize = 2; 800b1a0: 4b0f ldr r3, [pc, #60] @ (800b1e0 ) 800b1a2: 2202 movs r2, #2 800b1a4: 70da strb r2, [r3, #3] } /*Macro can be used to init interrupt behaviour*/ RFW_IT_INIT(); /*Initialise whitening Seed*/ RFW_WhiteInitState( &RFWPacket.Init, whiteSeed ); 800b1a6: 8abb ldrh r3, [r7, #20] 800b1a8: 4619 mov r1, r3 800b1aa: 480d ldr r0, [pc, #52] @ (800b1e0 ) 800b1ac: f000 fa8a bl 800b6c4 /*Initialise Crc Seed*/ RFW_CrcInitState( &RFWPacket.Init, CrcPolynomial, CrcSeed, CrcLength ); 800b1b0: 7dfb ldrb r3, [r7, #23] 800b1b2: 8a3a ldrh r2, [r7, #16] 800b1b4: 8a79 ldrh r1, [r7, #18] 800b1b6: 480a ldr r0, [pc, #40] @ (800b1e0 ) 800b1b8: f000 fa9f bl 800b6fa /*Enable the RFWPacket decoding*/ RFWPacket.Init.Enable = 1; 800b1bc: 4b08 ldr r3, [pc, #32] @ (800b1e0 ) 800b1be: 2201 movs r2, #1 800b1c0: 701a strb r2, [r3, #0] /* Initialize Timer for end of fixed packet, started at sync*/ TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent ); 800b1c2: 2300 movs r3, #0 800b1c4: 9300 str r3, [sp, #0] 800b1c6: 4b07 ldr r3, [pc, #28] @ (800b1e4 ) 800b1c8: 2200 movs r2, #0 800b1ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800b1ce: 4806 ldr r0, [pc, #24] @ (800b1e8 ) 800b1d0: f002 fc8e bl 800daf0 return 0; 800b1d4: 2300 movs r3, #0 #else return -1; #endif /* RFW_ENABLE == 1 */ } 800b1d6: 4618 mov r0, r3 800b1d8: 3720 adds r7, #32 800b1da: 46bd mov sp, r7 800b1dc: bd80 pop {r7, pc} 800b1de: bf00 nop 800b1e0: 2000039c .word 0x2000039c 800b1e4: 0800b9f5 .word 0x0800b9f5 800b1e8: 200003b8 .word 0x200003b8 0800b1ec : void RFW_DeInit( void ) { 800b1ec: b480 push {r7} 800b1ee: af00 add r7, sp, #0 #if (RFW_ENABLE == 1 ) RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/ 800b1f0: 4b03 ldr r3, [pc, #12] @ (800b200 ) 800b1f2: 2200 movs r2, #0 800b1f4: 701a strb r2, [r3, #0] #endif /* RFW_ENABLE == 1 */ } 800b1f6: bf00 nop 800b1f8: 46bd mov sp, r7 800b1fa: bc80 pop {r7} 800b1fc: 4770 bx lr 800b1fe: bf00 nop 800b200: 2000039c .word 0x2000039c 0800b204 : uint8_t RFW_Is_Init( void ) { 800b204: b480 push {r7} 800b206: af00 add r7, sp, #0 #if (RFW_ENABLE == 1 ) return RFWPacket.Init.Enable; 800b208: 4b02 ldr r3, [pc, #8] @ (800b214 ) 800b20a: 781b ldrb r3, [r3, #0] #else return 0; #endif /* RFW_ENABLE == 1 */ } 800b20c: 4618 mov r0, r3 800b20e: 46bd mov sp, r7 800b210: bc80 pop {r7} 800b212: 4770 bx lr 800b214: 2000039c .word 0x2000039c 0800b218 : uint8_t RFW_Is_LongPacketModeEnabled( void ) { 800b218: b480 push {r7} 800b21a: af00 add r7, sp, #0 #if (RFW_ENABLE == 1 ) return RFWPacket.LongPacketModeEnable; 800b21c: 4b02 ldr r3, [pc, #8] @ (800b228 ) 800b21e: 7e9b ldrb r3, [r3, #26] #else return 0; #endif /* RFW_ENABLE == 1 */ } 800b220: 4618 mov r0, r3 800b222: 46bd mov sp, r7 800b224: bc80 pop {r7} 800b226: 4770 bx lr 800b228: 2000039c .word 0x2000039c 0800b22c : void RFW_SetAntSwitch( uint8_t AntSwitch ) { 800b22c: b480 push {r7} 800b22e: b083 sub sp, #12 800b230: af00 add r7, sp, #0 800b232: 4603 mov r3, r0 800b234: 71fb strb r3, [r7, #7] #if (RFW_ENABLE == 1 ) RFWPacket.AntSwitchPaSelect = AntSwitch; 800b236: 4a04 ldr r2, [pc, #16] @ (800b248 ) 800b238: 79fb ldrb r3, [r7, #7] 800b23a: f882 3044 strb.w r3, [r2, #68] @ 0x44 #endif /* RFW_ENABLE == 1 */ } 800b23e: bf00 nop 800b240: 370c adds r7, #12 800b242: 46bd mov sp, r7 800b244: bc80 pop {r7} 800b246: 4770 bx lr 800b248: 2000039c .word 0x2000039c 0800b24c : int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ) { 800b24c: b580 push {r7, lr} 800b24e: b086 sub sp, #24 800b250: af00 add r7, sp, #0 800b252: 60f8 str r0, [r7, #12] 800b254: 460b mov r3, r1 800b256: 607a str r2, [r7, #4] 800b258: 72fb strb r3, [r7, #11] int32_t status = -1; 800b25a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b25e: 617b str r3, [r7, #20] #if (RFW_ENABLE == 1 ) uint8_t crc_result[2]; if( size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize > RADIO_BUF_SIZE ) 800b260: 7afb ldrb r3, [r7, #11] 800b262: 4a3a ldr r2, [pc, #232] @ (800b34c ) 800b264: 7852 ldrb r2, [r2, #1] 800b266: 4413 add r3, r2 800b268: 4a38 ldr r2, [pc, #224] @ (800b34c ) 800b26a: 78d2 ldrb r2, [r2, #3] 800b26c: 4413 add r3, r2 800b26e: 2bff cmp r3, #255 @ 0xff 800b270: dd09 ble.n 800b286 { RFW_MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); 800b272: 4b37 ldr r3, [pc, #220] @ (800b350 ) 800b274: 2201 movs r2, #1 800b276: 2100 movs r1, #0 800b278: 2002 movs r0, #2 800b27a: f002 fed5 bl 800e028 status = -1; 800b27e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b282: 617b str r3, [r7, #20] 800b284: e05d b.n 800b342 } else { /* Copy tx buffer in payload*/ RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], inOutBuffer, size ); 800b286: 4b31 ldr r3, [pc, #196] @ (800b34c ) 800b288: 785b ldrb r3, [r3, #1] 800b28a: 461a mov r2, r3 800b28c: 4b31 ldr r3, [pc, #196] @ (800b354 ) 800b28e: 4413 add r3, r2 800b290: 7afa ldrb r2, [r7, #11] 800b292: b292 uxth r2, r2 800b294: 68f9 ldr r1, [r7, #12] 800b296: 4618 mov r0, r3 800b298: f001 ffc8 bl 800d22c /* Calculate the crc on */ /* Payload Size without the packet length field nor the CRC */ /* Prepend payload size before Payload*/ if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) 800b29c: 4b2b ldr r3, [pc, #172] @ (800b34c ) 800b29e: 785b ldrb r3, [r3, #1] 800b2a0: 2b01 cmp r3, #1 800b2a2: d103 bne.n 800b2ac { ChunkBuffer[0] = size; 800b2a4: 4a2b ldr r2, [pc, #172] @ (800b354 ) 800b2a6: 7afb ldrb r3, [r7, #11] 800b2a8: 7013 strb r3, [r2, #0] 800b2aa: e005 b.n 800b2b8 } else { ChunkBuffer[0] = 0; 800b2ac: 4b29 ldr r3, [pc, #164] @ (800b354 ) 800b2ae: 2200 movs r2, #0 800b2b0: 701a strb r2, [r3, #0] ChunkBuffer[1] = size; 800b2b2: 4a28 ldr r2, [pc, #160] @ (800b354 ) 800b2b4: 7afb ldrb r3, [r7, #11] 800b2b6: 7053 strb r3, [r2, #1] } if( RFWPacket.Init.CrcEnable == 1 ) 800b2b8: 4b24 ldr r3, [pc, #144] @ (800b34c ) 800b2ba: 789b ldrb r3, [r3, #2] 800b2bc: 2b01 cmp r3, #1 800b2be: d11a bne.n 800b2f6 { /* Set the state of the Crc to crc_seed*/ RFW_CrcSetState( &RFWPacket ); 800b2c0: 4822 ldr r0, [pc, #136] @ (800b34c ) 800b2c2: f000 fa35 bl 800b730 /*Run the crc calculation on payload length and payload*/ RFW_CrcRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize, crc_result ); 800b2c6: 7afb ldrb r3, [r7, #11] 800b2c8: 4a20 ldr r2, [pc, #128] @ (800b34c ) 800b2ca: 7852 ldrb r2, [r2, #1] 800b2cc: 4413 add r3, r2 800b2ce: 461a mov r2, r3 800b2d0: f107 0310 add.w r3, r7, #16 800b2d4: 491f ldr r1, [pc, #124] @ (800b354 ) 800b2d6: 481d ldr r0, [pc, #116] @ (800b34c ) 800b2d8: f000 fa7f bl 800b7da /*append the crc result after the payload*/ RADIO_MEMCPY8( &ChunkBuffer[size + RFWPacket.Init.PayloadLengthFieldSize], crc_result, RFWPacket.Init.CrcFieldSize ); 800b2dc: 7afb ldrb r3, [r7, #11] 800b2de: 4a1b ldr r2, [pc, #108] @ (800b34c ) 800b2e0: 7852 ldrb r2, [r2, #1] 800b2e2: 4413 add r3, r2 800b2e4: 4a1b ldr r2, [pc, #108] @ (800b354 ) 800b2e6: 4413 add r3, r2 800b2e8: 4a18 ldr r2, [pc, #96] @ (800b34c ) 800b2ea: 78d2 ldrb r2, [r2, #3] 800b2ec: f107 0110 add.w r1, r7, #16 800b2f0: 4618 mov r0, r3 800b2f2: f001 ff9b bl 800d22c } /*init whitening at beginning of the packet*/ RFW_WhiteSetState( &RFWPacket ); 800b2f6: 4815 ldr r0, [pc, #84] @ (800b34c ) 800b2f8: f000 f9f2 bl 800b6e0 /*Run the whitening calculation on payload length, payload and crc*/ RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize ); 800b2fc: 7afb ldrb r3, [r7, #11] 800b2fe: 4a13 ldr r2, [pc, #76] @ (800b34c ) 800b300: 7852 ldrb r2, [r2, #1] 800b302: 4413 add r3, r2 800b304: 4a11 ldr r2, [pc, #68] @ (800b34c ) 800b306: 78d2 ldrb r2, [r2, #3] 800b308: 4413 add r3, r2 800b30a: 461a mov r2, r3 800b30c: 4911 ldr r1, [pc, #68] @ (800b354 ) 800b30e: 480f ldr r0, [pc, #60] @ (800b34c ) 800b310: f000 fa1b bl 800b74a /*Configure the Transmitter to send all*/ *outSize = ( uint8_t ) size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; 800b314: 4b0d ldr r3, [pc, #52] @ (800b34c ) 800b316: 785a ldrb r2, [r3, #1] 800b318: 7afb ldrb r3, [r7, #11] 800b31a: 4413 add r3, r2 800b31c: b2da uxtb r2, r3 800b31e: 4b0b ldr r3, [pc, #44] @ (800b34c ) 800b320: 78db ldrb r3, [r3, #3] 800b322: 4413 add r3, r2 800b324: b2da uxtb r2, r3 800b326: 687b ldr r3, [r7, #4] 800b328: 701a strb r2, [r3, #0] /*copy result*/ RADIO_MEMCPY8( inOutBuffer, ChunkBuffer, *outSize ); 800b32a: 687b ldr r3, [r7, #4] 800b32c: 781b ldrb r3, [r3, #0] 800b32e: 461a mov r2, r3 800b330: 4908 ldr r1, [pc, #32] @ (800b354 ) 800b332: 68f8 ldr r0, [r7, #12] 800b334: f001 ff7a bl 800d22c RFWPacket.LongPacketModeEnable = 0; 800b338: 4b04 ldr r3, [pc, #16] @ (800b34c ) 800b33a: 2200 movs r2, #0 800b33c: 769a strb r2, [r3, #26] status = 0; 800b33e: 2300 movs r3, #0 800b340: 617b str r3, [r7, #20] } #endif /* RFW_ENABLE == 1 */ return status; 800b342: 697b ldr r3, [r7, #20] } 800b344: 4618 mov r0, r3 800b346: 3718 adds r7, #24 800b348: 46bd mov sp, r7 800b34a: bd80 pop {r7, pc} 800b34c: 2000039c .word 0x2000039c 800b350: 0800f184 .word 0x0800f184 800b354: 200003f0 .word 0x200003f0 0800b358 : int32_t RFW_ReceiveInit( void ) { 800b358: b580 push {r7, lr} 800b35a: af00 add r7, sp, #0 #if (RFW_ENABLE == 1 ) /* Radio IRQ is set to DIO1 by default */ SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ 800b35c: 2300 movs r3, #0 800b35e: 2200 movs r2, #0 800b360: f64f 71fd movw r1, #65533 @ 0xfffd 800b364: f64f 70fd movw r0, #65533 @ 0xfffd 800b368: f7fe fe26 bl 8009fb8 IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ IRQ_RADIO_NONE, IRQ_RADIO_NONE ); /*init whitening at beginning of the packet*/ RFW_WhiteSetState( &RFWPacket ); 800b36c: 4807 ldr r0, [pc, #28] @ (800b38c ) 800b36e: f000 f9b7 bl 800b6e0 /* Set the state of the Crc to crc_seed*/ RFW_CrcSetState( &RFWPacket ); 800b372: 4806 ldr r0, [pc, #24] @ (800b38c ) 800b374: f000 f9dc bl 800b730 RFWPacket.RxPayloadOffset = 0; 800b378: 4b04 ldr r3, [pc, #16] @ (800b38c ) 800b37a: 2200 movs r2, #0 800b37c: 871a strh r2, [r3, #56] @ 0x38 RFWPacket.LongPacketModeEnable = 0; 800b37e: 4b03 ldr r3, [pc, #12] @ (800b38c ) 800b380: 2200 movs r2, #0 800b382: 769a strb r2, [r3, #26] return 0; 800b384: 2300 movs r3, #0 #else return -1; #endif /* RFW_ENABLE == 1 */ } 800b386: 4618 mov r0, r3 800b388: bd80 pop {r7, pc} 800b38a: bf00 nop 800b38c: 2000039c .word 0x2000039c 0800b390 : void RFW_DeInit_TxLongPacket( void ) { 800b390: b580 push {r7, lr} 800b392: b082 sub sp, #8 800b394: af00 add r7, sp, #0 #if (RFW_LONGPACKET_ENABLE == 1 ) /*long packet WA*/ uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); 800b396: f44f 60d7 mov.w r0, #1720 @ 0x6b8 800b39a: f7ff f9d9 bl 800a750 800b39e: 4603 mov r3, r0 800b3a0: 71fb strb r3, [r7, #7] SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */ 800b3a2: 79fb ldrb r3, [r7, #7] 800b3a4: f023 0302 bic.w r3, r3, #2 800b3a8: b2db uxtb r3, r3 800b3aa: 4619 mov r1, r3 800b3ac: f44f 60d7 mov.w r0, #1720 @ 0x6b8 800b3b0: f7ff f9ac bl 800a70c SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */ 800b3b4: 21ff movs r1, #255 @ 0xff 800b3b6: f240 60bb movw r0, #1723 @ 0x6bb 800b3ba: f7ff f9a7 bl 800a70c #endif /* RFW_LONGPACKET_ENABLE == 1 */ } 800b3be: bf00 nop 800b3c0: 3708 adds r7, #8 800b3c2: 46bd mov sp, r7 800b3c4: bd80 pop {r7, pc} ... 0800b3c8 : void RFW_ReceivePayload( void ) { 800b3c8: b580 push {r7, lr} 800b3ca: b086 sub sp, #24 800b3cc: af02 add r7, sp, #8 #if (RFW_ENABLE == 1 ) uint16_t PayloadLength = 0; 800b3ce: 2300 movs r3, #0 800b3d0: 80fb strh r3, [r7, #6] if( RFW_GetPacketLength( &PayloadLength ) == 0 ) 800b3d2: 1dbb adds r3, r7, #6 800b3d4: 4618 mov r0, r3 800b3d6: f000 fab7 bl 800b948 800b3da: 4603 mov r3, r0 800b3dc: 2b00 cmp r3, #0 800b3de: d15e bne.n 800b49e { uint32_t timeout; uint32_t packet_length = PayloadLength + RFWPacket.Init.CrcFieldSize; 800b3e0: 88fb ldrh r3, [r7, #6] 800b3e2: 461a mov r2, r3 800b3e4: 4b33 ldr r3, [pc, #204] @ (800b4b4 ) 800b3e6: 78db ldrb r3, [r3, #3] 800b3e8: 4413 add r3, r2 800b3ea: 60bb str r3, [r7, #8] /*record payload length*/ RFWPacket.PayloadLength = PayloadLength; 800b3ec: 88fa ldrh r2, [r7, #6] 800b3ee: 4b31 ldr r3, [pc, #196] @ (800b4b4 ) 800b3f0: 831a strh r2, [r3, #24] /*record remaining payload length*/ RFWPacket.LongPacketRemainingBytes = ( uint16_t ) packet_length; 800b3f2: 68bb ldr r3, [r7, #8] 800b3f4: b29a uxth r2, r3 800b3f6: 4b2f ldr r3, [pc, #188] @ (800b4b4 ) 800b3f8: 869a strh r2, [r3, #52] @ 0x34 /*record rx buffer offset*/ RFWPacket.RadioBufferOffset = RFWPacket.Init.PayloadLengthFieldSize; 800b3fa: 4b2e ldr r3, [pc, #184] @ (800b4b4 ) 800b3fc: 785a ldrb r2, [r3, #1] 800b3fe: 4b2d ldr r3, [pc, #180] @ (800b4b4 ) 800b400: f883 2036 strb.w r2, [r3, #54] @ 0x36 /*if decoded PayloadLength is longer than LongPacketMaxRxLength, reject packet*/ if( PayloadLength > RFWPacket.Init.LongPacketMaxRxLength ) 800b404: 4b2b ldr r3, [pc, #172] @ (800b4b4 ) 800b406: 899a ldrh r2, [r3, #12] 800b408: 88fb ldrh r3, [r7, #6] 800b40a: 429a cmp r2, r3 800b40c: d207 bcs.n 800b41e { SUBGRF_SetStandby( STDBY_RC ); 800b40e: 2000 movs r0, #0 800b410: f7fe fbf8 bl 8009c04 RFWPacket.Init.RadioEvents->RxError( ); 800b414: 4b27 ldr r3, [pc, #156] @ (800b4b4 ) 800b416: 691b ldr r3, [r3, #16] 800b418: 691b ldr r3, [r3, #16] 800b41a: 4798 blx r3 800b41c: e046 b.n 800b4ac return; } if( packet_length < LONGPACKET_CHUNK_LENGTH_BYTES ) 800b41e: 68bb ldr r3, [r7, #8] 800b420: 2b7f cmp r3, #127 @ 0x7f 800b422: d817 bhi.n 800b454 { /* all in one chunks*/ /* calculate time to end of packet*/ timeout = DIVC( ( packet_length ) * 8 * 1000, RFWPacket.BitRate ) + 2; 800b424: 68bb ldr r3, [r7, #8] 800b426: f44f 52fa mov.w r2, #8000 @ 0x1f40 800b42a: fb03 f202 mul.w r2, r3, r2 800b42e: 4b21 ldr r3, [pc, #132] @ (800b4b4 ) 800b430: 6c9b ldr r3, [r3, #72] @ 0x48 800b432: 4413 add r3, r2 800b434: 1e5a subs r2, r3, #1 800b436: 4b1f ldr r3, [pc, #124] @ (800b4b4 ) 800b438: 6c9b ldr r3, [r3, #72] @ 0x48 800b43a: fbb2 f3f3 udiv r3, r2, r3 800b43e: 3302 adds r3, #2 800b440: 60fb str r3, [r7, #12] /**/ /* start timer at the end of the packet*/ RFW_MW_LOG( TS_ON, VLEVEL_M, "end packet in %dms\r\n", timeout ); 800b442: 68fb ldr r3, [r7, #12] 800b444: 9300 str r3, [sp, #0] 800b446: 4b1c ldr r3, [pc, #112] @ (800b4b8 ) 800b448: 2201 movs r2, #1 800b44a: 2100 movs r1, #0 800b44c: 2002 movs r0, #2 800b44e: f002 fdeb bl 800e028 800b452: e01c b.n 800b48e } else if( packet_length < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES / 2 ) ) 800b454: 68bb ldr r3, [r7, #8] 800b456: 2bbf cmp r3, #191 @ 0xbf 800b458: d80f bhi.n 800b47a { /* packet contained in 2 chunks*/ /* make sure that crc not cut in chunk*/ timeout = DIVR( ( packet_length * 8 * 1000 ) / 2, RFWPacket.BitRate ); 800b45a: 68bb ldr r3, [r7, #8] 800b45c: f44f 52fa mov.w r2, #8000 @ 0x1f40 800b460: fb02 f303 mul.w r3, r2, r3 800b464: 085a lsrs r2, r3, #1 800b466: 4b13 ldr r3, [pc, #76] @ (800b4b4 ) 800b468: 6c9b ldr r3, [r3, #72] @ 0x48 800b46a: 085b lsrs r3, r3, #1 800b46c: 441a add r2, r3 800b46e: 4b11 ldr r3, [pc, #68] @ (800b4b4 ) 800b470: 6c9b ldr r3, [r3, #72] @ 0x48 800b472: fbb2 f3f3 udiv r3, r2, r3 800b476: 60fb str r3, [r7, #12] 800b478: e009 b.n 800b48e } else { /* packet contained in multiple chunk*/ /* program radio timer for first chunk*/ timeout = DIVR( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000, RFWPacket.BitRate ); 800b47a: 4b0e ldr r3, [pc, #56] @ (800b4b4 ) 800b47c: 6c9b ldr r3, [r3, #72] @ 0x48 800b47e: 085b lsrs r3, r3, #1 800b480: f503 227a add.w r2, r3, #1024000 @ 0xfa000 800b484: 4b0b ldr r3, [pc, #44] @ (800b4b4 ) 800b486: 6c9b ldr r3, [r3, #72] @ 0x48 800b488: fbb2 f3f3 udiv r3, r2, r3 800b48c: 60fb str r3, [r7, #12] } TimerSetValue( &RFWPacket.Timer, timeout ); 800b48e: 68f9 ldr r1, [r7, #12] 800b490: 480a ldr r0, [pc, #40] @ (800b4bc ) 800b492: f002 fc41 bl 800dd18 TimerStart( &RFWPacket.Timer ); 800b496: 4809 ldr r0, [pc, #36] @ (800b4bc ) 800b498: f002 fb60 bl 800db5c 800b49c: e006 b.n 800b4ac } else { /*timeout*/ SUBGRF_SetStandby( STDBY_RC ); 800b49e: 2000 movs r0, #0 800b4a0: f7fe fbb0 bl 8009c04 RFWPacket.Init.RadioEvents->RxTimeout( ); 800b4a4: 4b03 ldr r3, [pc, #12] @ (800b4b4 ) 800b4a6: 691b ldr r3, [r3, #16] 800b4a8: 68db ldr r3, [r3, #12] 800b4aa: 4798 blx r3 } #endif /* RFW_ENABLE == 1 */ } 800b4ac: 3710 adds r7, #16 800b4ae: 46bd mov sp, r7 800b4b0: bd80 pop {r7, pc} 800b4b2: bf00 nop 800b4b4: 2000039c .word 0x2000039c 800b4b8: 0800f19c .word 0x0800f19c 800b4bc: 200003b8 .word 0x200003b8 0800b4c0 : void RFW_SetRadioModem( RadioModems_t Modem ) { 800b4c0: b480 push {r7} 800b4c2: b083 sub sp, #12 800b4c4: af00 add r7, sp, #0 800b4c6: 4603 mov r3, r0 800b4c8: 71fb strb r3, [r7, #7] #if (RFW_ENABLE == 1 ) RFWPacket.Init.Modem = Modem; 800b4ca: 4a04 ldr r2, [pc, #16] @ (800b4dc ) 800b4cc: 79fb ldrb r3, [r7, #7] 800b4ce: 7393 strb r3, [r2, #14] #endif /* RFW_ENABLE == 1 */ } 800b4d0: bf00 nop 800b4d2: 370c adds r7, #12 800b4d4: 46bd mov sp, r7 800b4d6: bc80 pop {r7} 800b4d8: 4770 bx lr 800b4da: bf00 nop 800b4dc: 2000039c .word 0x2000039c 0800b4e0 : /* Private Functions Definition -----------------------------------------------*/ #if (RFW_LONGPACKET_ENABLE == 1 ) static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param ) { 800b4e0: b580 push {r7, lr} 800b4e2: b082 sub sp, #8 800b4e4: af00 add r7, sp, #0 800b4e6: 6078 str r0, [r7, #4] RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS(); 800b4e8: f000 f804 bl 800b4f4 } 800b4ec: bf00 nop 800b4ee: 3708 adds r7, #8 800b4f0: 46bd mov sp, r7 800b4f2: bd80 pop {r7, pc} 0800b4f4 : static void RFW_TransmitLongPacket_TxChunkProcess( void ) { 800b4f4: b590 push {r4, r7, lr} 800b4f6: b08d sub sp, #52 @ 0x34 800b4f8: af06 add r7, sp, #24 uint8_t *app_chunk_buffer_ptr = NULL; 800b4fa: 2300 movs r3, #0 800b4fc: 60bb str r3, [r7, #8] uint8_t chunk_size = 0; 800b4fe: 2300 movs r3, #0 800b500: 75fb strb r3, [r7, #23] uint8_t crc_result[2] = {0}; 800b502: 2300 movs r3, #0 800b504: 80bb strh r3, [r7, #4] uint8_t crc_size; uint32_t timeout;/*timeout for next chunk*/ /*records how much has been sent*/ uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_TXADRPTR ); /*radio has transmitted up to read_ptr*/ 800b506: f640 0002 movw r0, #2050 @ 0x802 800b50a: f7ff f921 bl 800a750 800b50e: 4603 mov r3, r0 800b510: 757b strb r3, [r7, #21] uint8_t write_ptr = SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ); /*from read_ptr to write_ptr still to be transmitted*/ 800b512: f240 60bb movw r0, #1723 @ 0x6bb 800b516: f7ff f91b bl 800a750 800b51a: 4603 mov r3, r0 800b51c: 753b strb r3, [r7, #20] /*calculates how much bytes were sent since previous radio loading*/ uint8_t bytes_sent = read_ptr - RFWPacket.RadioBufferOffset; 800b51e: 4b64 ldr r3, [pc, #400] @ (800b6b0 ) 800b520: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800b524: 7d7a ldrb r2, [r7, #21] 800b526: 1ad3 subs r3, r2, r3 800b528: 74fb strb r3, [r7, #19] /*bytes already loaded in the radio to send*/ uint8_t bytes_loaded = write_ptr - read_ptr; 800b52a: 7d3a ldrb r2, [r7, #20] 800b52c: 7d7b ldrb r3, [r7, #21] 800b52e: 1ad3 subs r3, r2, r3 800b530: 74bb strb r3, [r7, #18] /* Update offset tx, intentional wrap around*/ RFWPacket.RadioBufferOffset += bytes_sent; 800b532: 4b5f ldr r3, [pc, #380] @ (800b6b0 ) 800b534: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 800b538: 7cfb ldrb r3, [r7, #19] 800b53a: 4413 add r3, r2 800b53c: b2da uxtb r2, r3 800b53e: 4b5c ldr r3, [pc, #368] @ (800b6b0 ) 800b540: f883 2036 strb.w r2, [r3, #54] @ 0x36 /*record payload remaining bytes to send*/ RFWPacket.LongPacketRemainingBytes -= bytes_sent; 800b544: 4b5a ldr r3, [pc, #360] @ (800b6b0 ) 800b546: 8e9a ldrh r2, [r3, #52] @ 0x34 800b548: 7cfb ldrb r3, [r7, #19] 800b54a: b29b uxth r3, r3 800b54c: 1ad3 subs r3, r2, r3 800b54e: b29a uxth r2, r3 800b550: 4b57 ldr r3, [pc, #348] @ (800b6b0 ) 800b552: 869a strh r2, [r3, #52] @ 0x34 RFW_MW_LOG( TS_ON, VLEVEL_M, "read_ptr=%d, write_ptr=%d, bytes_sent=%d, bytes_loaded=%d,remaining to send=%d\r\n", 800b554: 7d7b ldrb r3, [r7, #21] 800b556: 7d3a ldrb r2, [r7, #20] 800b558: 7cf9 ldrb r1, [r7, #19] 800b55a: 7cb8 ldrb r0, [r7, #18] 800b55c: 4c54 ldr r4, [pc, #336] @ (800b6b0 ) 800b55e: 8ea4 ldrh r4, [r4, #52] @ 0x34 800b560: 9404 str r4, [sp, #16] 800b562: 9003 str r0, [sp, #12] 800b564: 9102 str r1, [sp, #8] 800b566: 9201 str r2, [sp, #4] 800b568: 9300 str r3, [sp, #0] 800b56a: 4b52 ldr r3, [pc, #328] @ (800b6b4 ) 800b56c: 2201 movs r2, #1 800b56e: 2100 movs r1, #0 800b570: 2002 movs r0, #2 800b572: f002 fd59 bl 800e028 read_ptr, write_ptr, bytes_sent, bytes_loaded, RFWPacket.LongPacketRemainingBytes ); if( RFWPacket.LongPacketRemainingBytes > 256 ) 800b576: 4b4e ldr r3, [pc, #312] @ (800b6b0 ) 800b578: 8e9b ldrh r3, [r3, #52] @ 0x34 800b57a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800b57e: d929 bls.n 800b5d4 { /*get next chunk */ /*make sure that at least full CrcFieldSize will be loaded for the last chunk*/ if( RFWPacket.LongPacketRemainingBytes > 256 + RFWPacket.Init.CrcFieldSize ) 800b580: 4b4b ldr r3, [pc, #300] @ (800b6b0 ) 800b582: 8e9b ldrh r3, [r3, #52] @ 0x34 800b584: 461a mov r2, r3 800b586: 4b4a ldr r3, [pc, #296] @ (800b6b0 ) 800b588: 78db ldrb r3, [r3, #3] 800b58a: f503 7380 add.w r3, r3, #256 @ 0x100 800b58e: 429a cmp r2, r3 800b590: dd02 ble.n 800b598 { chunk_size = bytes_sent; 800b592: 7cfb ldrb r3, [r7, #19] 800b594: 75fb strb r3, [r7, #23] 800b596: e004 b.n 800b5a2 } else { chunk_size = bytes_sent - RFWPacket.Init.CrcFieldSize; 800b598: 4b45 ldr r3, [pc, #276] @ (800b6b0 ) 800b59a: 78db ldrb r3, [r3, #3] 800b59c: 7cfa ldrb r2, [r7, #19] 800b59e: 1ad3 subs r3, r2, r3 800b5a0: 75fb strb r3, [r7, #23] } /*no crc since it is not the last chunk*/ crc_size = 0; 800b5a2: 2300 movs r3, #0 800b5a4: 75bb strb r3, [r7, #22] /*calculate timeout for next chunk*/ timeout = DIVR( chunk_size * 8 * 1000, RFWPacket.BitRate ); 800b5a6: 7dfb ldrb r3, [r7, #23] 800b5a8: f44f 52fa mov.w r2, #8000 @ 0x1f40 800b5ac: fb02 f303 mul.w r3, r2, r3 800b5b0: 461a mov r2, r3 800b5b2: 4b3f ldr r3, [pc, #252] @ (800b6b0 ) 800b5b4: 6c9b ldr r3, [r3, #72] @ 0x48 800b5b6: 085b lsrs r3, r3, #1 800b5b8: 441a add r2, r3 800b5ba: 4b3d ldr r3, [pc, #244] @ (800b6b0 ) 800b5bc: 6c9b ldr r3, [r3, #72] @ 0x48 800b5be: fbb2 f3f3 udiv r3, r2, r3 800b5c2: 60fb str r3, [r7, #12] TimerSetValue( &RFWPacket.Timer, timeout ); 800b5c4: 68f9 ldr r1, [r7, #12] 800b5c6: 483c ldr r0, [pc, #240] @ (800b6b8 ) 800b5c8: f002 fba6 bl 800dd18 TimerStart( &RFWPacket.Timer ); 800b5cc: 483a ldr r0, [pc, #232] @ (800b6b8 ) 800b5ce: f002 fac5 bl 800db5c 800b5d2: e015 b.n 800b600 } else { /*last chunk to send*/ if( RFWPacket.LongPacketRemainingBytes > bytes_loaded ) 800b5d4: 4b36 ldr r3, [pc, #216] @ (800b6b0 ) 800b5d6: 8e9a ldrh r2, [r3, #52] @ 0x34 800b5d8: 7cbb ldrb r3, [r7, #18] 800b5da: b29b uxth r3, r3 800b5dc: 429a cmp r2, r3 800b5de: d906 bls.n 800b5ee { chunk_size = RFWPacket.LongPacketRemainingBytes - bytes_loaded; 800b5e0: 4b33 ldr r3, [pc, #204] @ (800b6b0 ) 800b5e2: 8e9b ldrh r3, [r3, #52] @ 0x34 800b5e4: b2da uxtb r2, r3 800b5e6: 7cbb ldrb r3, [r7, #18] 800b5e8: 1ad3 subs r3, r2, r3 800b5ea: 75fb strb r3, [r7, #23] 800b5ec: e002 b.n 800b5f4 } else/* nothing to load anymore*/ { chunk_size = RFWPacket.Init.CrcFieldSize; 800b5ee: 4b30 ldr r3, [pc, #192] @ (800b6b0 ) 800b5f0: 78db ldrb r3, [r3, #3] 800b5f2: 75fb strb r3, [r7, #23] } /* crc, since it is the last chunk*/ crc_size = RFWPacket.Init.CrcFieldSize; 800b5f4: 4b2e ldr r3, [pc, #184] @ (800b6b0 ) 800b5f6: 78db ldrb r3, [r3, #3] 800b5f8: 75bb strb r3, [r7, #22] /*no more bytes to send*/ RFWPacket.LongPacketRemainingBytes = 0; 800b5fa: 4b2d ldr r3, [pc, #180] @ (800b6b0 ) 800b5fc: 2200 movs r2, #0 800b5fe: 869a strh r2, [r3, #52] @ 0x34 /*no need to program another timer, Tx done will complete the Tx process*/ } /*get new chunk from the app*/ RFWPacket.TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size - crc_size ); 800b600: 4b2b ldr r3, [pc, #172] @ (800b6b0 ) 800b602: 6c1b ldr r3, [r3, #64] @ 0x40 800b604: 7df9 ldrb r1, [r7, #23] 800b606: 7dba ldrb r2, [r7, #22] 800b608: 1a8a subs r2, r1, r2 800b60a: b2d1 uxtb r1, r2 800b60c: f107 0208 add.w r2, r7, #8 800b610: 4610 mov r0, r2 800b612: 4798 blx r3 /* Copy app_chunk_buffer_ptr in ChunkBuffer Buffer*/ RADIO_MEMCPY8( ChunkBuffer, app_chunk_buffer_ptr, chunk_size - crc_size ); 800b614: 68b9 ldr r1, [r7, #8] 800b616: 7dfb ldrb r3, [r7, #23] 800b618: b29a uxth r2, r3 800b61a: 7dbb ldrb r3, [r7, #22] 800b61c: b29b uxth r3, r3 800b61e: 1ad3 subs r3, r2, r3 800b620: b29b uxth r3, r3 800b622: 461a mov r2, r3 800b624: 4825 ldr r0, [pc, #148] @ (800b6bc ) 800b626: f001 fe01 bl 800d22c if( RFWPacket.Init.CrcEnable == 1 ) 800b62a: 4b21 ldr r3, [pc, #132] @ (800b6b0 ) 800b62c: 789b ldrb r3, [r3, #2] 800b62e: 2b01 cmp r3, #1 800b630: d113 bne.n 800b65a { /* Run the crc calculation on payload length and payload*/ RFW_CrcRun( &RFWPacket, ChunkBuffer, chunk_size - crc_size, crc_result ); 800b632: 7dfa ldrb r2, [r7, #23] 800b634: 7dbb ldrb r3, [r7, #22] 800b636: 1ad3 subs r3, r2, r3 800b638: 461a mov r2, r3 800b63a: 1d3b adds r3, r7, #4 800b63c: 491f ldr r1, [pc, #124] @ (800b6bc ) 800b63e: 481c ldr r0, [pc, #112] @ (800b6b0 ) 800b640: f000 f8cb bl 800b7da /* Append the crc result after the payload (if last chunk)*/ RADIO_MEMCPY8( &ChunkBuffer[chunk_size - crc_size], crc_result, crc_size ); 800b644: 7dfa ldrb r2, [r7, #23] 800b646: 7dbb ldrb r3, [r7, #22] 800b648: 1ad3 subs r3, r2, r3 800b64a: 4a1c ldr r2, [pc, #112] @ (800b6bc ) 800b64c: 4413 add r3, r2 800b64e: 7dba ldrb r2, [r7, #22] 800b650: b292 uxth r2, r2 800b652: 1d39 adds r1, r7, #4 800b654: 4618 mov r0, r3 800b656: f001 fde9 bl 800d22c } /* Run the whitening calculation on payload length, payload and crc*/ RFW_WhiteRun( &RFWPacket, ChunkBuffer, chunk_size ); 800b65a: 7dfb ldrb r3, [r7, #23] 800b65c: 461a mov r2, r3 800b65e: 4917 ldr r1, [pc, #92] @ (800b6bc ) 800b660: 4813 ldr r0, [pc, #76] @ (800b6b0 ) 800b662: f000 f872 bl 800b74a /*write next chunk*/ SUBGRF_WriteBuffer( write_ptr, ChunkBuffer, chunk_size ); 800b666: 7dfa ldrb r2, [r7, #23] 800b668: 7d3b ldrb r3, [r7, #20] 800b66a: 4914 ldr r1, [pc, #80] @ (800b6bc ) 800b66c: 4618 mov r0, r3 800b66e: f7ff f8d3 bl 800a818 /*update end ptr*/ SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, ( uint8_t )( chunk_size + write_ptr ) ); 800b672: 7dfa ldrb r2, [r7, #23] 800b674: 7d3b ldrb r3, [r7, #20] 800b676: 4413 add r3, r2 800b678: b2db uxtb r3, r3 800b67a: 4619 mov r1, r3 800b67c: f240 60bb movw r0, #1723 @ 0x6bb 800b680: f7ff f844 bl 800a70c RFW_MW_LOG( TS_ON, VLEVEL_M, "next chunk size=%d, new write ptr=%d\n\r", chunk_size + crc_size, 800b684: 7dfa ldrb r2, [r7, #23] 800b686: 7dbb ldrb r3, [r7, #22] 800b688: 4413 add r3, r2 800b68a: 7df9 ldrb r1, [r7, #23] 800b68c: 7dba ldrb r2, [r7, #22] 800b68e: 440a add r2, r1 800b690: b2d1 uxtb r1, r2 800b692: 7d3a ldrb r2, [r7, #20] 800b694: 440a add r2, r1 800b696: b2d2 uxtb r2, r2 800b698: 9201 str r2, [sp, #4] 800b69a: 9300 str r3, [sp, #0] 800b69c: 4b08 ldr r3, [pc, #32] @ (800b6c0 ) 800b69e: 2201 movs r2, #1 800b6a0: 2100 movs r1, #0 800b6a2: 2002 movs r0, #2 800b6a4: f002 fcc0 bl 800e028 ( uint8_t )( chunk_size + crc_size + write_ptr ) ); } 800b6a8: bf00 nop 800b6aa: 371c adds r7, #28 800b6ac: 46bd mov sp, r7 800b6ae: bd90 pop {r4, r7, pc} 800b6b0: 2000039c .word 0x2000039c 800b6b4: 0800f1b4 .word 0x0800f1b4 800b6b8: 200003b8 .word 0x200003b8 800b6bc: 200003f0 .word 0x200003f0 800b6c0: 0800f208 .word 0x0800f208 0800b6c4 : #endif /* RFW_LONGPACKET_ENABLE == 1 */ #if (RFW_ENABLE == 1 ) static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed ) { 800b6c4: b480 push {r7} 800b6c6: b083 sub sp, #12 800b6c8: af00 add r7, sp, #0 800b6ca: 6078 str r0, [r7, #4] 800b6cc: 460b mov r3, r1 800b6ce: 807b strh r3, [r7, #2] Init->WhiteSeed = WhiteSeed; 800b6d0: 687b ldr r3, [r7, #4] 800b6d2: 887a ldrh r2, [r7, #2] 800b6d4: 815a strh r2, [r3, #10] } 800b6d6: bf00 nop 800b6d8: 370c adds r7, #12 800b6da: 46bd mov sp, r7 800b6dc: bc80 pop {r7} 800b6de: 4770 bx lr 0800b6e0 : static void RFW_WhiteSetState( RadioFw_t *RFWPacket ) { 800b6e0: b480 push {r7} 800b6e2: b083 sub sp, #12 800b6e4: af00 add r7, sp, #0 800b6e6: 6078 str r0, [r7, #4] RFWPacket->WhiteLfsrState = RFWPacket->Init.WhiteSeed; 800b6e8: 687b ldr r3, [r7, #4] 800b6ea: 895a ldrh r2, [r3, #10] 800b6ec: 687b ldr r3, [r7, #4] 800b6ee: 82da strh r2, [r3, #22] } 800b6f0: bf00 nop 800b6f2: 370c adds r7, #12 800b6f4: 46bd mov sp, r7 800b6f6: bc80 pop {r7} 800b6f8: 4770 bx lr 0800b6fa : static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed, const RADIO_FSK_CrcTypes_t CrcType ) { 800b6fa: b480 push {r7} 800b6fc: b085 sub sp, #20 800b6fe: af00 add r7, sp, #0 800b700: 60f8 str r0, [r7, #12] 800b702: 4608 mov r0, r1 800b704: 4611 mov r1, r2 800b706: 461a mov r2, r3 800b708: 4603 mov r3, r0 800b70a: 817b strh r3, [r7, #10] 800b70c: 460b mov r3, r1 800b70e: 813b strh r3, [r7, #8] 800b710: 4613 mov r3, r2 800b712: 71fb strb r3, [r7, #7] Init->CrcPolynomial = CrcPolynomial; 800b714: 68fb ldr r3, [r7, #12] 800b716: 897a ldrh r2, [r7, #10] 800b718: 809a strh r2, [r3, #4] Init->CrcSeed = CrcSeed; 800b71a: 68fb ldr r3, [r7, #12] 800b71c: 893a ldrh r2, [r7, #8] 800b71e: 80da strh r2, [r3, #6] Init->CrcType = CrcType; 800b720: 68fb ldr r3, [r7, #12] 800b722: 79fa ldrb r2, [r7, #7] 800b724: 721a strb r2, [r3, #8] } 800b726: bf00 nop 800b728: 3714 adds r7, #20 800b72a: 46bd mov sp, r7 800b72c: bc80 pop {r7} 800b72e: 4770 bx lr 0800b730 : static void RFW_CrcSetState( RadioFw_t *RFWPacket ) { 800b730: b480 push {r7} 800b732: b083 sub sp, #12 800b734: af00 add r7, sp, #0 800b736: 6078 str r0, [r7, #4] RFWPacket->CrcLfsrState = RFWPacket->Init.CrcSeed; 800b738: 687b ldr r3, [r7, #4] 800b73a: 88da ldrh r2, [r3, #6] 800b73c: 687b ldr r3, [r7, #4] 800b73e: 829a strh r2, [r3, #20] } 800b740: bf00 nop 800b742: 370c adds r7, #12 800b744: 46bd mov sp, r7 800b746: bc80 pop {r7} 800b748: 4770 bx lr 0800b74a : static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size ) { 800b74a: b480 push {r7} 800b74c: b089 sub sp, #36 @ 0x24 800b74e: af00 add r7, sp, #0 800b750: 60f8 str r0, [r7, #12] 800b752: 60b9 str r1, [r7, #8] 800b754: 607a str r2, [r7, #4] /*run the whitening algo on Size bytes*/ uint16_t ibmwhite_state = RFWPacket->WhiteLfsrState; 800b756: 68fb ldr r3, [r7, #12] 800b758: 8adb ldrh r3, [r3, #22] 800b75a: 83fb strh r3, [r7, #30] for( int32_t i = 0; i < Size; i++ ) 800b75c: 2300 movs r3, #0 800b75e: 61bb str r3, [r7, #24] 800b760: e02f b.n 800b7c2 { Payload[i] ^= ibmwhite_state & 0xFF; 800b762: 69bb ldr r3, [r7, #24] 800b764: 68ba ldr r2, [r7, #8] 800b766: 4413 add r3, r2 800b768: 781b ldrb r3, [r3, #0] 800b76a: b25a sxtb r2, r3 800b76c: 8bfb ldrh r3, [r7, #30] 800b76e: b25b sxtb r3, r3 800b770: 4053 eors r3, r2 800b772: b259 sxtb r1, r3 800b774: 69bb ldr r3, [r7, #24] 800b776: 68ba ldr r2, [r7, #8] 800b778: 4413 add r3, r2 800b77a: b2ca uxtb r2, r1 800b77c: 701a strb r2, [r3, #0] for( int32_t j = 0; j < 8; j++ ) 800b77e: 2300 movs r3, #0 800b780: 617b str r3, [r7, #20] 800b782: e018 b.n 800b7b6 { uint8_t msb = ( ( ibmwhite_state >> 5 ) & 0x1 ) ^ ( ( ibmwhite_state >> 0 ) & 0x1 ); 800b784: 8bfb ldrh r3, [r7, #30] 800b786: 095b lsrs r3, r3, #5 800b788: b29b uxth r3, r3 800b78a: b2da uxtb r2, r3 800b78c: 8bfb ldrh r3, [r7, #30] 800b78e: b2db uxtb r3, r3 800b790: 4053 eors r3, r2 800b792: b2db uxtb r3, r3 800b794: f003 0301 and.w r3, r3, #1 800b798: 74fb strb r3, [r7, #19] ibmwhite_state = ( ( msb << 8 ) | ( ibmwhite_state >> 1 ) ); 800b79a: 7cfb ldrb r3, [r7, #19] 800b79c: b21b sxth r3, r3 800b79e: 021b lsls r3, r3, #8 800b7a0: b21a sxth r2, r3 800b7a2: 8bfb ldrh r3, [r7, #30] 800b7a4: 085b lsrs r3, r3, #1 800b7a6: b29b uxth r3, r3 800b7a8: b21b sxth r3, r3 800b7aa: 4313 orrs r3, r2 800b7ac: b21b sxth r3, r3 800b7ae: 83fb strh r3, [r7, #30] for( int32_t j = 0; j < 8; j++ ) 800b7b0: 697b ldr r3, [r7, #20] 800b7b2: 3301 adds r3, #1 800b7b4: 617b str r3, [r7, #20] 800b7b6: 697b ldr r3, [r7, #20] 800b7b8: 2b07 cmp r3, #7 800b7ba: dde3 ble.n 800b784 for( int32_t i = 0; i < Size; i++ ) 800b7bc: 69bb ldr r3, [r7, #24] 800b7be: 3301 adds r3, #1 800b7c0: 61bb str r3, [r7, #24] 800b7c2: 69bb ldr r3, [r7, #24] 800b7c4: 687a ldr r2, [r7, #4] 800b7c6: 429a cmp r2, r3 800b7c8: d8cb bhi.n 800b762 } } RFWPacket->WhiteLfsrState = ibmwhite_state; 800b7ca: 68fb ldr r3, [r7, #12] 800b7cc: 8bfa ldrh r2, [r7, #30] 800b7ce: 82da strh r2, [r3, #22] } 800b7d0: bf00 nop 800b7d2: 3724 adds r7, #36 @ 0x24 800b7d4: 46bd mov sp, r7 800b7d6: bc80 pop {r7} 800b7d8: 4770 bx lr 0800b7da : static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size, uint8_t CrcResult[2] ) { 800b7da: b580 push {r7, lr} 800b7dc: b088 sub sp, #32 800b7de: af00 add r7, sp, #0 800b7e0: 60f8 str r0, [r7, #12] 800b7e2: 60b9 str r1, [r7, #8] 800b7e4: 607a str r2, [r7, #4] 800b7e6: 603b str r3, [r7, #0] int32_t status = 0; 800b7e8: 2300 movs r3, #0 800b7ea: 617b str r3, [r7, #20] int32_t i = 0; 800b7ec: 2300 movs r3, #0 800b7ee: 61fb str r3, [r7, #28] uint16_t polynomial = RFWPacket->Init.CrcPolynomial; 800b7f0: 68fb ldr r3, [r7, #12] 800b7f2: 889b ldrh r3, [r3, #4] 800b7f4: 827b strh r3, [r7, #18] /* Restore state from previous chunk*/ uint16_t crc = RFWPacket->CrcLfsrState; 800b7f6: 68fb ldr r3, [r7, #12] 800b7f8: 8a9b ldrh r3, [r3, #20] 800b7fa: 837b strh r3, [r7, #26] for( i = 0; i < Size; i++ ) 800b7fc: 2300 movs r3, #0 800b7fe: 61fb str r3, [r7, #28] 800b800: e00d b.n 800b81e { crc = RFW_CrcRun1Byte( crc, Payload[i], polynomial ); 800b802: 69fb ldr r3, [r7, #28] 800b804: 68ba ldr r2, [r7, #8] 800b806: 4413 add r3, r2 800b808: 7819 ldrb r1, [r3, #0] 800b80a: 8a7a ldrh r2, [r7, #18] 800b80c: 8b7b ldrh r3, [r7, #26] 800b80e: 4618 mov r0, r3 800b810: f000 f82f bl 800b872 800b814: 4603 mov r3, r0 800b816: 837b strh r3, [r7, #26] for( i = 0; i < Size; i++ ) 800b818: 69fb ldr r3, [r7, #28] 800b81a: 3301 adds r3, #1 800b81c: 61fb str r3, [r7, #28] 800b81e: 69fb ldr r3, [r7, #28] 800b820: 687a ldr r2, [r7, #4] 800b822: 429a cmp r2, r3 800b824: d8ed bhi.n 800b802 } /*Save state for next chunk*/ RFWPacket->CrcLfsrState = crc; 800b826: 68fb ldr r3, [r7, #12] 800b828: 8b7a ldrh r2, [r7, #26] 800b82a: 829a strh r2, [r3, #20] if( RFWPacket->Init.CrcType == RADIO_FSK_CRC_2_BYTES_IBM ) 800b82c: 68fb ldr r3, [r7, #12] 800b82e: 7a1b ldrb r3, [r3, #8] 800b830: 2bf1 cmp r3, #241 @ 0xf1 800b832: d10b bne.n 800b84c { CrcResult[1] = crc & 0xFF; 800b834: 683b ldr r3, [r7, #0] 800b836: 3301 adds r3, #1 800b838: 8b7a ldrh r2, [r7, #26] 800b83a: b2d2 uxtb r2, r2 800b83c: 701a strb r2, [r3, #0] CrcResult[0] = crc >> 8; 800b83e: 8b7b ldrh r3, [r7, #26] 800b840: 0a1b lsrs r3, r3, #8 800b842: b29b uxth r3, r3 800b844: b2da uxtb r2, r3 800b846: 683b ldr r3, [r7, #0] 800b848: 701a strb r2, [r3, #0] 800b84a: e00d b.n 800b868 } else { crc = ~crc ; 800b84c: 8b7b ldrh r3, [r7, #26] 800b84e: 43db mvns r3, r3 800b850: 837b strh r3, [r7, #26] CrcResult[1] = crc & 0xFF; 800b852: 683b ldr r3, [r7, #0] 800b854: 3301 adds r3, #1 800b856: 8b7a ldrh r2, [r7, #26] 800b858: b2d2 uxtb r2, r2 800b85a: 701a strb r2, [r3, #0] CrcResult[0] = crc >> 8; 800b85c: 8b7b ldrh r3, [r7, #26] 800b85e: 0a1b lsrs r3, r3, #8 800b860: b29b uxth r3, r3 800b862: b2da uxtb r2, r3 800b864: 683b ldr r3, [r7, #0] 800b866: 701a strb r2, [r3, #0] } return status; 800b868: 697b ldr r3, [r7, #20] } 800b86a: 4618 mov r0, r3 800b86c: 3720 adds r7, #32 800b86e: 46bd mov sp, r7 800b870: bd80 pop {r7, pc} 0800b872 : uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial ) { 800b872: b480 push {r7} 800b874: b085 sub sp, #20 800b876: af00 add r7, sp, #0 800b878: 4603 mov r3, r0 800b87a: 80fb strh r3, [r7, #6] 800b87c: 460b mov r3, r1 800b87e: 717b strb r3, [r7, #5] 800b880: 4613 mov r3, r2 800b882: 807b strh r3, [r7, #2] uint8_t i; for( i = 0; i < 8; i++ ) 800b884: 2300 movs r3, #0 800b886: 73fb strb r3, [r7, #15] 800b888: e018 b.n 800b8bc { if( ( ( ( Crc & 0x8000 ) >> 8 ) ^ ( DataByte & 0x80 ) ) != 0 ) 800b88a: 88fb ldrh r3, [r7, #6] 800b88c: 121a asrs r2, r3, #8 800b88e: 797b ldrb r3, [r7, #5] 800b890: 4053 eors r3, r2 800b892: f003 0380 and.w r3, r3, #128 @ 0x80 800b896: 2b00 cmp r3, #0 800b898: d007 beq.n 800b8aa { Crc <<= 1; 800b89a: 88fb ldrh r3, [r7, #6] 800b89c: 005b lsls r3, r3, #1 800b89e: 80fb strh r3, [r7, #6] Crc ^= Polynomial; 800b8a0: 88fa ldrh r2, [r7, #6] 800b8a2: 887b ldrh r3, [r7, #2] 800b8a4: 4053 eors r3, r2 800b8a6: 80fb strh r3, [r7, #6] 800b8a8: e002 b.n 800b8b0 } else { Crc <<= 1; 800b8aa: 88fb ldrh r3, [r7, #6] 800b8ac: 005b lsls r3, r3, #1 800b8ae: 80fb strh r3, [r7, #6] } DataByte <<= 1; 800b8b0: 797b ldrb r3, [r7, #5] 800b8b2: 005b lsls r3, r3, #1 800b8b4: 717b strb r3, [r7, #5] for( i = 0; i < 8; i++ ) 800b8b6: 7bfb ldrb r3, [r7, #15] 800b8b8: 3301 adds r3, #1 800b8ba: 73fb strb r3, [r7, #15] 800b8bc: 7bfb ldrb r3, [r7, #15] 800b8be: 2b07 cmp r3, #7 800b8c0: d9e3 bls.n 800b88a } return Crc; 800b8c2: 88fb ldrh r3, [r7, #6] } 800b8c4: 4618 mov r0, r3 800b8c6: 3714 adds r7, #20 800b8c8: 46bd mov sp, r7 800b8ca: bc80 pop {r7} 800b8cc: 4770 bx lr ... 0800b8d0 : static int32_t RFW_PollRxBytes( uint32_t bytes ) { 800b8d0: b580 push {r7, lr} 800b8d2: b086 sub sp, #24 800b8d4: af00 add r7, sp, #0 800b8d6: 6078 str r0, [r7, #4] uint32_t now = TimerGetCurrentTime( ); 800b8d8: f002 fac8 bl 800de6c 800b8dc: 6138 str r0, [r7, #16] uint8_t reg_buff_ptr_ref = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); 800b8de: f640 0003 movw r0, #2051 @ 0x803 800b8e2: f7fe ff35 bl 800a750 800b8e6: 4603 mov r3, r0 800b8e8: 73fb strb r3, [r7, #15] uint8_t reg_buff_ptr = reg_buff_ptr_ref; 800b8ea: 7bfb ldrb r3, [r7, #15] 800b8ec: 75fb strb r3, [r7, #23] uint32_t timeout = DIVC( bytes * 8 * 1000, RFWPacket.BitRate ); 800b8ee: 687b ldr r3, [r7, #4] 800b8f0: f44f 52fa mov.w r2, #8000 @ 0x1f40 800b8f4: fb03 f202 mul.w r2, r3, r2 800b8f8: 4b12 ldr r3, [pc, #72] @ (800b944 ) 800b8fa: 6c9b ldr r3, [r3, #72] @ 0x48 800b8fc: 4413 add r3, r2 800b8fe: 1e5a subs r2, r3, #1 800b900: 4b10 ldr r3, [pc, #64] @ (800b944 ) 800b902: 6c9b ldr r3, [r3, #72] @ 0x48 800b904: fbb2 f3f3 udiv r3, r2, r3 800b908: 60bb str r3, [r7, #8] /* Wait that packet length is received */ while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) 800b90a: e00f b.n 800b92c { /*reading rx address pointer*/ reg_buff_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); 800b90c: f640 0003 movw r0, #2051 @ 0x803 800b910: f7fe ff1e bl 800a750 800b914: 4603 mov r3, r0 800b916: 75fb strb r3, [r7, #23] if( TimerGetElapsedTime( now ) > timeout ) 800b918: 6938 ldr r0, [r7, #16] 800b91a: f002 fab9 bl 800de90 800b91e: 4602 mov r2, r0 800b920: 68bb ldr r3, [r7, #8] 800b922: 4293 cmp r3, r2 800b924: d202 bcs.n 800b92c { /*timeout*/ return -1; 800b926: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b92a: e007 b.n 800b93c while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) 800b92c: 7dfa ldrb r2, [r7, #23] 800b92e: 7bfb ldrb r3, [r7, #15] 800b930: 1ad3 subs r3, r2, r3 800b932: 461a mov r2, r3 800b934: 687b ldr r3, [r7, #4] 800b936: 4293 cmp r3, r2 800b938: d8e8 bhi.n 800b90c } } return 0; 800b93a: 2300 movs r3, #0 } 800b93c: 4618 mov r0, r3 800b93e: 3718 adds r7, #24 800b940: 46bd mov sp, r7 800b942: bd80 pop {r7, pc} 800b944: 2000039c .word 0x2000039c 0800b948 : static int32_t RFW_GetPacketLength( uint16_t *PayloadLength ) { 800b948: b580 push {r7, lr} 800b94a: b086 sub sp, #24 800b94c: af02 add r7, sp, #8 800b94e: 6078 str r0, [r7, #4] if( 0UL != RFW_PollRxBytes( RFWPacket.Init.PayloadLengthFieldSize ) ) 800b950: 4b25 ldr r3, [pc, #148] @ (800b9e8 ) 800b952: 785b ldrb r3, [r3, #1] 800b954: 4618 mov r0, r3 800b956: f7ff ffbb bl 800b8d0 800b95a: 4603 mov r3, r0 800b95c: 2b00 cmp r3, #0 800b95e: d002 beq.n 800b966 { return -1; 800b960: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b964: e03b b.n 800b9de } /* Get buffer from Radio*/ SUBGRF_ReadBuffer( 0, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); 800b966: 4b20 ldr r3, [pc, #128] @ (800b9e8 ) 800b968: 785b ldrb r3, [r3, #1] 800b96a: 461a mov r2, r3 800b96c: 491f ldr r1, [pc, #124] @ (800b9ec ) 800b96e: 2000 movs r0, #0 800b970: f7fe ff74 bl 800a85c /* De-whiten packet length*/ RFW_WhiteRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); 800b974: 4b1c ldr r3, [pc, #112] @ (800b9e8 ) 800b976: 785b ldrb r3, [r3, #1] 800b978: 461a mov r2, r3 800b97a: 491c ldr r1, [pc, #112] @ (800b9ec ) 800b97c: 481a ldr r0, [pc, #104] @ (800b9e8 ) 800b97e: f7ff fee4 bl 800b74a /*do crc 1st calculation packetLengthField and store intermediate result */ if( RFWPacket.Init.CrcEnable == 1 ) 800b982: 4b19 ldr r3, [pc, #100] @ (800b9e8 ) 800b984: 789b ldrb r3, [r3, #2] 800b986: 2b01 cmp r3, #1 800b988: d108 bne.n 800b99c { /*run Crc algo on payloadLengthField*/ uint8_t crc_dummy[2]; RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize, crc_dummy ); 800b98a: 4b17 ldr r3, [pc, #92] @ (800b9e8 ) 800b98c: 785b ldrb r3, [r3, #1] 800b98e: 461a mov r2, r3 800b990: f107 030c add.w r3, r7, #12 800b994: 4915 ldr r1, [pc, #84] @ (800b9ec ) 800b996: 4814 ldr r0, [pc, #80] @ (800b9e8 ) 800b998: f7ff ff1f bl 800b7da } if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) 800b99c: 4b12 ldr r3, [pc, #72] @ (800b9e8 ) 800b99e: 785b ldrb r3, [r3, #1] 800b9a0: 2b01 cmp r3, #1 800b9a2: d105 bne.n 800b9b0 { *PayloadLength = ( uint16_t ) ChunkBuffer[0]; 800b9a4: 4b11 ldr r3, [pc, #68] @ (800b9ec ) 800b9a6: 781b ldrb r3, [r3, #0] 800b9a8: 461a mov r2, r3 800b9aa: 687b ldr r3, [r7, #4] 800b9ac: 801a strh r2, [r3, #0] 800b9ae: e00c b.n 800b9ca } else { /*packet length is 2 bytes*/ *PayloadLength = ( ( ( uint16_t ) ChunkBuffer[0] ) << 8 ) | ChunkBuffer[1]; 800b9b0: 4b0e ldr r3, [pc, #56] @ (800b9ec ) 800b9b2: 781b ldrb r3, [r3, #0] 800b9b4: b21b sxth r3, r3 800b9b6: 021b lsls r3, r3, #8 800b9b8: b21a sxth r2, r3 800b9ba: 4b0c ldr r3, [pc, #48] @ (800b9ec ) 800b9bc: 785b ldrb r3, [r3, #1] 800b9be: b21b sxth r3, r3 800b9c0: 4313 orrs r3, r2 800b9c2: b21b sxth r3, r3 800b9c4: b29a uxth r2, r3 800b9c6: 687b ldr r3, [r7, #4] 800b9c8: 801a strh r2, [r3, #0] } RFW_MW_LOG( TS_ON, VLEVEL_M, "PayloadLength=%d,\r\n", *PayloadLength ); 800b9ca: 687b ldr r3, [r7, #4] 800b9cc: 881b ldrh r3, [r3, #0] 800b9ce: 9300 str r3, [sp, #0] 800b9d0: 4b07 ldr r3, [pc, #28] @ (800b9f0 ) 800b9d2: 2201 movs r2, #1 800b9d4: 2100 movs r1, #0 800b9d6: 2002 movs r0, #2 800b9d8: f002 fb26 bl 800e028 return 0; 800b9dc: 2300 movs r3, #0 } 800b9de: 4618 mov r0, r3 800b9e0: 3710 adds r7, #16 800b9e2: 46bd mov sp, r7 800b9e4: bd80 pop {r7, pc} 800b9e6: bf00 nop 800b9e8: 2000039c .word 0x2000039c 800b9ec: 200003f0 .word 0x200003f0 800b9f0: 0800f230 .word 0x0800f230 0800b9f4 : static void RFW_GetPayloadTimerEvent( void *context ) { 800b9f4: b580 push {r7, lr} 800b9f6: b082 sub sp, #8 800b9f8: af00 add r7, sp, #0 800b9fa: 6078 str r0, [r7, #4] RFW_GET_PAYLOAD_PROCESS(); 800b9fc: f000 f804 bl 800ba08 } 800ba00: bf00 nop 800ba02: 3708 adds r7, #8 800ba04: 46bd mov sp, r7 800ba06: bd80 pop {r7, pc} 0800ba08 : static void RFW_GetPayloadProcess( void ) { 800ba08: b580 push {r7, lr} 800ba0a: b086 sub sp, #24 800ba0c: af04 add r7, sp, #16 /*long packet mode*/ uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); 800ba0e: f640 0003 movw r0, #2051 @ 0x803 800ba12: f7fe fe9d bl 800a750 800ba16: 4603 mov r3, r0 800ba18: 70fb strb r3, [r7, #3] uint8_t size = read_ptr - RFWPacket.RadioBufferOffset; 800ba1a: 4b83 ldr r3, [pc, #524] @ (800bc28 ) 800ba1c: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800ba20: 78fa ldrb r2, [r7, #3] 800ba22: 1ad3 subs r3, r2, r3 800ba24: 70bb strb r3, [r7, #2] uint32_t Timeout; /*check remaining size*/ if( RFWPacket.LongPacketRemainingBytes > size ) 800ba26: 4b80 ldr r3, [pc, #512] @ (800bc28 ) 800ba28: 8e9a ldrh r2, [r3, #52] @ 0x34 800ba2a: 78bb ldrb r3, [r7, #2] 800ba2c: b29b uxth r3, r3 800ba2e: 429a cmp r2, r3 800ba30: f240 80cd bls.w 800bbce { /* update LongPacketRemainingBytes*/ RFWPacket.LongPacketRemainingBytes -= size; 800ba34: 4b7c ldr r3, [pc, #496] @ (800bc28 ) 800ba36: 8e9a ldrh r2, [r3, #52] @ 0x34 800ba38: 78bb ldrb r3, [r7, #2] 800ba3a: b29b uxth r3, r3 800ba3c: 1ad3 subs r3, r2, r3 800ba3e: b29a uxth r2, r3 800ba40: 4b79 ldr r3, [pc, #484] @ (800bc28 ) 800ba42: 869a strh r2, [r3, #52] @ 0x34 /*intermediate chunk*/ RFW_MW_LOG( TS_ON, VLEVEL_M, "RxTxPldLen=0x%02X,\r\n", SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ) ); 800ba44: f240 60bb movw r0, #1723 @ 0x6bb 800ba48: f7fe fe82 bl 800a750 800ba4c: 4603 mov r3, r0 800ba4e: 9300 str r3, [sp, #0] 800ba50: 4b76 ldr r3, [pc, #472] @ (800bc2c ) 800ba52: 2201 movs r2, #1 800ba54: 2100 movs r1, #0 800ba56: 2002 movs r0, #2 800ba58: f002 fae6 bl 800e028 RFW_MW_LOG( TS_ON, VLEVEL_M, "RxAddrPtr=0x%02X,\r\n", read_ptr ); 800ba5c: 78fb ldrb r3, [r7, #3] 800ba5e: 9300 str r3, [sp, #0] 800ba60: 4b73 ldr r3, [pc, #460] @ (800bc30 ) 800ba62: 2201 movs r2, #1 800ba64: 2100 movs r1, #0 800ba66: 2002 movs r0, #2 800ba68: f002 fade bl 800e028 RFW_MW_LOG( TS_ON, VLEVEL_M, "offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, 800ba6c: 4b6e ldr r3, [pc, #440] @ (800bc28 ) 800ba6e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800ba72: 4619 mov r1, r3 800ba74: 78bb ldrb r3, [r7, #2] 800ba76: 4a6c ldr r2, [pc, #432] @ (800bc28 ) 800ba78: 8e92 ldrh r2, [r2, #52] @ 0x34 800ba7a: 9202 str r2, [sp, #8] 800ba7c: 9301 str r3, [sp, #4] 800ba7e: 9100 str r1, [sp, #0] 800ba80: 4b6c ldr r3, [pc, #432] @ (800bc34 ) 800ba82: 2201 movs r2, #1 800ba84: 2100 movs r1, #0 800ba86: 2002 movs r0, #2 800ba88: f002 face bl 800e028 RFWPacket.LongPacketRemainingBytes ); /*update pld length so that not reached*/ SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, read_ptr - 1 ); 800ba8c: 78fb ldrb r3, [r7, #3] 800ba8e: 3b01 subs r3, #1 800ba90: b2db uxtb r3, r3 800ba92: 4619 mov r1, r3 800ba94: f240 60bb movw r0, #1723 @ 0x6bb 800ba98: f7fe fe38 bl 800a70c /* read data from radio*/ SUBGRF_ReadBuffer( RFWPacket.RadioBufferOffset, ChunkBuffer, size ); 800ba9c: 4b62 ldr r3, [pc, #392] @ (800bc28 ) 800ba9e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800baa2: 78ba ldrb r2, [r7, #2] 800baa4: 4964 ldr r1, [pc, #400] @ (800bc38 ) 800baa6: 4618 mov r0, r3 800baa8: f7fe fed8 bl 800a85c /* update buffer Offset, with intentional wrap around*/ RFWPacket.RadioBufferOffset += size; 800baac: 4b5e ldr r3, [pc, #376] @ (800bc28 ) 800baae: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 800bab2: 78bb ldrb r3, [r7, #2] 800bab4: 4413 add r3, r2 800bab6: b2da uxtb r2, r3 800bab8: 4b5b ldr r3, [pc, #364] @ (800bc28 ) 800baba: f883 2036 strb.w r2, [r3, #54] @ 0x36 /*Run the de-whitening on current chunk*/ RFW_WhiteRun( &RFWPacket, ChunkBuffer, size ); 800babe: 78bb ldrb r3, [r7, #2] 800bac0: 461a mov r2, r3 800bac2: 495d ldr r1, [pc, #372] @ (800bc38 ) 800bac4: 4858 ldr r0, [pc, #352] @ (800bc28 ) 800bac6: f7ff fe40 bl 800b74a if( RFWPacket.Init.CrcEnable == 1 ) 800baca: 4b57 ldr r3, [pc, #348] @ (800bc28 ) 800bacc: 789b ldrb r3, [r3, #2] 800bace: 2b01 cmp r3, #1 800bad0: d105 bne.n 800bade { /*run Crc algo on partial chunk*/ uint8_t crc_dummy[2]; RFW_CrcRun( &RFWPacket, ChunkBuffer, size, crc_dummy ); 800bad2: 78ba ldrb r2, [r7, #2] 800bad4: 463b mov r3, r7 800bad6: 4958 ldr r1, [pc, #352] @ (800bc38 ) 800bad8: 4853 ldr r0, [pc, #332] @ (800bc28 ) 800bada: f7ff fe7e bl 800b7da } if( RFWPacket.LongPacketModeEnable == 1 ) 800bade: 4b52 ldr r3, [pc, #328] @ (800bc28 ) 800bae0: 7e9b ldrb r3, [r3, #26] 800bae2: 2b01 cmp r3, #1 800bae4: d106 bne.n 800baf4 { /*report rx data chunk to application*/ RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, size ); 800bae6: 4b50 ldr r3, [pc, #320] @ (800bc28 ) 800bae8: 6bdb ldr r3, [r3, #60] @ 0x3c 800baea: 78ba ldrb r2, [r7, #2] 800baec: 4611 mov r1, r2 800baee: 4852 ldr r0, [pc, #328] @ (800bc38 ) 800baf0: 4798 blx r3 800baf2: e02b b.n 800bb4c } else { if( RFWPacket.RxPayloadOffset += size < RADIO_BUF_SIZE ) 800baf4: 4b4c ldr r3, [pc, #304] @ (800bc28 ) 800baf6: 8f1b ldrh r3, [r3, #56] @ 0x38 800baf8: 78ba ldrb r2, [r7, #2] 800bafa: 2aff cmp r2, #255 @ 0xff 800bafc: bf14 ite ne 800bafe: 2201 movne r2, #1 800bb00: 2200 moveq r2, #0 800bb02: b2d2 uxtb r2, r2 800bb04: 4413 add r3, r2 800bb06: b29a uxth r2, r3 800bb08: 4b47 ldr r3, [pc, #284] @ (800bc28 ) 800bb0a: 871a strh r2, [r3, #56] @ 0x38 800bb0c: 4b46 ldr r3, [pc, #280] @ (800bc28 ) 800bb0e: 8f1b ldrh r3, [r3, #56] @ 0x38 800bb10: 2b00 cmp r3, #0 800bb12: d013 beq.n 800bb3c { RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, size ); 800bb14: 4b44 ldr r3, [pc, #272] @ (800bc28 ) 800bb16: 8f1b ldrh r3, [r3, #56] @ 0x38 800bb18: 461a mov r2, r3 800bb1a: 4b48 ldr r3, [pc, #288] @ (800bc3c ) 800bb1c: 4413 add r3, r2 800bb1e: 78ba ldrb r2, [r7, #2] 800bb20: b292 uxth r2, r2 800bb22: 4945 ldr r1, [pc, #276] @ (800bc38 ) 800bb24: 4618 mov r0, r3 800bb26: f001 fb81 bl 800d22c RFWPacket.RxPayloadOffset += size; 800bb2a: 4b3f ldr r3, [pc, #252] @ (800bc28 ) 800bb2c: 8f1a ldrh r2, [r3, #56] @ 0x38 800bb2e: 78bb ldrb r3, [r7, #2] 800bb30: b29b uxth r3, r3 800bb32: 4413 add r3, r2 800bb34: b29a uxth r2, r3 800bb36: 4b3c ldr r3, [pc, #240] @ (800bc28 ) 800bb38: 871a strh r2, [r3, #56] @ 0x38 800bb3a: e007 b.n 800bb4c } else { /*stop the radio*/ SUBGRF_SetStandby( STDBY_RC ); 800bb3c: 2000 movs r0, #0 800bb3e: f7fe f861 bl 8009c04 /*report CRC error*/ RFWPacket.Init.RadioEvents->RxError( ); 800bb42: 4b39 ldr r3, [pc, #228] @ (800bc28 ) 800bb44: 691b ldr r3, [r3, #16] 800bb46: 691b ldr r3, [r3, #16] 800bb48: 4798 blx r3 return; 800bb4a: e069 b.n 800bc20 } } /*calculate next timer timeout*/ if( RFWPacket.LongPacketRemainingBytes < LONGPACKET_CHUNK_LENGTH_BYTES ) 800bb4c: 4b36 ldr r3, [pc, #216] @ (800bc28 ) 800bb4e: 8e9b ldrh r3, [r3, #52] @ 0x34 800bb50: 2b7f cmp r3, #127 @ 0x7f 800bb52: d812 bhi.n 800bb7a { /*for the next and last chunk DIVC +1 to make sure crc is received.*/ Timeout = DIVC( ( RFWPacket.LongPacketRemainingBytes ) * 8 * 1000, RFWPacket.BitRate ) + 2; 800bb54: 4b34 ldr r3, [pc, #208] @ (800bc28 ) 800bb56: 8e9b ldrh r3, [r3, #52] @ 0x34 800bb58: 461a mov r2, r3 800bb5a: f44f 53fa mov.w r3, #8000 @ 0x1f40 800bb5e: fb02 f303 mul.w r3, r2, r3 800bb62: 461a mov r2, r3 800bb64: 4b30 ldr r3, [pc, #192] @ (800bc28 ) 800bb66: 6c9b ldr r3, [r3, #72] @ 0x48 800bb68: 4413 add r3, r2 800bb6a: 1e5a subs r2, r3, #1 800bb6c: 4b2e ldr r3, [pc, #184] @ (800bc28 ) 800bb6e: 6c9b ldr r3, [r3, #72] @ 0x48 800bb70: fbb2 f3f3 udiv r3, r2, r3 800bb74: 3302 adds r3, #2 800bb76: 607b str r3, [r7, #4] 800bb78: e021 b.n 800bbbe } else if( RFWPacket.LongPacketRemainingBytes < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES ) / 2 ) 800bb7a: 4b2b ldr r3, [pc, #172] @ (800bc28 ) 800bb7c: 8e9b ldrh r3, [r3, #52] @ 0x34 800bb7e: 2bbf cmp r3, #191 @ 0xbf 800bb80: d813 bhi.n 800bbaa { /*this is to make sure that last chunk will always be greater than LONGPACKET_CHUNK_LENGTH_BYTES/2 */ Timeout = DIVR( ( RFWPacket.LongPacketRemainingBytes / 2 ) * 8 * 1000, RFWPacket.BitRate ); 800bb82: 4b29 ldr r3, [pc, #164] @ (800bc28 ) 800bb84: 8e9b ldrh r3, [r3, #52] @ 0x34 800bb86: 085b lsrs r3, r3, #1 800bb88: b29b uxth r3, r3 800bb8a: 461a mov r2, r3 800bb8c: f44f 53fa mov.w r3, #8000 @ 0x1f40 800bb90: fb02 f303 mul.w r3, r2, r3 800bb94: 461a mov r2, r3 800bb96: 4b24 ldr r3, [pc, #144] @ (800bc28 ) 800bb98: 6c9b ldr r3, [r3, #72] @ 0x48 800bb9a: 085b lsrs r3, r3, #1 800bb9c: 441a add r2, r3 800bb9e: 4b22 ldr r3, [pc, #136] @ (800bc28 ) 800bba0: 6c9b ldr r3, [r3, #72] @ 0x48 800bba2: fbb2 f3f3 udiv r3, r2, r3 800bba6: 607b str r3, [r7, #4] 800bba8: e009 b.n 800bbbe } else { /*size value is close to LONGPACKET_CHUNK_LENGTH_BYTES with +/- errors compensated in closed loop here*/ Timeout = DIVR( ( LONGPACKET_CHUNK_LENGTH_BYTES ) * 8 * 1000, RFWPacket.BitRate ); 800bbaa: 4b1f ldr r3, [pc, #124] @ (800bc28 ) 800bbac: 6c9b ldr r3, [r3, #72] @ 0x48 800bbae: 085b lsrs r3, r3, #1 800bbb0: f503 227a add.w r2, r3, #1024000 @ 0xfa000 800bbb4: 4b1c ldr r3, [pc, #112] @ (800bc28 ) 800bbb6: 6c9b ldr r3, [r3, #72] @ 0x48 800bbb8: fbb2 f3f3 udiv r3, r2, r3 800bbbc: 607b str r3, [r7, #4] } TimerSetValue( &RFWPacket.Timer, Timeout ); 800bbbe: 6879 ldr r1, [r7, #4] 800bbc0: 481f ldr r0, [pc, #124] @ (800bc40 ) 800bbc2: f002 f8a9 bl 800dd18 TimerStart( &RFWPacket.Timer ); 800bbc6: 481e ldr r0, [pc, #120] @ (800bc40 ) 800bbc8: f001 ffc8 bl 800db5c 800bbcc: e028 b.n 800bc20 } else { if( RFWPacket.LongPacketRemainingBytes < RFWPacket.Init.CrcFieldSize ) 800bbce: 4b16 ldr r3, [pc, #88] @ (800bc28 ) 800bbd0: 8e9b ldrh r3, [r3, #52] @ 0x34 800bbd2: 4a15 ldr r2, [pc, #84] @ (800bc28 ) 800bbd4: 78d2 ldrb r2, [r2, #3] 800bbd6: 4293 cmp r3, r2 800bbd8: d204 bcs.n 800bbe4 { /* force LongPacketRemainingBytes to CrcFieldSize: this should never happen*/ RFWPacket.LongPacketRemainingBytes = RFWPacket.Init.CrcFieldSize; 800bbda: 4b13 ldr r3, [pc, #76] @ (800bc28 ) 800bbdc: 78db ldrb r3, [r3, #3] 800bbde: 461a mov r2, r3 800bbe0: 4b11 ldr r3, [pc, #68] @ (800bc28 ) 800bbe2: 869a strh r2, [r3, #52] @ 0x34 } /*last chunk*/ RFW_MW_LOG( TS_ON, VLEVEL_M, "LastChunk. offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, 800bbe4: 4b10 ldr r3, [pc, #64] @ (800bc28 ) 800bbe6: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800bbea: 4619 mov r1, r3 800bbec: 78bb ldrb r3, [r7, #2] 800bbee: 4a0e ldr r2, [pc, #56] @ (800bc28 ) 800bbf0: 8e92 ldrh r2, [r2, #52] @ 0x34 800bbf2: 9202 str r2, [sp, #8] 800bbf4: 9301 str r3, [sp, #4] 800bbf6: 9100 str r1, [sp, #0] 800bbf8: 4b12 ldr r3, [pc, #72] @ (800bc44 ) 800bbfa: 2201 movs r2, #1 800bbfc: 2100 movs r1, #0 800bbfe: 2002 movs r0, #2 800bc00: f002 fa12 bl 800e028 RFWPacket.LongPacketRemainingBytes ); size = RFWPacket.LongPacketRemainingBytes; 800bc04: 4b08 ldr r3, [pc, #32] @ (800bc28 ) 800bc06: 8e9b ldrh r3, [r3, #52] @ 0x34 800bc08: 70bb strb r3, [r7, #2] /* update LongPacketRemainingBytes*/ RFWPacket.LongPacketRemainingBytes = 0; 800bc0a: 4b07 ldr r3, [pc, #28] @ (800bc28 ) 800bc0c: 2200 movs r2, #0 800bc0e: 869a strh r2, [r3, #52] @ 0x34 /*Process last chunk*/ RFW_GetPayload( RFWPacket.RadioBufferOffset, size ); 800bc10: 4b05 ldr r3, [pc, #20] @ (800bc28 ) 800bc12: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800bc16: 78ba ldrb r2, [r7, #2] 800bc18: 4611 mov r1, r2 800bc1a: 4618 mov r0, r3 800bc1c: f000 f814 bl 800bc48 } } 800bc20: 3708 adds r7, #8 800bc22: 46bd mov sp, r7 800bc24: bd80 pop {r7, pc} 800bc26: bf00 nop 800bc28: 2000039c .word 0x2000039c 800bc2c: 0800f244 .word 0x0800f244 800bc30: 0800f25c .word 0x0800f25c 800bc34: 0800f270 .word 0x0800f270 800bc38: 200003f0 .word 0x200003f0 800bc3c: 200004f0 .word 0x200004f0 800bc40: 200003b8 .word 0x200003b8 800bc44: 0800f298 .word 0x0800f298 0800bc48 : static void RFW_GetPayload( uint8_t Offset, uint8_t Length ) { 800bc48: b5b0 push {r4, r5, r7, lr} 800bc4a: b088 sub sp, #32 800bc4c: af04 add r7, sp, #16 800bc4e: 4603 mov r3, r0 800bc50: 460a mov r2, r1 800bc52: 71fb strb r3, [r7, #7] 800bc54: 4613 mov r3, r2 800bc56: 71bb strb r3, [r7, #6] uint8_t crc_result[2]; /*stop the radio*/ SUBGRF_SetStandby( STDBY_RC ); 800bc58: 2000 movs r0, #0 800bc5a: f7fd ffd3 bl 8009c04 /*read data buffer*/ SUBGRF_ReadBuffer( Offset, ChunkBuffer, Length ); 800bc5e: 79ba ldrb r2, [r7, #6] 800bc60: 79fb ldrb r3, [r7, #7] 800bc62: 495a ldr r1, [pc, #360] @ (800bdcc ) 800bc64: 4618 mov r0, r3 800bc66: f7fe fdf9 bl 800a85c /*Run the de-whitening on all packet*/ RFW_WhiteRun( &RFWPacket, ChunkBuffer, Length ); 800bc6a: 79bb ldrb r3, [r7, #6] 800bc6c: 461a mov r2, r3 800bc6e: 4957 ldr r1, [pc, #348] @ (800bdcc ) 800bc70: 4857 ldr r0, [pc, #348] @ (800bdd0 ) 800bc72: f7ff fd6a bl 800b74a if( RFWPacket.Init.CrcEnable == 1 ) 800bc76: 4b56 ldr r3, [pc, #344] @ (800bdd0 ) 800bc78: 789b ldrb r3, [r3, #2] 800bc7a: 2b01 cmp r3, #1 800bc7c: d10a bne.n 800bc94 { RFW_CrcRun( &RFWPacket, ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize, crc_result ); 800bc7e: 79bb ldrb r3, [r7, #6] 800bc80: 4a53 ldr r2, [pc, #332] @ (800bdd0 ) 800bc82: 78d2 ldrb r2, [r2, #3] 800bc84: 1a9b subs r3, r3, r2 800bc86: 461a mov r2, r3 800bc88: f107 030c add.w r3, r7, #12 800bc8c: 494f ldr r1, [pc, #316] @ (800bdcc ) 800bc8e: 4850 ldr r0, [pc, #320] @ (800bdd0 ) 800bc90: f7ff fda3 bl 800b7da } if( RFWPacket.LongPacketModeEnable == 1 ) 800bc94: 4b4e ldr r3, [pc, #312] @ (800bdd0 ) 800bc96: 7e9b ldrb r3, [r3, #26] 800bc98: 2b01 cmp r3, #1 800bc9a: d10a bne.n 800bcb2 { /*report rx data chunk to application*/ RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); 800bc9c: 4b4c ldr r3, [pc, #304] @ (800bdd0 ) 800bc9e: 6bdb ldr r3, [r3, #60] @ 0x3c 800bca0: 4a4b ldr r2, [pc, #300] @ (800bdd0 ) 800bca2: 78d2 ldrb r2, [r2, #3] 800bca4: 79b9 ldrb r1, [r7, #6] 800bca6: 1a8a subs r2, r1, r2 800bca8: b2d2 uxtb r2, r2 800bcaa: 4611 mov r1, r2 800bcac: 4847 ldr r0, [pc, #284] @ (800bdcc ) 800bcae: 4798 blx r3 800bcb0: e02a b.n 800bd08 } else { if( RFWPacket.RxPayloadOffset + Length - RFWPacket.Init.CrcFieldSize < RADIO_BUF_SIZE ) 800bcb2: 4b47 ldr r3, [pc, #284] @ (800bdd0 ) 800bcb4: 8f1b ldrh r3, [r3, #56] @ 0x38 800bcb6: 461a mov r2, r3 800bcb8: 79bb ldrb r3, [r7, #6] 800bcba: 4413 add r3, r2 800bcbc: 4a44 ldr r2, [pc, #272] @ (800bdd0 ) 800bcbe: 78d2 ldrb r2, [r2, #3] 800bcc0: 1a9b subs r3, r3, r2 800bcc2: 2bfe cmp r3, #254 @ 0xfe 800bcc4: dc1b bgt.n 800bcfe { RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); 800bcc6: 4b42 ldr r3, [pc, #264] @ (800bdd0 ) 800bcc8: 8f1b ldrh r3, [r3, #56] @ 0x38 800bcca: 461a mov r2, r3 800bccc: 4b41 ldr r3, [pc, #260] @ (800bdd4 ) 800bcce: 18d0 adds r0, r2, r3 800bcd0: 79bb ldrb r3, [r7, #6] 800bcd2: b29b uxth r3, r3 800bcd4: 4a3e ldr r2, [pc, #248] @ (800bdd0 ) 800bcd6: 78d2 ldrb r2, [r2, #3] 800bcd8: 1a9b subs r3, r3, r2 800bcda: b29b uxth r3, r3 800bcdc: 461a mov r2, r3 800bcde: 493b ldr r1, [pc, #236] @ (800bdcc ) 800bce0: f001 faa4 bl 800d22c RFWPacket.RxPayloadOffset += Length - RFWPacket.Init.CrcFieldSize; 800bce4: 4b3a ldr r3, [pc, #232] @ (800bdd0 ) 800bce6: 8f1a ldrh r2, [r3, #56] @ 0x38 800bce8: 79bb ldrb r3, [r7, #6] 800bcea: b29b uxth r3, r3 800bcec: 4938 ldr r1, [pc, #224] @ (800bdd0 ) 800bcee: 78c9 ldrb r1, [r1, #3] 800bcf0: 1a5b subs r3, r3, r1 800bcf2: b29b uxth r3, r3 800bcf4: 4413 add r3, r2 800bcf6: b29a uxth r2, r3 800bcf8: 4b35 ldr r3, [pc, #212] @ (800bdd0 ) 800bcfa: 871a strh r2, [r3, #56] @ 0x38 800bcfc: e004 b.n 800bd08 } else { /*report CRC error*/ RFWPacket.Init.RadioEvents->RxError( ); 800bcfe: 4b34 ldr r3, [pc, #208] @ (800bdd0 ) 800bd00: 691b ldr r3, [r3, #16] 800bd02: 691b ldr r3, [r3, #16] 800bd04: 4798 blx r3 800bd06: e05d b.n 800bdc4 return; } } TimerStop( RFWPacket.RxTimeoutTimer ); 800bd08: 4b31 ldr r3, [pc, #196] @ (800bdd0 ) 800bd0a: 6cdb ldr r3, [r3, #76] @ 0x4c 800bd0c: 4618 mov r0, r3 800bd0e: f001 ff93 bl 800dc38 /* CRC check*/ RFW_MW_LOG( TS_ON, VLEVEL_M, "crc_result= 0x%02X%02X, crc_payload=0x%02X%02X\r\n", crc_result[0], crc_result[1], 800bd12: 7b3b ldrb r3, [r7, #12] 800bd14: 4619 mov r1, r3 800bd16: 7b7b ldrb r3, [r7, #13] 800bd18: 4618 mov r0, r3 800bd1a: 79bb ldrb r3, [r7, #6] 800bd1c: 3b02 subs r3, #2 800bd1e: 4a2b ldr r2, [pc, #172] @ (800bdcc ) 800bd20: 5cd3 ldrb r3, [r2, r3] 800bd22: 461c mov r4, r3 800bd24: 79bb ldrb r3, [r7, #6] 800bd26: 3b01 subs r3, #1 800bd28: 4a28 ldr r2, [pc, #160] @ (800bdcc ) 800bd2a: 5cd3 ldrb r3, [r2, r3] 800bd2c: 9303 str r3, [sp, #12] 800bd2e: 9402 str r4, [sp, #8] 800bd30: 9001 str r0, [sp, #4] 800bd32: 9100 str r1, [sp, #0] 800bd34: 4b28 ldr r3, [pc, #160] @ (800bdd8 ) 800bd36: 2201 movs r2, #1 800bd38: 2100 movs r1, #0 800bd3a: 2002 movs r0, #2 800bd3c: f002 f974 bl 800e028 ChunkBuffer[Length - 2], ChunkBuffer[Length - 1] ); if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && 800bd40: 7b3a ldrb r2, [r7, #12] 800bd42: 79bb ldrb r3, [r7, #6] 800bd44: 3b02 subs r3, #2 800bd46: 4921 ldr r1, [pc, #132] @ (800bdcc ) 800bd48: 5ccb ldrb r3, [r1, r3] 800bd4a: 429a cmp r2, r3 800bd4c: d106 bne.n 800bd5c ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || 800bd4e: 7b7a ldrb r2, [r7, #13] 800bd50: 79bb ldrb r3, [r7, #6] 800bd52: 3b01 subs r3, #1 800bd54: 491d ldr r1, [pc, #116] @ (800bdcc ) 800bd56: 5ccb ldrb r3, [r1, r3] if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && 800bd58: 429a cmp r2, r3 800bd5a: d003 beq.n 800bd64 ( RFWPacket.Init.CrcEnable == 0 ) ) 800bd5c: 4b1c ldr r3, [pc, #112] @ (800bdd0 ) 800bd5e: 789b ldrb r3, [r3, #2] ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || 800bd60: 2b00 cmp r3, #0 800bd62: d126 bne.n 800bdb2 { /*read Rssi sampled at Sync*/ uint8_t rssi_sync = SUBGRF_ReadRegister( 0x06CA ); 800bd64: f240 60ca movw r0, #1738 @ 0x6ca 800bd68: f7fe fcf2 bl 800a750 800bd6c: 4603 mov r3, r0 800bd6e: 73fb strb r3, [r7, #15] /* Get Carrier Frequency Offset*/ int32_t cfo; SUBGRF_GetCFO( RFWPacket.BitRate, &cfo ); 800bd70: 4b17 ldr r3, [pc, #92] @ (800bdd0 ) 800bd72: 6c9b ldr r3, [r3, #72] @ 0x48 800bd74: f107 0208 add.w r2, r7, #8 800bd78: 4611 mov r1, r2 800bd7a: 4618 mov r0, r3 800bd7c: f7fe ff22 bl 800abc4 /*ChunkBuffer[1] to remove packet Length*/ RFWPacket.Init.RadioEvents->RxDone( RxBuffer, 800bd80: 4b13 ldr r3, [pc, #76] @ (800bdd0 ) 800bd82: 691b ldr r3, [r3, #16] 800bd84: 689c ldr r4, [r3, #8] 800bd86: 4b12 ldr r3, [pc, #72] @ (800bdd0 ) 800bd88: 8f19 ldrh r1, [r3, #56] @ 0x38 800bd8a: 7bfb ldrb r3, [r7, #15] 800bd8c: 085b lsrs r3, r3, #1 800bd8e: b2db uxtb r3, r3 800bd90: 425b negs r3, r3 800bd92: b29b uxth r3, r3 800bd94: b218 sxth r0, r3 RFWPacket.RxPayloadOffset, -( rssi_sync >> 1 ), ( int8_t ) DIVR( cfo, 1000 ) ); 800bd96: 68bb ldr r3, [r7, #8] 800bd98: f503 73fa add.w r3, r3, #500 @ 0x1f4 800bd9c: 4a0f ldr r2, [pc, #60] @ (800bddc ) 800bd9e: fb82 5203 smull r5, r2, r2, r3 800bda2: 1192 asrs r2, r2, #6 800bda4: 17db asrs r3, r3, #31 800bda6: 1ad3 subs r3, r2, r3 RFWPacket.Init.RadioEvents->RxDone( RxBuffer, 800bda8: b25b sxtb r3, r3 800bdaa: 4602 mov r2, r0 800bdac: 4809 ldr r0, [pc, #36] @ (800bdd4 ) 800bdae: 47a0 blx r4 { 800bdb0: e003 b.n 800bdba } else { /*report CRC error*/ RFWPacket.Init.RadioEvents->RxError( ); 800bdb2: 4b07 ldr r3, [pc, #28] @ (800bdd0 ) 800bdb4: 691b ldr r3, [r3, #16] 800bdb6: 691b ldr r3, [r3, #16] 800bdb8: 4798 blx r3 } DBG_GPIO_RADIO_RX( RST ); 800bdba: f44f 5180 mov.w r1, #4096 @ 0x1000 800bdbe: 4808 ldr r0, [pc, #32] @ (800bde0 ) 800bdc0: f7fe ff8d bl 800acde } 800bdc4: 3710 adds r7, #16 800bdc6: 46bd mov sp, r7 800bdc8: bdb0 pop {r4, r5, r7, pc} 800bdca: bf00 nop 800bdcc: 200003f0 .word 0x200003f0 800bdd0: 2000039c .word 0x2000039c 800bdd4: 200004f0 .word 0x200004f0 800bdd8: 0800f2c8 .word 0x0800f2c8 800bddc: 10624dd3 .word 0x10624dd3 800bde0: 48000400 .word 0x48000400 0800bde4 : #include "subghz_phy_app.h" #include "sys_app.h" #include "stm32_seq.h" void MX_SubGHz_Phy_Init(void) { 800bde4: b580 push {r7, lr} 800bde6: af00 add r7, sp, #0 SystemApp_Init(); 800bde8: f7f4 feb4 bl 8000b54 SubghzApp_Init(); 800bdec: f000 f80c bl 800be08 } 800bdf0: bf00 nop 800bdf2: bd80 pop {r7, pc} 0800bdf4 : void MX_SubGHz_Phy_Process(void) { 800bdf4: b580 push {r7, lr} 800bdf6: af00 add r7, sp, #0 SubghzApp_Process(); 800bdf8: f000 f846 bl 800be88 UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); 800bdfc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800be00: f001 fd26 bl 800d850 } 800be04: bf00 nop 800be06: bd80 pop {r7, pc} 0800be08 : static void App_ReconfigureUart(uint32_t baudrate); static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]); static char *App_SkipSpaces(char *s); void SubghzApp_Init(void) { 800be08: b580 push {r7, lr} 800be0a: af00 add r7, sp, #0 RadioEvents.TxDone = OnTxDone; 800be0c: 4b13 ldr r3, [pc, #76] @ (800be5c ) 800be0e: 4a14 ldr r2, [pc, #80] @ (800be60 ) 800be10: 601a str r2, [r3, #0] RadioEvents.RxDone = OnRxDone; 800be12: 4b12 ldr r3, [pc, #72] @ (800be5c ) 800be14: 4a13 ldr r2, [pc, #76] @ (800be64 ) 800be16: 609a str r2, [r3, #8] RadioEvents.TxTimeout = OnTxTimeout; 800be18: 4b10 ldr r3, [pc, #64] @ (800be5c ) 800be1a: 4a13 ldr r2, [pc, #76] @ (800be68 ) 800be1c: 605a str r2, [r3, #4] RadioEvents.RxTimeout = OnRxTimeout; 800be1e: 4b0f ldr r3, [pc, #60] @ (800be5c ) 800be20: 4a12 ldr r2, [pc, #72] @ (800be6c ) 800be22: 60da str r2, [r3, #12] RadioEvents.RxError = OnRxError; 800be24: 4b0d ldr r3, [pc, #52] @ (800be5c ) 800be26: 4a12 ldr r2, [pc, #72] @ (800be70 ) 800be28: 611a str r2, [r3, #16] Radio.Init(&RadioEvents); 800be2a: 4b12 ldr r3, [pc, #72] @ (800be74 ) 800be2c: 681b ldr r3, [r3, #0] 800be2e: 480b ldr r0, [pc, #44] @ (800be5c ) 800be30: 4798 blx r3 App_RadioApplyConfig(); 800be32: f000 f97d bl 800c130 App_RadioEnterRx(); 800be36: f000 fa2f bl 800c298 g_uart_last_data_tick = HAL_GetTick(); 800be3a: f7f4 ff05 bl 8000c48 800be3e: 4603 mov r3, r0 800be40: 4a0d ldr r2, [pc, #52] @ (800be78 ) 800be42: 6013 str r3, [r2, #0] (void)vcom_ReceiveInit(UartRxByteCallback); 800be44: 480d ldr r0, [pc, #52] @ (800be7c ) 800be46: f7f5 fbb1 bl 80015ac App_Printf("\r\nSTM32WL UART<->SUBGHZ bridge started\r\n"); 800be4a: 480d ldr r0, [pc, #52] @ (800be80 ) 800be4c: f000 ff98 bl 800cd80 App_Printf("DATA mode, escape sequence: silence 800 ms + +++ + silence 800 ms\r\n"); 800be50: 480c ldr r0, [pc, #48] @ (800be84 ) 800be52: f000 ff95 bl 800cd80 } 800be56: bf00 nop 800be58: bd80 pop {r7, pc} 800be5a: bf00 nop 800be5c: 200005f0 .word 0x200005f0 800be60: 0800cfad .word 0x0800cfad 800be64: 0800cfc5 .word 0x0800cfc5 800be68: 0800d029 .word 0x0800d029 800be6c: 0800d041 .word 0x0800d041 800be70: 0800d059 .word 0x0800d059 800be74: 0800fb7c .word 0x0800fb7c 800be78: 20000b50 .word 0x20000b50 800be7c: 0800c4e5 .word 0x0800c4e5 800be80: 0800f2fc .word 0x0800f2fc 800be84: 0800f328 .word 0x0800f328 0800be88 : void SubghzApp_Process(void) { 800be88: b580 push {r7, lr} 800be8a: af00 add r7, sp, #0 App_ProcessEscape(); 800be8c: f000 f8c6 bl 800c01c App_ProcessUartPacketizer(); 800be90: f000 f898 bl 800bfc4 App_ProcessRadioEvents(); 800be94: f000 f804 bl 800bea0 App_StartNextTxIfPossible(); 800be98: f000 f910 bl 800c0bc } 800be9c: bf00 nop 800be9e: bd80 pop {r7, pc} 0800bea0 : static void App_ProcessRadioEvents(void) { 800bea0: b580 push {r7, lr} 800bea2: af00 add r7, sp, #0 if (g_radio_tx_done != 0U) 800bea4: 4b38 ldr r3, [pc, #224] @ (800bf88 ) 800bea6: 781b ldrb r3, [r3, #0] 800bea8: b2db uxtb r3, r3 800beaa: 2b00 cmp r3, #0 800beac: d00f beq.n 800bece { g_radio_tx_done = 0U; 800beae: 4b36 ldr r3, [pc, #216] @ (800bf88 ) 800beb0: 2200 movs r2, #0 800beb2: 701a strb r2, [r3, #0] g_radio_busy = 0U; 800beb4: 4b35 ldr r3, [pc, #212] @ (800bf8c ) 800beb6: 2200 movs r2, #0 800beb8: 701a strb r2, [r3, #0] g_stat_uart_packets_tx++; 800beba: 4b35 ldr r3, [pc, #212] @ (800bf90 ) 800bebc: 681b ldr r3, [r3, #0] 800bebe: 3301 adds r3, #1 800bec0: 4a33 ldr r2, [pc, #204] @ (800bf90 ) 800bec2: 6013 str r3, [r2, #0] App_QueuePop(); 800bec4: f000 faf0 bl 800c4a8 g_radio_needs_rx_restart = 1U; 800bec8: 4b32 ldr r3, [pc, #200] @ (800bf94 ) 800beca: 2201 movs r2, #1 800becc: 701a strb r2, [r3, #0] } if (g_radio_tx_timeout != 0U) 800bece: 4b32 ldr r3, [pc, #200] @ (800bf98 ) 800bed0: 781b ldrb r3, [r3, #0] 800bed2: b2db uxtb r3, r3 800bed4: 2b00 cmp r3, #0 800bed6: d00d beq.n 800bef4 { g_radio_tx_timeout = 0U; 800bed8: 4b2f ldr r3, [pc, #188] @ (800bf98 ) 800beda: 2200 movs r2, #0 800bedc: 701a strb r2, [r3, #0] g_radio_busy = 0U; 800bede: 4b2b ldr r3, [pc, #172] @ (800bf8c ) 800bee0: 2200 movs r2, #0 800bee2: 701a strb r2, [r3, #0] App_QueuePop(); 800bee4: f000 fae0 bl 800c4a8 App_Printf("\r\n[WARN] radio tx timeout\r\n"); 800bee8: 482c ldr r0, [pc, #176] @ (800bf9c ) 800beea: f000 ff49 bl 800cd80 g_radio_needs_rx_restart = 1U; 800beee: 4b29 ldr r3, [pc, #164] @ (800bf94 ) 800bef0: 2201 movs r2, #1 800bef2: 701a strb r2, [r3, #0] } if (g_radio_rx_done != 0U) 800bef4: 4b2a ldr r3, [pc, #168] @ (800bfa0 ) 800bef6: 781b ldrb r3, [r3, #0] 800bef8: b2db uxtb r3, r3 800befa: 2b00 cmp r3, #0 800befc: d01c beq.n 800bf38 { g_radio_rx_done = 0U; 800befe: 4b28 ldr r3, [pc, #160] @ (800bfa0 ) 800bf00: 2200 movs r2, #0 800bf02: 701a strb r2, [r3, #0] g_stat_radio_packets_rx++; 800bf04: 4b27 ldr r3, [pc, #156] @ (800bfa4 ) 800bf06: 681b ldr r3, [r3, #0] 800bf08: 3301 adds r3, #1 800bf0a: 4a26 ldr r2, [pc, #152] @ (800bfa4 ) 800bf0c: 6013 str r3, [r2, #0] g_stat_radio_bytes_rx += g_rx_payload_len; 800bf0e: 4b26 ldr r3, [pc, #152] @ (800bfa8 ) 800bf10: 881b ldrh r3, [r3, #0] 800bf12: 461a mov r2, r3 800bf14: 4b25 ldr r3, [pc, #148] @ (800bfac ) 800bf16: 681b ldr r3, [r3, #0] 800bf18: 4413 add r3, r2 800bf1a: 4a24 ldr r2, [pc, #144] @ (800bfac ) 800bf1c: 6013 str r3, [r2, #0] if (g_mode == APP_MODE_DATA) 800bf1e: 4b24 ldr r3, [pc, #144] @ (800bfb0 ) 800bf20: 781b ldrb r3, [r3, #0] 800bf22: 2b00 cmp r3, #0 800bf24: d105 bne.n 800bf32 { App_Write(g_rx_payload, g_rx_payload_len); 800bf26: 4b20 ldr r3, [pc, #128] @ (800bfa8 ) 800bf28: 881b ldrh r3, [r3, #0] 800bf2a: 4619 mov r1, r3 800bf2c: 4821 ldr r0, [pc, #132] @ (800bfb4 ) 800bf2e: f000 ff53 bl 800cdd8 } g_radio_needs_rx_restart = 1U; 800bf32: 4b18 ldr r3, [pc, #96] @ (800bf94 ) 800bf34: 2201 movs r2, #1 800bf36: 701a strb r2, [r3, #0] } if ((g_radio_rx_timeout != 0U) || (g_radio_rx_error != 0U)) 800bf38: 4b1f ldr r3, [pc, #124] @ (800bfb8 ) 800bf3a: 781b ldrb r3, [r3, #0] 800bf3c: b2db uxtb r3, r3 800bf3e: 2b00 cmp r3, #0 800bf40: d104 bne.n 800bf4c 800bf42: 4b1e ldr r3, [pc, #120] @ (800bfbc ) 800bf44: 781b ldrb r3, [r3, #0] 800bf46: b2db uxtb r3, r3 800bf48: 2b00 cmp r3, #0 800bf4a: d008 beq.n 800bf5e { g_radio_rx_timeout = 0U; 800bf4c: 4b1a ldr r3, [pc, #104] @ (800bfb8 ) 800bf4e: 2200 movs r2, #0 800bf50: 701a strb r2, [r3, #0] g_radio_rx_error = 0U; 800bf52: 4b1a ldr r3, [pc, #104] @ (800bfbc ) 800bf54: 2200 movs r2, #0 800bf56: 701a strb r2, [r3, #0] g_radio_needs_rx_restart = 1U; 800bf58: 4b0e ldr r3, [pc, #56] @ (800bf94 ) 800bf5a: 2201 movs r2, #1 800bf5c: 701a strb r2, [r3, #0] } if ((g_radio_needs_rx_restart != 0U) && (g_radio_busy == 0U) && (g_tx_q_count == 0U)) 800bf5e: 4b0d ldr r3, [pc, #52] @ (800bf94 ) 800bf60: 781b ldrb r3, [r3, #0] 800bf62: b2db uxtb r3, r3 800bf64: 2b00 cmp r3, #0 800bf66: d00d beq.n 800bf84 800bf68: 4b08 ldr r3, [pc, #32] @ (800bf8c ) 800bf6a: 781b ldrb r3, [r3, #0] 800bf6c: b2db uxtb r3, r3 800bf6e: 2b00 cmp r3, #0 800bf70: d108 bne.n 800bf84 800bf72: 4b13 ldr r3, [pc, #76] @ (800bfc0 ) 800bf74: 781b ldrb r3, [r3, #0] 800bf76: 2b00 cmp r3, #0 800bf78: d104 bne.n 800bf84 { g_radio_needs_rx_restart = 0U; 800bf7a: 4b06 ldr r3, [pc, #24] @ (800bf94 ) 800bf7c: 2200 movs r2, #0 800bf7e: 701a strb r2, [r3, #0] App_RadioEnterRx(); 800bf80: f000 f98a bl 800c298 } } 800bf84: bf00 nop 800bf86: bd80 pop {r7, pc} 800bf88: 2000060c .word 0x2000060c 800bf8c: 20000615 .word 0x20000615 800bf90: 20000bcc .word 0x20000bcc 800bf94: 20000616 .word 0x20000616 800bf98: 2000060d .word 0x2000060d 800bf9c: 0800f36c .word 0x0800f36c 800bfa0: 2000060e .word 0x2000060e 800bfa4: 20000bd4 .word 0x20000bd4 800bfa8: 200006f4 .word 0x200006f4 800bfac: 20000bd8 .word 0x20000bd8 800bfb0: 20000b64 .word 0x20000b64 800bfb4: 20000618 .word 0x20000618 800bfb8: 2000060f .word 0x2000060f 800bfbc: 20000610 .word 0x20000610 800bfc0: 20000a6e .word 0x20000a6e 0800bfc4 : static void App_ProcessUartPacketizer(void) { 800bfc4: b580 push {r7, lr} 800bfc6: b082 sub sp, #8 800bfc8: af00 add r7, sp, #0 uint32_t now = HAL_GetTick(); 800bfca: f7f4 fe3d bl 8000c48 800bfce: 6078 str r0, [r7, #4] if (g_mode != APP_MODE_DATA) 800bfd0: 4b0d ldr r3, [pc, #52] @ (800c008 ) 800bfd2: 781b ldrb r3, [r3, #0] 800bfd4: 2b00 cmp r3, #0 800bfd6: d112 bne.n 800bffe { return; } if ((g_uart_build_len > 0U) && 800bfd8: 4b0c ldr r3, [pc, #48] @ (800c00c ) 800bfda: 881b ldrh r3, [r3, #0] 800bfdc: 2b00 cmp r3, #0 800bfde: d00f beq.n 800c000 ((now - g_uart_last_data_tick) >= g_cfg.uart_packet_timeout_ms) && 800bfe0: 4b0b ldr r3, [pc, #44] @ (800c010 ) 800bfe2: 681b ldr r3, [r3, #0] 800bfe4: 687a ldr r2, [r7, #4] 800bfe6: 1ad3 subs r3, r2, r3 800bfe8: 4a0a ldr r2, [pc, #40] @ (800c014 ) 800bfea: 8b52 ldrh r2, [r2, #26] if ((g_uart_build_len > 0U) && 800bfec: 4293 cmp r3, r2 800bfee: d307 bcc.n 800c000 (g_escape.active == 0U)) 800bff0: 4b09 ldr r3, [pc, #36] @ (800c018 ) 800bff2: 781b ldrb r3, [r3, #0] ((now - g_uart_last_data_tick) >= g_cfg.uart_packet_timeout_ms) && 800bff4: 2b00 cmp r3, #0 800bff6: d103 bne.n 800c000 { App_DataModeFlushBuilder(); 800bff8: f000 f9f0 bl 800c3dc 800bffc: e000 b.n 800c000 return; 800bffe: bf00 nop } } 800c000: 3708 adds r7, #8 800c002: 46bd mov sp, r7 800c004: bd80 pop {r7, pc} 800c006: bf00 nop 800c008: 20000b64 .word 0x20000b64 800c00c: 20000b4c .word 0x20000b4c 800c010: 20000b50 .word 0x20000b50 800c014: 2000000c .word 0x2000000c 800c018: 20000b54 .word 0x20000b54 0800c01c : static void App_ProcessEscape(void) { 800c01c: b580 push {r7, lr} 800c01e: b082 sub sp, #8 800c020: af00 add r7, sp, #0 uint32_t now = HAL_GetTick(); 800c022: f7f4 fe11 bl 8000c48 800c026: 6038 str r0, [r7, #0] uint8_t i; if ((g_mode != APP_MODE_DATA) || (g_escape.active == 0U)) 800c028: 4b22 ldr r3, [pc, #136] @ (800c0b4 ) 800c02a: 781b ldrb r3, [r3, #0] 800c02c: 2b00 cmp r3, #0 800c02e: d13c bne.n 800c0aa 800c030: 4b21 ldr r3, [pc, #132] @ (800c0b8 ) 800c032: 781b ldrb r3, [r3, #0] 800c034: 2b00 cmp r3, #0 800c036: d038 beq.n 800c0aa { return; } if ((g_escape.count == 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) 800c038: 4b1f ldr r3, [pc, #124] @ (800c0b8 ) 800c03a: 785b ldrb r3, [r3, #1] 800c03c: 2b03 cmp r3, #3 800c03e: d10f bne.n 800c060 800c040: 4b1d ldr r3, [pc, #116] @ (800c0b8 ) 800c042: 68db ldr r3, [r3, #12] 800c044: 683a ldr r2, [r7, #0] 800c046: 1ad3 subs r3, r2, r3 800c048: f5b3 7f48 cmp.w r3, #800 @ 0x320 800c04c: d308 bcc.n 800c060 { g_escape.active = 0U; 800c04e: 4b1a ldr r3, [pc, #104] @ (800c0b8 ) 800c050: 2200 movs r2, #0 800c052: 701a strb r2, [r3, #0] g_escape.count = 0U; 800c054: 4b18 ldr r3, [pc, #96] @ (800c0b8 ) 800c056: 2200 movs r2, #0 800c058: 705a strb r2, [r3, #1] App_EnterConfigMode(); 800c05a: f000 f929 bl 800c2b0 return; 800c05e: e025 b.n 800c0ac } if ((g_escape.count < 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) 800c060: 4b15 ldr r3, [pc, #84] @ (800c0b8 ) 800c062: 785b ldrb r3, [r3, #1] 800c064: 2b02 cmp r3, #2 800c066: d821 bhi.n 800c0ac 800c068: 4b13 ldr r3, [pc, #76] @ (800c0b8 ) 800c06a: 68db ldr r3, [r3, #12] 800c06c: 683a ldr r2, [r7, #0] 800c06e: 1ad3 subs r3, r2, r3 800c070: f5b3 7f48 cmp.w r3, #800 @ 0x320 800c074: d31a bcc.n 800c0ac { for (i = 0U; i < g_escape.count; i++) 800c076: 2300 movs r3, #0 800c078: 71fb strb r3, [r7, #7] 800c07a: e00a b.n 800c092 { App_DataModeFeedByte(g_escape.bytes[i], now); 800c07c: 79fb ldrb r3, [r7, #7] 800c07e: 4a0e ldr r2, [pc, #56] @ (800c0b8 ) 800c080: 4413 add r3, r2 800c082: 789b ldrb r3, [r3, #2] 800c084: 6839 ldr r1, [r7, #0] 800c086: 4618 mov r0, r3 800c088: f000 f966 bl 800c358 for (i = 0U; i < g_escape.count; i++) 800c08c: 79fb ldrb r3, [r7, #7] 800c08e: 3301 adds r3, #1 800c090: 71fb strb r3, [r7, #7] 800c092: 4b09 ldr r3, [pc, #36] @ (800c0b8 ) 800c094: 785b ldrb r3, [r3, #1] 800c096: 79fa ldrb r2, [r7, #7] 800c098: 429a cmp r2, r3 800c09a: d3ef bcc.n 800c07c } g_escape.active = 0U; 800c09c: 4b06 ldr r3, [pc, #24] @ (800c0b8 ) 800c09e: 2200 movs r2, #0 800c0a0: 701a strb r2, [r3, #0] g_escape.count = 0U; 800c0a2: 4b05 ldr r3, [pc, #20] @ (800c0b8 ) 800c0a4: 2200 movs r2, #0 800c0a6: 705a strb r2, [r3, #1] 800c0a8: e000 b.n 800c0ac return; 800c0aa: bf00 nop } } 800c0ac: 3708 adds r7, #8 800c0ae: 46bd mov sp, r7 800c0b0: bd80 pop {r7, pc} 800c0b2: bf00 nop 800c0b4: 20000b64 .word 0x20000b64 800c0b8: 20000b54 .word 0x20000b54 0800c0bc : static void App_StartNextTxIfPossible(void) { 800c0bc: b598 push {r3, r4, r7, lr} 800c0be: af00 add r7, sp, #0 if ((g_mode != APP_MODE_DATA) || (g_radio_busy != 0U) || (g_tx_q_count == 0U)) 800c0c0: 4b15 ldr r3, [pc, #84] @ (800c118 ) 800c0c2: 781b ldrb r3, [r3, #0] 800c0c4: 2b00 cmp r3, #0 800c0c6: d124 bne.n 800c112 800c0c8: 4b14 ldr r3, [pc, #80] @ (800c11c ) 800c0ca: 781b ldrb r3, [r3, #0] 800c0cc: b2db uxtb r3, r3 800c0ce: 2b00 cmp r3, #0 800c0d0: d11f bne.n 800c112 800c0d2: 4b13 ldr r3, [pc, #76] @ (800c120 ) 800c0d4: 781b ldrb r3, [r3, #0] 800c0d6: 2b00 cmp r3, #0 800c0d8: d01b beq.n 800c112 { return; } App_RadioConfigureTx(); 800c0da: f000 f891 bl 800c200 g_radio_busy = 1U; 800c0de: 4b0f ldr r3, [pc, #60] @ (800c11c ) 800c0e0: 2201 movs r2, #1 800c0e2: 701a strb r2, [r3, #0] (void)Radio.Send(g_tx_queue[g_tx_q_head].data, g_tx_queue[g_tx_q_head].len); 800c0e4: 4b0f ldr r3, [pc, #60] @ (800c124 ) 800c0e6: 6a9b ldr r3, [r3, #40] @ 0x28 800c0e8: 4a0f ldr r2, [pc, #60] @ (800c128 ) 800c0ea: 7812 ldrb r2, [r2, #0] 800c0ec: 4611 mov r1, r2 800c0ee: 22dd movs r2, #221 @ 0xdd 800c0f0: fb01 f202 mul.w r2, r1, r2 800c0f4: 490d ldr r1, [pc, #52] @ (800c12c ) 800c0f6: 1850 adds r0, r2, r1 800c0f8: 4a0b ldr r2, [pc, #44] @ (800c128 ) 800c0fa: 7812 ldrb r2, [r2, #0] 800c0fc: 4614 mov r4, r2 800c0fe: 490b ldr r1, [pc, #44] @ (800c12c ) 800c100: 22dd movs r2, #221 @ 0xdd 800c102: fb04 f202 mul.w r2, r4, r2 800c106: 440a add r2, r1 800c108: 32dc adds r2, #220 @ 0xdc 800c10a: 7812 ldrb r2, [r2, #0] 800c10c: 4611 mov r1, r2 800c10e: 4798 blx r3 800c110: e000 b.n 800c114 return; 800c112: bf00 nop } 800c114: bd98 pop {r3, r4, r7, pc} 800c116: bf00 nop 800c118: 20000b64 .word 0x20000b64 800c11c: 20000615 .word 0x20000615 800c120: 20000a6e .word 0x20000a6e 800c124: 0800fb7c .word 0x0800fb7c 800c128: 20000a6c .word 0x20000a6c 800c12c: 200006f8 .word 0x200006f8 0800c130 : static void App_RadioApplyConfig(void) { 800c130: b580 push {r7, lr} 800c132: af00 add r7, sp, #0 Radio.SetChannel(g_cfg.rf_frequency); 800c134: 4b05 ldr r3, [pc, #20] @ (800c14c ) 800c136: 68db ldr r3, [r3, #12] 800c138: 4a05 ldr r2, [pc, #20] @ (800c150 ) 800c13a: 6812 ldr r2, [r2, #0] 800c13c: 4610 mov r0, r2 800c13e: 4798 blx r3 g_radio_needs_rx_restart = 1U; 800c140: 4b04 ldr r3, [pc, #16] @ (800c154 ) 800c142: 2201 movs r2, #1 800c144: 701a strb r2, [r3, #0] } 800c146: bf00 nop 800c148: bd80 pop {r7, pc} 800c14a: bf00 nop 800c14c: 0800fb7c .word 0x0800fb7c 800c150: 2000000c .word 0x2000000c 800c154: 20000616 .word 0x20000616 0800c158 : static void App_RadioConfigureRx(void) { 800c158: b590 push {r4, r7, lr} 800c15a: b08f sub sp, #60 @ 0x3c 800c15c: af00 add r7, sp, #0 RxConfigGeneric_t rx = {0}; 800c15e: 463b mov r3, r7 800c160: 2238 movs r2, #56 @ 0x38 800c162: 2100 movs r1, #0 800c164: 4618 mov r0, r3 800c166: f002 fb0f bl 800e788 Radio.SetChannel(g_cfg.rf_frequency); 800c16a: 4b22 ldr r3, [pc, #136] @ (800c1f4 ) 800c16c: 68db ldr r3, [r3, #12] 800c16e: 4a22 ldr r2, [pc, #136] @ (800c1f8 ) 800c170: 6812 ldr r2, [r2, #0] 800c172: 4610 mov r0, r2 800c174: 4798 blx r3 rx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; 800c176: 2309 movs r3, #9 800c178: f887 3020 strb.w r3, [r7, #32] rx.fsk.Bandwidth = g_cfg.fsk_bandwidth; 800c17c: 4b1e ldr r3, [pc, #120] @ (800c1f8 ) 800c17e: 68db ldr r3, [r3, #12] 800c180: 607b str r3, [r7, #4] rx.fsk.BitRate = g_cfg.fsk_bitrate; 800c182: 4b1d ldr r3, [pc, #116] @ (800c1f8 ) 800c184: 689b ldr r3, [r3, #8] 800c186: 60bb str r3, [r7, #8] rx.fsk.PreambleLen = g_cfg.fsk_preamble_len; 800c188: 4b1b ldr r3, [pc, #108] @ (800c1f8 ) 800c18a: 8a9b ldrh r3, [r3, #20] 800c18c: 60fb str r3, [r7, #12] rx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; 800c18e: 2303 movs r3, #3 800c190: 77bb strb r3, [r7, #30] rx.fsk.PreambleMinDetect = RADIO_FSK_PREAMBLE_DETECTOR_08_BITS; 800c192: 2304 movs r3, #4 800c194: 77fb strb r3, [r7, #31] rx.fsk.SyncWord = g_cfg.syncword; 800c196: 4b19 ldr r3, [pc, #100] @ (800c1fc ) 800c198: 613b str r3, [r7, #16] rx.fsk.whiteSeed = RADIO_WHITENING_SEED; 800c19a: f240 13ff movw r3, #511 @ 0x1ff 800c19e: 83bb strh r3, [r7, #28] rx.fsk.LengthMode = RADIO_FSK_PACKET_VARIABLE_LENGTH; 800c1a0: 2301 movs r3, #1 800c1a2: f887 3022 strb.w r3, [r7, #34] @ 0x22 rx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; 800c1a6: 23f1 movs r3, #241 @ 0xf1 800c1a8: f887 3023 strb.w r3, [r7, #35] @ 0x23 rx.fsk.CrcPolynomial = RADIO_CRC_POLY; 800c1ac: f248 0305 movw r3, #32773 @ 0x8005 800c1b0: 833b strh r3, [r7, #24] rx.fsk.CrcSeed = RADIO_CRC_SEED; 800c1b2: f64f 73ff movw r3, #65535 @ 0xffff 800c1b6: 837b strh r3, [r7, #26] rx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; 800c1b8: 2301 movs r3, #1 800c1ba: f887 3024 strb.w r3, [r7, #36] @ 0x24 rx.fsk.MaxPayloadLength = RADIO_MAX_PAYLOAD_SIZE; 800c1be: 23dc movs r3, #220 @ 0xdc 800c1c0: 617b str r3, [r7, #20] rx.fsk.StopTimerOnPreambleDetect = 0; 800c1c2: 2300 movs r3, #0 800c1c4: 603b str r3, [r7, #0] rx.fsk.AddrComp = RADIO_FSK_ADDRESSCOMP_FILT_OFF; 800c1c6: 2300 movs r3, #0 800c1c8: f887 3021 strb.w r3, [r7, #33] @ 0x21 Radio.Standby(); 800c1cc: 4b09 ldr r3, [pc, #36] @ (800c1f4 ) 800c1ce: 6b1b ldr r3, [r3, #48] @ 0x30 800c1d0: 4798 blx r3 if (0UL != Radio.RadioSetRxGenericConfig(GENERIC_FSK, &rx, RX_CONTINUOUS_ON, 0U)) 800c1d2: 4b08 ldr r3, [pc, #32] @ (800c1f4 ) 800c1d4: 6f5c ldr r4, [r3, #116] @ 0x74 800c1d6: 4639 mov r1, r7 800c1d8: 2300 movs r3, #0 800c1da: 2201 movs r2, #1 800c1dc: 2000 movs r0, #0 800c1de: 47a0 blx r4 800c1e0: 4603 mov r3, r0 800c1e2: 2b00 cmp r3, #0 800c1e4: d001 beq.n 800c1ea { Error_Handler(); 800c1e6: f7f4 faf3 bl 80007d0 } } 800c1ea: bf00 nop 800c1ec: 373c adds r7, #60 @ 0x3c 800c1ee: 46bd mov sp, r7 800c1f0: bd90 pop {r4, r7, pc} 800c1f2: bf00 nop 800c1f4: 0800fb7c .word 0x0800fb7c 800c1f8: 2000000c .word 0x2000000c 800c1fc: 20000022 .word 0x20000022 0800c200 : static void App_RadioConfigureTx(void) { 800c200: b590 push {r4, r7, lr} 800c202: b089 sub sp, #36 @ 0x24 800c204: af00 add r7, sp, #0 TxConfigGeneric_t tx = {0}; 800c206: 1d3b adds r3, r7, #4 800c208: 2200 movs r2, #0 800c20a: 601a str r2, [r3, #0] 800c20c: 605a str r2, [r3, #4] 800c20e: 609a str r2, [r3, #8] 800c210: 60da str r2, [r3, #12] 800c212: 611a str r2, [r3, #16] 800c214: 615a str r2, [r3, #20] 800c216: 619a str r2, [r3, #24] Radio.SetChannel(g_cfg.rf_frequency); 800c218: 4b1c ldr r3, [pc, #112] @ (800c28c ) 800c21a: 68db ldr r3, [r3, #12] 800c21c: 4a1c ldr r2, [pc, #112] @ (800c290 ) 800c21e: 6812 ldr r2, [r2, #0] 800c220: 4610 mov r0, r2 800c222: 4798 blx r3 tx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; 800c224: 2309 movs r3, #9 800c226: 75fb strb r3, [r7, #23] tx.fsk.FrequencyDeviation = g_cfg.fsk_fdev; 800c228: 4b19 ldr r3, [pc, #100] @ (800c290 ) 800c22a: 691b ldr r3, [r3, #16] 800c22c: 61fb str r3, [r7, #28] tx.fsk.BitRate = g_cfg.fsk_bitrate; 800c22e: 4b18 ldr r3, [pc, #96] @ (800c290 ) 800c230: 689b ldr r3, [r3, #8] 800c232: 607b str r3, [r7, #4] tx.fsk.PreambleLen = g_cfg.fsk_preamble_len; 800c234: 4b16 ldr r3, [pc, #88] @ (800c290 ) 800c236: 8a9b ldrh r3, [r3, #20] 800c238: 60bb str r3, [r7, #8] tx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; 800c23a: 2303 movs r3, #3 800c23c: 75bb strb r3, [r7, #22] tx.fsk.SyncWord = g_cfg.syncword; 800c23e: 4b15 ldr r3, [pc, #84] @ (800c294 ) 800c240: 60fb str r3, [r7, #12] tx.fsk.whiteSeed = RADIO_WHITENING_SEED; 800c242: f240 13ff movw r3, #511 @ 0x1ff 800c246: 82bb strh r3, [r7, #20] tx.fsk.HeaderType = RADIO_FSK_PACKET_VARIABLE_LENGTH; 800c248: 2301 movs r3, #1 800c24a: 763b strb r3, [r7, #24] tx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; 800c24c: 23f1 movs r3, #241 @ 0xf1 800c24e: 767b strb r3, [r7, #25] tx.fsk.CrcPolynomial = RADIO_CRC_POLY; 800c250: f248 0305 movw r3, #32773 @ 0x8005 800c254: 823b strh r3, [r7, #16] tx.fsk.CrcSeed = RADIO_CRC_SEED; 800c256: f64f 73ff movw r3, #65535 @ 0xffff 800c25a: 827b strh r3, [r7, #18] tx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; 800c25c: 2301 movs r3, #1 800c25e: 76bb strb r3, [r7, #26] Radio.Standby(); 800c260: 4b0a ldr r3, [pc, #40] @ (800c28c ) 800c262: 6b1b ldr r3, [r3, #48] @ 0x30 800c264: 4798 blx r3 if (0UL != Radio.RadioSetTxGenericConfig(GENERIC_FSK, &tx, g_cfg.tx_power, TX_TIMEOUT_VALUE_MS)) 800c266: 4b09 ldr r3, [pc, #36] @ (800c28c ) 800c268: 6f9c ldr r4, [r3, #120] @ 0x78 800c26a: 4b09 ldr r3, [pc, #36] @ (800c290 ) 800c26c: f993 2004 ldrsb.w r2, [r3, #4] 800c270: 1d39 adds r1, r7, #4 800c272: f640 33b8 movw r3, #3000 @ 0xbb8 800c276: 2000 movs r0, #0 800c278: 47a0 blx r4 800c27a: 4603 mov r3, r0 800c27c: 2b00 cmp r3, #0 800c27e: d001 beq.n 800c284 { Error_Handler(); 800c280: f7f4 faa6 bl 80007d0 } } 800c284: bf00 nop 800c286: 3724 adds r7, #36 @ 0x24 800c288: 46bd mov sp, r7 800c28a: bd90 pop {r4, r7, pc} 800c28c: 0800fb7c .word 0x0800fb7c 800c290: 2000000c .word 0x2000000c 800c294: 20000022 .word 0x20000022 0800c298 : static void App_RadioEnterRx(void) { 800c298: b580 push {r7, lr} 800c29a: af00 add r7, sp, #0 App_RadioConfigureRx(); 800c29c: f7ff ff5c bl 800c158 Radio.Rx(RX_TIMEOUT_VALUE_MS); 800c2a0: 4b02 ldr r3, [pc, #8] @ (800c2ac ) 800c2a2: 6b5b ldr r3, [r3, #52] @ 0x34 800c2a4: 2000 movs r0, #0 800c2a6: 4798 blx r3 } 800c2a8: bf00 nop 800c2aa: bd80 pop {r7, pc} 800c2ac: 0800fb7c .word 0x0800fb7c 0800c2b0 : static void App_EnterConfigMode(void) { 800c2b0: b580 push {r7, lr} 800c2b2: af00 add r7, sp, #0 App_ResetDataPath(); 800c2b4: f000 f82e bl 800c314 g_mode = APP_MODE_CONFIG; 800c2b8: 4b06 ldr r3, [pc, #24] @ (800c2d4 ) 800c2ba: 2201 movs r2, #1 800c2bc: 701a strb r2, [r3, #0] App_Printf("\r\n\r\n[CONFIG MODE]\r\n"); 800c2be: 4806 ldr r0, [pc, #24] @ (800c2d8 ) 800c2c0: f000 fd5e bl 800cd80 App_Printf("type 'help' for commands\r\n"); 800c2c4: 4805 ldr r0, [pc, #20] @ (800c2dc ) 800c2c6: f000 fd5b bl 800cd80 App_PrintConfigPrompt(); 800c2ca: f000 fc45 bl 800cb58 } 800c2ce: bf00 nop 800c2d0: bd80 pop {r7, pc} 800c2d2: bf00 nop 800c2d4: 20000b64 .word 0x20000b64 800c2d8: 0800f388 .word 0x0800f388 800c2dc: 0800f39c .word 0x0800f39c 0800c2e0 : static void App_ExitConfigMode(void) { 800c2e0: b580 push {r7, lr} 800c2e2: af00 add r7, sp, #0 g_cfg_line_len = 0U; 800c2e4: 4b07 ldr r3, [pc, #28] @ (800c304 ) 800c2e6: 2200 movs r2, #0 800c2e8: 801a strh r2, [r3, #0] App_ResetDataPath(); 800c2ea: f000 f813 bl 800c314 g_mode = APP_MODE_DATA; 800c2ee: 4b06 ldr r3, [pc, #24] @ (800c308 ) 800c2f0: 2200 movs r2, #0 800c2f2: 701a strb r2, [r3, #0] App_Printf("\r\n[DATA MODE]\r\n"); 800c2f4: 4805 ldr r0, [pc, #20] @ (800c30c ) 800c2f6: f000 fd43 bl 800cd80 g_radio_needs_rx_restart = 1U; 800c2fa: 4b05 ldr r3, [pc, #20] @ (800c310 ) 800c2fc: 2201 movs r2, #1 800c2fe: 701a strb r2, [r3, #0] } 800c300: bf00 nop 800c302: bd80 pop {r7, pc} 800c304: 20000bc8 .word 0x20000bc8 800c308: 20000b64 .word 0x20000b64 800c30c: 0800f3b8 .word 0x0800f3b8 800c310: 20000616 .word 0x20000616 0800c314 : static void App_ResetDataPath(void) { 800c314: b480 push {r7} 800c316: af00 add r7, sp, #0 g_uart_build_len = 0U; 800c318: 4b0a ldr r3, [pc, #40] @ (800c344 ) 800c31a: 2200 movs r2, #0 800c31c: 801a strh r2, [r3, #0] g_escape.active = 0U; 800c31e: 4b0a ldr r3, [pc, #40] @ (800c348 ) 800c320: 2200 movs r2, #0 800c322: 701a strb r2, [r3, #0] g_escape.count = 0U; 800c324: 4b08 ldr r3, [pc, #32] @ (800c348 ) 800c326: 2200 movs r2, #0 800c328: 705a strb r2, [r3, #1] g_tx_q_head = 0U; 800c32a: 4b08 ldr r3, [pc, #32] @ (800c34c ) 800c32c: 2200 movs r2, #0 800c32e: 701a strb r2, [r3, #0] g_tx_q_tail = 0U; 800c330: 4b07 ldr r3, [pc, #28] @ (800c350 ) 800c332: 2200 movs r2, #0 800c334: 701a strb r2, [r3, #0] g_tx_q_count = 0U; 800c336: 4b07 ldr r3, [pc, #28] @ (800c354 ) 800c338: 2200 movs r2, #0 800c33a: 701a strb r2, [r3, #0] } 800c33c: bf00 nop 800c33e: 46bd mov sp, r7 800c340: bc80 pop {r7} 800c342: 4770 bx lr 800c344: 20000b4c .word 0x20000b4c 800c348: 20000b54 .word 0x20000b54 800c34c: 20000a6c .word 0x20000a6c 800c350: 20000a6d .word 0x20000a6d 800c354: 20000a6e .word 0x20000a6e 0800c358 : static void App_DataModeFeedByte(uint8_t ch, uint32_t now) { 800c358: b580 push {r7, lr} 800c35a: b082 sub sp, #8 800c35c: af00 add r7, sp, #0 800c35e: 4603 mov r3, r0 800c360: 6039 str r1, [r7, #0] 800c362: 71fb strb r3, [r7, #7] if (g_uart_build_len < UART_DATA_BUFFER_SIZE) 800c364: 4b19 ldr r3, [pc, #100] @ (800c3cc ) 800c366: 881b ldrh r3, [r3, #0] 800c368: 2bdb cmp r3, #219 @ 0xdb 800c36a: d812 bhi.n 800c392 { g_uart_build_buf[g_uart_build_len++] = ch; 800c36c: 4b17 ldr r3, [pc, #92] @ (800c3cc ) 800c36e: 881b ldrh r3, [r3, #0] 800c370: 1c5a adds r2, r3, #1 800c372: b291 uxth r1, r2 800c374: 4a15 ldr r2, [pc, #84] @ (800c3cc ) 800c376: 8011 strh r1, [r2, #0] 800c378: 4619 mov r1, r3 800c37a: 4a15 ldr r2, [pc, #84] @ (800c3d0 ) 800c37c: 79fb ldrb r3, [r7, #7] 800c37e: 5453 strb r3, [r2, r1] g_uart_last_data_tick = now; 800c380: 4a14 ldr r2, [pc, #80] @ (800c3d4 ) 800c382: 683b ldr r3, [r7, #0] 800c384: 6013 str r3, [r2, #0] g_stat_uart_bytes_tx++; 800c386: 4b14 ldr r3, [pc, #80] @ (800c3d8 ) 800c388: 681b ldr r3, [r3, #0] 800c38a: 3301 adds r3, #1 800c38c: 4a12 ldr r2, [pc, #72] @ (800c3d8 ) 800c38e: 6013 str r3, [r2, #0] g_uart_build_buf[g_uart_build_len++] = ch; g_uart_last_data_tick = now; g_stat_uart_bytes_tx++; } } } 800c390: e017 b.n 800c3c2 App_DataModeFlushBuilder(); 800c392: f000 f823 bl 800c3dc if (g_uart_build_len < UART_DATA_BUFFER_SIZE) 800c396: 4b0d ldr r3, [pc, #52] @ (800c3cc ) 800c398: 881b ldrh r3, [r3, #0] 800c39a: 2bdb cmp r3, #219 @ 0xdb 800c39c: d811 bhi.n 800c3c2 g_uart_build_buf[g_uart_build_len++] = ch; 800c39e: 4b0b ldr r3, [pc, #44] @ (800c3cc ) 800c3a0: 881b ldrh r3, [r3, #0] 800c3a2: 1c5a adds r2, r3, #1 800c3a4: b291 uxth r1, r2 800c3a6: 4a09 ldr r2, [pc, #36] @ (800c3cc ) 800c3a8: 8011 strh r1, [r2, #0] 800c3aa: 4619 mov r1, r3 800c3ac: 4a08 ldr r2, [pc, #32] @ (800c3d0 ) 800c3ae: 79fb ldrb r3, [r7, #7] 800c3b0: 5453 strb r3, [r2, r1] g_uart_last_data_tick = now; 800c3b2: 4a08 ldr r2, [pc, #32] @ (800c3d4 ) 800c3b4: 683b ldr r3, [r7, #0] 800c3b6: 6013 str r3, [r2, #0] g_stat_uart_bytes_tx++; 800c3b8: 4b07 ldr r3, [pc, #28] @ (800c3d8 ) 800c3ba: 681b ldr r3, [r3, #0] 800c3bc: 3301 adds r3, #1 800c3be: 4a06 ldr r2, [pc, #24] @ (800c3d8 ) 800c3c0: 6013 str r3, [r2, #0] } 800c3c2: bf00 nop 800c3c4: 3708 adds r7, #8 800c3c6: 46bd mov sp, r7 800c3c8: bd80 pop {r7, pc} 800c3ca: bf00 nop 800c3cc: 20000b4c .word 0x20000b4c 800c3d0: 20000a70 .word 0x20000a70 800c3d4: 20000b50 .word 0x20000b50 800c3d8: 20000bd0 .word 0x20000bd0 0800c3dc : static void App_DataModeFlushBuilder(void) { 800c3dc: b580 push {r7, lr} 800c3de: af00 add r7, sp, #0 if (g_uart_build_len == 0U) 800c3e0: 4b0b ldr r3, [pc, #44] @ (800c410 ) 800c3e2: 881b ldrh r3, [r3, #0] 800c3e4: 2b00 cmp r3, #0 800c3e6: d011 beq.n 800c40c { return; } if (App_QueuePush(g_uart_build_buf, g_uart_build_len) == 0U) 800c3e8: 4b09 ldr r3, [pc, #36] @ (800c410 ) 800c3ea: 881b ldrh r3, [r3, #0] 800c3ec: 4619 mov r1, r3 800c3ee: 4809 ldr r0, [pc, #36] @ (800c414 ) 800c3f0: f000 f814 bl 800c41c 800c3f4: 4603 mov r3, r0 800c3f6: 2b00 cmp r3, #0 800c3f8: d104 bne.n 800c404 { g_stat_queue_overflow++; 800c3fa: 4b07 ldr r3, [pc, #28] @ (800c418 ) 800c3fc: 681b ldr r3, [r3, #0] 800c3fe: 3301 adds r3, #1 800c400: 4a05 ldr r2, [pc, #20] @ (800c418 ) 800c402: 6013 str r3, [r2, #0] } g_uart_build_len = 0U; 800c404: 4b02 ldr r3, [pc, #8] @ (800c410 ) 800c406: 2200 movs r2, #0 800c408: 801a strh r2, [r3, #0] 800c40a: e000 b.n 800c40e return; 800c40c: bf00 nop } 800c40e: bd80 pop {r7, pc} 800c410: 20000b4c .word 0x20000b4c 800c414: 20000a70 .word 0x20000a70 800c418: 20000bdc .word 0x20000bdc 0800c41c : static uint8_t App_QueuePush(const uint8_t *data, uint16_t len) { 800c41c: b580 push {r7, lr} 800c41e: b082 sub sp, #8 800c420: af00 add r7, sp, #0 800c422: 6078 str r0, [r7, #4] 800c424: 460b mov r3, r1 800c426: 807b strh r3, [r7, #2] if ((len == 0U) || (len > RADIO_MAX_PAYLOAD_SIZE) || (g_tx_q_count >= TX_QUEUE_DEPTH)) 800c428: 887b ldrh r3, [r7, #2] 800c42a: 2b00 cmp r3, #0 800c42c: d006 beq.n 800c43c 800c42e: 887b ldrh r3, [r7, #2] 800c430: 2bdc cmp r3, #220 @ 0xdc 800c432: d803 bhi.n 800c43c 800c434: 4b19 ldr r3, [pc, #100] @ (800c49c ) 800c436: 781b ldrb r3, [r3, #0] 800c438: 2b03 cmp r3, #3 800c43a: d901 bls.n 800c440 { return 0U; 800c43c: 2300 movs r3, #0 800c43e: e029 b.n 800c494 } memcpy(g_tx_queue[g_tx_q_tail].data, data, len); 800c440: 4b17 ldr r3, [pc, #92] @ (800c4a0 ) 800c442: 781b ldrb r3, [r3, #0] 800c444: 461a mov r2, r3 800c446: 23dd movs r3, #221 @ 0xdd 800c448: fb02 f303 mul.w r3, r2, r3 800c44c: 4a15 ldr r2, [pc, #84] @ (800c4a4 ) 800c44e: 4413 add r3, r2 800c450: 887a ldrh r2, [r7, #2] 800c452: 6879 ldr r1, [r7, #4] 800c454: 4618 mov r0, r3 800c456: f002 f9dd bl 800e814 g_tx_queue[g_tx_q_tail].len = (uint8_t)len; 800c45a: 4b11 ldr r3, [pc, #68] @ (800c4a0 ) 800c45c: 781b ldrb r3, [r3, #0] 800c45e: 4618 mov r0, r3 800c460: 887b ldrh r3, [r7, #2] 800c462: b2d9 uxtb r1, r3 800c464: 4a0f ldr r2, [pc, #60] @ (800c4a4 ) 800c466: 23dd movs r3, #221 @ 0xdd 800c468: fb00 f303 mul.w r3, r0, r3 800c46c: 4413 add r3, r2 800c46e: 33dc adds r3, #220 @ 0xdc 800c470: 460a mov r2, r1 800c472: 701a strb r2, [r3, #0] g_tx_q_tail = (uint8_t)((g_tx_q_tail + 1U) % TX_QUEUE_DEPTH); 800c474: 4b0a ldr r3, [pc, #40] @ (800c4a0 ) 800c476: 781b ldrb r3, [r3, #0] 800c478: 3301 adds r3, #1 800c47a: b2db uxtb r3, r3 800c47c: f003 0303 and.w r3, r3, #3 800c480: b2da uxtb r2, r3 800c482: 4b07 ldr r3, [pc, #28] @ (800c4a0 ) 800c484: 701a strb r2, [r3, #0] g_tx_q_count++; 800c486: 4b05 ldr r3, [pc, #20] @ (800c49c ) 800c488: 781b ldrb r3, [r3, #0] 800c48a: 3301 adds r3, #1 800c48c: b2da uxtb r2, r3 800c48e: 4b03 ldr r3, [pc, #12] @ (800c49c ) 800c490: 701a strb r2, [r3, #0] return 1U; 800c492: 2301 movs r3, #1 } 800c494: 4618 mov r0, r3 800c496: 3708 adds r7, #8 800c498: 46bd mov sp, r7 800c49a: bd80 pop {r7, pc} 800c49c: 20000a6e .word 0x20000a6e 800c4a0: 20000a6d .word 0x20000a6d 800c4a4: 200006f8 .word 0x200006f8 0800c4a8 : static void App_QueuePop(void) { 800c4a8: b480 push {r7} 800c4aa: af00 add r7, sp, #0 if (g_tx_q_count == 0U) 800c4ac: 4b0b ldr r3, [pc, #44] @ (800c4dc ) 800c4ae: 781b ldrb r3, [r3, #0] 800c4b0: 2b00 cmp r3, #0 800c4b2: d00f beq.n 800c4d4 { return; } g_tx_q_head = (uint8_t)((g_tx_q_head + 1U) % TX_QUEUE_DEPTH); 800c4b4: 4b0a ldr r3, [pc, #40] @ (800c4e0 ) 800c4b6: 781b ldrb r3, [r3, #0] 800c4b8: 3301 adds r3, #1 800c4ba: b2db uxtb r3, r3 800c4bc: f003 0303 and.w r3, r3, #3 800c4c0: b2da uxtb r2, r3 800c4c2: 4b07 ldr r3, [pc, #28] @ (800c4e0 ) 800c4c4: 701a strb r2, [r3, #0] g_tx_q_count--; 800c4c6: 4b05 ldr r3, [pc, #20] @ (800c4dc ) 800c4c8: 781b ldrb r3, [r3, #0] 800c4ca: 3b01 subs r3, #1 800c4cc: b2da uxtb r2, r3 800c4ce: 4b03 ldr r3, [pc, #12] @ (800c4dc ) 800c4d0: 701a strb r2, [r3, #0] 800c4d2: e000 b.n 800c4d6 return; 800c4d4: bf00 nop } 800c4d6: 46bd mov sp, r7 800c4d8: bc80 pop {r7} 800c4da: 4770 bx lr 800c4dc: 20000a6e .word 0x20000a6e 800c4e0: 20000a6c .word 0x20000a6c 0800c4e4 : static void UartRxByteCallback(uint8_t *rxChar, uint16_t size, uint8_t error) { 800c4e4: b580 push {r7, lr} 800c4e6: b084 sub sp, #16 800c4e8: af00 add r7, sp, #0 800c4ea: 6078 str r0, [r7, #4] 800c4ec: 460b mov r3, r1 800c4ee: 807b strh r3, [r7, #2] 800c4f0: 4613 mov r3, r2 800c4f2: 707b strb r3, [r7, #1] uint8_t ch; uint32_t now; uint8_t i; if ((error != 0U) || (size == 0U) || (rxChar == NULL)) 800c4f4: 787b ldrb r3, [r7, #1] 800c4f6: 2b00 cmp r3, #0 800c4f8: f040 808a bne.w 800c610 800c4fc: 887b ldrh r3, [r7, #2] 800c4fe: 2b00 cmp r3, #0 800c500: f000 8086 beq.w 800c610 800c504: 687b ldr r3, [r7, #4] 800c506: 2b00 cmp r3, #0 800c508: f000 8082 beq.w 800c610 { return; } ch = rxChar[0]; 800c50c: 687b ldr r3, [r7, #4] 800c50e: 781b ldrb r3, [r3, #0] 800c510: 73bb strb r3, [r7, #14] now = HAL_GetTick(); 800c512: f7f4 fb99 bl 8000c48 800c516: 60b8 str r0, [r7, #8] if (g_mode == APP_MODE_CONFIG) 800c518: 4b3f ldr r3, [pc, #252] @ (800c618 ) 800c51a: 781b ldrb r3, [r3, #0] 800c51c: 2b01 cmp r3, #1 800c51e: d104 bne.n 800c52a { App_ConfigFeedByte(ch); 800c520: 7bbb ldrb r3, [r7, #14] 800c522: 4618 mov r0, r3 800c524: f000 f87e bl 800c624 return; 800c528: e073 b.n 800c612 } if (g_escape.active == 0U) 800c52a: 4b3c ldr r3, [pc, #240] @ (800c61c ) 800c52c: 781b ldrb r3, [r3, #0] 800c52e: 2b00 cmp r3, #0 800c530: d11f bne.n 800c572 { if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) 800c532: 4b3b ldr r3, [pc, #236] @ (800c620 ) 800c534: 681b ldr r3, [r3, #0] 800c536: 68ba ldr r2, [r7, #8] 800c538: 1ad3 subs r3, r2, r3 800c53a: f5b3 7f48 cmp.w r3, #800 @ 0x320 800c53e: d312 bcc.n 800c566 800c540: 7bbb ldrb r3, [r7, #14] 800c542: 2b2b cmp r3, #43 @ 0x2b 800c544: d10f bne.n 800c566 { g_escape.active = 1U; 800c546: 4b35 ldr r3, [pc, #212] @ (800c61c ) 800c548: 2201 movs r2, #1 800c54a: 701a strb r2, [r3, #0] g_escape.count = 1U; 800c54c: 4b33 ldr r3, [pc, #204] @ (800c61c ) 800c54e: 2201 movs r2, #1 800c550: 705a strb r2, [r3, #1] g_escape.bytes[0] = ch; 800c552: 4a32 ldr r2, [pc, #200] @ (800c61c ) 800c554: 7bbb ldrb r3, [r7, #14] 800c556: 7093 strb r3, [r2, #2] g_escape.start_tick = now; 800c558: 4a30 ldr r2, [pc, #192] @ (800c61c ) 800c55a: 68bb ldr r3, [r7, #8] 800c55c: 6093 str r3, [r2, #8] g_escape.last_tick = now; 800c55e: 4a2f ldr r2, [pc, #188] @ (800c61c ) 800c560: 68bb ldr r3, [r7, #8] 800c562: 60d3 str r3, [r2, #12] return; 800c564: e055 b.n 800c612 } App_DataModeFeedByte(ch, now); 800c566: 7bbb ldrb r3, [r7, #14] 800c568: 68b9 ldr r1, [r7, #8] 800c56a: 4618 mov r0, r3 800c56c: f7ff fef4 bl 800c358 return; 800c570: e04f b.n 800c612 } if ((ch == '+') && (g_escape.count < 3U)) 800c572: 7bbb ldrb r3, [r7, #14] 800c574: 2b2b cmp r3, #43 @ 0x2b 800c576: d112 bne.n 800c59e 800c578: 4b28 ldr r3, [pc, #160] @ (800c61c ) 800c57a: 785b ldrb r3, [r3, #1] 800c57c: 2b02 cmp r3, #2 800c57e: d80e bhi.n 800c59e { g_escape.bytes[g_escape.count++] = ch; 800c580: 4b26 ldr r3, [pc, #152] @ (800c61c ) 800c582: 785b ldrb r3, [r3, #1] 800c584: 1c5a adds r2, r3, #1 800c586: b2d1 uxtb r1, r2 800c588: 4a24 ldr r2, [pc, #144] @ (800c61c ) 800c58a: 7051 strb r1, [r2, #1] 800c58c: 461a mov r2, r3 800c58e: 4b23 ldr r3, [pc, #140] @ (800c61c ) 800c590: 4413 add r3, r2 800c592: 7bba ldrb r2, [r7, #14] 800c594: 709a strb r2, [r3, #2] g_escape.last_tick = now; 800c596: 4a21 ldr r2, [pc, #132] @ (800c61c ) 800c598: 68bb ldr r3, [r7, #8] 800c59a: 60d3 str r3, [r2, #12] return; 800c59c: e039 b.n 800c612 } for (i = 0U; i < g_escape.count; i++) 800c59e: 2300 movs r3, #0 800c5a0: 73fb strb r3, [r7, #15] 800c5a2: e00a b.n 800c5ba { App_DataModeFeedByte(g_escape.bytes[i], now); 800c5a4: 7bfb ldrb r3, [r7, #15] 800c5a6: 4a1d ldr r2, [pc, #116] @ (800c61c ) 800c5a8: 4413 add r3, r2 800c5aa: 789b ldrb r3, [r3, #2] 800c5ac: 68b9 ldr r1, [r7, #8] 800c5ae: 4618 mov r0, r3 800c5b0: f7ff fed2 bl 800c358 for (i = 0U; i < g_escape.count; i++) 800c5b4: 7bfb ldrb r3, [r7, #15] 800c5b6: 3301 adds r3, #1 800c5b8: 73fb strb r3, [r7, #15] 800c5ba: 4b18 ldr r3, [pc, #96] @ (800c61c ) 800c5bc: 785b ldrb r3, [r3, #1] 800c5be: 7bfa ldrb r2, [r7, #15] 800c5c0: 429a cmp r2, r3 800c5c2: d3ef bcc.n 800c5a4 } g_escape.active = 0U; 800c5c4: 4b15 ldr r3, [pc, #84] @ (800c61c ) 800c5c6: 2200 movs r2, #0 800c5c8: 701a strb r2, [r3, #0] g_escape.count = 0U; 800c5ca: 4b14 ldr r3, [pc, #80] @ (800c61c ) 800c5cc: 2200 movs r2, #0 800c5ce: 705a strb r2, [r3, #1] if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) 800c5d0: 4b13 ldr r3, [pc, #76] @ (800c620 ) 800c5d2: 681b ldr r3, [r3, #0] 800c5d4: 68ba ldr r2, [r7, #8] 800c5d6: 1ad3 subs r3, r2, r3 800c5d8: f5b3 7f48 cmp.w r3, #800 @ 0x320 800c5dc: d312 bcc.n 800c604 800c5de: 7bbb ldrb r3, [r7, #14] 800c5e0: 2b2b cmp r3, #43 @ 0x2b 800c5e2: d10f bne.n 800c604 { g_escape.active = 1U; 800c5e4: 4b0d ldr r3, [pc, #52] @ (800c61c ) 800c5e6: 2201 movs r2, #1 800c5e8: 701a strb r2, [r3, #0] g_escape.count = 1U; 800c5ea: 4b0c ldr r3, [pc, #48] @ (800c61c ) 800c5ec: 2201 movs r2, #1 800c5ee: 705a strb r2, [r3, #1] g_escape.bytes[0] = ch; 800c5f0: 4a0a ldr r2, [pc, #40] @ (800c61c ) 800c5f2: 7bbb ldrb r3, [r7, #14] 800c5f4: 7093 strb r3, [r2, #2] g_escape.start_tick = now; 800c5f6: 4a09 ldr r2, [pc, #36] @ (800c61c ) 800c5f8: 68bb ldr r3, [r7, #8] 800c5fa: 6093 str r3, [r2, #8] g_escape.last_tick = now; 800c5fc: 4a07 ldr r2, [pc, #28] @ (800c61c ) 800c5fe: 68bb ldr r3, [r7, #8] 800c600: 60d3 str r3, [r2, #12] return; 800c602: e006 b.n 800c612 } App_DataModeFeedByte(ch, now); 800c604: 7bbb ldrb r3, [r7, #14] 800c606: 68b9 ldr r1, [r7, #8] 800c608: 4618 mov r0, r3 800c60a: f7ff fea5 bl 800c358 800c60e: e000 b.n 800c612 return; 800c610: bf00 nop } 800c612: 3710 adds r7, #16 800c614: 46bd mov sp, r7 800c616: bd80 pop {r7, pc} 800c618: 20000b64 .word 0x20000b64 800c61c: 20000b54 .word 0x20000b54 800c620: 20000b50 .word 0x20000b50 0800c624 : static void App_ConfigFeedByte(uint8_t ch) { 800c624: b580 push {r7, lr} 800c626: b082 sub sp, #8 800c628: af00 add r7, sp, #0 800c62a: 4603 mov r3, r0 800c62c: 71fb strb r3, [r7, #7] if ((ch == '\r') || (ch == '\n')) 800c62e: 79fb ldrb r3, [r7, #7] 800c630: 2b0d cmp r3, #13 800c632: d002 beq.n 800c63a 800c634: 79fb ldrb r3, [r7, #7] 800c636: 2b0a cmp r3, #10 800c638: d115 bne.n 800c666 { if (g_cfg_line_len > 0U) 800c63a: 4b26 ldr r3, [pc, #152] @ (800c6d4 ) 800c63c: 881b ldrh r3, [r3, #0] 800c63e: 2b00 cmp r3, #0 800c640: d00e beq.n 800c660 { g_cfg_line[g_cfg_line_len] = '\0'; 800c642: 4b24 ldr r3, [pc, #144] @ (800c6d4 ) 800c644: 881b ldrh r3, [r3, #0] 800c646: 461a mov r2, r3 800c648: 4b23 ldr r3, [pc, #140] @ (800c6d8 ) 800c64a: 2100 movs r1, #0 800c64c: 5499 strb r1, [r3, r2] App_Printf("\r\n"); 800c64e: 4823 ldr r0, [pc, #140] @ (800c6dc ) 800c650: f000 fb96 bl 800cd80 App_ConfigExecuteLine(g_cfg_line); 800c654: 4820 ldr r0, [pc, #128] @ (800c6d8 ) 800c656: f000 f847 bl 800c6e8 g_cfg_line_len = 0U; 800c65a: 4b1e ldr r3, [pc, #120] @ (800c6d4 ) 800c65c: 2200 movs r2, #0 800c65e: 801a strh r2, [r3, #0] } App_PrintConfigPrompt(); 800c660: f000 fa7a bl 800cb58 return; 800c664: e032 b.n 800c6cc } if ((ch == 0x08U) || (ch == 0x7FU)) 800c666: 79fb ldrb r3, [r7, #7] 800c668: 2b08 cmp r3, #8 800c66a: d002 beq.n 800c672 800c66c: 79fb ldrb r3, [r7, #7] 800c66e: 2b7f cmp r3, #127 @ 0x7f 800c670: d10e bne.n 800c690 { if (g_cfg_line_len > 0U) 800c672: 4b18 ldr r3, [pc, #96] @ (800c6d4 ) 800c674: 881b ldrh r3, [r3, #0] 800c676: 2b00 cmp r3, #0 800c678: d027 beq.n 800c6ca { g_cfg_line_len--; 800c67a: 4b16 ldr r3, [pc, #88] @ (800c6d4 ) 800c67c: 881b ldrh r3, [r3, #0] 800c67e: 3b01 subs r3, #1 800c680: b29a uxth r2, r3 800c682: 4b14 ldr r3, [pc, #80] @ (800c6d4 ) 800c684: 801a strh r2, [r3, #0] App_Write((const uint8_t *)"\b \b", 3U); 800c686: 2103 movs r1, #3 800c688: 4815 ldr r0, [pc, #84] @ (800c6e0 ) 800c68a: f000 fba5 bl 800cdd8 } return; 800c68e: e01c b.n 800c6ca } if ((isprint(ch) != 0) && (g_cfg_line_len < (CONFIG_LINE_SIZE - 1U))) 800c690: 79fb ldrb r3, [r7, #7] 800c692: 3301 adds r3, #1 800c694: 4a13 ldr r2, [pc, #76] @ (800c6e4 ) 800c696: 4413 add r3, r2 800c698: 781b ldrb r3, [r3, #0] 800c69a: f003 0397 and.w r3, r3, #151 @ 0x97 800c69e: 2b00 cmp r3, #0 800c6a0: d014 beq.n 800c6cc 800c6a2: 4b0c ldr r3, [pc, #48] @ (800c6d4 ) 800c6a4: 881b ldrh r3, [r3, #0] 800c6a6: 2b5e cmp r3, #94 @ 0x5e 800c6a8: d810 bhi.n 800c6cc { g_cfg_line[g_cfg_line_len++] = (char)ch; 800c6aa: 4b0a ldr r3, [pc, #40] @ (800c6d4 ) 800c6ac: 881b ldrh r3, [r3, #0] 800c6ae: 1c5a adds r2, r3, #1 800c6b0: b291 uxth r1, r2 800c6b2: 4a08 ldr r2, [pc, #32] @ (800c6d4 ) 800c6b4: 8011 strh r1, [r2, #0] 800c6b6: 461a mov r2, r3 800c6b8: 79f9 ldrb r1, [r7, #7] 800c6ba: 4b07 ldr r3, [pc, #28] @ (800c6d8 ) 800c6bc: 5499 strb r1, [r3, r2] App_Write(&ch, 1U); 800c6be: 1dfb adds r3, r7, #7 800c6c0: 2101 movs r1, #1 800c6c2: 4618 mov r0, r3 800c6c4: f000 fb88 bl 800cdd8 800c6c8: e000 b.n 800c6cc return; 800c6ca: bf00 nop } } 800c6cc: 3708 adds r7, #8 800c6ce: 46bd mov sp, r7 800c6d0: bd80 pop {r7, pc} 800c6d2: bf00 nop 800c6d4: 20000bc8 .word 0x20000bc8 800c6d8: 20000b68 .word 0x20000b68 800c6dc: 0800f3c8 .word 0x0800f3c8 800c6e0: 0800f3cc .word 0x0800f3cc 800c6e4: 0800fccc .word 0x0800fccc 0800c6e8 : static void App_ConfigExecuteLine(char *line) { 800c6e8: b580 push {r7, lr} 800c6ea: b086 sub sp, #24 800c6ec: af00 add r7, sp, #0 800c6ee: 6078 str r0, [r7, #4] char *arg; uint32_t u32; uint8_t sync[3]; line = App_SkipSpaces(line); 800c6f0: 6878 ldr r0, [r7, #4] 800c6f2: f000 fc39 bl 800cf68 800c6f6: 6078 str r0, [r7, #4] if (*line == '\0') 800c6f8: 687b ldr r3, [r7, #4] 800c6fa: 781b ldrb r3, [r3, #0] 800c6fc: 2b00 cmp r3, #0 800c6fe: f000 8210 beq.w 800cb22 { return; } if ((strcmp(line, "help") == 0) || (strcmp(line, "?") == 0)) 800c702: 49a4 ldr r1, [pc, #656] @ (800c994 ) 800c704: 6878 ldr r0, [r7, #4] 800c706: f7f3 fd3b bl 8000180 800c70a: 4603 mov r3, r0 800c70c: 2b00 cmp r3, #0 800c70e: d006 beq.n 800c71e 800c710: 49a1 ldr r1, [pc, #644] @ (800c998 ) 800c712: 6878 ldr r0, [r7, #4] 800c714: f7f3 fd34 bl 8000180 800c718: 4603 mov r3, r0 800c71a: 2b00 cmp r3, #0 800c71c: d102 bne.n 800c724 { App_PrintHelp(); 800c71e: f000 fa2b bl 800cb78 return; 800c722: e1ff b.n 800cb24 } if ((strcmp(line, "show") == 0) || (strcmp(line, "status") == 0)) 800c724: 499d ldr r1, [pc, #628] @ (800c99c ) 800c726: 6878 ldr r0, [r7, #4] 800c728: f7f3 fd2a bl 8000180 800c72c: 4603 mov r3, r0 800c72e: 2b00 cmp r3, #0 800c730: d006 beq.n 800c740 800c732: 499b ldr r1, [pc, #620] @ (800c9a0 ) 800c734: 6878 ldr r0, [r7, #4] 800c736: f7f3 fd23 bl 8000180 800c73a: 4603 mov r3, r0 800c73c: 2b00 cmp r3, #0 800c73e: d102 bne.n 800c746 { App_PrintStatus(); 800c740: f000 fa64 bl 800cc0c return; 800c744: e1ee b.n 800cb24 } if (strcmp(line, "exit") == 0) 800c746: 4997 ldr r1, [pc, #604] @ (800c9a4 ) 800c748: 6878 ldr r0, [r7, #4] 800c74a: f7f3 fd19 bl 8000180 800c74e: 4603 mov r3, r0 800c750: 2b00 cmp r3, #0 800c752: d102 bne.n 800c75a { App_ExitConfigMode(); 800c754: f7ff fdc4 bl 800c2e0 return; 800c758: e1e4 b.n 800cb24 } if (strcmp(line, "defaults") == 0) 800c75a: 4993 ldr r1, [pc, #588] @ (800c9a8 ) 800c75c: 6878 ldr r0, [r7, #4] 800c75e: f7f3 fd0f bl 8000180 800c762: 4603 mov r3, r0 800c764: 2b00 cmp r3, #0 800c766: d126 bne.n 800c7b6 { g_cfg.rf_frequency = RF_FREQUENCY_DEFAULT; 800c768: 4b90 ldr r3, [pc, #576] @ (800c9ac ) 800c76a: 4a91 ldr r2, [pc, #580] @ (800c9b0 ) 800c76c: 601a str r2, [r3, #0] g_cfg.tx_power = TX_OUTPUT_POWER_DEFAULT; 800c76e: 4b8f ldr r3, [pc, #572] @ (800c9ac ) 800c770: 220e movs r2, #14 800c772: 711a strb r2, [r3, #4] g_cfg.fsk_bitrate = FSK_DATARATE_DEFAULT; 800c774: 4b8d ldr r3, [pc, #564] @ (800c9ac ) 800c776: f24c 3250 movw r2, #50000 @ 0xc350 800c77a: 609a str r2, [r3, #8] g_cfg.fsk_bandwidth = FSK_BANDWIDTH_DEFAULT; 800c77c: 4b8b ldr r3, [pc, #556] @ (800c9ac ) 800c77e: f24c 3250 movw r2, #50000 @ 0xc350 800c782: 60da str r2, [r3, #12] g_cfg.fsk_fdev = FSK_FDEV_DEFAULT; 800c784: 4b89 ldr r3, [pc, #548] @ (800c9ac ) 800c786: f246 12a8 movw r2, #25000 @ 0x61a8 800c78a: 611a str r2, [r3, #16] g_cfg.fsk_preamble_len = FSK_PREAMBLE_LENGTH_DEFAULT; 800c78c: 4b87 ldr r3, [pc, #540] @ (800c9ac ) 800c78e: 2204 movs r2, #4 800c790: 829a strh r2, [r3, #20] g_cfg.syncword[0] = 0xC1U; 800c792: 4b86 ldr r3, [pc, #536] @ (800c9ac ) 800c794: 22c1 movs r2, #193 @ 0xc1 800c796: 759a strb r2, [r3, #22] g_cfg.syncword[1] = 0x94U; 800c798: 4b84 ldr r3, [pc, #528] @ (800c9ac ) 800c79a: 2294 movs r2, #148 @ 0x94 800c79c: 75da strb r2, [r3, #23] g_cfg.syncword[2] = 0xC1U; 800c79e: 4b83 ldr r3, [pc, #524] @ (800c9ac ) 800c7a0: 22c1 movs r2, #193 @ 0xc1 800c7a2: 761a strb r2, [r3, #24] g_cfg.uart_packet_timeout_ms = DEFAULT_UART_PACKET_TIMEOUT_MS; 800c7a4: 4b81 ldr r3, [pc, #516] @ (800c9ac ) 800c7a6: 2214 movs r2, #20 800c7a8: 835a strh r2, [r3, #26] App_RadioApplyConfig(); 800c7aa: f7ff fcc1 bl 800c130 App_Printf("defaults restored\r\n"); 800c7ae: 4881 ldr r0, [pc, #516] @ (800c9b4 ) 800c7b0: f000 fae6 bl 800cd80 return; 800c7b4: e1b6 b.n 800cb24 } if (strncmp(line, "freq ", 5) == 0) 800c7b6: 2205 movs r2, #5 800c7b8: 497f ldr r1, [pc, #508] @ (800c9b8 ) 800c7ba: 6878 ldr r0, [r7, #4] 800c7bc: f001 ffec bl 800e798 800c7c0: 4603 mov r3, r0 800c7c2: 2b00 cmp r3, #0 800c7c4: d11f bne.n 800c806 { u32 = strtoul(&line[5], NULL, 10); 800c7c6: 687b ldr r3, [r7, #4] 800c7c8: 3305 adds r3, #5 800c7ca: 220a movs r2, #10 800c7cc: 2100 movs r1, #0 800c7ce: 4618 mov r0, r3 800c7d0: f001 ff94 bl 800e6fc 800c7d4: 6138 str r0, [r7, #16] if (u32 < 150000000UL || u32 > 960000000UL) 800c7d6: 693b ldr r3, [r7, #16] 800c7d8: 4a78 ldr r2, [pc, #480] @ (800c9bc ) 800c7da: 4293 cmp r3, r2 800c7dc: d903 bls.n 800c7e6 800c7de: 693b ldr r3, [r7, #16] 800c7e0: 4a77 ldr r2, [pc, #476] @ (800c9c0 ) 800c7e2: 4293 cmp r3, r2 800c7e4: d903 bls.n 800c7ee { App_Printf("bad frequency\r\n"); 800c7e6: 4877 ldr r0, [pc, #476] @ (800c9c4 ) 800c7e8: f000 faca bl 800cd80 return; 800c7ec: e19a b.n 800cb24 } g_cfg.rf_frequency = u32; 800c7ee: 4a6f ldr r2, [pc, #444] @ (800c9ac ) 800c7f0: 693b ldr r3, [r7, #16] 800c7f2: 6013 str r3, [r2, #0] App_RadioApplyConfig(); 800c7f4: f7ff fc9c bl 800c130 App_Printf("freq=%lu\r\n", (unsigned long)g_cfg.rf_frequency); 800c7f8: 4b6c ldr r3, [pc, #432] @ (800c9ac ) 800c7fa: 681b ldr r3, [r3, #0] 800c7fc: 4619 mov r1, r3 800c7fe: 4872 ldr r0, [pc, #456] @ (800c9c8 ) 800c800: f000 fabe bl 800cd80 return; 800c804: e18e b.n 800cb24 } if (strncmp(line, "power ", 6) == 0) 800c806: 2206 movs r2, #6 800c808: 4970 ldr r1, [pc, #448] @ (800c9cc ) 800c80a: 6878 ldr r0, [r7, #4] 800c80c: f001 ffc4 bl 800e798 800c810: 4603 mov r3, r0 800c812: 2b00 cmp r3, #0 800c814: d120 bne.n 800c858 { long pwr = strtol(&line[6], NULL, 10); 800c816: 687b ldr r3, [r7, #4] 800c818: 3306 adds r3, #6 800c81a: 220a movs r2, #10 800c81c: 2100 movs r1, #0 800c81e: 4618 mov r0, r3 800c820: f001 fef4 bl 800e60c 800c824: 60f8 str r0, [r7, #12] if ((pwr < -9L) || (pwr > 22L)) 800c826: 68fb ldr r3, [r7, #12] 800c828: f113 0f09 cmn.w r3, #9 800c82c: db02 blt.n 800c834 800c82e: 68fb ldr r3, [r7, #12] 800c830: 2b16 cmp r3, #22 800c832: dd03 ble.n 800c83c { App_Printf("bad power\r\n"); 800c834: 4866 ldr r0, [pc, #408] @ (800c9d0 ) 800c836: f000 faa3 bl 800cd80 return; 800c83a: e173 b.n 800cb24 } g_cfg.tx_power = (int8_t)pwr; 800c83c: 68fb ldr r3, [r7, #12] 800c83e: b25a sxtb r2, r3 800c840: 4b5a ldr r3, [pc, #360] @ (800c9ac ) 800c842: 711a strb r2, [r3, #4] App_RadioApplyConfig(); 800c844: f7ff fc74 bl 800c130 App_Printf("power=%d\r\n", g_cfg.tx_power); 800c848: 4b58 ldr r3, [pc, #352] @ (800c9ac ) 800c84a: f993 3004 ldrsb.w r3, [r3, #4] 800c84e: 4619 mov r1, r3 800c850: 4860 ldr r0, [pc, #384] @ (800c9d4 ) 800c852: f000 fa95 bl 800cd80 return; 800c856: e165 b.n 800cb24 } if (strncmp(line, "bitrate ", 8) == 0) 800c858: 2208 movs r2, #8 800c85a: 495f ldr r1, [pc, #380] @ (800c9d8 ) 800c85c: 6878 ldr r0, [r7, #4] 800c85e: f001 ff9b bl 800e798 800c862: 4603 mov r3, r0 800c864: 2b00 cmp r3, #0 800c866: d11f bne.n 800c8a8 { u32 = strtoul(&line[8], NULL, 10); 800c868: 687b ldr r3, [r7, #4] 800c86a: 3308 adds r3, #8 800c86c: 220a movs r2, #10 800c86e: 2100 movs r1, #0 800c870: 4618 mov r0, r3 800c872: f001 ff43 bl 800e6fc 800c876: 6138 str r0, [r7, #16] if ((u32 < 600UL) || (u32 > 300000UL)) 800c878: 693b ldr r3, [r7, #16] 800c87a: f5b3 7f16 cmp.w r3, #600 @ 0x258 800c87e: d303 bcc.n 800c888 800c880: 693b ldr r3, [r7, #16] 800c882: 4a56 ldr r2, [pc, #344] @ (800c9dc ) 800c884: 4293 cmp r3, r2 800c886: d903 bls.n 800c890 { App_Printf("bad bitrate\r\n"); 800c888: 4855 ldr r0, [pc, #340] @ (800c9e0 ) 800c88a: f000 fa79 bl 800cd80 return; 800c88e: e149 b.n 800cb24 } g_cfg.fsk_bitrate = u32; 800c890: 4a46 ldr r2, [pc, #280] @ (800c9ac ) 800c892: 693b ldr r3, [r7, #16] 800c894: 6093 str r3, [r2, #8] App_RadioApplyConfig(); 800c896: f7ff fc4b bl 800c130 App_Printf("bitrate=%lu\r\n", (unsigned long)g_cfg.fsk_bitrate); 800c89a: 4b44 ldr r3, [pc, #272] @ (800c9ac ) 800c89c: 689b ldr r3, [r3, #8] 800c89e: 4619 mov r1, r3 800c8a0: 4850 ldr r0, [pc, #320] @ (800c9e4 ) 800c8a2: f000 fa6d bl 800cd80 return; 800c8a6: e13d b.n 800cb24 } if (strncmp(line, "bandwidth ", 10) == 0) 800c8a8: 220a movs r2, #10 800c8aa: 494f ldr r1, [pc, #316] @ (800c9e8 ) 800c8ac: 6878 ldr r0, [r7, #4] 800c8ae: f001 ff73 bl 800e798 800c8b2: 4603 mov r3, r0 800c8b4: 2b00 cmp r3, #0 800c8b6: d120 bne.n 800c8fa { u32 = strtoul(&line[10], NULL, 10); 800c8b8: 687b ldr r3, [r7, #4] 800c8ba: 330a adds r3, #10 800c8bc: 220a movs r2, #10 800c8be: 2100 movs r1, #0 800c8c0: 4618 mov r0, r3 800c8c2: f001 ff1b bl 800e6fc 800c8c6: 6138 str r0, [r7, #16] if ((u32 < 2600UL) || (u32 > 250000UL)) 800c8c8: 693b ldr r3, [r7, #16] 800c8ca: f640 2227 movw r2, #2599 @ 0xa27 800c8ce: 4293 cmp r3, r2 800c8d0: d903 bls.n 800c8da 800c8d2: 693b ldr r3, [r7, #16] 800c8d4: 4a45 ldr r2, [pc, #276] @ (800c9ec ) 800c8d6: 4293 cmp r3, r2 800c8d8: d903 bls.n 800c8e2 { App_Printf("bad bandwidth\r\n"); 800c8da: 4845 ldr r0, [pc, #276] @ (800c9f0 ) 800c8dc: f000 fa50 bl 800cd80 return; 800c8e0: e120 b.n 800cb24 } g_cfg.fsk_bandwidth = u32; 800c8e2: 4a32 ldr r2, [pc, #200] @ (800c9ac ) 800c8e4: 693b ldr r3, [r7, #16] 800c8e6: 60d3 str r3, [r2, #12] App_RadioApplyConfig(); 800c8e8: f7ff fc22 bl 800c130 App_Printf("bandwidth=%lu\r\n", (unsigned long)g_cfg.fsk_bandwidth); 800c8ec: 4b2f ldr r3, [pc, #188] @ (800c9ac ) 800c8ee: 68db ldr r3, [r3, #12] 800c8f0: 4619 mov r1, r3 800c8f2: 4840 ldr r0, [pc, #256] @ (800c9f4 ) 800c8f4: f000 fa44 bl 800cd80 return; 800c8f8: e114 b.n 800cb24 } if (strncmp(line, "fdev ", 5) == 0) 800c8fa: 2205 movs r2, #5 800c8fc: 493e ldr r1, [pc, #248] @ (800c9f8 ) 800c8fe: 6878 ldr r0, [r7, #4] 800c900: f001 ff4a bl 800e798 800c904: 4603 mov r3, r0 800c906: 2b00 cmp r3, #0 800c908: d11b bne.n 800c942 { u32 = strtoul(&line[5], NULL, 10); 800c90a: 687b ldr r3, [r7, #4] 800c90c: 3305 adds r3, #5 800c90e: 220a movs r2, #10 800c910: 2100 movs r1, #0 800c912: 4618 mov r0, r3 800c914: f001 fef2 bl 800e6fc 800c918: 6138 str r0, [r7, #16] if (u32 > 200000UL) 800c91a: 693b ldr r3, [r7, #16] 800c91c: 4a37 ldr r2, [pc, #220] @ (800c9fc ) 800c91e: 4293 cmp r3, r2 800c920: d903 bls.n 800c92a { App_Printf("bad fdev\r\n"); 800c922: 4837 ldr r0, [pc, #220] @ (800ca00 ) 800c924: f000 fa2c bl 800cd80 return; 800c928: e0fc b.n 800cb24 } g_cfg.fsk_fdev = u32; 800c92a: 4a20 ldr r2, [pc, #128] @ (800c9ac ) 800c92c: 693b ldr r3, [r7, #16] 800c92e: 6113 str r3, [r2, #16] App_RadioApplyConfig(); 800c930: f7ff fbfe bl 800c130 App_Printf("fdev=%lu\r\n", (unsigned long)g_cfg.fsk_fdev); 800c934: 4b1d ldr r3, [pc, #116] @ (800c9ac ) 800c936: 691b ldr r3, [r3, #16] 800c938: 4619 mov r1, r3 800c93a: 4832 ldr r0, [pc, #200] @ (800ca04 ) 800c93c: f000 fa20 bl 800cd80 return; 800c940: e0f0 b.n 800cb24 } if (strncmp(line, "preamble ", 9) == 0) 800c942: 2209 movs r2, #9 800c944: 4930 ldr r1, [pc, #192] @ (800ca08 ) 800c946: 6878 ldr r0, [r7, #4] 800c948: f001 ff26 bl 800e798 800c94c: 4603 mov r3, r0 800c94e: 2b00 cmp r3, #0 800c950: d160 bne.n 800ca14 { u32 = strtoul(&line[9], NULL, 10); 800c952: 687b ldr r3, [r7, #4] 800c954: 3309 adds r3, #9 800c956: 220a movs r2, #10 800c958: 2100 movs r1, #0 800c95a: 4618 mov r0, r3 800c95c: f001 fece bl 800e6fc 800c960: 6138 str r0, [r7, #16] if ((u32 < 2UL) || (u32 > 65535UL)) 800c962: 693b ldr r3, [r7, #16] 800c964: 2b01 cmp r3, #1 800c966: d903 bls.n 800c970 800c968: 693b ldr r3, [r7, #16] 800c96a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800c96e: d303 bcc.n 800c978 { App_Printf("bad preamble\r\n"); 800c970: 4826 ldr r0, [pc, #152] @ (800ca0c ) 800c972: f000 fa05 bl 800cd80 return; 800c976: e0d5 b.n 800cb24 } g_cfg.fsk_preamble_len = (uint16_t)u32; 800c978: 693b ldr r3, [r7, #16] 800c97a: b29a uxth r2, r3 800c97c: 4b0b ldr r3, [pc, #44] @ (800c9ac ) 800c97e: 829a strh r2, [r3, #20] App_RadioApplyConfig(); 800c980: f7ff fbd6 bl 800c130 App_Printf("preamble=%u\r\n", g_cfg.fsk_preamble_len); 800c984: 4b09 ldr r3, [pc, #36] @ (800c9ac ) 800c986: 8a9b ldrh r3, [r3, #20] 800c988: 4619 mov r1, r3 800c98a: 4821 ldr r0, [pc, #132] @ (800ca10 ) 800c98c: f000 f9f8 bl 800cd80 return; 800c990: e0c8 b.n 800cb24 800c992: bf00 nop 800c994: 0800f3d0 .word 0x0800f3d0 800c998: 0800f3d8 .word 0x0800f3d8 800c99c: 0800f3dc .word 0x0800f3dc 800c9a0: 0800f3e4 .word 0x0800f3e4 800c9a4: 0800f3ec .word 0x0800f3ec 800c9a8: 0800f3f4 .word 0x0800f3f4 800c9ac: 2000000c .word 0x2000000c 800c9b0: 19d094e0 .word 0x19d094e0 800c9b4: 0800f400 .word 0x0800f400 800c9b8: 0800f414 .word 0x0800f414 800c9bc: 08f0d17f .word 0x08f0d17f 800c9c0: 39387000 .word 0x39387000 800c9c4: 0800f41c .word 0x0800f41c 800c9c8: 0800f42c .word 0x0800f42c 800c9cc: 0800f438 .word 0x0800f438 800c9d0: 0800f440 .word 0x0800f440 800c9d4: 0800f44c .word 0x0800f44c 800c9d8: 0800f458 .word 0x0800f458 800c9dc: 000493e0 .word 0x000493e0 800c9e0: 0800f464 .word 0x0800f464 800c9e4: 0800f474 .word 0x0800f474 800c9e8: 0800f484 .word 0x0800f484 800c9ec: 0003d090 .word 0x0003d090 800c9f0: 0800f490 .word 0x0800f490 800c9f4: 0800f4a0 .word 0x0800f4a0 800c9f8: 0800f4b0 .word 0x0800f4b0 800c9fc: 00030d40 .word 0x00030d40 800ca00: 0800f4b8 .word 0x0800f4b8 800ca04: 0800f4c4 .word 0x0800f4c4 800ca08: 0800f4d0 .word 0x0800f4d0 800ca0c: 0800f4dc .word 0x0800f4dc 800ca10: 0800f4ec .word 0x0800f4ec } if (strncmp(line, "timeout ", 8) == 0) 800ca14: 2208 movs r2, #8 800ca16: 4945 ldr r1, [pc, #276] @ (800cb2c ) 800ca18: 6878 ldr r0, [r7, #4] 800ca1a: f001 febd bl 800e798 800ca1e: 4603 mov r3, r0 800ca20: 2b00 cmp r3, #0 800ca22: d11d bne.n 800ca60 { u32 = strtoul(&line[8], NULL, 10); 800ca24: 687b ldr r3, [r7, #4] 800ca26: 3308 adds r3, #8 800ca28: 220a movs r2, #10 800ca2a: 2100 movs r1, #0 800ca2c: 4618 mov r0, r3 800ca2e: f001 fe65 bl 800e6fc 800ca32: 6138 str r0, [r7, #16] if ((u32 < 1UL) || (u32 > 1000UL)) 800ca34: 693b ldr r3, [r7, #16] 800ca36: 2b00 cmp r3, #0 800ca38: d003 beq.n 800ca42 800ca3a: 693b ldr r3, [r7, #16] 800ca3c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800ca40: d903 bls.n 800ca4a { App_Printf("bad timeout\r\n"); 800ca42: 483b ldr r0, [pc, #236] @ (800cb30 ) 800ca44: f000 f99c bl 800cd80 return; 800ca48: e06c b.n 800cb24 } g_cfg.uart_packet_timeout_ms = (uint16_t)u32; 800ca4a: 693b ldr r3, [r7, #16] 800ca4c: b29a uxth r2, r3 800ca4e: 4b39 ldr r3, [pc, #228] @ (800cb34 ) 800ca50: 835a strh r2, [r3, #26] App_Printf("timeout=%u\r\n", g_cfg.uart_packet_timeout_ms); 800ca52: 4b38 ldr r3, [pc, #224] @ (800cb34 ) 800ca54: 8b5b ldrh r3, [r3, #26] 800ca56: 4619 mov r1, r3 800ca58: 4837 ldr r0, [pc, #220] @ (800cb38 ) 800ca5a: f000 f991 bl 800cd80 return; 800ca5e: e061 b.n 800cb24 } if (strncmp(line, "uart ", 5) == 0) 800ca60: 2205 movs r2, #5 800ca62: 4936 ldr r1, [pc, #216] @ (800cb3c ) 800ca64: 6878 ldr r0, [r7, #4] 800ca66: f001 fe97 bl 800e798 800ca6a: 4603 mov r3, r0 800ca6c: 2b00 cmp r3, #0 800ca6e: d122 bne.n 800cab6 { u32 = strtoul(&line[5], NULL, 10); 800ca70: 687b ldr r3, [r7, #4] 800ca72: 3305 adds r3, #5 800ca74: 220a movs r2, #10 800ca76: 2100 movs r1, #0 800ca78: 4618 mov r0, r3 800ca7a: f001 fe3f bl 800e6fc 800ca7e: 6138 str r0, [r7, #16] if ((u32 < 1200UL) || (u32 > 921600UL)) 800ca80: 693b ldr r3, [r7, #16] 800ca82: f5b3 6f96 cmp.w r3, #1200 @ 0x4b0 800ca86: d303 bcc.n 800ca90 800ca88: 693b ldr r3, [r7, #16] 800ca8a: f5b3 2f61 cmp.w r3, #921600 @ 0xe1000 800ca8e: d903 bls.n 800ca98 { App_Printf("bad uart baudrate\r\n"); 800ca90: 482b ldr r0, [pc, #172] @ (800cb40 ) 800ca92: f000 f975 bl 800cd80 return; 800ca96: e045 b.n 800cb24 } g_cfg.uart_baudrate = u32; 800ca98: 4a26 ldr r2, [pc, #152] @ (800cb34 ) 800ca9a: 693b ldr r3, [r7, #16] 800ca9c: 61d3 str r3, [r2, #28] App_Printf("switching uart to %lu baud\r\n", (unsigned long)g_cfg.uart_baudrate); 800ca9e: 4b25 ldr r3, [pc, #148] @ (800cb34 ) 800caa0: 69db ldr r3, [r3, #28] 800caa2: 4619 mov r1, r3 800caa4: 4827 ldr r0, [pc, #156] @ (800cb44 ) 800caa6: f000 f96b bl 800cd80 App_ReconfigureUart(g_cfg.uart_baudrate); 800caaa: 4b22 ldr r3, [pc, #136] @ (800cb34 ) 800caac: 69db ldr r3, [r3, #28] 800caae: 4618 mov r0, r3 800cab0: f000 f9ac bl 800ce0c return; 800cab4: e036 b.n 800cb24 } if (strncmp(line, "sync ", 5) == 0) 800cab6: 2205 movs r2, #5 800cab8: 4923 ldr r1, [pc, #140] @ (800cb48 ) 800caba: 6878 ldr r0, [r7, #4] 800cabc: f001 fe6c bl 800e798 800cac0: 4603 mov r3, r0 800cac2: 2b00 cmp r3, #0 800cac4: d128 bne.n 800cb18 { arg = App_SkipSpaces(&line[5]); 800cac6: 687b ldr r3, [r7, #4] 800cac8: 3305 adds r3, #5 800caca: 4618 mov r0, r3 800cacc: f000 fa4c bl 800cf68 800cad0: 6178 str r0, [r7, #20] if (App_ParseHexSyncWord(arg, sync) == 0U) 800cad2: f107 0308 add.w r3, r7, #8 800cad6: 4619 mov r1, r3 800cad8: 6978 ldr r0, [r7, #20] 800cada: f000 f9cf bl 800ce7c 800cade: 4603 mov r3, r0 800cae0: 2b00 cmp r3, #0 800cae2: d103 bne.n 800caec { App_Printf("bad sync, use 6 hex chars, e.g. C194C1\r\n"); 800cae4: 4819 ldr r0, [pc, #100] @ (800cb4c ) 800cae6: f000 f94b bl 800cd80 return; 800caea: e01b b.n 800cb24 } memcpy(g_cfg.syncword, sync, sizeof(sync)); 800caec: 4b11 ldr r3, [pc, #68] @ (800cb34 ) 800caee: 3316 adds r3, #22 800caf0: f107 0208 add.w r2, r7, #8 800caf4: 8811 ldrh r1, [r2, #0] 800caf6: 7892 ldrb r2, [r2, #2] 800caf8: 8019 strh r1, [r3, #0] 800cafa: 709a strb r2, [r3, #2] App_RadioApplyConfig(); 800cafc: f7ff fb18 bl 800c130 App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); 800cb00: 4b0c ldr r3, [pc, #48] @ (800cb34 ) 800cb02: 7d9b ldrb r3, [r3, #22] 800cb04: 4619 mov r1, r3 800cb06: 4b0b ldr r3, [pc, #44] @ (800cb34 ) 800cb08: 7ddb ldrb r3, [r3, #23] 800cb0a: 461a mov r2, r3 800cb0c: 4b09 ldr r3, [pc, #36] @ (800cb34 ) 800cb0e: 7e1b ldrb r3, [r3, #24] 800cb10: 480f ldr r0, [pc, #60] @ (800cb50 ) 800cb12: f000 f935 bl 800cd80 return; 800cb16: e005 b.n 800cb24 } App_Printf("unknown command: %s\r\n", line); 800cb18: 6879 ldr r1, [r7, #4] 800cb1a: 480e ldr r0, [pc, #56] @ (800cb54 ) 800cb1c: f000 f930 bl 800cd80 800cb20: e000 b.n 800cb24 return; 800cb22: bf00 nop } 800cb24: 3718 adds r7, #24 800cb26: 46bd mov sp, r7 800cb28: bd80 pop {r7, pc} 800cb2a: bf00 nop 800cb2c: 0800f4fc .word 0x0800f4fc 800cb30: 0800f508 .word 0x0800f508 800cb34: 2000000c .word 0x2000000c 800cb38: 0800f518 .word 0x0800f518 800cb3c: 0800f528 .word 0x0800f528 800cb40: 0800f530 .word 0x0800f530 800cb44: 0800f544 .word 0x0800f544 800cb48: 0800f564 .word 0x0800f564 800cb4c: 0800f56c .word 0x0800f56c 800cb50: 0800f598 .word 0x0800f598 800cb54: 0800f5ac .word 0x0800f5ac 0800cb58 : static void App_PrintConfigPrompt(void) { 800cb58: b580 push {r7, lr} 800cb5a: af00 add r7, sp, #0 if (g_mode == APP_MODE_CONFIG) 800cb5c: 4b04 ldr r3, [pc, #16] @ (800cb70 ) 800cb5e: 781b ldrb r3, [r3, #0] 800cb60: 2b01 cmp r3, #1 800cb62: d102 bne.n 800cb6a { App_Printf("cfg> "); 800cb64: 4803 ldr r0, [pc, #12] @ (800cb74 ) 800cb66: f000 f90b bl 800cd80 } } 800cb6a: bf00 nop 800cb6c: bd80 pop {r7, pc} 800cb6e: bf00 nop 800cb70: 20000b64 .word 0x20000b64 800cb74: 0800f5c4 .word 0x0800f5c4 0800cb78 : static void App_PrintHelp(void) { 800cb78: b580 push {r7, lr} 800cb7a: af00 add r7, sp, #0 App_Printf("commands:\r\n"); 800cb7c: 4815 ldr r0, [pc, #84] @ (800cbd4 ) 800cb7e: f000 f8ff bl 800cd80 App_Printf(" help - this help\r\n"); 800cb82: 4815 ldr r0, [pc, #84] @ (800cbd8 ) 800cb84: f000 f8fc bl 800cd80 App_Printf(" show - current config and counters\r\n"); 800cb88: 4814 ldr r0, [pc, #80] @ (800cbdc ) 800cb8a: f000 f8f9 bl 800cd80 App_Printf(" freq - rf frequency\r\n"); 800cb8e: 4814 ldr r0, [pc, #80] @ (800cbe0 ) 800cb90: f000 f8f6 bl 800cd80 App_Printf(" power - tx power (-9..22)\r\n"); 800cb94: 4813 ldr r0, [pc, #76] @ (800cbe4 ) 800cb96: f000 f8f3 bl 800cd80 App_Printf(" bitrate - fsk bitrate\r\n"); 800cb9a: 4813 ldr r0, [pc, #76] @ (800cbe8 ) 800cb9c: f000 f8f0 bl 800cd80 App_Printf(" bandwidth - fsk rx bandwidth\r\n"); 800cba0: 4812 ldr r0, [pc, #72] @ (800cbec ) 800cba2: f000 f8ed bl 800cd80 App_Printf(" fdev - fsk frequency deviation\r\n"); 800cba6: 4812 ldr r0, [pc, #72] @ (800cbf0 ) 800cba8: f000 f8ea bl 800cd80 App_Printf(" preamble - fsk preamble length\r\n"); 800cbac: 4811 ldr r0, [pc, #68] @ (800cbf4 ) 800cbae: f000 f8e7 bl 800cd80 App_Printf(" sync - 3-byte syncword, example C194C1\r\n"); 800cbb2: 4811 ldr r0, [pc, #68] @ (800cbf8 ) 800cbb4: f000 f8e4 bl 800cd80 App_Printf(" timeout - uart silence before rf packet send\r\n"); 800cbb8: 4810 ldr r0, [pc, #64] @ (800cbfc ) 800cbba: f000 f8e1 bl 800cd80 App_Printf(" uart - change uart baudrate immediately\r\n"); 800cbbe: 4810 ldr r0, [pc, #64] @ (800cc00 ) 800cbc0: f000 f8de bl 800cd80 App_Printf(" defaults - restore default config\r\n"); 800cbc4: 480f ldr r0, [pc, #60] @ (800cc04 ) 800cbc6: f000 f8db bl 800cd80 App_Printf(" exit - return to transparent bridge mode\r\n"); 800cbca: 480f ldr r0, [pc, #60] @ (800cc08 ) 800cbcc: f000 f8d8 bl 800cd80 } 800cbd0: bf00 nop 800cbd2: bd80 pop {r7, pc} 800cbd4: 0800f5cc .word 0x0800f5cc 800cbd8: 0800f5d8 .word 0x0800f5d8 800cbdc: 0800f600 .word 0x0800f600 800cbe0: 0800f638 .word 0x0800f638 800cbe4: 0800f660 .word 0x0800f660 800cbe8: 0800f690 .word 0x0800f690 800cbec: 0800f6b8 .word 0x0800f6b8 800cbf0: 0800f6e4 .word 0x0800f6e4 800cbf4: 0800f718 .word 0x0800f718 800cbf8: 0800f748 .word 0x0800f748 800cbfc: 0800f784 .word 0x0800f784 800cc00: 0800f7c4 .word 0x0800f7c4 800cc04: 0800f800 .word 0x0800f800 800cc08: 0800f834 .word 0x0800f834 0800cc0c : static void App_PrintStatus(void) { 800cc0c: b580 push {r7, lr} 800cc0e: af00 add r7, sp, #0 App_Printf("mode=%s\r\n", (g_mode == APP_MODE_CONFIG) ? "config" : "data"); 800cc10: 4b3d ldr r3, [pc, #244] @ (800cd08 ) 800cc12: 781b ldrb r3, [r3, #0] 800cc14: 2b01 cmp r3, #1 800cc16: d101 bne.n 800cc1c 800cc18: 4b3c ldr r3, [pc, #240] @ (800cd0c ) 800cc1a: e000 b.n 800cc1e 800cc1c: 4b3c ldr r3, [pc, #240] @ (800cd10 ) 800cc1e: 4619 mov r1, r3 800cc20: 483c ldr r0, [pc, #240] @ (800cd14 ) 800cc22: f000 f8ad bl 800cd80 App_Printf("freq=%lu Hz\r\n", (unsigned long)g_cfg.rf_frequency); 800cc26: 4b3c ldr r3, [pc, #240] @ (800cd18 ) 800cc28: 681b ldr r3, [r3, #0] 800cc2a: 4619 mov r1, r3 800cc2c: 483b ldr r0, [pc, #236] @ (800cd1c ) 800cc2e: f000 f8a7 bl 800cd80 App_Printf("power=%d dBm\r\n", g_cfg.tx_power); 800cc32: 4b39 ldr r3, [pc, #228] @ (800cd18 ) 800cc34: f993 3004 ldrsb.w r3, [r3, #4] 800cc38: 4619 mov r1, r3 800cc3a: 4839 ldr r0, [pc, #228] @ (800cd20 ) 800cc3c: f000 f8a0 bl 800cd80 App_Printf("bitrate=%lu bps\r\n", (unsigned long)g_cfg.fsk_bitrate); 800cc40: 4b35 ldr r3, [pc, #212] @ (800cd18 ) 800cc42: 689b ldr r3, [r3, #8] 800cc44: 4619 mov r1, r3 800cc46: 4837 ldr r0, [pc, #220] @ (800cd24 ) 800cc48: f000 f89a bl 800cd80 App_Printf("bandwidth=%lu Hz\r\n", (unsigned long)g_cfg.fsk_bandwidth); 800cc4c: 4b32 ldr r3, [pc, #200] @ (800cd18 ) 800cc4e: 68db ldr r3, [r3, #12] 800cc50: 4619 mov r1, r3 800cc52: 4835 ldr r0, [pc, #212] @ (800cd28 ) 800cc54: f000 f894 bl 800cd80 App_Printf("fdev=%lu Hz\r\n", (unsigned long)g_cfg.fsk_fdev); 800cc58: 4b2f ldr r3, [pc, #188] @ (800cd18 ) 800cc5a: 691b ldr r3, [r3, #16] 800cc5c: 4619 mov r1, r3 800cc5e: 4833 ldr r0, [pc, #204] @ (800cd2c ) 800cc60: f000 f88e bl 800cd80 App_Printf("preamble=%u bytes\r\n", g_cfg.fsk_preamble_len); 800cc64: 4b2c ldr r3, [pc, #176] @ (800cd18 ) 800cc66: 8a9b ldrh r3, [r3, #20] 800cc68: 4619 mov r1, r3 800cc6a: 4831 ldr r0, [pc, #196] @ (800cd30 ) 800cc6c: f000 f888 bl 800cd80 App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); 800cc70: 4b29 ldr r3, [pc, #164] @ (800cd18 ) 800cc72: 7d9b ldrb r3, [r3, #22] 800cc74: 4619 mov r1, r3 800cc76: 4b28 ldr r3, [pc, #160] @ (800cd18 ) 800cc78: 7ddb ldrb r3, [r3, #23] 800cc7a: 461a mov r2, r3 800cc7c: 4b26 ldr r3, [pc, #152] @ (800cd18 ) 800cc7e: 7e1b ldrb r3, [r3, #24] 800cc80: 482c ldr r0, [pc, #176] @ (800cd34 ) 800cc82: f000 f87d bl 800cd80 App_Printf("uart_baud=%lu\r\n", (unsigned long)g_cfg.uart_baudrate); 800cc86: 4b24 ldr r3, [pc, #144] @ (800cd18 ) 800cc88: 69db ldr r3, [r3, #28] 800cc8a: 4619 mov r1, r3 800cc8c: 482a ldr r0, [pc, #168] @ (800cd38 ) 800cc8e: f000 f877 bl 800cd80 App_Printf("uart_pkt_timeout=%u ms\r\n", g_cfg.uart_packet_timeout_ms); 800cc92: 4b21 ldr r3, [pc, #132] @ (800cd18 ) 800cc94: 8b5b ldrh r3, [r3, #26] 800cc96: 4619 mov r1, r3 800cc98: 4828 ldr r0, [pc, #160] @ (800cd3c ) 800cc9a: f000 f871 bl 800cd80 App_Printf("tx_queue=%u/%u\r\n", g_tx_q_count, TX_QUEUE_DEPTH); 800cc9e: 4b28 ldr r3, [pc, #160] @ (800cd40 ) 800cca0: 781b ldrb r3, [r3, #0] 800cca2: 2204 movs r2, #4 800cca4: 4619 mov r1, r3 800cca6: 4827 ldr r0, [pc, #156] @ (800cd44 ) 800cca8: f000 f86a bl 800cd80 App_Printf("last_rx_rssi=%d dBm\r\n", (int)g_last_rx_rssi); 800ccac: 4b26 ldr r3, [pc, #152] @ (800cd48 ) 800ccae: 881b ldrh r3, [r3, #0] 800ccb0: b21b sxth r3, r3 800ccb2: 4619 mov r1, r3 800ccb4: 4825 ldr r0, [pc, #148] @ (800cd4c ) 800ccb6: f000 f863 bl 800cd80 App_Printf("last_rx_cfo=%d\r\n", (int)g_last_rx_cfo); 800ccba: 4b25 ldr r3, [pc, #148] @ (800cd50 ) 800ccbc: 781b ldrb r3, [r3, #0] 800ccbe: b25b sxtb r3, r3 800ccc0: 4619 mov r1, r3 800ccc2: 4824 ldr r0, [pc, #144] @ (800cd54 ) 800ccc4: f000 f85c bl 800cd80 App_Printf("stat_uart_packets_tx=%lu\r\n", (unsigned long)g_stat_uart_packets_tx); 800ccc8: 4b23 ldr r3, [pc, #140] @ (800cd58 ) 800ccca: 681b ldr r3, [r3, #0] 800cccc: 4619 mov r1, r3 800ccce: 4823 ldr r0, [pc, #140] @ (800cd5c ) 800ccd0: f000 f856 bl 800cd80 App_Printf("stat_uart_bytes_tx=%lu\r\n", (unsigned long)g_stat_uart_bytes_tx); 800ccd4: 4b22 ldr r3, [pc, #136] @ (800cd60 ) 800ccd6: 681b ldr r3, [r3, #0] 800ccd8: 4619 mov r1, r3 800ccda: 4822 ldr r0, [pc, #136] @ (800cd64 ) 800ccdc: f000 f850 bl 800cd80 App_Printf("stat_radio_packets_rx=%lu\r\n", (unsigned long)g_stat_radio_packets_rx); 800cce0: 4b21 ldr r3, [pc, #132] @ (800cd68 ) 800cce2: 681b ldr r3, [r3, #0] 800cce4: 4619 mov r1, r3 800cce6: 4821 ldr r0, [pc, #132] @ (800cd6c ) 800cce8: f000 f84a bl 800cd80 App_Printf("stat_radio_bytes_rx=%lu\r\n", (unsigned long)g_stat_radio_bytes_rx); 800ccec: 4b20 ldr r3, [pc, #128] @ (800cd70 ) 800ccee: 681b ldr r3, [r3, #0] 800ccf0: 4619 mov r1, r3 800ccf2: 4820 ldr r0, [pc, #128] @ (800cd74 ) 800ccf4: f000 f844 bl 800cd80 App_Printf("stat_queue_overflow=%lu\r\n", (unsigned long)g_stat_queue_overflow); 800ccf8: 4b1f ldr r3, [pc, #124] @ (800cd78 ) 800ccfa: 681b ldr r3, [r3, #0] 800ccfc: 4619 mov r1, r3 800ccfe: 481f ldr r0, [pc, #124] @ (800cd7c ) 800cd00: f000 f83e bl 800cd80 } 800cd04: bf00 nop 800cd06: bd80 pop {r7, pc} 800cd08: 20000b64 .word 0x20000b64 800cd0c: 0800f874 .word 0x0800f874 800cd10: 0800f87c .word 0x0800f87c 800cd14: 0800f884 .word 0x0800f884 800cd18: 2000000c .word 0x2000000c 800cd1c: 0800f890 .word 0x0800f890 800cd20: 0800f8a0 .word 0x0800f8a0 800cd24: 0800f8b0 .word 0x0800f8b0 800cd28: 0800f8c4 .word 0x0800f8c4 800cd2c: 0800f8d8 .word 0x0800f8d8 800cd30: 0800f8e8 .word 0x0800f8e8 800cd34: 0800f598 .word 0x0800f598 800cd38: 0800f8fc .word 0x0800f8fc 800cd3c: 0800f90c .word 0x0800f90c 800cd40: 20000a6e .word 0x20000a6e 800cd44: 0800f928 .word 0x0800f928 800cd48: 20000612 .word 0x20000612 800cd4c: 0800f93c .word 0x0800f93c 800cd50: 20000614 .word 0x20000614 800cd54: 0800f954 .word 0x0800f954 800cd58: 20000bcc .word 0x20000bcc 800cd5c: 0800f968 .word 0x0800f968 800cd60: 20000bd0 .word 0x20000bd0 800cd64: 0800f984 .word 0x0800f984 800cd68: 20000bd4 .word 0x20000bd4 800cd6c: 0800f9a0 .word 0x0800f9a0 800cd70: 20000bd8 .word 0x20000bd8 800cd74: 0800f9bc .word 0x0800f9bc 800cd78: 20000bdc .word 0x20000bdc 800cd7c: 0800f9d8 .word 0x0800f9d8 0800cd80 : static void App_Printf(const char *fmt, ...) { 800cd80: b40f push {r0, r1, r2, r3} 800cd82: b580 push {r7, lr} 800cd84: b0b2 sub sp, #200 @ 0xc8 800cd86: af00 add r7, sp, #0 char buffer[192]; va_list ap; int len; va_start(ap, fmt); 800cd88: f107 03d4 add.w r3, r7, #212 @ 0xd4 800cd8c: 603b str r3, [r7, #0] len = vsnprintf(buffer, sizeof(buffer), fmt, ap); 800cd8e: 1d38 adds r0, r7, #4 800cd90: 683b ldr r3, [r7, #0] 800cd92: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 800cd96: 21c0 movs r1, #192 @ 0xc0 800cd98: f001 fce8 bl 800e76c 800cd9c: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 va_end(ap); if (len <= 0) 800cda0: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800cda4: 2b00 cmp r3, #0 800cda6: dd0f ble.n 800cdc8 { return; } if ((size_t)len >= sizeof(buffer)) 800cda8: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800cdac: 2bbf cmp r3, #191 @ 0xbf 800cdae: d902 bls.n 800cdb6 { len = (int)(sizeof(buffer) - 1U); 800cdb0: 23bf movs r3, #191 @ 0xbf 800cdb2: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 } App_Write((const uint8_t *)buffer, (uint16_t)len); 800cdb6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800cdba: b29a uxth r2, r3 800cdbc: 1d3b adds r3, r7, #4 800cdbe: 4611 mov r1, r2 800cdc0: 4618 mov r0, r3 800cdc2: f000 f809 bl 800cdd8 800cdc6: e000 b.n 800cdca return; 800cdc8: bf00 nop } 800cdca: 37c8 adds r7, #200 @ 0xc8 800cdcc: 46bd mov sp, r7 800cdce: e8bd 4080 ldmia.w sp!, {r7, lr} 800cdd2: b004 add sp, #16 800cdd4: 4770 bx lr ... 0800cdd8 : static void App_Write(const uint8_t *data, uint16_t len) { 800cdd8: b580 push {r7, lr} 800cdda: b082 sub sp, #8 800cddc: af00 add r7, sp, #0 800cdde: 6078 str r0, [r7, #4] 800cde0: 460b mov r3, r1 800cde2: 807b strh r3, [r7, #2] if ((data == NULL) || (len == 0U)) 800cde4: 687b ldr r3, [r7, #4] 800cde6: 2b00 cmp r3, #0 800cde8: d00a beq.n 800ce00 800cdea: 887b ldrh r3, [r7, #2] 800cdec: 2b00 cmp r3, #0 800cdee: d007 beq.n 800ce00 { return; } (void)HAL_UART_Transmit(&huart2, (uint8_t *)data, len, 1000U); 800cdf0: 887a ldrh r2, [r7, #2] 800cdf2: f44f 737a mov.w r3, #1000 @ 0x3e8 800cdf6: 6879 ldr r1, [r7, #4] 800cdf8: 4803 ldr r0, [pc, #12] @ (800ce08 ) 800cdfa: f7f8 fa26 bl 800524a 800cdfe: e000 b.n 800ce02 return; 800ce00: bf00 nop } 800ce02: 3708 adds r7, #8 800ce04: 46bd mov sp, r7 800ce06: bd80 pop {r7, pc} 800ce08: 200000fc .word 0x200000fc 0800ce0c : static void App_ReconfigureUart(uint32_t baudrate) { 800ce0c: b580 push {r7, lr} 800ce0e: b082 sub sp, #8 800ce10: af00 add r7, sp, #0 800ce12: 6078 str r0, [r7, #4] huart2.Init.BaudRate = baudrate; 800ce14: 4a17 ldr r2, [pc, #92] @ (800ce74 ) 800ce16: 687b ldr r3, [r7, #4] 800ce18: 6053 str r3, [r2, #4] (void)HAL_UART_AbortReceive(&huart2); 800ce1a: 4816 ldr r0, [pc, #88] @ (800ce74 ) 800ce1c: f7f8 fb7a bl 8005514 if (HAL_UART_Init(&huart2) != HAL_OK) 800ce20: 4814 ldr r0, [pc, #80] @ (800ce74 ) 800ce22: f7f8 f9c2 bl 80051aa 800ce26: 4603 mov r3, r0 800ce28: 2b00 cmp r3, #0 800ce2a: d001 beq.n 800ce30 { Error_Handler(); 800ce2c: f7f3 fcd0 bl 80007d0 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 800ce30: 2100 movs r1, #0 800ce32: 4810 ldr r0, [pc, #64] @ (800ce74 ) 800ce34: f7fa fc3d bl 80076b2 800ce38: 4603 mov r3, r0 800ce3a: 2b00 cmp r3, #0 800ce3c: d001 beq.n 800ce42 { Error_Handler(); 800ce3e: f7f3 fcc7 bl 80007d0 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800ce42: 2100 movs r1, #0 800ce44: 480b ldr r0, [pc, #44] @ (800ce74 ) 800ce46: f7fa fc72 bl 800772e 800ce4a: 4603 mov r3, r0 800ce4c: 2b00 cmp r3, #0 800ce4e: d001 beq.n 800ce54 { Error_Handler(); 800ce50: f7f3 fcbe bl 80007d0 } if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) 800ce54: 4807 ldr r0, [pc, #28] @ (800ce74 ) 800ce56: f7fa fbf1 bl 800763c 800ce5a: 4603 mov r3, r0 800ce5c: 2b00 cmp r3, #0 800ce5e: d001 beq.n 800ce64 { Error_Handler(); 800ce60: f7f3 fcb6 bl 80007d0 } (void)vcom_ReceiveInit(UartRxByteCallback); 800ce64: 4804 ldr r0, [pc, #16] @ (800ce78 ) 800ce66: f7f4 fba1 bl 80015ac } 800ce6a: bf00 nop 800ce6c: 3708 adds r7, #8 800ce6e: 46bd mov sp, r7 800ce70: bd80 pop {r7, pc} 800ce72: bf00 nop 800ce74: 200000fc .word 0x200000fc 800ce78: 0800c4e5 .word 0x0800c4e5 0800ce7c : static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]) { 800ce7c: b580 push {r7, lr} 800ce7e: b088 sub sp, #32 800ce80: af00 add r7, sp, #0 800ce82: 6078 str r0, [r7, #4] 800ce84: 6039 str r1, [r7, #0] char buf[7]; char *endptr; unsigned long value; size_t i; size_t n = 0U; 800ce86: 2300 movs r3, #0 800ce88: 61bb str r3, [r7, #24] if ((text == NULL) || (out == NULL)) 800ce8a: 687b ldr r3, [r7, #4] 800ce8c: 2b00 cmp r3, #0 800ce8e: d002 beq.n 800ce96 800ce90: 683b ldr r3, [r7, #0] 800ce92: 2b00 cmp r3, #0 800ce94: d117 bne.n 800cec6 { return 0U; 800ce96: 2300 movs r3, #0 800ce98: e05f b.n 800cf5a } while ((*text != '\0') && (n < 6U)) { if (isxdigit((unsigned char)*text) != 0) 800ce9a: 687b ldr r3, [r7, #4] 800ce9c: 781b ldrb r3, [r3, #0] 800ce9e: 3301 adds r3, #1 800cea0: 4a30 ldr r2, [pc, #192] @ (800cf64 ) 800cea2: 4413 add r3, r2 800cea4: 781b ldrb r3, [r3, #0] 800cea6: f003 0344 and.w r3, r3, #68 @ 0x44 800ceaa: 2b00 cmp r3, #0 800ceac: d008 beq.n 800cec0 { buf[n++] = *text; 800ceae: 69bb ldr r3, [r7, #24] 800ceb0: 1c5a adds r2, r3, #1 800ceb2: 61ba str r2, [r7, #24] 800ceb4: 687a ldr r2, [r7, #4] 800ceb6: 7812 ldrb r2, [r2, #0] 800ceb8: 3320 adds r3, #32 800ceba: 443b add r3, r7 800cebc: f803 2c14 strb.w r2, [r3, #-20] } text++; 800cec0: 687b ldr r3, [r7, #4] 800cec2: 3301 adds r3, #1 800cec4: 607b str r3, [r7, #4] while ((*text != '\0') && (n < 6U)) 800cec6: 687b ldr r3, [r7, #4] 800cec8: 781b ldrb r3, [r3, #0] 800ceca: 2b00 cmp r3, #0 800cecc: d002 beq.n 800ced4 800cece: 69bb ldr r3, [r7, #24] 800ced0: 2b05 cmp r3, #5 800ced2: d9e2 bls.n 800ce9a } if (n != 6U) 800ced4: 69bb ldr r3, [r7, #24] 800ced6: 2b06 cmp r3, #6 800ced8: d001 beq.n 800cede { return 0U; 800ceda: 2300 movs r3, #0 800cedc: e03d b.n 800cf5a } for (i = 0U; i < n; i++) 800cede: 2300 movs r3, #0 800cee0: 61fb str r3, [r7, #28] 800cee2: e011 b.n 800cf08 { if (isxdigit((unsigned char)buf[i]) == 0) 800cee4: f107 020c add.w r2, r7, #12 800cee8: 69fb ldr r3, [r7, #28] 800ceea: 4413 add r3, r2 800ceec: 781b ldrb r3, [r3, #0] 800ceee: 3301 adds r3, #1 800cef0: 4a1c ldr r2, [pc, #112] @ (800cf64 ) 800cef2: 4413 add r3, r2 800cef4: 781b ldrb r3, [r3, #0] 800cef6: f003 0344 and.w r3, r3, #68 @ 0x44 800cefa: 2b00 cmp r3, #0 800cefc: d101 bne.n 800cf02 { return 0U; 800cefe: 2300 movs r3, #0 800cf00: e02b b.n 800cf5a for (i = 0U; i < n; i++) 800cf02: 69fb ldr r3, [r7, #28] 800cf04: 3301 adds r3, #1 800cf06: 61fb str r3, [r7, #28] 800cf08: 69fa ldr r2, [r7, #28] 800cf0a: 69bb ldr r3, [r7, #24] 800cf0c: 429a cmp r2, r3 800cf0e: d3e9 bcc.n 800cee4 } } buf[6] = '\0'; 800cf10: 2300 movs r3, #0 800cf12: 74bb strb r3, [r7, #18] value = strtoul(buf, &endptr, 16); 800cf14: f107 0108 add.w r1, r7, #8 800cf18: f107 030c add.w r3, r7, #12 800cf1c: 2210 movs r2, #16 800cf1e: 4618 mov r0, r3 800cf20: f001 fbec bl 800e6fc 800cf24: 6178 str r0, [r7, #20] if ((endptr == NULL) || (*endptr != '\0')) 800cf26: 68bb ldr r3, [r7, #8] 800cf28: 2b00 cmp r3, #0 800cf2a: d003 beq.n 800cf34 800cf2c: 68bb ldr r3, [r7, #8] 800cf2e: 781b ldrb r3, [r3, #0] 800cf30: 2b00 cmp r3, #0 800cf32: d001 beq.n 800cf38 { return 0U; 800cf34: 2300 movs r3, #0 800cf36: e010 b.n 800cf5a } out[0] = (uint8_t)((value >> 16) & 0xFFU); 800cf38: 697b ldr r3, [r7, #20] 800cf3a: 0c1b lsrs r3, r3, #16 800cf3c: b2da uxtb r2, r3 800cf3e: 683b ldr r3, [r7, #0] 800cf40: 701a strb r2, [r3, #0] out[1] = (uint8_t)((value >> 8) & 0xFFU); 800cf42: 697b ldr r3, [r7, #20] 800cf44: 0a1a lsrs r2, r3, #8 800cf46: 683b ldr r3, [r7, #0] 800cf48: 3301 adds r3, #1 800cf4a: b2d2 uxtb r2, r2 800cf4c: 701a strb r2, [r3, #0] out[2] = (uint8_t)(value & 0xFFU); 800cf4e: 683b ldr r3, [r7, #0] 800cf50: 3302 adds r3, #2 800cf52: 697a ldr r2, [r7, #20] 800cf54: b2d2 uxtb r2, r2 800cf56: 701a strb r2, [r3, #0] return 1U; 800cf58: 2301 movs r3, #1 } 800cf5a: 4618 mov r0, r3 800cf5c: 3720 adds r7, #32 800cf5e: 46bd mov sp, r7 800cf60: bd80 pop {r7, pc} 800cf62: bf00 nop 800cf64: 0800fccc .word 0x0800fccc 0800cf68 : static char *App_SkipSpaces(char *s) { 800cf68: b480 push {r7} 800cf6a: b083 sub sp, #12 800cf6c: af00 add r7, sp, #0 800cf6e: 6078 str r0, [r7, #4] while ((s != NULL) && (*s != '\0') && isspace((unsigned char)*s)) 800cf70: e002 b.n 800cf78 { s++; 800cf72: 687b ldr r3, [r7, #4] 800cf74: 3301 adds r3, #1 800cf76: 607b str r3, [r7, #4] while ((s != NULL) && (*s != '\0') && isspace((unsigned char)*s)) 800cf78: 687b ldr r3, [r7, #4] 800cf7a: 2b00 cmp r3, #0 800cf7c: d00d beq.n 800cf9a 800cf7e: 687b ldr r3, [r7, #4] 800cf80: 781b ldrb r3, [r3, #0] 800cf82: 2b00 cmp r3, #0 800cf84: d009 beq.n 800cf9a 800cf86: 687b ldr r3, [r7, #4] 800cf88: 781b ldrb r3, [r3, #0] 800cf8a: 3301 adds r3, #1 800cf8c: 4a06 ldr r2, [pc, #24] @ (800cfa8 ) 800cf8e: 4413 add r3, r2 800cf90: 781b ldrb r3, [r3, #0] 800cf92: f003 0308 and.w r3, r3, #8 800cf96: 2b00 cmp r3, #0 800cf98: d1eb bne.n 800cf72 } return s; 800cf9a: 687b ldr r3, [r7, #4] } 800cf9c: 4618 mov r0, r3 800cf9e: 370c adds r7, #12 800cfa0: 46bd mov sp, r7 800cfa2: bc80 pop {r7} 800cfa4: 4770 bx lr 800cfa6: bf00 nop 800cfa8: 0800fccc .word 0x0800fccc 0800cfac : static void OnTxDone(void) { 800cfac: b480 push {r7} 800cfae: af00 add r7, sp, #0 g_radio_tx_done = 1U; 800cfb0: 4b03 ldr r3, [pc, #12] @ (800cfc0 ) 800cfb2: 2201 movs r2, #1 800cfb4: 701a strb r2, [r3, #0] } 800cfb6: bf00 nop 800cfb8: 46bd mov sp, r7 800cfba: bc80 pop {r7} 800cfbc: 4770 bx lr 800cfbe: bf00 nop 800cfc0: 2000060c .word 0x2000060c 0800cfc4 : static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t cfo) { 800cfc4: b580 push {r7, lr} 800cfc6: b084 sub sp, #16 800cfc8: af00 add r7, sp, #0 800cfca: 60f8 str r0, [r7, #12] 800cfcc: 4608 mov r0, r1 800cfce: 4611 mov r1, r2 800cfd0: 461a mov r2, r3 800cfd2: 4603 mov r3, r0 800cfd4: 817b strh r3, [r7, #10] 800cfd6: 460b mov r3, r1 800cfd8: 813b strh r3, [r7, #8] 800cfda: 4613 mov r3, r2 800cfdc: 71fb strb r3, [r7, #7] g_last_rx_rssi = rssi; 800cfde: 4a0d ldr r2, [pc, #52] @ (800d014 ) 800cfe0: 893b ldrh r3, [r7, #8] 800cfe2: 8013 strh r3, [r2, #0] g_last_rx_cfo = cfo; 800cfe4: 4a0c ldr r2, [pc, #48] @ (800d018 ) 800cfe6: 79fb ldrb r3, [r7, #7] 800cfe8: 7013 strb r3, [r2, #0] if (size > RADIO_MAX_PAYLOAD_SIZE) 800cfea: 897b ldrh r3, [r7, #10] 800cfec: 2bdc cmp r3, #220 @ 0xdc 800cfee: d901 bls.n 800cff4 { size = RADIO_MAX_PAYLOAD_SIZE; 800cff0: 23dc movs r3, #220 @ 0xdc 800cff2: 817b strh r3, [r7, #10] } memcpy(g_rx_payload, payload, size); 800cff4: 897b ldrh r3, [r7, #10] 800cff6: 461a mov r2, r3 800cff8: 68f9 ldr r1, [r7, #12] 800cffa: 4808 ldr r0, [pc, #32] @ (800d01c ) 800cffc: f001 fc0a bl 800e814 g_rx_payload_len = size; 800d000: 4a07 ldr r2, [pc, #28] @ (800d020 ) 800d002: 897b ldrh r3, [r7, #10] 800d004: 8013 strh r3, [r2, #0] g_radio_rx_done = 1U; 800d006: 4b07 ldr r3, [pc, #28] @ (800d024 ) 800d008: 2201 movs r2, #1 800d00a: 701a strb r2, [r3, #0] } 800d00c: bf00 nop 800d00e: 3710 adds r7, #16 800d010: 46bd mov sp, r7 800d012: bd80 pop {r7, pc} 800d014: 20000612 .word 0x20000612 800d018: 20000614 .word 0x20000614 800d01c: 20000618 .word 0x20000618 800d020: 200006f4 .word 0x200006f4 800d024: 2000060e .word 0x2000060e 0800d028 : static void OnTxTimeout(void) { 800d028: b480 push {r7} 800d02a: af00 add r7, sp, #0 g_radio_tx_timeout = 1U; 800d02c: 4b03 ldr r3, [pc, #12] @ (800d03c ) 800d02e: 2201 movs r2, #1 800d030: 701a strb r2, [r3, #0] } 800d032: bf00 nop 800d034: 46bd mov sp, r7 800d036: bc80 pop {r7} 800d038: 4770 bx lr 800d03a: bf00 nop 800d03c: 2000060d .word 0x2000060d 0800d040 : static void OnRxTimeout(void) { 800d040: b480 push {r7} 800d042: af00 add r7, sp, #0 g_radio_rx_timeout = 1U; 800d044: 4b03 ldr r3, [pc, #12] @ (800d054 ) 800d046: 2201 movs r2, #1 800d048: 701a strb r2, [r3, #0] } 800d04a: bf00 nop 800d04c: 46bd mov sp, r7 800d04e: bc80 pop {r7} 800d050: 4770 bx lr 800d052: bf00 nop 800d054: 2000060f .word 0x2000060f 0800d058 : static void OnRxError(void) { 800d058: b480 push {r7} 800d05a: af00 add r7, sp, #0 g_radio_rx_error = 1U; 800d05c: 4b03 ldr r3, [pc, #12] @ (800d06c ) 800d05e: 2201 movs r2, #1 800d060: 701a strb r2, [r3, #0] } 800d062: bf00 nop 800d064: 46bd mov sp, r7 800d066: bc80 pop {r7} 800d068: 4770 bx lr 800d06a: bf00 nop 800d06c: 20000610 .word 0x20000610 0800d070 : /* USER CODE END PFP */ /* Exported functions --------------------------------------------------------*/ int32_t RBI_Init(void) { 800d070: b580 push {r7, lr} 800d072: af00 add r7, sp, #0 * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_Init(); 800d074: f7f4 fb70 bl 8001758 800d078: 4603 mov r3, r0 /* USER CODE BEGIN RBI_Init_2 */ #warning user to provide its board code or to call his board driver functions /* USER CODE END RBI_Init_2 */ return retcode; #endif /* USE_BSP_DRIVER */ } 800d07a: 4618 mov r0, r3 800d07c: bd80 pop {r7, pc} 0800d07e : return retcode; #endif /* USE_BSP_DRIVER */ } int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config) { 800d07e: b580 push {r7, lr} 800d080: b082 sub sp, #8 800d082: af00 add r7, sp, #0 800d084: 4603 mov r3, r0 800d086: 71fb strb r3, [r7, #7] * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config); 800d088: 79fb ldrb r3, [r7, #7] 800d08a: 4618 mov r0, r3 800d08c: f7f4 fba2 bl 80017d4 800d090: 4603 mov r3, r0 /* USER CODE BEGIN RBI_ConfigRFSwitch_2 */ #warning user to provide its board code or to call his board driver functions /* USER CODE END RBI_ConfigRFSwitch_2 */ return retcode; #endif /* USE_BSP_DRIVER */ } 800d092: 4618 mov r0, r3 800d094: 3708 adds r7, #8 800d096: 46bd mov sp, r7 800d098: bd80 pop {r7, pc} 0800d09a : int32_t RBI_GetTxConfig(void) { 800d09a: b580 push {r7, lr} 800d09c: af00 add r7, sp, #0 * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_GetTxConfig(); 800d09e: f7f4 fbf5 bl 800188c 800d0a2: 4603 mov r3, r0 /* USER CODE BEGIN RBI_GetTxConfig_2 */ #warning user to provide its board code or to call his board driver functions /* USER CODE END RBI_GetTxConfig_2 */ return retcode; #endif /* USE_BSP_DRIVER */ } 800d0a4: 4618 mov r0, r3 800d0a6: bd80 pop {r7, pc} 0800d0a8 : int32_t RBI_IsTCXO(void) { 800d0a8: b580 push {r7, lr} 800d0aa: af00 add r7, sp, #0 * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_IsTCXO(); 800d0ac: f7f4 fbf5 bl 800189a 800d0b0: 4603 mov r3, r0 /* USER CODE BEGIN RBI_IsTCXO_2 */ #warning user to provide its board code or to call his board driver functions /* USER CODE END RBI_IsTCXO_2 */ return retcode; #endif /* USE_BSP_DRIVER */ } 800d0b2: 4618 mov r0, r3 800d0b4: bd80 pop {r7, pc} 0800d0b6 : int32_t RBI_IsDCDC(void) { 800d0b6: b580 push {r7, lr} 800d0b8: af00 add r7, sp, #0 * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_IsDCDC(); 800d0ba: f7f4 fbf5 bl 80018a8 800d0be: 4603 mov r3, r0 /* USER CODE BEGIN RBI_IsDCDC_2 */ #warning user to provide its board code or to call his board driver functions /* USER CODE END RBI_IsDCDC_2 */ return retcode; #endif /* USE_BSP_DRIVER */ } 800d0c0: 4618 mov r0, r3 800d0c2: bd80 pop {r7, pc} 0800d0c4 : int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config) { 800d0c4: b580 push {r7, lr} 800d0c6: b082 sub sp, #8 800d0c8: af00 add r7, sp, #0 800d0ca: 4603 mov r3, r0 800d0cc: 71fb strb r3, [r7, #7] * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: * on board RF switch configuration (pin control, number of port etc) * on TCXO configuration * on DC/DC configuration * on maximum output power that the board can deliver*/ return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config); 800d0ce: 79fb ldrb r3, [r7, #7] 800d0d0: 4618 mov r0, r3 800d0d2: f7f4 fbf0 bl 80018b6 800d0d6: 4603 mov r3, r0 ret = 22; /*dBm*/ } /* USER CODE END RBI_GetRFOMaxPowerConfig_2 */ return ret; #endif /* USE_BSP_DRIVER */ } 800d0d8: 4618 mov r0, r3 800d0da: 3708 adds r7, #8 800d0dc: 46bd mov sp, r7 800d0de: bd80 pop {r7, pc} 0800d0e0 : /** @addtogroup TINY_LPM_Exported_function * @{ */ void UTIL_LPM_Init( void ) { 800d0e0: b480 push {r7} 800d0e2: af00 add r7, sp, #0 StopModeDisable = UTIL_LPM_NO_BIT_SET; 800d0e4: 4b04 ldr r3, [pc, #16] @ (800d0f8 ) 800d0e6: 2200 movs r2, #0 800d0e8: 601a str r2, [r3, #0] OffModeDisable = UTIL_LPM_NO_BIT_SET; 800d0ea: 4b04 ldr r3, [pc, #16] @ (800d0fc ) 800d0ec: 2200 movs r2, #0 800d0ee: 601a str r2, [r3, #0] UTIL_LPM_INIT_CRITICAL_SECTION( ); } 800d0f0: bf00 nop 800d0f2: 46bd mov sp, r7 800d0f4: bc80 pop {r7} 800d0f6: 4770 bx lr 800d0f8: 20000be0 .word 0x20000be0 800d0fc: 20000be4 .word 0x20000be4 0800d100 : void UTIL_LPM_DeInit( void ) { } void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) { 800d100: b480 push {r7} 800d102: b087 sub sp, #28 800d104: af00 add r7, sp, #0 800d106: 6078 str r0, [r7, #4] 800d108: 460b mov r3, r1 800d10a: 70fb strb r3, [r7, #3] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800d10c: f3ef 8310 mrs r3, PRIMASK 800d110: 613b str r3, [r7, #16] return(result); 800d112: 693b ldr r3, [r7, #16] UTIL_LPM_ENTER_CRITICAL_SECTION( ); 800d114: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800d116: b672 cpsid i } 800d118: bf00 nop switch( state ) 800d11a: 78fb ldrb r3, [r7, #3] 800d11c: 2b00 cmp r3, #0 800d11e: d008 beq.n 800d132 800d120: 2b01 cmp r3, #1 800d122: d10e bne.n 800d142 { case UTIL_LPM_DISABLE: { StopModeDisable |= lpm_id_bm; 800d124: 4b0d ldr r3, [pc, #52] @ (800d15c ) 800d126: 681a ldr r2, [r3, #0] 800d128: 687b ldr r3, [r7, #4] 800d12a: 4313 orrs r3, r2 800d12c: 4a0b ldr r2, [pc, #44] @ (800d15c ) 800d12e: 6013 str r3, [r2, #0] break; 800d130: e008 b.n 800d144 } case UTIL_LPM_ENABLE: { StopModeDisable &= ( ~lpm_id_bm ); 800d132: 687b ldr r3, [r7, #4] 800d134: 43da mvns r2, r3 800d136: 4b09 ldr r3, [pc, #36] @ (800d15c ) 800d138: 681b ldr r3, [r3, #0] 800d13a: 4013 ands r3, r2 800d13c: 4a07 ldr r2, [pc, #28] @ (800d15c ) 800d13e: 6013 str r3, [r2, #0] break; 800d140: e000 b.n 800d144 } default : { break; 800d142: bf00 nop 800d144: 697b ldr r3, [r7, #20] 800d146: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800d148: 68fb ldr r3, [r7, #12] 800d14a: f383 8810 msr PRIMASK, r3 } 800d14e: bf00 nop } } UTIL_LPM_EXIT_CRITICAL_SECTION( ); } 800d150: bf00 nop 800d152: 371c adds r7, #28 800d154: 46bd mov sp, r7 800d156: bc80 pop {r7} 800d158: 4770 bx lr 800d15a: bf00 nop 800d15c: 20000be0 .word 0x20000be0 0800d160 : void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) { 800d160: b480 push {r7} 800d162: b087 sub sp, #28 800d164: af00 add r7, sp, #0 800d166: 6078 str r0, [r7, #4] 800d168: 460b mov r3, r1 800d16a: 70fb strb r3, [r7, #3] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800d16c: f3ef 8310 mrs r3, PRIMASK 800d170: 613b str r3, [r7, #16] return(result); 800d172: 693b ldr r3, [r7, #16] UTIL_LPM_ENTER_CRITICAL_SECTION( ); 800d174: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800d176: b672 cpsid i } 800d178: bf00 nop switch(state) 800d17a: 78fb ldrb r3, [r7, #3] 800d17c: 2b00 cmp r3, #0 800d17e: d008 beq.n 800d192 800d180: 2b01 cmp r3, #1 800d182: d10e bne.n 800d1a2 { case UTIL_LPM_DISABLE: { OffModeDisable |= lpm_id_bm; 800d184: 4b0d ldr r3, [pc, #52] @ (800d1bc ) 800d186: 681a ldr r2, [r3, #0] 800d188: 687b ldr r3, [r7, #4] 800d18a: 4313 orrs r3, r2 800d18c: 4a0b ldr r2, [pc, #44] @ (800d1bc ) 800d18e: 6013 str r3, [r2, #0] break; 800d190: e008 b.n 800d1a4 } case UTIL_LPM_ENABLE: { OffModeDisable &= ( ~lpm_id_bm ); 800d192: 687b ldr r3, [r7, #4] 800d194: 43da mvns r2, r3 800d196: 4b09 ldr r3, [pc, #36] @ (800d1bc ) 800d198: 681b ldr r3, [r3, #0] 800d19a: 4013 ands r3, r2 800d19c: 4a07 ldr r2, [pc, #28] @ (800d1bc ) 800d19e: 6013 str r3, [r2, #0] break; 800d1a0: e000 b.n 800d1a4 } default : { break; 800d1a2: bf00 nop 800d1a4: 697b ldr r3, [r7, #20] 800d1a6: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800d1a8: 68fb ldr r3, [r7, #12] 800d1aa: f383 8810 msr PRIMASK, r3 } 800d1ae: bf00 nop } } UTIL_LPM_EXIT_CRITICAL_SECTION( ); } 800d1b0: bf00 nop 800d1b2: 371c adds r7, #28 800d1b4: 46bd mov sp, r7 800d1b6: bc80 pop {r7} 800d1b8: 4770 bx lr 800d1ba: bf00 nop 800d1bc: 20000be4 .word 0x20000be4 0800d1c0 : return mode_selected; } void UTIL_LPM_EnterLowPower( void ) { 800d1c0: b580 push {r7, lr} 800d1c2: b084 sub sp, #16 800d1c4: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800d1c6: f3ef 8310 mrs r3, PRIMASK 800d1ca: 60bb str r3, [r7, #8] return(result); 800d1cc: 68bb ldr r3, [r7, #8] UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ); 800d1ce: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 800d1d0: b672 cpsid i } 800d1d2: bf00 nop if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) 800d1d4: 4b12 ldr r3, [pc, #72] @ (800d220 ) 800d1d6: 681b ldr r3, [r3, #0] 800d1d8: 2b00 cmp r3, #0 800d1da: d006 beq.n 800d1ea { /** * At least one user disallows Stop Mode * SLEEP mode is required */ UTIL_PowerDriver.EnterSleepMode( ); 800d1dc: 4b11 ldr r3, [pc, #68] @ (800d224 ) 800d1de: 681b ldr r3, [r3, #0] 800d1e0: 4798 blx r3 UTIL_PowerDriver.ExitSleepMode( ); 800d1e2: 4b10 ldr r3, [pc, #64] @ (800d224 ) 800d1e4: 685b ldr r3, [r3, #4] 800d1e6: 4798 blx r3 800d1e8: e010 b.n 800d20c } else { if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) 800d1ea: 4b0f ldr r3, [pc, #60] @ (800d228 ) 800d1ec: 681b ldr r3, [r3, #0] 800d1ee: 2b00 cmp r3, #0 800d1f0: d006 beq.n 800d200 { /** * At least one user disallows Off Mode * STOP mode is required */ UTIL_PowerDriver.EnterStopMode( ); 800d1f2: 4b0c ldr r3, [pc, #48] @ (800d224 ) 800d1f4: 689b ldr r3, [r3, #8] 800d1f6: 4798 blx r3 UTIL_PowerDriver.ExitStopMode( ); 800d1f8: 4b0a ldr r3, [pc, #40] @ (800d224 ) 800d1fa: 68db ldr r3, [r3, #12] 800d1fc: 4798 blx r3 800d1fe: e005 b.n 800d20c else { /** * OFF mode is required */ UTIL_PowerDriver.EnterOffMode( ); 800d200: 4b08 ldr r3, [pc, #32] @ (800d224 ) 800d202: 691b ldr r3, [r3, #16] 800d204: 4798 blx r3 UTIL_PowerDriver.ExitOffMode( ); 800d206: 4b07 ldr r3, [pc, #28] @ (800d224 ) 800d208: 695b ldr r3, [r3, #20] 800d20a: 4798 blx r3 800d20c: 68fb ldr r3, [r7, #12] 800d20e: 607b str r3, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800d210: 687b ldr r3, [r7, #4] 800d212: f383 8810 msr PRIMASK, r3 } 800d216: bf00 nop } } UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ); } 800d218: bf00 nop 800d21a: 3710 adds r7, #16 800d21c: 46bd mov sp, r7 800d21e: bd80 pop {r7, pc} 800d220: 20000be0 .word 0x20000be0 800d224: 0800fa4c .word 0x0800fa4c 800d228: 20000be4 .word 0x20000be4 0800d22c : /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Functions Definition ------------------------------------------------------*/ void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ) { 800d22c: b480 push {r7} 800d22e: b087 sub sp, #28 800d230: af00 add r7, sp, #0 800d232: 60f8 str r0, [r7, #12] 800d234: 60b9 str r1, [r7, #8] 800d236: 4613 mov r3, r2 800d238: 80fb strh r3, [r7, #6] uint8_t* dst8= (uint8_t *) dst; 800d23a: 68fb ldr r3, [r7, #12] 800d23c: 617b str r3, [r7, #20] uint8_t* src8= (uint8_t *) src; 800d23e: 68bb ldr r3, [r7, #8] 800d240: 613b str r3, [r7, #16] while( size-- ) 800d242: e007 b.n 800d254 { *dst8++ = *src8++; 800d244: 693a ldr r2, [r7, #16] 800d246: 1c53 adds r3, r2, #1 800d248: 613b str r3, [r7, #16] 800d24a: 697b ldr r3, [r7, #20] 800d24c: 1c59 adds r1, r3, #1 800d24e: 6179 str r1, [r7, #20] 800d250: 7812 ldrb r2, [r2, #0] 800d252: 701a strb r2, [r3, #0] while( size-- ) 800d254: 88fb ldrh r3, [r7, #6] 800d256: 1e5a subs r2, r3, #1 800d258: 80fa strh r2, [r7, #6] 800d25a: 2b00 cmp r3, #0 800d25c: d1f2 bne.n 800d244 } } 800d25e: bf00 nop 800d260: bf00 nop 800d262: 371c adds r7, #28 800d264: 46bd mov sp, r7 800d266: bc80 pop {r7} 800d268: 4770 bx lr 0800d26a : *dst8-- = *src8++; } } void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ) { 800d26a: b480 push {r7} 800d26c: b085 sub sp, #20 800d26e: af00 add r7, sp, #0 800d270: 6078 str r0, [r7, #4] 800d272: 460b mov r3, r1 800d274: 70fb strb r3, [r7, #3] 800d276: 4613 mov r3, r2 800d278: 803b strh r3, [r7, #0] uint8_t* dst8= (uint8_t *) dst; 800d27a: 687b ldr r3, [r7, #4] 800d27c: 60fb str r3, [r7, #12] while( size-- ) 800d27e: e004 b.n 800d28a { *dst8++ = value; 800d280: 68fb ldr r3, [r7, #12] 800d282: 1c5a adds r2, r3, #1 800d284: 60fa str r2, [r7, #12] 800d286: 78fa ldrb r2, [r7, #3] 800d288: 701a strb r2, [r3, #0] while( size-- ) 800d28a: 883b ldrh r3, [r7, #0] 800d28c: 1e5a subs r2, r3, #1 800d28e: 803a strh r2, [r7, #0] 800d290: 2b00 cmp r3, #0 800d292: d1f5 bne.n 800d280 } } 800d294: bf00 nop 800d296: bf00 nop 800d298: 3714 adds r7, #20 800d29a: 46bd mov sp, r7 800d29c: bc80 pop {r7} 800d29e: 4770 bx lr 0800d2a0 : * @addtogroup SYSTIME_exported_function * @{ */ SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ) { 800d2a0: b082 sub sp, #8 800d2a2: b480 push {r7} 800d2a4: b087 sub sp, #28 800d2a6: af00 add r7, sp, #0 800d2a8: 60f8 str r0, [r7, #12] 800d2aa: 1d38 adds r0, r7, #4 800d2ac: e880 0006 stmia.w r0, {r1, r2} 800d2b0: 627b str r3, [r7, #36] @ 0x24 SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; 800d2b2: 2300 movs r3, #0 800d2b4: 613b str r3, [r7, #16] 800d2b6: 2300 movs r3, #0 800d2b8: 82bb strh r3, [r7, #20] c.Seconds = a.Seconds + b.Seconds; 800d2ba: 687a ldr r2, [r7, #4] 800d2bc: 6a7b ldr r3, [r7, #36] @ 0x24 800d2be: 4413 add r3, r2 800d2c0: 613b str r3, [r7, #16] c.SubSeconds = a.SubSeconds + b.SubSeconds; 800d2c2: f9b7 3008 ldrsh.w r3, [r7, #8] 800d2c6: b29a uxth r2, r3 800d2c8: f9b7 3028 ldrsh.w r3, [r7, #40] @ 0x28 800d2cc: b29b uxth r3, r3 800d2ce: 4413 add r3, r2 800d2d0: b29b uxth r3, r3 800d2d2: b21b sxth r3, r3 800d2d4: 82bb strh r3, [r7, #20] if( c.SubSeconds >= 1000 ) 800d2d6: f9b7 3014 ldrsh.w r3, [r7, #20] 800d2da: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800d2de: db0a blt.n 800d2f6 { c.Seconds++; 800d2e0: 693b ldr r3, [r7, #16] 800d2e2: 3301 adds r3, #1 800d2e4: 613b str r3, [r7, #16] c.SubSeconds -= 1000; 800d2e6: f9b7 3014 ldrsh.w r3, [r7, #20] 800d2ea: b29b uxth r3, r3 800d2ec: f5a3 737a sub.w r3, r3, #1000 @ 0x3e8 800d2f0: b29b uxth r3, r3 800d2f2: b21b sxth r3, r3 800d2f4: 82bb strh r3, [r7, #20] } return c; 800d2f6: 68fb ldr r3, [r7, #12] 800d2f8: 461a mov r2, r3 800d2fa: f107 0310 add.w r3, r7, #16 800d2fe: e893 0003 ldmia.w r3, {r0, r1} 800d302: e882 0003 stmia.w r2, {r0, r1} } 800d306: 68f8 ldr r0, [r7, #12] 800d308: 371c adds r7, #28 800d30a: 46bd mov sp, r7 800d30c: bc80 pop {r7} 800d30e: b002 add sp, #8 800d310: 4770 bx lr ... 0800d314 : UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds ); UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds ); } SysTime_t SysTimeGet( void ) { 800d314: b580 push {r7, lr} 800d316: b08a sub sp, #40 @ 0x28 800d318: af02 add r7, sp, #8 800d31a: 6078 str r0, [r7, #4] SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; 800d31c: 2300 movs r3, #0 800d31e: 61bb str r3, [r7, #24] 800d320: 2300 movs r3, #0 800d322: 83bb strh r3, [r7, #28] SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 }; 800d324: 2300 movs r3, #0 800d326: 613b str r3, [r7, #16] 800d328: 2300 movs r3, #0 800d32a: 82bb strh r3, [r7, #20] SysTime_t DeltaTime; calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); 800d32c: 4b14 ldr r3, [pc, #80] @ (800d380 ) 800d32e: 691b ldr r3, [r3, #16] 800d330: f107 0218 add.w r2, r7, #24 800d334: 3204 adds r2, #4 800d336: 4610 mov r0, r2 800d338: 4798 blx r3 800d33a: 4603 mov r3, r0 800d33c: 61bb str r3, [r7, #24] DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); 800d33e: 4b10 ldr r3, [pc, #64] @ (800d380 ) 800d340: 68db ldr r3, [r3, #12] 800d342: 4798 blx r3 800d344: 4603 mov r3, r0 800d346: b21b sxth r3, r3 800d348: 81bb strh r3, [r7, #12] DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); 800d34a: 4b0d ldr r3, [pc, #52] @ (800d380 ) 800d34c: 685b ldr r3, [r3, #4] 800d34e: 4798 blx r3 800d350: 4603 mov r3, r0 800d352: 60bb str r3, [r7, #8] sysTime = SysTimeAdd( DeltaTime, calendarTime ); 800d354: f107 0010 add.w r0, r7, #16 800d358: 69fb ldr r3, [r7, #28] 800d35a: 9300 str r3, [sp, #0] 800d35c: 69bb ldr r3, [r7, #24] 800d35e: f107 0208 add.w r2, r7, #8 800d362: ca06 ldmia r2, {r1, r2} 800d364: f7ff ff9c bl 800d2a0 return sysTime; 800d368: 687b ldr r3, [r7, #4] 800d36a: 461a mov r2, r3 800d36c: f107 0310 add.w r3, r7, #16 800d370: e893 0003 ldmia.w r3, {r0, r1} 800d374: e882 0003 stmia.w r2, {r0, r1} } 800d378: 6878 ldr r0, [r7, #4] 800d37a: 3720 adds r7, #32 800d37c: 46bd mov sp, r7 800d37e: bd80 pop {r7, pc} 800d380: 0800fb30 .word 0x0800fb30 0800d384 : return sc - s; } #endif static int ee_skip_atoi(const char **s) { 800d384: b480 push {r7} 800d386: b085 sub sp, #20 800d388: af00 add r7, sp, #0 800d38a: 6078 str r0, [r7, #4] int i = 0; 800d38c: 2300 movs r3, #0 800d38e: 60fb str r3, [r7, #12] while (is_digit(**s)) i = i*10 + *((*s)++) - '0'; 800d390: e00e b.n 800d3b0 800d392: 68fa ldr r2, [r7, #12] 800d394: 4613 mov r3, r2 800d396: 009b lsls r3, r3, #2 800d398: 4413 add r3, r2 800d39a: 005b lsls r3, r3, #1 800d39c: 4618 mov r0, r3 800d39e: 687b ldr r3, [r7, #4] 800d3a0: 681b ldr r3, [r3, #0] 800d3a2: 1c59 adds r1, r3, #1 800d3a4: 687a ldr r2, [r7, #4] 800d3a6: 6011 str r1, [r2, #0] 800d3a8: 781b ldrb r3, [r3, #0] 800d3aa: 4403 add r3, r0 800d3ac: 3b30 subs r3, #48 @ 0x30 800d3ae: 60fb str r3, [r7, #12] 800d3b0: 687b ldr r3, [r7, #4] 800d3b2: 681b ldr r3, [r3, #0] 800d3b4: 781b ldrb r3, [r3, #0] 800d3b6: 2b2f cmp r3, #47 @ 0x2f 800d3b8: d904 bls.n 800d3c4 800d3ba: 687b ldr r3, [r7, #4] 800d3bc: 681b ldr r3, [r3, #0] 800d3be: 781b ldrb r3, [r3, #0] 800d3c0: 2b39 cmp r3, #57 @ 0x39 800d3c2: d9e6 bls.n 800d392 return i; 800d3c4: 68fb ldr r3, [r7, #12] } 800d3c6: 4618 mov r0, r3 800d3c8: 3714 adds r7, #20 800d3ca: 46bd mov sp, r7 800d3cc: bc80 pop {r7} 800d3ce: 4770 bx lr 0800d3d0 : #define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0) static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type) { 800d3d0: b480 push {r7} 800d3d2: b099 sub sp, #100 @ 0x64 800d3d4: af00 add r7, sp, #0 800d3d6: 60f8 str r0, [r7, #12] 800d3d8: 60b9 str r1, [r7, #8] 800d3da: 607a str r2, [r7, #4] 800d3dc: 603b str r3, [r7, #0] char c; char sign, tmp[66]; char *dig = lower_digits; 800d3de: 4b71 ldr r3, [pc, #452] @ (800d5a4 ) 800d3e0: 681b ldr r3, [r3, #0] 800d3e2: 65bb str r3, [r7, #88] @ 0x58 int i; if (type & UPPERCASE) dig = upper_digits; 800d3e4: 6f3b ldr r3, [r7, #112] @ 0x70 800d3e6: f003 0340 and.w r3, r3, #64 @ 0x40 800d3ea: 2b00 cmp r3, #0 800d3ec: d002 beq.n 800d3f4 800d3ee: 4b6e ldr r3, [pc, #440] @ (800d5a8 ) 800d3f0: 681b ldr r3, [r3, #0] 800d3f2: 65bb str r3, [r7, #88] @ 0x58 #ifdef TINY_PRINTF #else if (type & LEFT) type &= ~ZEROPAD; #endif if (base < 2 || base > 36) return 0; 800d3f4: 683b ldr r3, [r7, #0] 800d3f6: 2b01 cmp r3, #1 800d3f8: dd02 ble.n 800d400 800d3fa: 683b ldr r3, [r7, #0] 800d3fc: 2b24 cmp r3, #36 @ 0x24 800d3fe: dd01 ble.n 800d404 800d400: 2300 movs r3, #0 800d402: e0ca b.n 800d59a c = (type & ZEROPAD) ? '0' : ' '; 800d404: 6f3b ldr r3, [r7, #112] @ 0x70 800d406: f003 0301 and.w r3, r3, #1 800d40a: 2b00 cmp r3, #0 800d40c: d001 beq.n 800d412 800d40e: 2330 movs r3, #48 @ 0x30 800d410: e000 b.n 800d414 800d412: 2320 movs r3, #32 800d414: f887 3053 strb.w r3, [r7, #83] @ 0x53 sign = 0; 800d418: 2300 movs r3, #0 800d41a: f887 305f strb.w r3, [r7, #95] @ 0x5f if (type & SIGN) 800d41e: 6f3b ldr r3, [r7, #112] @ 0x70 800d420: f003 0302 and.w r3, r3, #2 800d424: 2b00 cmp r3, #0 800d426: d00b beq.n 800d440 { if (num < 0) 800d428: 687b ldr r3, [r7, #4] 800d42a: 2b00 cmp r3, #0 800d42c: da08 bge.n 800d440 { sign = '-'; 800d42e: 232d movs r3, #45 @ 0x2d 800d430: f887 305f strb.w r3, [r7, #95] @ 0x5f num = -num; 800d434: 687b ldr r3, [r7, #4] 800d436: 425b negs r3, r3 800d438: 607b str r3, [r7, #4] size--; 800d43a: 6ebb ldr r3, [r7, #104] @ 0x68 800d43c: 3b01 subs r3, #1 800d43e: 66bb str r3, [r7, #104] @ 0x68 else if (base == 8) size--; } #endif i = 0; 800d440: 2300 movs r3, #0 800d442: 657b str r3, [r7, #84] @ 0x54 if (num == 0) 800d444: 687b ldr r3, [r7, #4] 800d446: 2b00 cmp r3, #0 800d448: d11e bne.n 800d488 tmp[i++] = '0'; 800d44a: 6d7b ldr r3, [r7, #84] @ 0x54 800d44c: 1c5a adds r2, r3, #1 800d44e: 657a str r2, [r7, #84] @ 0x54 800d450: 3360 adds r3, #96 @ 0x60 800d452: 443b add r3, r7 800d454: 2230 movs r2, #48 @ 0x30 800d456: f803 2c50 strb.w r2, [r3, #-80] 800d45a: e018 b.n 800d48e else { while (num != 0) { tmp[i++] = dig[((unsigned long) num) % (unsigned) base]; 800d45c: 687b ldr r3, [r7, #4] 800d45e: 683a ldr r2, [r7, #0] 800d460: fbb3 f1f2 udiv r1, r3, r2 800d464: fb01 f202 mul.w r2, r1, r2 800d468: 1a9b subs r3, r3, r2 800d46a: 6dba ldr r2, [r7, #88] @ 0x58 800d46c: 441a add r2, r3 800d46e: 6d7b ldr r3, [r7, #84] @ 0x54 800d470: 1c59 adds r1, r3, #1 800d472: 6579 str r1, [r7, #84] @ 0x54 800d474: 7812 ldrb r2, [r2, #0] 800d476: 3360 adds r3, #96 @ 0x60 800d478: 443b add r3, r7 800d47a: f803 2c50 strb.w r2, [r3, #-80] num = ((unsigned long) num) / (unsigned) base; 800d47e: 687a ldr r2, [r7, #4] 800d480: 683b ldr r3, [r7, #0] 800d482: fbb2 f3f3 udiv r3, r2, r3 800d486: 607b str r3, [r7, #4] while (num != 0) 800d488: 687b ldr r3, [r7, #4] 800d48a: 2b00 cmp r3, #0 800d48c: d1e6 bne.n 800d45c } } if (i > precision) precision = i; 800d48e: 6d7a ldr r2, [r7, #84] @ 0x54 800d490: 6efb ldr r3, [r7, #108] @ 0x6c 800d492: 429a cmp r2, r3 800d494: dd01 ble.n 800d49a 800d496: 6d7b ldr r3, [r7, #84] @ 0x54 800d498: 66fb str r3, [r7, #108] @ 0x6c size -= precision; 800d49a: 6eba ldr r2, [r7, #104] @ 0x68 800d49c: 6efb ldr r3, [r7, #108] @ 0x6c 800d49e: 1ad3 subs r3, r2, r3 800d4a0: 66bb str r3, [r7, #104] @ 0x68 if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' '); 800d4a2: 6f3b ldr r3, [r7, #112] @ 0x70 800d4a4: f003 0301 and.w r3, r3, #1 800d4a8: 2b00 cmp r3, #0 800d4aa: d112 bne.n 800d4d2 800d4ac: e00c b.n 800d4c8 800d4ae: 68fb ldr r3, [r7, #12] 800d4b0: 1c5a adds r2, r3, #1 800d4b2: 60fa str r2, [r7, #12] 800d4b4: 2220 movs r2, #32 800d4b6: 701a strb r2, [r3, #0] 800d4b8: 68bb ldr r3, [r7, #8] 800d4ba: 3b01 subs r3, #1 800d4bc: 60bb str r3, [r7, #8] 800d4be: 68bb ldr r3, [r7, #8] 800d4c0: 2b00 cmp r3, #0 800d4c2: d101 bne.n 800d4c8 800d4c4: 68fb ldr r3, [r7, #12] 800d4c6: e068 b.n 800d59a 800d4c8: 6ebb ldr r3, [r7, #104] @ 0x68 800d4ca: 1e5a subs r2, r3, #1 800d4cc: 66ba str r2, [r7, #104] @ 0x68 800d4ce: 2b00 cmp r3, #0 800d4d0: dced bgt.n 800d4ae if (sign) ASSIGN_STR(sign); 800d4d2: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800d4d6: 2b00 cmp r3, #0 800d4d8: d01b beq.n 800d512 800d4da: 68fb ldr r3, [r7, #12] 800d4dc: 1c5a adds r2, r3, #1 800d4de: 60fa str r2, [r7, #12] 800d4e0: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 800d4e4: 701a strb r2, [r3, #0] 800d4e6: 68bb ldr r3, [r7, #8] 800d4e8: 3b01 subs r3, #1 800d4ea: 60bb str r3, [r7, #8] 800d4ec: 68bb ldr r3, [r7, #8] 800d4ee: 2b00 cmp r3, #0 800d4f0: d10f bne.n 800d512 800d4f2: 68fb ldr r3, [r7, #12] 800d4f4: e051 b.n 800d59a } } #endif #ifdef TINY_PRINTF while (size-- > 0) ASSIGN_STR(c); 800d4f6: 68fb ldr r3, [r7, #12] 800d4f8: 1c5a adds r2, r3, #1 800d4fa: 60fa str r2, [r7, #12] 800d4fc: f897 2053 ldrb.w r2, [r7, #83] @ 0x53 800d500: 701a strb r2, [r3, #0] 800d502: 68bb ldr r3, [r7, #8] 800d504: 3b01 subs r3, #1 800d506: 60bb str r3, [r7, #8] 800d508: 68bb ldr r3, [r7, #8] 800d50a: 2b00 cmp r3, #0 800d50c: d101 bne.n 800d512 800d50e: 68fb ldr r3, [r7, #12] 800d510: e043 b.n 800d59a 800d512: 6ebb ldr r3, [r7, #104] @ 0x68 800d514: 1e5a subs r2, r3, #1 800d516: 66ba str r2, [r7, #104] @ 0x68 800d518: 2b00 cmp r3, #0 800d51a: dcec bgt.n 800d4f6 #else if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c); #endif while (i < precision--) ASSIGN_STR('0'); 800d51c: e00c b.n 800d538 800d51e: 68fb ldr r3, [r7, #12] 800d520: 1c5a adds r2, r3, #1 800d522: 60fa str r2, [r7, #12] 800d524: 2230 movs r2, #48 @ 0x30 800d526: 701a strb r2, [r3, #0] 800d528: 68bb ldr r3, [r7, #8] 800d52a: 3b01 subs r3, #1 800d52c: 60bb str r3, [r7, #8] 800d52e: 68bb ldr r3, [r7, #8] 800d530: 2b00 cmp r3, #0 800d532: d101 bne.n 800d538 800d534: 68fb ldr r3, [r7, #12] 800d536: e030 b.n 800d59a 800d538: 6efb ldr r3, [r7, #108] @ 0x6c 800d53a: 1e5a subs r2, r3, #1 800d53c: 66fa str r2, [r7, #108] @ 0x6c 800d53e: 6d7a ldr r2, [r7, #84] @ 0x54 800d540: 429a cmp r2, r3 800d542: dbec blt.n 800d51e while (i-- > 0) ASSIGN_STR(tmp[i]); 800d544: e010 b.n 800d568 800d546: 68fb ldr r3, [r7, #12] 800d548: 1c5a adds r2, r3, #1 800d54a: 60fa str r2, [r7, #12] 800d54c: f107 0110 add.w r1, r7, #16 800d550: 6d7a ldr r2, [r7, #84] @ 0x54 800d552: 440a add r2, r1 800d554: 7812 ldrb r2, [r2, #0] 800d556: 701a strb r2, [r3, #0] 800d558: 68bb ldr r3, [r7, #8] 800d55a: 3b01 subs r3, #1 800d55c: 60bb str r3, [r7, #8] 800d55e: 68bb ldr r3, [r7, #8] 800d560: 2b00 cmp r3, #0 800d562: d101 bne.n 800d568 800d564: 68fb ldr r3, [r7, #12] 800d566: e018 b.n 800d59a 800d568: 6d7b ldr r3, [r7, #84] @ 0x54 800d56a: 1e5a subs r2, r3, #1 800d56c: 657a str r2, [r7, #84] @ 0x54 800d56e: 2b00 cmp r3, #0 800d570: dce9 bgt.n 800d546 while (size-- > 0) ASSIGN_STR(' '); 800d572: e00c b.n 800d58e 800d574: 68fb ldr r3, [r7, #12] 800d576: 1c5a adds r2, r3, #1 800d578: 60fa str r2, [r7, #12] 800d57a: 2220 movs r2, #32 800d57c: 701a strb r2, [r3, #0] 800d57e: 68bb ldr r3, [r7, #8] 800d580: 3b01 subs r3, #1 800d582: 60bb str r3, [r7, #8] 800d584: 68bb ldr r3, [r7, #8] 800d586: 2b00 cmp r3, #0 800d588: d101 bne.n 800d58e 800d58a: 68fb ldr r3, [r7, #12] 800d58c: e005 b.n 800d59a 800d58e: 6ebb ldr r3, [r7, #104] @ 0x68 800d590: 1e5a subs r2, r3, #1 800d592: 66ba str r2, [r7, #104] @ 0x68 800d594: 2b00 cmp r3, #0 800d596: dced bgt.n 800d574 return str; 800d598: 68fb ldr r3, [r7, #12] } 800d59a: 4618 mov r0, r3 800d59c: 3764 adds r7, #100 @ 0x64 800d59e: 46bd mov sp, r7 800d5a0: bc80 pop {r7} 800d5a2: 4770 bx lr 800d5a4: 2000002c .word 0x2000002c 800d5a8: 20000030 .word 0x20000030 0800d5ac : #define CHECK_STR_SIZE(_buf, _str, _size) \ if ((((_str) - (_buf)) >= ((_size)-1))) { break; } int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args) { 800d5ac: b580 push {r7, lr} 800d5ae: b092 sub sp, #72 @ 0x48 800d5b0: af04 add r7, sp, #16 800d5b2: 60f8 str r0, [r7, #12] 800d5b4: 60b9 str r1, [r7, #8] 800d5b6: 607a str r2, [r7, #4] 800d5b8: 603b str r3, [r7, #0] int field_width; // Width of output field int precision; // Min. # of digits for integers; max number of chars for from string int qualifier; // 'h', 'l', or 'L' for integer fields if (size <= 0) 800d5ba: 68bb ldr r3, [r7, #8] 800d5bc: 2b00 cmp r3, #0 800d5be: dc01 bgt.n 800d5c4 { return 0; 800d5c0: 2300 movs r3, #0 800d5c2: e13e b.n 800d842 } for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) 800d5c4: 68fb ldr r3, [r7, #12] 800d5c6: 62fb str r3, [r7, #44] @ 0x2c 800d5c8: e128 b.n 800d81c { CHECK_STR_SIZE(buf, str, size); 800d5ca: 6afa ldr r2, [r7, #44] @ 0x2c 800d5cc: 68fb ldr r3, [r7, #12] 800d5ce: 1ad2 subs r2, r2, r3 800d5d0: 68bb ldr r3, [r7, #8] 800d5d2: 3b01 subs r3, #1 800d5d4: 429a cmp r2, r3 800d5d6: f280 812e bge.w 800d836 if (*fmt != '%') 800d5da: 687b ldr r3, [r7, #4] 800d5dc: 781b ldrb r3, [r3, #0] 800d5de: 2b25 cmp r3, #37 @ 0x25 800d5e0: d006 beq.n 800d5f0 { *str++ = *fmt; 800d5e2: 687a ldr r2, [r7, #4] 800d5e4: 6afb ldr r3, [r7, #44] @ 0x2c 800d5e6: 1c59 adds r1, r3, #1 800d5e8: 62f9 str r1, [r7, #44] @ 0x2c 800d5ea: 7812 ldrb r2, [r2, #0] 800d5ec: 701a strb r2, [r3, #0] continue; 800d5ee: e112 b.n 800d816 } // Process flags flags = 0; 800d5f0: 2300 movs r3, #0 800d5f2: 623b str r3, [r7, #32] #ifdef TINY_PRINTF /* Support %0, but not %-, %+, %space and %# */ fmt++; 800d5f4: 687b ldr r3, [r7, #4] 800d5f6: 3301 adds r3, #1 800d5f8: 607b str r3, [r7, #4] if (*fmt == '0') 800d5fa: 687b ldr r3, [r7, #4] 800d5fc: 781b ldrb r3, [r3, #0] 800d5fe: 2b30 cmp r3, #48 @ 0x30 800d600: d103 bne.n 800d60a { flags |= ZEROPAD; 800d602: 6a3b ldr r3, [r7, #32] 800d604: f043 0301 orr.w r3, r3, #1 800d608: 623b str r3, [r7, #32] case '0': flags |= ZEROPAD; goto repeat; } #endif // Get field width field_width = -1; 800d60a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d60e: 61fb str r3, [r7, #28] if (is_digit(*fmt)) 800d610: 687b ldr r3, [r7, #4] 800d612: 781b ldrb r3, [r3, #0] 800d614: 2b2f cmp r3, #47 @ 0x2f 800d616: d908 bls.n 800d62a 800d618: 687b ldr r3, [r7, #4] 800d61a: 781b ldrb r3, [r3, #0] 800d61c: 2b39 cmp r3, #57 @ 0x39 800d61e: d804 bhi.n 800d62a field_width = ee_skip_atoi(&fmt); 800d620: 1d3b adds r3, r7, #4 800d622: 4618 mov r0, r3 800d624: f7ff feae bl 800d384 800d628: 61f8 str r0, [r7, #28] } } #endif // Get the precision precision = -1; 800d62a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d62e: 61bb str r3, [r7, #24] if (precision < 0) precision = 0; } #endif // Get the conversion qualifier qualifier = -1; 800d630: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d634: 617b str r3, [r7, #20] fmt++; } #endif // Default base base = 10; 800d636: 230a movs r3, #10 800d638: 633b str r3, [r7, #48] @ 0x30 switch (*fmt) 800d63a: 687b ldr r3, [r7, #4] 800d63c: 781b ldrb r3, [r3, #0] 800d63e: 3b58 subs r3, #88 @ 0x58 800d640: 2b20 cmp r3, #32 800d642: f200 8094 bhi.w 800d76e 800d646: a201 add r2, pc, #4 @ (adr r2, 800d64c ) 800d648: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d64c: 0800d757 .word 0x0800d757 800d650: 0800d76f .word 0x0800d76f 800d654: 0800d76f .word 0x0800d76f 800d658: 0800d76f .word 0x0800d76f 800d65c: 0800d76f .word 0x0800d76f 800d660: 0800d76f .word 0x0800d76f 800d664: 0800d76f .word 0x0800d76f 800d668: 0800d76f .word 0x0800d76f 800d66c: 0800d76f .word 0x0800d76f 800d670: 0800d76f .word 0x0800d76f 800d674: 0800d76f .word 0x0800d76f 800d678: 0800d6db .word 0x0800d6db 800d67c: 0800d765 .word 0x0800d765 800d680: 0800d76f .word 0x0800d76f 800d684: 0800d76f .word 0x0800d76f 800d688: 0800d76f .word 0x0800d76f 800d68c: 0800d76f .word 0x0800d76f 800d690: 0800d765 .word 0x0800d765 800d694: 0800d76f .word 0x0800d76f 800d698: 0800d76f .word 0x0800d76f 800d69c: 0800d76f .word 0x0800d76f 800d6a0: 0800d76f .word 0x0800d76f 800d6a4: 0800d76f .word 0x0800d76f 800d6a8: 0800d76f .word 0x0800d76f 800d6ac: 0800d76f .word 0x0800d76f 800d6b0: 0800d76f .word 0x0800d76f 800d6b4: 0800d76f .word 0x0800d76f 800d6b8: 0800d6fb .word 0x0800d6fb 800d6bc: 0800d76f .word 0x0800d76f 800d6c0: 0800d7bb .word 0x0800d7bb 800d6c4: 0800d76f .word 0x0800d76f 800d6c8: 0800d76f .word 0x0800d76f 800d6cc: 0800d75f .word 0x0800d75f case 'c': #ifdef TINY_PRINTF #else if (!(flags & LEFT)) #endif while (--field_width > 0) *str++ = ' '; 800d6d0: 6afb ldr r3, [r7, #44] @ 0x2c 800d6d2: 1c5a adds r2, r3, #1 800d6d4: 62fa str r2, [r7, #44] @ 0x2c 800d6d6: 2220 movs r2, #32 800d6d8: 701a strb r2, [r3, #0] 800d6da: 69fb ldr r3, [r7, #28] 800d6dc: 3b01 subs r3, #1 800d6de: 61fb str r3, [r7, #28] 800d6e0: 69fb ldr r3, [r7, #28] 800d6e2: 2b00 cmp r3, #0 800d6e4: dcf4 bgt.n 800d6d0 *str++ = (unsigned char) va_arg(args, int); 800d6e6: 683b ldr r3, [r7, #0] 800d6e8: 1d1a adds r2, r3, #4 800d6ea: 603a str r2, [r7, #0] 800d6ec: 6819 ldr r1, [r3, #0] 800d6ee: 6afb ldr r3, [r7, #44] @ 0x2c 800d6f0: 1c5a adds r2, r3, #1 800d6f2: 62fa str r2, [r7, #44] @ 0x2c 800d6f4: b2ca uxtb r2, r1 800d6f6: 701a strb r2, [r3, #0] #ifdef TINY_PRINTF #else while (--field_width > 0) *str++ = ' '; #endif continue; 800d6f8: e08d b.n 800d816 case 's': s = va_arg(args, char *); 800d6fa: 683b ldr r3, [r7, #0] 800d6fc: 1d1a adds r2, r3, #4 800d6fe: 603a str r2, [r7, #0] 800d700: 681b ldr r3, [r3, #0] 800d702: 627b str r3, [r7, #36] @ 0x24 if (!s) s = ""; 800d704: 6a7b ldr r3, [r7, #36] @ 0x24 800d706: 2b00 cmp r3, #0 800d708: d101 bne.n 800d70e 800d70a: 4b50 ldr r3, [pc, #320] @ (800d84c ) 800d70c: 627b str r3, [r7, #36] @ 0x24 #ifdef TINY_PRINTF len = strlen(s); 800d70e: 6a78 ldr r0, [r7, #36] @ 0x24 800d710: f7f2 fd40 bl 8000194 800d714: 4603 mov r3, r0 800d716: 613b str r3, [r7, #16] #else len = strnlen(s, precision); if (!(flags & LEFT)) #endif while (len < field_width--) *str++ = ' '; 800d718: e004 b.n 800d724 800d71a: 6afb ldr r3, [r7, #44] @ 0x2c 800d71c: 1c5a adds r2, r3, #1 800d71e: 62fa str r2, [r7, #44] @ 0x2c 800d720: 2220 movs r2, #32 800d722: 701a strb r2, [r3, #0] 800d724: 69fb ldr r3, [r7, #28] 800d726: 1e5a subs r2, r3, #1 800d728: 61fa str r2, [r7, #28] 800d72a: 693a ldr r2, [r7, #16] 800d72c: 429a cmp r2, r3 800d72e: dbf4 blt.n 800d71a for (i = 0; i < len; ++i) *str++ = *s++; 800d730: 2300 movs r3, #0 800d732: 62bb str r3, [r7, #40] @ 0x28 800d734: e00a b.n 800d74c 800d736: 6a7a ldr r2, [r7, #36] @ 0x24 800d738: 1c53 adds r3, r2, #1 800d73a: 627b str r3, [r7, #36] @ 0x24 800d73c: 6afb ldr r3, [r7, #44] @ 0x2c 800d73e: 1c59 adds r1, r3, #1 800d740: 62f9 str r1, [r7, #44] @ 0x2c 800d742: 7812 ldrb r2, [r2, #0] 800d744: 701a strb r2, [r3, #0] 800d746: 6abb ldr r3, [r7, #40] @ 0x28 800d748: 3301 adds r3, #1 800d74a: 62bb str r3, [r7, #40] @ 0x28 800d74c: 6aba ldr r2, [r7, #40] @ 0x28 800d74e: 693b ldr r3, [r7, #16] 800d750: 429a cmp r2, r3 800d752: dbf0 blt.n 800d736 #ifdef TINY_PRINTF #else while (len < field_width--) *str++ = ' '; #endif continue; 800d754: e05f b.n 800d816 base = 8; break; #endif case 'X': flags |= UPPERCASE; 800d756: 6a3b ldr r3, [r7, #32] 800d758: f043 0340 orr.w r3, r3, #64 @ 0x40 800d75c: 623b str r3, [r7, #32] case 'x': base = 16; 800d75e: 2310 movs r3, #16 800d760: 633b str r3, [r7, #48] @ 0x30 break; 800d762: e02b b.n 800d7bc case 'd': case 'i': flags |= SIGN; 800d764: 6a3b ldr r3, [r7, #32] 800d766: f043 0302 orr.w r3, r3, #2 800d76a: 623b str r3, [r7, #32] case 'u': break; 800d76c: e025 b.n 800d7ba continue; #endif default: if (*fmt != '%') *str++ = '%'; 800d76e: 687b ldr r3, [r7, #4] 800d770: 781b ldrb r3, [r3, #0] 800d772: 2b25 cmp r3, #37 @ 0x25 800d774: d004 beq.n 800d780 800d776: 6afb ldr r3, [r7, #44] @ 0x2c 800d778: 1c5a adds r2, r3, #1 800d77a: 62fa str r2, [r7, #44] @ 0x2c 800d77c: 2225 movs r2, #37 @ 0x25 800d77e: 701a strb r2, [r3, #0] CHECK_STR_SIZE(buf, str, size); 800d780: 6afa ldr r2, [r7, #44] @ 0x2c 800d782: 68fb ldr r3, [r7, #12] 800d784: 1ad2 subs r2, r2, r3 800d786: 68bb ldr r3, [r7, #8] 800d788: 3b01 subs r3, #1 800d78a: 429a cmp r2, r3 800d78c: da16 bge.n 800d7bc if (*fmt) 800d78e: 687b ldr r3, [r7, #4] 800d790: 781b ldrb r3, [r3, #0] 800d792: 2b00 cmp r3, #0 800d794: d006 beq.n 800d7a4 *str++ = *fmt; 800d796: 687a ldr r2, [r7, #4] 800d798: 6afb ldr r3, [r7, #44] @ 0x2c 800d79a: 1c59 adds r1, r3, #1 800d79c: 62f9 str r1, [r7, #44] @ 0x2c 800d79e: 7812 ldrb r2, [r2, #0] 800d7a0: 701a strb r2, [r3, #0] 800d7a2: e002 b.n 800d7aa else --fmt; 800d7a4: 687b ldr r3, [r7, #4] 800d7a6: 3b01 subs r3, #1 800d7a8: 607b str r3, [r7, #4] CHECK_STR_SIZE(buf, str, size); 800d7aa: 6afa ldr r2, [r7, #44] @ 0x2c 800d7ac: 68fb ldr r3, [r7, #12] 800d7ae: 1ad2 subs r2, r2, r3 800d7b0: 68bb ldr r3, [r7, #8] 800d7b2: 3b01 subs r3, #1 800d7b4: 429a cmp r2, r3 800d7b6: db2d blt.n 800d814 800d7b8: e000 b.n 800d7bc break; 800d7ba: bf00 nop continue; } if (qualifier == 'l') 800d7bc: 697b ldr r3, [r7, #20] 800d7be: 2b6c cmp r3, #108 @ 0x6c 800d7c0: d105 bne.n 800d7ce num = va_arg(args, unsigned long); 800d7c2: 683b ldr r3, [r7, #0] 800d7c4: 1d1a adds r2, r3, #4 800d7c6: 603a str r2, [r7, #0] 800d7c8: 681b ldr r3, [r3, #0] 800d7ca: 637b str r3, [r7, #52] @ 0x34 800d7cc: e00f b.n 800d7ee else if (flags & SIGN) 800d7ce: 6a3b ldr r3, [r7, #32] 800d7d0: f003 0302 and.w r3, r3, #2 800d7d4: 2b00 cmp r3, #0 800d7d6: d005 beq.n 800d7e4 num = va_arg(args, int); 800d7d8: 683b ldr r3, [r7, #0] 800d7da: 1d1a adds r2, r3, #4 800d7dc: 603a str r2, [r7, #0] 800d7de: 681b ldr r3, [r3, #0] 800d7e0: 637b str r3, [r7, #52] @ 0x34 800d7e2: e004 b.n 800d7ee else num = va_arg(args, unsigned int); 800d7e4: 683b ldr r3, [r7, #0] 800d7e6: 1d1a adds r2, r3, #4 800d7e8: 603a str r2, [r7, #0] 800d7ea: 681b ldr r3, [r3, #0] 800d7ec: 637b str r3, [r7, #52] @ 0x34 str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags); 800d7ee: 68bb ldr r3, [r7, #8] 800d7f0: 1e5a subs r2, r3, #1 800d7f2: 6af9 ldr r1, [r7, #44] @ 0x2c 800d7f4: 68fb ldr r3, [r7, #12] 800d7f6: 1acb subs r3, r1, r3 800d7f8: 1ad1 subs r1, r2, r3 800d7fa: 6b7a ldr r2, [r7, #52] @ 0x34 800d7fc: 6a3b ldr r3, [r7, #32] 800d7fe: 9302 str r3, [sp, #8] 800d800: 69bb ldr r3, [r7, #24] 800d802: 9301 str r3, [sp, #4] 800d804: 69fb ldr r3, [r7, #28] 800d806: 9300 str r3, [sp, #0] 800d808: 6b3b ldr r3, [r7, #48] @ 0x30 800d80a: 6af8 ldr r0, [r7, #44] @ 0x2c 800d80c: f7ff fde0 bl 800d3d0 800d810: 62f8 str r0, [r7, #44] @ 0x2c 800d812: e000 b.n 800d816 continue; 800d814: bf00 nop for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) 800d816: 687b ldr r3, [r7, #4] 800d818: 3301 adds r3, #1 800d81a: 607b str r3, [r7, #4] 800d81c: 687b ldr r3, [r7, #4] 800d81e: 781b ldrb r3, [r3, #0] 800d820: 2b00 cmp r3, #0 800d822: f47f aed2 bne.w 800d5ca 800d826: 6afa ldr r2, [r7, #44] @ 0x2c 800d828: 68fb ldr r3, [r7, #12] 800d82a: 1ad2 subs r2, r2, r3 800d82c: 68bb ldr r3, [r7, #8] 800d82e: 3b01 subs r3, #1 800d830: 429a cmp r2, r3 800d832: f6bf aeca bge.w 800d5ca } *str = '\0'; 800d836: 6afb ldr r3, [r7, #44] @ 0x2c 800d838: 2200 movs r2, #0 800d83a: 701a strb r2, [r3, #0] return str - buf; 800d83c: 6afa ldr r2, [r7, #44] @ 0x2c 800d83e: 68fb ldr r3, [r7, #12] 800d840: 1ad3 subs r3, r2, r3 } 800d842: 4618 mov r0, r3 800d844: 3738 adds r7, #56 @ 0x38 800d846: 46bd mov sp, r7 800d848: bd80 pop {r7, pc} 800d84a: bf00 nop 800d84c: 0800fa44 .word 0x0800fa44 0800d850 : * That is the reason why many variables that are used only in that function are declared static. * Note: These variables could have been declared static in the function. * */ void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) { 800d850: b580 push {r7, lr} 800d852: b090 sub sp, #64 @ 0x40 800d854: af00 add r7, sp, #0 800d856: 6078 str r0, [r7, #4] /* * When this function is nested, the mask to be applied cannot be larger than the first call * The mask is always getting smaller and smaller * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task */ super_mask_backup = SuperMask; 800d858: 4b73 ldr r3, [pc, #460] @ (800da28 ) 800d85a: 681b ldr r3, [r3, #0] 800d85c: 62bb str r3, [r7, #40] @ 0x28 SuperMask &= Mask_bm; 800d85e: 4b72 ldr r3, [pc, #456] @ (800da28 ) 800d860: 681a ldr r2, [r3, #0] 800d862: 687b ldr r3, [r7, #4] 800d864: 4013 ands r3, r2 800d866: 4a70 ldr r2, [pc, #448] @ (800da28 ) 800d868: 6013 str r3, [r2, #0] * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask * SuperMask that comes from UTIL_SEQ_Run * If the waited event is there, exit from UTIL_SEQ_Run() to return to the * waiting task */ local_taskset = TaskSet; 800d86a: 4b70 ldr r3, [pc, #448] @ (800da2c ) 800d86c: 681b ldr r3, [r3, #0] 800d86e: 63bb str r3, [r7, #56] @ 0x38 local_evtset = EvtSet; 800d870: 4b6f ldr r3, [pc, #444] @ (800da30 ) 800d872: 681b ldr r3, [r3, #0] 800d874: 637b str r3, [r7, #52] @ 0x34 local_taskmask = TaskMask; 800d876: 4b6f ldr r3, [pc, #444] @ (800da34 ) 800d878: 681b ldr r3, [r3, #0] 800d87a: 633b str r3, [r7, #48] @ 0x30 local_evtwaited = EvtWaited; 800d87c: 4b6e ldr r3, [pc, #440] @ (800da38 ) 800d87e: 681b ldr r3, [r3, #0] 800d880: 62fb str r3, [r7, #44] @ 0x2c while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) 800d882: e08d b.n 800d9a0 { counter = 0U; 800d884: 2300 movs r3, #0 800d886: 63fb str r3, [r7, #60] @ 0x3c /* * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending * on the priority parameter given from UTIL_SEQ_SetTask() * The while loop is looking for a flag set from the highest priority maskr to the lower */ while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) 800d888: e002 b.n 800d890 { counter++; 800d88a: 6bfb ldr r3, [r7, #60] @ 0x3c 800d88c: 3301 adds r3, #1 800d88e: 63fb str r3, [r7, #60] @ 0x3c while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) 800d890: 4a6a ldr r2, [pc, #424] @ (800da3c ) 800d892: 6bfb ldr r3, [r7, #60] @ 0x3c 800d894: f852 2033 ldr.w r2, [r2, r3, lsl #3] 800d898: 6b3b ldr r3, [r7, #48] @ 0x30 800d89a: 401a ands r2, r3 800d89c: 4b62 ldr r3, [pc, #392] @ (800da28 ) 800d89e: 681b ldr r3, [r3, #0] 800d8a0: 4013 ands r3, r2 800d8a2: 2b00 cmp r3, #0 800d8a4: d0f1 beq.n 800d88a } current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; 800d8a6: 4a65 ldr r2, [pc, #404] @ (800da3c ) 800d8a8: 6bfb ldr r3, [r7, #60] @ 0x3c 800d8aa: f852 2033 ldr.w r2, [r2, r3, lsl #3] 800d8ae: 6b3b ldr r3, [r7, #48] @ 0x30 800d8b0: 401a ands r2, r3 800d8b2: 4b5d ldr r3, [pc, #372] @ (800da28 ) 800d8b4: 681b ldr r3, [r3, #0] 800d8b6: 4013 ands r3, r2 800d8b8: 627b str r3, [r7, #36] @ 0x24 * so that the second one can be executed. * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask * * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once */ if ((TaskPrio[counter].round_robin & current_task_set) == 0U) 800d8ba: 4a60 ldr r2, [pc, #384] @ (800da3c ) 800d8bc: 6bfb ldr r3, [r7, #60] @ 0x3c 800d8be: 00db lsls r3, r3, #3 800d8c0: 4413 add r3, r2 800d8c2: 685a ldr r2, [r3, #4] 800d8c4: 6a7b ldr r3, [r7, #36] @ 0x24 800d8c6: 4013 ands r3, r2 800d8c8: 2b00 cmp r3, #0 800d8ca: d106 bne.n 800d8da { TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; 800d8cc: 4a5b ldr r2, [pc, #364] @ (800da3c ) 800d8ce: 6bfb ldr r3, [r7, #60] @ 0x3c 800d8d0: 00db lsls r3, r3, #3 800d8d2: 4413 add r3, r2 800d8d4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d8d8: 605a str r2, [r3, #4] /* * Read the flag index of the task to be executed * Once the index is read, the associated task will be executed even though a higher priority stack is requested * before task execution. */ CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); 800d8da: 4a58 ldr r2, [pc, #352] @ (800da3c ) 800d8dc: 6bfb ldr r3, [r7, #60] @ 0x3c 800d8de: 00db lsls r3, r3, #3 800d8e0: 4413 add r3, r2 800d8e2: 685a ldr r2, [r3, #4] 800d8e4: 6a7b ldr r3, [r7, #36] @ 0x24 800d8e6: 4013 ands r3, r2 800d8e8: 4618 mov r0, r3 800d8ea: f000 f8b9 bl 800da60 800d8ee: 4603 mov r3, r0 800d8f0: 461a mov r2, r3 800d8f2: 4b53 ldr r3, [pc, #332] @ (800da40 ) 800d8f4: 601a str r2, [r3, #0] /* * remove from the roun_robin mask the task that has been selected to be executed */ TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx); 800d8f6: 4a51 ldr r2, [pc, #324] @ (800da3c ) 800d8f8: 6bfb ldr r3, [r7, #60] @ 0x3c 800d8fa: 00db lsls r3, r3, #3 800d8fc: 4413 add r3, r2 800d8fe: 685a ldr r2, [r3, #4] 800d900: 4b4f ldr r3, [pc, #316] @ (800da40 ) 800d902: 681b ldr r3, [r3, #0] 800d904: 2101 movs r1, #1 800d906: fa01 f303 lsl.w r3, r1, r3 800d90a: 43db mvns r3, r3 800d90c: 401a ands r2, r3 800d90e: 494b ldr r1, [pc, #300] @ (800da3c ) 800d910: 6bfb ldr r3, [r7, #60] @ 0x3c 800d912: 00db lsls r3, r3, #3 800d914: 440b add r3, r1 800d916: 605a str r2, [r3, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800d918: f3ef 8310 mrs r3, PRIMASK 800d91c: 61bb str r3, [r7, #24] return(result); 800d91e: 69bb ldr r3, [r7, #24] UTIL_SEQ_ENTER_CRITICAL_SECTION( ); 800d920: 623b str r3, [r7, #32] __ASM volatile ("cpsid i" : : : "memory"); 800d922: b672 cpsid i } 800d924: bf00 nop /* remove from the list or pending task the one that has been selected to be executed */ TaskSet &= ~(1U << CurrentTaskIdx); 800d926: 4b46 ldr r3, [pc, #280] @ (800da40 ) 800d928: 681b ldr r3, [r3, #0] 800d92a: 2201 movs r2, #1 800d92c: fa02 f303 lsl.w r3, r2, r3 800d930: 43da mvns r2, r3 800d932: 4b3e ldr r3, [pc, #248] @ (800da2c ) 800d934: 681b ldr r3, [r3, #0] 800d936: 4013 ands r3, r2 800d938: 4a3c ldr r2, [pc, #240] @ (800da2c ) 800d93a: 6013 str r3, [r2, #0] /* remove from all priority mask the task that has been selected to be executed */ for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) 800d93c: 2301 movs r3, #1 800d93e: 63fb str r3, [r7, #60] @ 0x3c 800d940: e013 b.n 800d96a { TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx); 800d942: 6bfb ldr r3, [r7, #60] @ 0x3c 800d944: 3b01 subs r3, #1 800d946: 4a3d ldr r2, [pc, #244] @ (800da3c ) 800d948: f852 1033 ldr.w r1, [r2, r3, lsl #3] 800d94c: 4b3c ldr r3, [pc, #240] @ (800da40 ) 800d94e: 681b ldr r3, [r3, #0] 800d950: 2201 movs r2, #1 800d952: fa02 f303 lsl.w r3, r2, r3 800d956: 43da mvns r2, r3 800d958: 6bfb ldr r3, [r7, #60] @ 0x3c 800d95a: 3b01 subs r3, #1 800d95c: 400a ands r2, r1 800d95e: 4937 ldr r1, [pc, #220] @ (800da3c ) 800d960: f841 2033 str.w r2, [r1, r3, lsl #3] for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) 800d964: 6bfb ldr r3, [r7, #60] @ 0x3c 800d966: 3b01 subs r3, #1 800d968: 63fb str r3, [r7, #60] @ 0x3c 800d96a: 6bfb ldr r3, [r7, #60] @ 0x3c 800d96c: 2b00 cmp r3, #0 800d96e: d1e8 bne.n 800d942 800d970: 6a3b ldr r3, [r7, #32] 800d972: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800d974: 697b ldr r3, [r7, #20] 800d976: f383 8810 msr PRIMASK, r3 } 800d97a: bf00 nop } UTIL_SEQ_EXIT_CRITICAL_SECTION( ); /* Execute the task */ TaskCb[CurrentTaskIdx]( ); 800d97c: 4b30 ldr r3, [pc, #192] @ (800da40 ) 800d97e: 681b ldr r3, [r3, #0] 800d980: 4a30 ldr r2, [pc, #192] @ (800da44 ) 800d982: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800d986: 4798 blx r3 local_taskset = TaskSet; 800d988: 4b28 ldr r3, [pc, #160] @ (800da2c ) 800d98a: 681b ldr r3, [r3, #0] 800d98c: 63bb str r3, [r7, #56] @ 0x38 local_evtset = EvtSet; 800d98e: 4b28 ldr r3, [pc, #160] @ (800da30 ) 800d990: 681b ldr r3, [r3, #0] 800d992: 637b str r3, [r7, #52] @ 0x34 local_taskmask = TaskMask; 800d994: 4b27 ldr r3, [pc, #156] @ (800da34 ) 800d996: 681b ldr r3, [r3, #0] 800d998: 633b str r3, [r7, #48] @ 0x30 local_evtwaited = EvtWaited; 800d99a: 4b27 ldr r3, [pc, #156] @ (800da38 ) 800d99c: 681b ldr r3, [r3, #0] 800d99e: 62fb str r3, [r7, #44] @ 0x2c while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) 800d9a0: 6bba ldr r2, [r7, #56] @ 0x38 800d9a2: 6b3b ldr r3, [r7, #48] @ 0x30 800d9a4: 401a ands r2, r3 800d9a6: 4b20 ldr r3, [pc, #128] @ (800da28 ) 800d9a8: 681b ldr r3, [r3, #0] 800d9aa: 4013 ands r3, r2 800d9ac: 2b00 cmp r3, #0 800d9ae: d005 beq.n 800d9bc 800d9b0: 6b7a ldr r2, [r7, #52] @ 0x34 800d9b2: 6afb ldr r3, [r7, #44] @ 0x2c 800d9b4: 4013 ands r3, r2 800d9b6: 2b00 cmp r3, #0 800d9b8: f43f af64 beq.w 800d884 } /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; 800d9bc: 4b20 ldr r3, [pc, #128] @ (800da40 ) 800d9be: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d9c2: 601a str r2, [r3, #0] UTIL_SEQ_PreIdle( ); 800d9c4: f000 f840 bl 800da48 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800d9c8: f3ef 8310 mrs r3, PRIMASK 800d9cc: 613b str r3, [r7, #16] return(result); 800d9ce: 693b ldr r3, [r7, #16] UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); 800d9d0: 61fb str r3, [r7, #28] __ASM volatile ("cpsid i" : : : "memory"); 800d9d2: b672 cpsid i } 800d9d4: bf00 nop local_taskset = TaskSet; 800d9d6: 4b15 ldr r3, [pc, #84] @ (800da2c ) 800d9d8: 681b ldr r3, [r3, #0] 800d9da: 63bb str r3, [r7, #56] @ 0x38 local_evtset = EvtSet; 800d9dc: 4b14 ldr r3, [pc, #80] @ (800da30 ) 800d9de: 681b ldr r3, [r3, #0] 800d9e0: 637b str r3, [r7, #52] @ 0x34 local_taskmask = TaskMask; 800d9e2: 4b14 ldr r3, [pc, #80] @ (800da34 ) 800d9e4: 681b ldr r3, [r3, #0] 800d9e6: 633b str r3, [r7, #48] @ 0x30 if ((local_taskset & local_taskmask & SuperMask) == 0U) 800d9e8: 6bba ldr r2, [r7, #56] @ 0x38 800d9ea: 6b3b ldr r3, [r7, #48] @ 0x30 800d9ec: 401a ands r2, r3 800d9ee: 4b0e ldr r3, [pc, #56] @ (800da28 ) 800d9f0: 681b ldr r3, [r3, #0] 800d9f2: 4013 ands r3, r2 800d9f4: 2b00 cmp r3, #0 800d9f6: d107 bne.n 800da08 { if ((local_evtset & EvtWaited)== 0U) 800d9f8: 4b0f ldr r3, [pc, #60] @ (800da38 ) 800d9fa: 681a ldr r2, [r3, #0] 800d9fc: 6b7b ldr r3, [r7, #52] @ 0x34 800d9fe: 4013 ands r3, r2 800da00: 2b00 cmp r3, #0 800da02: d101 bne.n 800da08 { UTIL_SEQ_Idle( ); 800da04: f7f3 f8ca bl 8000b9c 800da08: 69fb ldr r3, [r7, #28] 800da0a: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800da0c: 68fb ldr r3, [r7, #12] 800da0e: f383 8810 msr PRIMASK, r3 } 800da12: bf00 nop } } UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); UTIL_SEQ_PostIdle( ); 800da14: f000 f81e bl 800da54 /* restore the mask from UTIL_SEQ_Run() */ SuperMask = super_mask_backup; 800da18: 4a03 ldr r2, [pc, #12] @ (800da28 ) 800da1a: 6abb ldr r3, [r7, #40] @ 0x28 800da1c: 6013 str r3, [r2, #0] return; 800da1e: bf00 nop } 800da20: 3740 adds r7, #64 @ 0x40 800da22: 46bd mov sp, r7 800da24: bd80 pop {r7, pc} 800da26: bf00 nop 800da28: 20000038 .word 0x20000038 800da2c: 20000be8 .word 0x20000be8 800da30: 20000bec .word 0x20000bec 800da34: 20000034 .word 0x20000034 800da38: 20000bf0 .word 0x20000bf0 800da3c: 20000bfc .word 0x20000bfc 800da40: 20000bf4 .word 0x20000bf4 800da44: 20000bf8 .word 0x20000bf8 0800da48 : { return; } __WEAK void UTIL_SEQ_PreIdle( void ) { 800da48: b480 push {r7} 800da4a: af00 add r7, sp, #0 /* * Unless specified by the application, there is nothing to be done */ return; 800da4c: bf00 nop } 800da4e: 46bd mov sp, r7 800da50: bc80 pop {r7} 800da52: 4770 bx lr 0800da54 : __WEAK void UTIL_SEQ_PostIdle( void ) { 800da54: b480 push {r7} 800da56: af00 add r7, sp, #0 /* * Unless specified by the application, there is nothing to be done */ return; 800da58: bf00 nop } 800da5a: 46bd mov sp, r7 800da5c: bc80 pop {r7} 800da5e: 4770 bx lr 0800da60 : * @brief return the position of the first bit set to 1 * @param Value 32 bit value * @retval bit position */ uint8_t SEQ_BitPosition(uint32_t Value) { 800da60: b480 push {r7} 800da62: b085 sub sp, #20 800da64: af00 add r7, sp, #0 800da66: 6078 str r0, [r7, #4] uint8_t n = 0U; 800da68: 2300 movs r3, #0 800da6a: 73fb strb r3, [r7, #15] uint32_t lvalue = Value; 800da6c: 687b ldr r3, [r7, #4] 800da6e: 60bb str r3, [r7, #8] if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; } 800da70: 68bb ldr r3, [r7, #8] 800da72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800da76: d204 bcs.n 800da82 800da78: 2310 movs r3, #16 800da7a: 73fb strb r3, [r7, #15] 800da7c: 68bb ldr r3, [r7, #8] 800da7e: 041b lsls r3, r3, #16 800da80: 60bb str r3, [r7, #8] if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; } 800da82: 68bb ldr r3, [r7, #8] 800da84: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800da88: d205 bcs.n 800da96 800da8a: 7bfb ldrb r3, [r7, #15] 800da8c: 3308 adds r3, #8 800da8e: 73fb strb r3, [r7, #15] 800da90: 68bb ldr r3, [r7, #8] 800da92: 021b lsls r3, r3, #8 800da94: 60bb str r3, [r7, #8] if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; } 800da96: 68bb ldr r3, [r7, #8] 800da98: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800da9c: d205 bcs.n 800daaa 800da9e: 7bfb ldrb r3, [r7, #15] 800daa0: 3304 adds r3, #4 800daa2: 73fb strb r3, [r7, #15] 800daa4: 68bb ldr r3, [r7, #8] 800daa6: 011b lsls r3, r3, #4 800daa8: 60bb str r3, [r7, #8] n += SEQ_clz_table_4bit[lvalue >> (32-4)]; 800daaa: 68bb ldr r3, [r7, #8] 800daac: 0f1b lsrs r3, r3, #28 800daae: 4a07 ldr r2, [pc, #28] @ (800dacc ) 800dab0: 5cd2 ldrb r2, [r2, r3] 800dab2: 7bfb ldrb r3, [r7, #15] 800dab4: 4413 add r3, r2 800dab6: 73fb strb r3, [r7, #15] return (uint8_t)(31U-n); 800dab8: 7bfb ldrb r3, [r7, #15] 800daba: f1c3 031f rsb r3, r3, #31 800dabe: b2db uxtb r3, r3 } 800dac0: 4618 mov r0, r3 800dac2: 3714 adds r7, #20 800dac4: 46bd mov sp, r7 800dac6: bc80 pop {r7} 800dac8: 4770 bx lr 800daca: bf00 nop 800dacc: 0800fcbc .word 0x0800fcbc 0800dad0 : * @addtogroup TIMER_SERVER_exported_function * @{ */ UTIL_TIMER_Status_t UTIL_TIMER_Init(void) { 800dad0: b580 push {r7, lr} 800dad2: af00 add r7, sp, #0 UTIL_TIMER_INIT_CRITICAL_SECTION(); TimerListHead = NULL; 800dad4: 4b04 ldr r3, [pc, #16] @ (800dae8 ) 800dad6: 2200 movs r2, #0 800dad8: 601a str r2, [r3, #0] return UTIL_TimerDriver.InitTimer(); 800dada: 4b04 ldr r3, [pc, #16] @ (800daec ) 800dadc: 681b ldr r3, [r3, #0] 800dade: 4798 blx r3 800dae0: 4603 mov r3, r0 } 800dae2: 4618 mov r0, r3 800dae4: bd80 pop {r7, pc} 800dae6: bf00 nop 800dae8: 20000c04 .word 0x20000c04 800daec: 0800fb04 .word 0x0800fb04 0800daf0 : { return UTIL_TimerDriver.DeInitTimer(); } UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument) { 800daf0: b580 push {r7, lr} 800daf2: b084 sub sp, #16 800daf4: af00 add r7, sp, #0 800daf6: 60f8 str r0, [r7, #12] 800daf8: 60b9 str r1, [r7, #8] 800dafa: 603b str r3, [r7, #0] 800dafc: 4613 mov r3, r2 800dafe: 71fb strb r3, [r7, #7] if((TimerObject != NULL) && (Callback != NULL)) 800db00: 68fb ldr r3, [r7, #12] 800db02: 2b00 cmp r3, #0 800db04: d023 beq.n 800db4e 800db06: 683b ldr r3, [r7, #0] 800db08: 2b00 cmp r3, #0 800db0a: d020 beq.n 800db4e { TimerObject->Timestamp = 0U; 800db0c: 68fb ldr r3, [r7, #12] 800db0e: 2200 movs r2, #0 800db10: 601a str r2, [r3, #0] TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); 800db12: 4b11 ldr r3, [pc, #68] @ (800db58 ) 800db14: 6a5b ldr r3, [r3, #36] @ 0x24 800db16: 68b8 ldr r0, [r7, #8] 800db18: 4798 blx r3 800db1a: 4602 mov r2, r0 800db1c: 68fb ldr r3, [r7, #12] 800db1e: 605a str r2, [r3, #4] TimerObject->IsPending = 0U; 800db20: 68fb ldr r3, [r7, #12] 800db22: 2200 movs r2, #0 800db24: 721a strb r2, [r3, #8] TimerObject->IsRunning = 0U; 800db26: 68fb ldr r3, [r7, #12] 800db28: 2200 movs r2, #0 800db2a: 725a strb r2, [r3, #9] TimerObject->IsReloadStopped = 0U; 800db2c: 68fb ldr r3, [r7, #12] 800db2e: 2200 movs r2, #0 800db30: 729a strb r2, [r3, #10] TimerObject->Callback = Callback; 800db32: 68fb ldr r3, [r7, #12] 800db34: 683a ldr r2, [r7, #0] 800db36: 60da str r2, [r3, #12] TimerObject->argument = Argument; 800db38: 68fb ldr r3, [r7, #12] 800db3a: 69ba ldr r2, [r7, #24] 800db3c: 611a str r2, [r3, #16] TimerObject->Mode = Mode; 800db3e: 68fb ldr r3, [r7, #12] 800db40: 79fa ldrb r2, [r7, #7] 800db42: 72da strb r2, [r3, #11] TimerObject->Next = NULL; 800db44: 68fb ldr r3, [r7, #12] 800db46: 2200 movs r2, #0 800db48: 615a str r2, [r3, #20] return UTIL_TIMER_OK; 800db4a: 2300 movs r3, #0 800db4c: e000 b.n 800db50 } else { return UTIL_TIMER_INVALID_PARAM; 800db4e: 2301 movs r3, #1 } } 800db50: 4618 mov r0, r3 800db52: 3710 adds r7, #16 800db54: 46bd mov sp, r7 800db56: bd80 pop {r7, pc} 800db58: 0800fb04 .word 0x0800fb04 0800db5c : UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject) { 800db5c: b580 push {r7, lr} 800db5e: b08a sub sp, #40 @ 0x28 800db60: af00 add r7, sp, #0 800db62: 6078 str r0, [r7, #4] UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 800db64: 2300 movs r3, #0 800db66: f887 3027 strb.w r3, [r7, #39] @ 0x27 uint32_t elapsedTime; uint32_t minValue; uint32_t ticks; if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U)) 800db6a: 687b ldr r3, [r7, #4] 800db6c: 2b00 cmp r3, #0 800db6e: d056 beq.n 800dc1e 800db70: 6878 ldr r0, [r7, #4] 800db72: f000 f9a9 bl 800dec8 800db76: 4603 mov r3, r0 800db78: f083 0301 eor.w r3, r3, #1 800db7c: b2db uxtb r3, r3 800db7e: 2b00 cmp r3, #0 800db80: d04d beq.n 800dc1e 800db82: 687b ldr r3, [r7, #4] 800db84: 7a5b ldrb r3, [r3, #9] 800db86: 2b00 cmp r3, #0 800db88: d149 bne.n 800dc1e __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800db8a: f3ef 8310 mrs r3, PRIMASK 800db8e: 613b str r3, [r7, #16] return(result); 800db90: 693b ldr r3, [r7, #16] { UTIL_TIMER_ENTER_CRITICAL_SECTION(); 800db92: 61fb str r3, [r7, #28] __ASM volatile ("cpsid i" : : : "memory"); 800db94: b672 cpsid i } 800db96: bf00 nop ticks = TimerObject->ReloadValue; 800db98: 687b ldr r3, [r7, #4] 800db9a: 685b ldr r3, [r3, #4] 800db9c: 623b str r3, [r7, #32] minValue = UTIL_TimerDriver.GetMinimumTimeout( ); 800db9e: 4b24 ldr r3, [pc, #144] @ (800dc30 ) 800dba0: 6a1b ldr r3, [r3, #32] 800dba2: 4798 blx r3 800dba4: 61b8 str r0, [r7, #24] if( ticks < minValue ) 800dba6: 6a3a ldr r2, [r7, #32] 800dba8: 69bb ldr r3, [r7, #24] 800dbaa: 429a cmp r2, r3 800dbac: d201 bcs.n 800dbb2 { ticks = minValue; 800dbae: 69bb ldr r3, [r7, #24] 800dbb0: 623b str r3, [r7, #32] } TimerObject->Timestamp = ticks; 800dbb2: 687b ldr r3, [r7, #4] 800dbb4: 6a3a ldr r2, [r7, #32] 800dbb6: 601a str r2, [r3, #0] TimerObject->IsPending = 0U; 800dbb8: 687b ldr r3, [r7, #4] 800dbba: 2200 movs r2, #0 800dbbc: 721a strb r2, [r3, #8] TimerObject->IsRunning = 1U; 800dbbe: 687b ldr r3, [r7, #4] 800dbc0: 2201 movs r2, #1 800dbc2: 725a strb r2, [r3, #9] TimerObject->IsReloadStopped = 0U; 800dbc4: 687b ldr r3, [r7, #4] 800dbc6: 2200 movs r2, #0 800dbc8: 729a strb r2, [r3, #10] if( TimerListHead == NULL ) 800dbca: 4b1a ldr r3, [pc, #104] @ (800dc34 ) 800dbcc: 681b ldr r3, [r3, #0] 800dbce: 2b00 cmp r3, #0 800dbd0: d106 bne.n 800dbe0 { UTIL_TimerDriver.SetTimerContext(); 800dbd2: 4b17 ldr r3, [pc, #92] @ (800dc30 ) 800dbd4: 691b ldr r3, [r3, #16] 800dbd6: 4798 blx r3 TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */ 800dbd8: 6878 ldr r0, [r7, #4] 800dbda: f000 f9eb bl 800dfb4 800dbde: e017 b.n 800dc10 } else { elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( ); 800dbe0: 4b13 ldr r3, [pc, #76] @ (800dc30 ) 800dbe2: 699b ldr r3, [r3, #24] 800dbe4: 4798 blx r3 800dbe6: 6178 str r0, [r7, #20] TimerObject->Timestamp += elapsedTime; 800dbe8: 687b ldr r3, [r7, #4] 800dbea: 681a ldr r2, [r3, #0] 800dbec: 697b ldr r3, [r7, #20] 800dbee: 441a add r2, r3 800dbf0: 687b ldr r3, [r7, #4] 800dbf2: 601a str r2, [r3, #0] if( TimerObject->Timestamp < TimerListHead->Timestamp ) 800dbf4: 687b ldr r3, [r7, #4] 800dbf6: 681a ldr r2, [r3, #0] 800dbf8: 4b0e ldr r3, [pc, #56] @ (800dc34 ) 800dbfa: 681b ldr r3, [r3, #0] 800dbfc: 681b ldr r3, [r3, #0] 800dbfe: 429a cmp r2, r3 800dc00: d203 bcs.n 800dc0a { TimerInsertNewHeadTimer( TimerObject); 800dc02: 6878 ldr r0, [r7, #4] 800dc04: f000 f9d6 bl 800dfb4 800dc08: e002 b.n 800dc10 } else { TimerInsertTimer( TimerObject); 800dc0a: 6878 ldr r0, [r7, #4] 800dc0c: f000 f9a2 bl 800df54 800dc10: 69fb ldr r3, [r7, #28] 800dc12: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800dc14: 68fb ldr r3, [r7, #12] 800dc16: f383 8810 msr PRIMASK, r3 } 800dc1a: bf00 nop { 800dc1c: e002 b.n 800dc24 } UTIL_TIMER_EXIT_CRITICAL_SECTION(); } else { ret = UTIL_TIMER_INVALID_PARAM; 800dc1e: 2301 movs r3, #1 800dc20: f887 3027 strb.w r3, [r7, #39] @ 0x27 } return ret; 800dc24: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 } 800dc28: 4618 mov r0, r3 800dc2a: 3728 adds r7, #40 @ 0x28 800dc2c: 46bd mov sp, r7 800dc2e: bd80 pop {r7, pc} 800dc30: 0800fb04 .word 0x0800fb04 800dc34: 20000c04 .word 0x20000c04 0800dc38 : } return ret; } UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject ) { 800dc38: b580 push {r7, lr} 800dc3a: b088 sub sp, #32 800dc3c: af00 add r7, sp, #0 800dc3e: 6078 str r0, [r7, #4] UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 800dc40: 2300 movs r3, #0 800dc42: 77fb strb r3, [r7, #31] if (NULL != TimerObject) 800dc44: 687b ldr r3, [r7, #4] 800dc46: 2b00 cmp r3, #0 800dc48: d05b beq.n 800dd02 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800dc4a: f3ef 8310 mrs r3, PRIMASK 800dc4e: 60fb str r3, [r7, #12] return(result); 800dc50: 68fb ldr r3, [r7, #12] { UTIL_TIMER_ENTER_CRITICAL_SECTION(); 800dc52: 613b str r3, [r7, #16] __ASM volatile ("cpsid i" : : : "memory"); 800dc54: b672 cpsid i } 800dc56: bf00 nop UTIL_TIMER_Object_t* prev = TimerListHead; 800dc58: 4b2d ldr r3, [pc, #180] @ (800dd10 ) 800dc5a: 681b ldr r3, [r3, #0] 800dc5c: 61bb str r3, [r7, #24] UTIL_TIMER_Object_t* cur = TimerListHead; 800dc5e: 4b2c ldr r3, [pc, #176] @ (800dd10 ) 800dc60: 681b ldr r3, [r3, #0] 800dc62: 617b str r3, [r7, #20] TimerObject->IsReloadStopped = 1U; 800dc64: 687b ldr r3, [r7, #4] 800dc66: 2201 movs r2, #1 800dc68: 729a strb r2, [r3, #10] /* List is empty or the Obj to stop does not exist */ if(NULL != TimerListHead) 800dc6a: 4b29 ldr r3, [pc, #164] @ (800dd10 ) 800dc6c: 681b ldr r3, [r3, #0] 800dc6e: 2b00 cmp r3, #0 800dc70: d041 beq.n 800dcf6 { TimerObject->IsRunning = 0U; 800dc72: 687b ldr r3, [r7, #4] 800dc74: 2200 movs r2, #0 800dc76: 725a strb r2, [r3, #9] if( TimerListHead == TimerObject ) /* Stop the Head */ 800dc78: 4b25 ldr r3, [pc, #148] @ (800dd10 ) 800dc7a: 681b ldr r3, [r3, #0] 800dc7c: 687a ldr r2, [r7, #4] 800dc7e: 429a cmp r2, r3 800dc80: d134 bne.n 800dcec { TimerListHead->IsPending = 0; 800dc82: 4b23 ldr r3, [pc, #140] @ (800dd10 ) 800dc84: 681b ldr r3, [r3, #0] 800dc86: 2200 movs r2, #0 800dc88: 721a strb r2, [r3, #8] if( TimerListHead->Next != NULL ) 800dc8a: 4b21 ldr r3, [pc, #132] @ (800dd10 ) 800dc8c: 681b ldr r3, [r3, #0] 800dc8e: 695b ldr r3, [r3, #20] 800dc90: 2b00 cmp r3, #0 800dc92: d00a beq.n 800dcaa { TimerListHead = TimerListHead->Next; 800dc94: 4b1e ldr r3, [pc, #120] @ (800dd10 ) 800dc96: 681b ldr r3, [r3, #0] 800dc98: 695b ldr r3, [r3, #20] 800dc9a: 4a1d ldr r2, [pc, #116] @ (800dd10 ) 800dc9c: 6013 str r3, [r2, #0] TimerSetTimeout( TimerListHead ); 800dc9e: 4b1c ldr r3, [pc, #112] @ (800dd10 ) 800dca0: 681b ldr r3, [r3, #0] 800dca2: 4618 mov r0, r3 800dca4: f000 f92c bl 800df00 800dca8: e023 b.n 800dcf2 } else { UTIL_TimerDriver.StopTimerEvt( ); 800dcaa: 4b1a ldr r3, [pc, #104] @ (800dd14 ) 800dcac: 68db ldr r3, [r3, #12] 800dcae: 4798 blx r3 TimerListHead = NULL; 800dcb0: 4b17 ldr r3, [pc, #92] @ (800dd10 ) 800dcb2: 2200 movs r2, #0 800dcb4: 601a str r2, [r3, #0] 800dcb6: e01c b.n 800dcf2 } else /* Stop an object within the list */ { while( cur != NULL ) { if( cur == TimerObject ) 800dcb8: 697a ldr r2, [r7, #20] 800dcba: 687b ldr r3, [r7, #4] 800dcbc: 429a cmp r2, r3 800dcbe: d110 bne.n 800dce2 { if( cur->Next != NULL ) 800dcc0: 697b ldr r3, [r7, #20] 800dcc2: 695b ldr r3, [r3, #20] 800dcc4: 2b00 cmp r3, #0 800dcc6: d006 beq.n 800dcd6 { cur = cur->Next; 800dcc8: 697b ldr r3, [r7, #20] 800dcca: 695b ldr r3, [r3, #20] 800dccc: 617b str r3, [r7, #20] prev->Next = cur; 800dcce: 69bb ldr r3, [r7, #24] 800dcd0: 697a ldr r2, [r7, #20] 800dcd2: 615a str r2, [r3, #20] else { cur = NULL; prev->Next = cur; } break; 800dcd4: e00d b.n 800dcf2 cur = NULL; 800dcd6: 2300 movs r3, #0 800dcd8: 617b str r3, [r7, #20] prev->Next = cur; 800dcda: 69bb ldr r3, [r7, #24] 800dcdc: 697a ldr r2, [r7, #20] 800dcde: 615a str r2, [r3, #20] break; 800dce0: e007 b.n 800dcf2 } else { prev = cur; 800dce2: 697b ldr r3, [r7, #20] 800dce4: 61bb str r3, [r7, #24] cur = cur->Next; 800dce6: 697b ldr r3, [r7, #20] 800dce8: 695b ldr r3, [r3, #20] 800dcea: 617b str r3, [r7, #20] while( cur != NULL ) 800dcec: 697b ldr r3, [r7, #20] 800dcee: 2b00 cmp r3, #0 800dcf0: d1e2 bne.n 800dcb8 } } } ret = UTIL_TIMER_OK; 800dcf2: 2300 movs r3, #0 800dcf4: 77fb strb r3, [r7, #31] 800dcf6: 693b ldr r3, [r7, #16] 800dcf8: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800dcfa: 68bb ldr r3, [r7, #8] 800dcfc: f383 8810 msr PRIMASK, r3 } 800dd00: e001 b.n 800dd06 } UTIL_TIMER_EXIT_CRITICAL_SECTION(); } else { ret = UTIL_TIMER_INVALID_PARAM; 800dd02: 2301 movs r3, #1 800dd04: 77fb strb r3, [r7, #31] } return ret; 800dd06: 7ffb ldrb r3, [r7, #31] } 800dd08: 4618 mov r0, r3 800dd0a: 3720 adds r7, #32 800dd0c: 46bd mov sp, r7 800dd0e: bd80 pop {r7, pc} 800dd10: 20000c04 .word 0x20000c04 800dd14: 0800fb04 .word 0x0800fb04 0800dd18 : UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue) { 800dd18: b580 push {r7, lr} 800dd1a: b084 sub sp, #16 800dd1c: af00 add r7, sp, #0 800dd1e: 6078 str r0, [r7, #4] 800dd20: 6039 str r1, [r7, #0] UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; 800dd22: 2300 movs r3, #0 800dd24: 73fb strb r3, [r7, #15] if(NULL == TimerObject) 800dd26: 687b ldr r3, [r7, #4] 800dd28: 2b00 cmp r3, #0 800dd2a: d102 bne.n 800dd32 { ret = UTIL_TIMER_INVALID_PARAM; 800dd2c: 2301 movs r3, #1 800dd2e: 73fb strb r3, [r7, #15] 800dd30: e014 b.n 800dd5c } else { TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue); 800dd32: 4b0d ldr r3, [pc, #52] @ (800dd68 ) 800dd34: 6a5b ldr r3, [r3, #36] @ 0x24 800dd36: 6838 ldr r0, [r7, #0] 800dd38: 4798 blx r3 800dd3a: 4602 mov r2, r0 800dd3c: 687b ldr r3, [r7, #4] 800dd3e: 605a str r2, [r3, #4] if(TimerExists(TimerObject)) 800dd40: 6878 ldr r0, [r7, #4] 800dd42: f000 f8c1 bl 800dec8 800dd46: 4603 mov r3, r0 800dd48: 2b00 cmp r3, #0 800dd4a: d007 beq.n 800dd5c { (void)UTIL_TIMER_Stop(TimerObject); 800dd4c: 6878 ldr r0, [r7, #4] 800dd4e: f7ff ff73 bl 800dc38 ret = UTIL_TIMER_Start(TimerObject); 800dd52: 6878 ldr r0, [r7, #4] 800dd54: f7ff ff02 bl 800db5c 800dd58: 4603 mov r3, r0 800dd5a: 73fb strb r3, [r7, #15] } } return ret; 800dd5c: 7bfb ldrb r3, [r7, #15] } 800dd5e: 4618 mov r0, r3 800dd60: 3710 adds r7, #16 800dd62: 46bd mov sp, r7 800dd64: bd80 pop {r7, pc} 800dd66: bf00 nop 800dd68: 0800fb04 .word 0x0800fb04 0800dd6c : } return NextTimer; } void UTIL_TIMER_IRQ_Handler( void ) { 800dd6c: b590 push {r4, r7, lr} 800dd6e: b089 sub sp, #36 @ 0x24 800dd70: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800dd72: f3ef 8310 mrs r3, PRIMASK 800dd76: 60bb str r3, [r7, #8] return(result); 800dd78: 68bb ldr r3, [r7, #8] UTIL_TIMER_Object_t* cur; uint32_t old, now, DeltaContext; UTIL_TIMER_ENTER_CRITICAL_SECTION(); 800dd7a: 61bb str r3, [r7, #24] __ASM volatile ("cpsid i" : : : "memory"); 800dd7c: b672 cpsid i } 800dd7e: bf00 nop old = UTIL_TimerDriver.GetTimerContext( ); 800dd80: 4b38 ldr r3, [pc, #224] @ (800de64 ) 800dd82: 695b ldr r3, [r3, #20] 800dd84: 4798 blx r3 800dd86: 6178 str r0, [r7, #20] now = UTIL_TimerDriver.SetTimerContext( ); 800dd88: 4b36 ldr r3, [pc, #216] @ (800de64 ) 800dd8a: 691b ldr r3, [r3, #16] 800dd8c: 4798 blx r3 800dd8e: 6138 str r0, [r7, #16] DeltaContext = now - old; /*intentional wrap around */ 800dd90: 693a ldr r2, [r7, #16] 800dd92: 697b ldr r3, [r7, #20] 800dd94: 1ad3 subs r3, r2, r3 800dd96: 60fb str r3, [r7, #12] /* update timeStamp based upon new Time Reference*/ /* because delta context should never exceed 2^32*/ if ( TimerListHead != NULL ) 800dd98: 4b33 ldr r3, [pc, #204] @ (800de68 ) 800dd9a: 681b ldr r3, [r3, #0] 800dd9c: 2b00 cmp r3, #0 800dd9e: d037 beq.n 800de10 { cur = TimerListHead; 800dda0: 4b31 ldr r3, [pc, #196] @ (800de68 ) 800dda2: 681b ldr r3, [r3, #0] 800dda4: 61fb str r3, [r7, #28] do { if (cur->Timestamp > DeltaContext) 800dda6: 69fb ldr r3, [r7, #28] 800dda8: 681b ldr r3, [r3, #0] 800ddaa: 68fa ldr r2, [r7, #12] 800ddac: 429a cmp r2, r3 800ddae: d206 bcs.n 800ddbe { cur->Timestamp -= DeltaContext; 800ddb0: 69fb ldr r3, [r7, #28] 800ddb2: 681a ldr r2, [r3, #0] 800ddb4: 68fb ldr r3, [r7, #12] 800ddb6: 1ad2 subs r2, r2, r3 800ddb8: 69fb ldr r3, [r7, #28] 800ddba: 601a str r2, [r3, #0] 800ddbc: e002 b.n 800ddc4 } else { cur->Timestamp = 0; 800ddbe: 69fb ldr r3, [r7, #28] 800ddc0: 2200 movs r2, #0 800ddc2: 601a str r2, [r3, #0] } cur = cur->Next; 800ddc4: 69fb ldr r3, [r7, #28] 800ddc6: 695b ldr r3, [r3, #20] 800ddc8: 61fb str r3, [r7, #28] } while(cur != NULL); 800ddca: 69fb ldr r3, [r7, #28] 800ddcc: 2b00 cmp r3, #0 800ddce: d1ea bne.n 800dda6 } /* Execute expired timer and update the list */ while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) 800ddd0: e01e b.n 800de10 { cur = TimerListHead; 800ddd2: 4b25 ldr r3, [pc, #148] @ (800de68 ) 800ddd4: 681b ldr r3, [r3, #0] 800ddd6: 61fb str r3, [r7, #28] TimerListHead = TimerListHead->Next; 800ddd8: 4b23 ldr r3, [pc, #140] @ (800de68 ) 800ddda: 681b ldr r3, [r3, #0] 800dddc: 695b ldr r3, [r3, #20] 800ddde: 4a22 ldr r2, [pc, #136] @ (800de68 ) 800dde0: 6013 str r3, [r2, #0] cur->IsPending = 0; 800dde2: 69fb ldr r3, [r7, #28] 800dde4: 2200 movs r2, #0 800dde6: 721a strb r2, [r3, #8] cur->IsRunning = 0; 800dde8: 69fb ldr r3, [r7, #28] 800ddea: 2200 movs r2, #0 800ddec: 725a strb r2, [r3, #9] cur->Callback(cur->argument); 800ddee: 69fb ldr r3, [r7, #28] 800ddf0: 68db ldr r3, [r3, #12] 800ddf2: 69fa ldr r2, [r7, #28] 800ddf4: 6912 ldr r2, [r2, #16] 800ddf6: 4610 mov r0, r2 800ddf8: 4798 blx r3 if(( cur->Mode == UTIL_TIMER_PERIODIC) && (cur->IsReloadStopped == 0U)) 800ddfa: 69fb ldr r3, [r7, #28] 800ddfc: 7adb ldrb r3, [r3, #11] 800ddfe: 2b01 cmp r3, #1 800de00: d106 bne.n 800de10 800de02: 69fb ldr r3, [r7, #28] 800de04: 7a9b ldrb r3, [r3, #10] 800de06: 2b00 cmp r3, #0 800de08: d102 bne.n 800de10 { (void)UTIL_TIMER_Start(cur); 800de0a: 69f8 ldr r0, [r7, #28] 800de0c: f7ff fea6 bl 800db5c while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) 800de10: 4b15 ldr r3, [pc, #84] @ (800de68 ) 800de12: 681b ldr r3, [r3, #0] 800de14: 2b00 cmp r3, #0 800de16: d00d beq.n 800de34 800de18: 4b13 ldr r3, [pc, #76] @ (800de68 ) 800de1a: 681b ldr r3, [r3, #0] 800de1c: 681b ldr r3, [r3, #0] 800de1e: 2b00 cmp r3, #0 800de20: d0d7 beq.n 800ddd2 800de22: 4b11 ldr r3, [pc, #68] @ (800de68 ) 800de24: 681b ldr r3, [r3, #0] 800de26: 681c ldr r4, [r3, #0] 800de28: 4b0e ldr r3, [pc, #56] @ (800de64 ) 800de2a: 699b ldr r3, [r3, #24] 800de2c: 4798 blx r3 800de2e: 4603 mov r3, r0 800de30: 429c cmp r4, r3 800de32: d3ce bcc.n 800ddd2 } } /* start the next TimerListHead if it exists and it is not pending*/ if(( TimerListHead != NULL ) && (TimerListHead->IsPending == 0U)) 800de34: 4b0c ldr r3, [pc, #48] @ (800de68 ) 800de36: 681b ldr r3, [r3, #0] 800de38: 2b00 cmp r3, #0 800de3a: d009 beq.n 800de50 800de3c: 4b0a ldr r3, [pc, #40] @ (800de68 ) 800de3e: 681b ldr r3, [r3, #0] 800de40: 7a1b ldrb r3, [r3, #8] 800de42: 2b00 cmp r3, #0 800de44: d104 bne.n 800de50 { TimerSetTimeout( TimerListHead ); 800de46: 4b08 ldr r3, [pc, #32] @ (800de68 ) 800de48: 681b ldr r3, [r3, #0] 800de4a: 4618 mov r0, r3 800de4c: f000 f858 bl 800df00 800de50: 69bb ldr r3, [r7, #24] 800de52: 607b str r3, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800de54: 687b ldr r3, [r7, #4] 800de56: f383 8810 msr PRIMASK, r3 } 800de5a: bf00 nop } UTIL_TIMER_EXIT_CRITICAL_SECTION(); } 800de5c: bf00 nop 800de5e: 3724 adds r7, #36 @ 0x24 800de60: 46bd mov sp, r7 800de62: bd90 pop {r4, r7, pc} 800de64: 0800fb04 .word 0x0800fb04 800de68: 20000c04 .word 0x20000c04 0800de6c : UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void) { 800de6c: b580 push {r7, lr} 800de6e: b082 sub sp, #8 800de70: af00 add r7, sp, #0 uint32_t now = UTIL_TimerDriver.GetTimerValue( ); 800de72: 4b06 ldr r3, [pc, #24] @ (800de8c ) 800de74: 69db ldr r3, [r3, #28] 800de76: 4798 blx r3 800de78: 6078 str r0, [r7, #4] return UTIL_TimerDriver.Tick2ms(now); 800de7a: 4b04 ldr r3, [pc, #16] @ (800de8c ) 800de7c: 6a9b ldr r3, [r3, #40] @ 0x28 800de7e: 6878 ldr r0, [r7, #4] 800de80: 4798 blx r3 800de82: 4603 mov r3, r0 } 800de84: 4618 mov r0, r3 800de86: 3708 adds r7, #8 800de88: 46bd mov sp, r7 800de8a: bd80 pop {r7, pc} 800de8c: 0800fb04 .word 0x0800fb04 0800de90 : UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past ) { 800de90: b580 push {r7, lr} 800de92: b084 sub sp, #16 800de94: af00 add r7, sp, #0 800de96: 6078 str r0, [r7, #4] uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( ); 800de98: 4b0a ldr r3, [pc, #40] @ (800dec4 ) 800de9a: 69db ldr r3, [r3, #28] 800de9c: 4798 blx r3 800de9e: 60f8 str r0, [r7, #12] uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past ); 800dea0: 4b08 ldr r3, [pc, #32] @ (800dec4 ) 800dea2: 6a5b ldr r3, [r3, #36] @ 0x24 800dea4: 6878 ldr r0, [r7, #4] 800dea6: 4798 blx r3 800dea8: 60b8 str r0, [r7, #8] /* intentional wrap around. Works Ok if tick duation below 1ms */ return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks ); 800deaa: 4b06 ldr r3, [pc, #24] @ (800dec4 ) 800deac: 6a9b ldr r3, [r3, #40] @ 0x28 800deae: 68f9 ldr r1, [r7, #12] 800deb0: 68ba ldr r2, [r7, #8] 800deb2: 1a8a subs r2, r1, r2 800deb4: 4610 mov r0, r2 800deb6: 4798 blx r3 800deb8: 4603 mov r3, r0 } 800deba: 4618 mov r0, r3 800debc: 3710 adds r7, #16 800debe: 46bd mov sp, r7 800dec0: bd80 pop {r7, pc} 800dec2: bf00 nop 800dec4: 0800fb04 .word 0x0800fb04 0800dec8 : * * @param TimerObject Structure containing the timer object parameters * @retval 1 (the object is already in the list) or 0 */ bool TimerExists( UTIL_TIMER_Object_t *TimerObject ) { 800dec8: b480 push {r7} 800deca: b085 sub sp, #20 800decc: af00 add r7, sp, #0 800dece: 6078 str r0, [r7, #4] UTIL_TIMER_Object_t* cur = TimerListHead; 800ded0: 4b0a ldr r3, [pc, #40] @ (800defc ) 800ded2: 681b ldr r3, [r3, #0] 800ded4: 60fb str r3, [r7, #12] while( cur != NULL ) 800ded6: e008 b.n 800deea { if( cur == TimerObject ) 800ded8: 68fa ldr r2, [r7, #12] 800deda: 687b ldr r3, [r7, #4] 800dedc: 429a cmp r2, r3 800dede: d101 bne.n 800dee4 { return true; 800dee0: 2301 movs r3, #1 800dee2: e006 b.n 800def2 } cur = cur->Next; 800dee4: 68fb ldr r3, [r7, #12] 800dee6: 695b ldr r3, [r3, #20] 800dee8: 60fb str r3, [r7, #12] while( cur != NULL ) 800deea: 68fb ldr r3, [r7, #12] 800deec: 2b00 cmp r3, #0 800deee: d1f3 bne.n 800ded8 } return false; 800def0: 2300 movs r3, #0 } 800def2: 4618 mov r0, r3 800def4: 3714 adds r7, #20 800def6: 46bd mov sp, r7 800def8: bc80 pop {r7} 800defa: 4770 bx lr 800defc: 20000c04 .word 0x20000c04 0800df00 : * @brief Sets a timeout with the duration "timestamp" * * @param TimerObject Structure containing the timer object parameters */ void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ) { 800df00: b590 push {r4, r7, lr} 800df02: b085 sub sp, #20 800df04: af00 add r7, sp, #0 800df06: 6078 str r0, [r7, #4] uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( ); 800df08: 4b11 ldr r3, [pc, #68] @ (800df50 ) 800df0a: 6a1b ldr r3, [r3, #32] 800df0c: 4798 blx r3 800df0e: 60f8 str r0, [r7, #12] TimerObject->IsPending = 1; 800df10: 687b ldr r3, [r7, #4] 800df12: 2201 movs r2, #1 800df14: 721a strb r2, [r3, #8] /* In case deadline too soon */ if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) ) 800df16: 687b ldr r3, [r7, #4] 800df18: 681c ldr r4, [r3, #0] 800df1a: 4b0d ldr r3, [pc, #52] @ (800df50 ) 800df1c: 699b ldr r3, [r3, #24] 800df1e: 4798 blx r3 800df20: 4602 mov r2, r0 800df22: 68fb ldr r3, [r7, #12] 800df24: 4413 add r3, r2 800df26: 429c cmp r4, r3 800df28: d207 bcs.n 800df3a { TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks; 800df2a: 4b09 ldr r3, [pc, #36] @ (800df50 ) 800df2c: 699b ldr r3, [r3, #24] 800df2e: 4798 blx r3 800df30: 4602 mov r2, r0 800df32: 68fb ldr r3, [r7, #12] 800df34: 441a add r2, r3 800df36: 687b ldr r3, [r7, #4] 800df38: 601a str r2, [r3, #0] } UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp ); 800df3a: 4b05 ldr r3, [pc, #20] @ (800df50 ) 800df3c: 689b ldr r3, [r3, #8] 800df3e: 687a ldr r2, [r7, #4] 800df40: 6812 ldr r2, [r2, #0] 800df42: 4610 mov r0, r2 800df44: 4798 blx r3 } 800df46: bf00 nop 800df48: 3714 adds r7, #20 800df4a: 46bd mov sp, r7 800df4c: bd90 pop {r4, r7, pc} 800df4e: bf00 nop 800df50: 0800fb04 .word 0x0800fb04 0800df54 : * next timer to expire. * * @param TimerObject Structure containing the timer object parameters */ void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject) { 800df54: b480 push {r7} 800df56: b085 sub sp, #20 800df58: af00 add r7, sp, #0 800df5a: 6078 str r0, [r7, #4] UTIL_TIMER_Object_t* cur = TimerListHead; 800df5c: 4b14 ldr r3, [pc, #80] @ (800dfb0 ) 800df5e: 681b ldr r3, [r3, #0] 800df60: 60fb str r3, [r7, #12] UTIL_TIMER_Object_t* next = TimerListHead->Next; 800df62: 4b13 ldr r3, [pc, #76] @ (800dfb0 ) 800df64: 681b ldr r3, [r3, #0] 800df66: 695b ldr r3, [r3, #20] 800df68: 60bb str r3, [r7, #8] while (cur->Next != NULL ) 800df6a: e012 b.n 800df92 { if( TimerObject->Timestamp > next->Timestamp ) 800df6c: 687b ldr r3, [r7, #4] 800df6e: 681a ldr r2, [r3, #0] 800df70: 68bb ldr r3, [r7, #8] 800df72: 681b ldr r3, [r3, #0] 800df74: 429a cmp r2, r3 800df76: d905 bls.n 800df84 { cur = next; 800df78: 68bb ldr r3, [r7, #8] 800df7a: 60fb str r3, [r7, #12] next = next->Next; 800df7c: 68bb ldr r3, [r7, #8] 800df7e: 695b ldr r3, [r3, #20] 800df80: 60bb str r3, [r7, #8] 800df82: e006 b.n 800df92 } else { cur->Next = TimerObject; 800df84: 68fb ldr r3, [r7, #12] 800df86: 687a ldr r2, [r7, #4] 800df88: 615a str r2, [r3, #20] TimerObject->Next = next; 800df8a: 687b ldr r3, [r7, #4] 800df8c: 68ba ldr r2, [r7, #8] 800df8e: 615a str r2, [r3, #20] return; 800df90: e009 b.n 800dfa6 while (cur->Next != NULL ) 800df92: 68fb ldr r3, [r7, #12] 800df94: 695b ldr r3, [r3, #20] 800df96: 2b00 cmp r3, #0 800df98: d1e8 bne.n 800df6c } } cur->Next = TimerObject; 800df9a: 68fb ldr r3, [r7, #12] 800df9c: 687a ldr r2, [r7, #4] 800df9e: 615a str r2, [r3, #20] TimerObject->Next = NULL; 800dfa0: 687b ldr r3, [r7, #4] 800dfa2: 2200 movs r2, #0 800dfa4: 615a str r2, [r3, #20] } 800dfa6: 3714 adds r7, #20 800dfa8: 46bd mov sp, r7 800dfaa: bc80 pop {r7} 800dfac: 4770 bx lr 800dfae: bf00 nop 800dfb0: 20000c04 .word 0x20000c04 0800dfb4 : * * @remark The list is automatically sorted. The list head always contains the * next timer to expire. */ void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ) { 800dfb4: b580 push {r7, lr} 800dfb6: b084 sub sp, #16 800dfb8: af00 add r7, sp, #0 800dfba: 6078 str r0, [r7, #4] UTIL_TIMER_Object_t* cur = TimerListHead; 800dfbc: 4b0b ldr r3, [pc, #44] @ (800dfec ) 800dfbe: 681b ldr r3, [r3, #0] 800dfc0: 60fb str r3, [r7, #12] if( cur != NULL ) 800dfc2: 68fb ldr r3, [r7, #12] 800dfc4: 2b00 cmp r3, #0 800dfc6: d002 beq.n 800dfce { cur->IsPending = 0; 800dfc8: 68fb ldr r3, [r7, #12] 800dfca: 2200 movs r2, #0 800dfcc: 721a strb r2, [r3, #8] } TimerObject->Next = cur; 800dfce: 687b ldr r3, [r7, #4] 800dfd0: 68fa ldr r2, [r7, #12] 800dfd2: 615a str r2, [r3, #20] TimerListHead = TimerObject; 800dfd4: 4a05 ldr r2, [pc, #20] @ (800dfec ) 800dfd6: 687b ldr r3, [r7, #4] 800dfd8: 6013 str r3, [r2, #0] TimerSetTimeout( TimerListHead ); 800dfda: 4b04 ldr r3, [pc, #16] @ (800dfec ) 800dfdc: 681b ldr r3, [r3, #0] 800dfde: 4618 mov r0, r3 800dfe0: f7ff ff8e bl 800df00 } 800dfe4: bf00 nop 800dfe6: 3710 adds r7, #16 800dfe8: 46bd mov sp, r7 800dfea: bd80 pop {r7, pc} 800dfec: 20000c04 .word 0x20000c04 0800dff0 : /** @addtogroup ADV_TRACE_exported_function * @{ */ UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void) { 800dff0: b580 push {r7, lr} 800dff2: af00 add r7, sp, #0 /* initialize the Ptr for Read/Write */ (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Ctx, 0x0, sizeof(ADV_TRACE_Context)); 800dff4: 2218 movs r2, #24 800dff6: 2100 movs r1, #0 800dff8: 4807 ldr r0, [pc, #28] @ (800e018 ) 800dffa: f7ff f936 bl 800d26a (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Buffer, 0x0, sizeof(ADV_TRACE_Buffer)); 800dffe: f44f 7200 mov.w r2, #512 @ 0x200 800e002: 2100 movs r1, #0 800e004: 4805 ldr r0, [pc, #20] @ (800e01c ) 800e006: f7ff f930 bl 800d26a #endif /* Allocate Lock resource */ UTIL_ADV_TRACE_INIT_CRITICAL_SECTION(); /* Initialize the Low Level interface */ return UTIL_TraceDriver.Init(TRACE_TxCpltCallback); 800e00a: 4b05 ldr r3, [pc, #20] @ (800e020 ) 800e00c: 681b ldr r3, [r3, #0] 800e00e: 4805 ldr r0, [pc, #20] @ (800e024 ) 800e010: 4798 blx r3 800e012: 4603 mov r3, r0 } 800e014: 4618 mov r0, r3 800e016: bd80 pop {r7, pc} 800e018: 20000c08 .word 0x20000c08 800e01c: 20000c20 .word 0x20000c20 800e020: 0800fb44 .word 0x0800fb44 800e024: 0800e26d .word 0x0800e26d 0800e028 : return UTIL_TraceDriver.StartRx(UserCallback); } #if defined(UTIL_ADV_TRACE_CONDITIONNAL) UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const char *strFormat, ...) { 800e028: b408 push {r3} 800e02a: b580 push {r7, lr} 800e02c: b08d sub sp, #52 @ 0x34 800e02e: af00 add r7, sp, #0 800e030: 60f8 str r0, [r7, #12] 800e032: 60b9 str r1, [r7, #8] 800e034: 607a str r2, [r7, #4] va_list vaArgs; #if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) uint8_t buf[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; uint16_t timestamp_size = 0u; 800e036: 2300 movs r3, #0 800e038: 82fb strh r3, [r7, #22] uint16_t writepos; uint16_t idx; #else uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE+UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; #endif uint16_t buff_size = 0u; 800e03a: 2300 movs r3, #0 800e03c: 85bb strh r3, [r7, #44] @ 0x2c /* check verbose level */ if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) 800e03e: 4b37 ldr r3, [pc, #220] @ (800e11c ) 800e040: 7a1b ldrb r3, [r3, #8] 800e042: 461a mov r2, r3 800e044: 68fb ldr r3, [r7, #12] 800e046: 4293 cmp r3, r2 800e048: d902 bls.n 800e050 { return UTIL_ADV_TRACE_GIVEUP; 800e04a: f06f 0304 mvn.w r3, #4 800e04e: e05e b.n 800e10e } if((Region & ADV_TRACE_Ctx.RegionMask) != Region) 800e050: 4b32 ldr r3, [pc, #200] @ (800e11c ) 800e052: 68da ldr r2, [r3, #12] 800e054: 68bb ldr r3, [r7, #8] 800e056: 4013 ands r3, r2 800e058: 68ba ldr r2, [r7, #8] 800e05a: 429a cmp r2, r3 800e05c: d002 beq.n 800e064 { return UTIL_ADV_TRACE_REGIONMASKED; 800e05e: f06f 0305 mvn.w r3, #5 800e062: e054 b.n 800e10e } #if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) 800e064: 4b2d ldr r3, [pc, #180] @ (800e11c ) 800e066: 685b ldr r3, [r3, #4] 800e068: 2b00 cmp r3, #0 800e06a: d00a beq.n 800e082 800e06c: 687b ldr r3, [r7, #4] 800e06e: 2b00 cmp r3, #0 800e070: d007 beq.n 800e082 { ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size); 800e072: 4b2a ldr r3, [pc, #168] @ (800e11c ) 800e074: 685b ldr r3, [r3, #4] 800e076: f107 0116 add.w r1, r7, #22 800e07a: f107 0218 add.w r2, r7, #24 800e07e: 4610 mov r0, r2 800e080: 4798 blx r3 } va_start( vaArgs, strFormat); 800e082: f107 0340 add.w r3, r7, #64 @ 0x40 800e086: 62bb str r3, [r7, #40] @ 0x28 buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); 800e088: 6abb ldr r3, [r7, #40] @ 0x28 800e08a: 6bfa ldr r2, [r7, #60] @ 0x3c 800e08c: f44f 7180 mov.w r1, #256 @ 0x100 800e090: 4823 ldr r0, [pc, #140] @ (800e120 ) 800e092: f7ff fa8b bl 800d5ac 800e096: 4603 mov r3, r0 800e098: 85bb strh r3, [r7, #44] @ 0x2c TRACE_Lock(); 800e09a: f000 f9f1 bl 800e480 /* if allocation is ok, write data into the buffer */ if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1) 800e09e: 8afa ldrh r2, [r7, #22] 800e0a0: 8dbb ldrh r3, [r7, #44] @ 0x2c 800e0a2: 4413 add r3, r2 800e0a4: b29b uxth r3, r3 800e0a6: f107 0214 add.w r2, r7, #20 800e0aa: 4611 mov r1, r2 800e0ac: 4618 mov r0, r3 800e0ae: f000 f969 bl 800e384 800e0b2: 4603 mov r3, r0 800e0b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e0b8: d025 beq.n 800e106 } UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); #endif /* copy the timestamp */ for (idx = 0u; idx < timestamp_size; idx++) 800e0ba: 2300 movs r3, #0 800e0bc: 85fb strh r3, [r7, #46] @ 0x2e 800e0be: e00e b.n 800e0de { ADV_TRACE_Buffer[writepos] = buf[idx]; 800e0c0: 8dfb ldrh r3, [r7, #46] @ 0x2e 800e0c2: 8aba ldrh r2, [r7, #20] 800e0c4: 3330 adds r3, #48 @ 0x30 800e0c6: 443b add r3, r7 800e0c8: f813 1c18 ldrb.w r1, [r3, #-24] 800e0cc: 4b15 ldr r3, [pc, #84] @ (800e124 ) 800e0ce: 5499 strb r1, [r3, r2] writepos = writepos + 1u; 800e0d0: 8abb ldrh r3, [r7, #20] 800e0d2: 3301 adds r3, #1 800e0d4: b29b uxth r3, r3 800e0d6: 82bb strh r3, [r7, #20] for (idx = 0u; idx < timestamp_size; idx++) 800e0d8: 8dfb ldrh r3, [r7, #46] @ 0x2e 800e0da: 3301 adds r3, #1 800e0dc: 85fb strh r3, [r7, #46] @ 0x2e 800e0de: 8afb ldrh r3, [r7, #22] 800e0e0: 8dfa ldrh r2, [r7, #46] @ 0x2e 800e0e2: 429a cmp r2, r3 800e0e4: d3ec bcc.n 800e0c0 } /* copy the data */ (void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); 800e0e6: 8abb ldrh r3, [r7, #20] 800e0e8: 461a mov r2, r3 800e0ea: 4b0e ldr r3, [pc, #56] @ (800e124 ) 800e0ec: 18d0 adds r0, r2, r3 800e0ee: 6abb ldr r3, [r7, #40] @ 0x28 800e0f0: 6bfa ldr r2, [r7, #60] @ 0x3c 800e0f2: f44f 7180 mov.w r1, #256 @ 0x100 800e0f6: f7ff fa59 bl 800d5ac va_end(vaArgs); TRACE_UnLock(); 800e0fa: f000 f9df bl 800e4bc return TRACE_Send(); 800e0fe: f000 f831 bl 800e164 800e102: 4603 mov r3, r0 800e104: e003 b.n 800e10e } va_end(vaArgs); TRACE_UnLock(); 800e106: f000 f9d9 bl 800e4bc ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; } UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); #endif return UTIL_ADV_TRACE_MEM_FULL; 800e10a: f06f 0302 mvn.w r3, #2 buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); va_end(vaArgs); return UTIL_ADV_TRACE_Send(buf, buff_size); #endif } 800e10e: 4618 mov r0, r3 800e110: 3734 adds r7, #52 @ 0x34 800e112: 46bd mov sp, r7 800e114: e8bd 4080 ldmia.w sp!, {r7, lr} 800e118: b001 add sp, #4 800e11a: 4770 bx lr 800e11c: 20000c08 .word 0x20000c08 800e120: 20000e20 .word 0x20000e20 800e124: 20000c20 .word 0x20000c20 0800e128 : } #endif #if defined(UTIL_ADV_TRACE_CONDITIONNAL) void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb) { 800e128: b480 push {r7} 800e12a: b083 sub sp, #12 800e12c: af00 add r7, sp, #0 800e12e: 6078 str r0, [r7, #4] ADV_TRACE_Ctx.timestamp_func = *cb; 800e130: 4a03 ldr r2, [pc, #12] @ (800e140 ) 800e132: 687b ldr r3, [r7, #4] 800e134: 6053 str r3, [r2, #4] } 800e136: bf00 nop 800e138: 370c adds r7, #12 800e13a: 46bd mov sp, r7 800e13c: bc80 pop {r7} 800e13e: 4770 bx lr 800e140: 20000c08 .word 0x20000c08 0800e144 : void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level) { 800e144: b480 push {r7} 800e146: b083 sub sp, #12 800e148: af00 add r7, sp, #0 800e14a: 4603 mov r3, r0 800e14c: 71fb strb r3, [r7, #7] ADV_TRACE_Ctx.CurrentVerboseLevel = Level; 800e14e: 4a04 ldr r2, [pc, #16] @ (800e160 ) 800e150: 79fb ldrb r3, [r7, #7] 800e152: 7213 strb r3, [r2, #8] } 800e154: bf00 nop 800e156: 370c adds r7, #12 800e158: 46bd mov sp, r7 800e15a: bc80 pop {r7} 800e15c: 4770 bx lr 800e15e: bf00 nop 800e160: 20000c08 .word 0x20000c08 0800e164 : /** * @brief send the data of the trace to low layer * @retval Status based on @ref UTIL_ADV_TRACE_Status_t */ static UTIL_ADV_TRACE_Status_t TRACE_Send(void) { 800e164: b580 push {r7, lr} 800e166: b088 sub sp, #32 800e168: af00 add r7, sp, #0 UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; 800e16a: 2300 movs r3, #0 800e16c: 77fb strb r3, [r7, #31] uint8_t *ptr = NULL; 800e16e: 2300 movs r3, #0 800e170: 61bb str r3, [r7, #24] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800e172: f3ef 8310 mrs r3, PRIMASK 800e176: 613b str r3, [r7, #16] return(result); 800e178: 693b ldr r3, [r7, #16] UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); 800e17a: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800e17c: b672 cpsid i } 800e17e: bf00 nop if(TRACE_IsLocked() == 0u) 800e180: f000 f9ba bl 800e4f8 800e184: 4603 mov r3, r0 800e186: 2b00 cmp r3, #0 800e188: d15d bne.n 800e246 { TRACE_Lock(); 800e18a: f000 f979 bl 800e480 if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) 800e18e: 4b34 ldr r3, [pc, #208] @ (800e260 ) 800e190: 8a1a ldrh r2, [r3, #16] 800e192: 4b33 ldr r3, [pc, #204] @ (800e260 ) 800e194: 8a5b ldrh r3, [r3, #18] 800e196: 429a cmp r2, r3 800e198: d04d beq.n 800e236 { #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) 800e19a: 4b31 ldr r3, [pc, #196] @ (800e260 ) 800e19c: 789b ldrb r3, [r3, #2] 800e19e: 2b01 cmp r3, #1 800e1a0: d117 bne.n 800e1d2 { ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr); 800e1a2: 4b2f ldr r3, [pc, #188] @ (800e260 ) 800e1a4: 881a ldrh r2, [r3, #0] 800e1a6: 4b2e ldr r3, [pc, #184] @ (800e260 ) 800e1a8: 8a1b ldrh r3, [r3, #16] 800e1aa: 1ad3 subs r3, r2, r3 800e1ac: b29a uxth r2, r3 800e1ae: 4b2c ldr r3, [pc, #176] @ (800e260 ) 800e1b0: 829a strh r2, [r3, #20] ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; 800e1b2: 4b2b ldr r3, [pc, #172] @ (800e260 ) 800e1b4: 2202 movs r2, #2 800e1b6: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.unchunk_enabled = 0; 800e1b8: 4b29 ldr r3, [pc, #164] @ (800e260 ) 800e1ba: 2200 movs r2, #0 800e1bc: 801a strh r2, [r3, #0] UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); if(0u == ADV_TRACE_Ctx.TraceSentSize) 800e1be: 4b28 ldr r3, [pc, #160] @ (800e260 ) 800e1c0: 8a9b ldrh r3, [r3, #20] 800e1c2: 2b00 cmp r3, #0 800e1c4: d105 bne.n 800e1d2 { ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; 800e1c6: 4b26 ldr r3, [pc, #152] @ (800e260 ) 800e1c8: 2200 movs r2, #0 800e1ca: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.TraceRdPtr = 0; 800e1cc: 4b24 ldr r3, [pc, #144] @ (800e260 ) 800e1ce: 2200 movs r2, #0 800e1d0: 821a strh r2, [r3, #16] } } if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) 800e1d2: 4b23 ldr r3, [pc, #140] @ (800e260 ) 800e1d4: 789b ldrb r3, [r3, #2] 800e1d6: 2b00 cmp r3, #0 800e1d8: d115 bne.n 800e206 { #endif if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) 800e1da: 4b21 ldr r3, [pc, #132] @ (800e260 ) 800e1dc: 8a5a ldrh r2, [r3, #18] 800e1de: 4b20 ldr r3, [pc, #128] @ (800e260 ) 800e1e0: 8a1b ldrh r3, [r3, #16] 800e1e2: 429a cmp r2, r3 800e1e4: d908 bls.n 800e1f8 { ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; 800e1e6: 4b1e ldr r3, [pc, #120] @ (800e260 ) 800e1e8: 8a5a ldrh r2, [r3, #18] 800e1ea: 4b1d ldr r3, [pc, #116] @ (800e260 ) 800e1ec: 8a1b ldrh r3, [r3, #16] 800e1ee: 1ad3 subs r3, r2, r3 800e1f0: b29a uxth r2, r3 800e1f2: 4b1b ldr r3, [pc, #108] @ (800e260 ) 800e1f4: 829a strh r2, [r3, #20] 800e1f6: e006 b.n 800e206 } else /* TraceRdPtr > TraceWrPtr */ { ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; 800e1f8: 4b19 ldr r3, [pc, #100] @ (800e260 ) 800e1fa: 8a1b ldrh r3, [r3, #16] 800e1fc: f5c3 7300 rsb r3, r3, #512 @ 0x200 800e200: b29a uxth r2, r3 800e202: 4b17 ldr r3, [pc, #92] @ (800e260 ) 800e204: 829a strh r2, [r3, #20] } #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE } #endif ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; 800e206: 4b16 ldr r3, [pc, #88] @ (800e260 ) 800e208: 8a1b ldrh r3, [r3, #16] 800e20a: 461a mov r2, r3 800e20c: 4b15 ldr r3, [pc, #84] @ (800e264 ) 800e20e: 4413 add r3, r2 800e210: 61bb str r3, [r7, #24] 800e212: 697b ldr r3, [r7, #20] 800e214: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e216: 68fb ldr r3, [r7, #12] 800e218: f383 8810 msr PRIMASK, r3 } 800e21c: bf00 nop UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); UTIL_ADV_TRACE_PreSendHook(); 800e21e: f7f2 fce3 bl 8000be8 UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); 800e222: 4b11 ldr r3, [pc, #68] @ (800e268 ) 800e224: 68db ldr r3, [r3, #12] 800e226: 4a0e ldr r2, [pc, #56] @ (800e260 ) 800e228: 8a92 ldrh r2, [r2, #20] 800e22a: 4611 mov r1, r2 800e22c: 69b8 ldr r0, [r7, #24] 800e22e: 4798 blx r3 800e230: 4603 mov r3, r0 800e232: 77fb strb r3, [r7, #31] 800e234: e00d b.n 800e252 } else { TRACE_UnLock(); 800e236: f000 f941 bl 800e4bc 800e23a: 697b ldr r3, [r7, #20] 800e23c: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e23e: 68bb ldr r3, [r7, #8] 800e240: f383 8810 msr PRIMASK, r3 } 800e244: e005 b.n 800e252 800e246: 697b ldr r3, [r7, #20] 800e248: 607b str r3, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e24a: 687b ldr r3, [r7, #4] 800e24c: f383 8810 msr PRIMASK, r3 } 800e250: bf00 nop else { UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); } return ret; 800e252: f997 301f ldrsb.w r3, [r7, #31] } 800e256: 4618 mov r0, r3 800e258: 3720 adds r7, #32 800e25a: 46bd mov sp, r7 800e25c: bd80 pop {r7, pc} 800e25e: bf00 nop 800e260: 20000c08 .word 0x20000c08 800e264: 20000c20 .word 0x20000c20 800e268: 0800fb44 .word 0x0800fb44 0800e26c : * @brief Tx callback called by the low layer level to inform a transfer complete * @param Ptr pointer not used only for HAL compatibility * @retval none */ static void TRACE_TxCpltCallback(void *Ptr) { 800e26c: b580 push {r7, lr} 800e26e: b088 sub sp, #32 800e270: af00 add r7, sp, #0 800e272: 6078 str r0, [r7, #4] uint8_t *ptr = NULL; 800e274: 2300 movs r3, #0 800e276: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800e278: f3ef 8310 mrs r3, PRIMASK 800e27c: 617b str r3, [r7, #20] return(result); 800e27e: 697b ldr r3, [r7, #20] UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); 800e280: 61bb str r3, [r7, #24] __ASM volatile ("cpsid i" : : : "memory"); 800e282: b672 cpsid i } 800e284: bf00 nop ADV_TRACE_Ctx.TraceSentSize = 0u; } #endif #if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status) 800e286: 4b3c ldr r3, [pc, #240] @ (800e378 ) 800e288: 789b ldrb r3, [r3, #2] 800e28a: 2b02 cmp r3, #2 800e28c: d106 bne.n 800e29c { ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; 800e28e: 4b3a ldr r3, [pc, #232] @ (800e378 ) 800e290: 2200 movs r2, #0 800e292: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.TraceRdPtr = 0; 800e294: 4b38 ldr r3, [pc, #224] @ (800e378 ) 800e296: 2200 movs r2, #0 800e298: 821a strh r2, [r3, #16] 800e29a: e00a b.n 800e2b2 UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n"); } else { ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; 800e29c: 4b36 ldr r3, [pc, #216] @ (800e378 ) 800e29e: 8a1a ldrh r2, [r3, #16] 800e2a0: 4b35 ldr r3, [pc, #212] @ (800e378 ) 800e2a2: 8a9b ldrh r3, [r3, #20] 800e2a4: 4413 add r3, r2 800e2a6: b29b uxth r3, r3 800e2a8: f3c3 0308 ubfx r3, r3, #0, #9 800e2ac: b29a uxth r2, r3 800e2ae: 4b32 ldr r3, [pc, #200] @ (800e378 ) 800e2b0: 821a strh r2, [r3, #16] UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); return; } #endif if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock)) 800e2b2: 4b31 ldr r3, [pc, #196] @ (800e378 ) 800e2b4: 8a1a ldrh r2, [r3, #16] 800e2b6: 4b30 ldr r3, [pc, #192] @ (800e378 ) 800e2b8: 8a5b ldrh r3, [r3, #18] 800e2ba: 429a cmp r2, r3 800e2bc: d04d beq.n 800e35a 800e2be: 4b2e ldr r3, [pc, #184] @ (800e378 ) 800e2c0: 8adb ldrh r3, [r3, #22] 800e2c2: 2b01 cmp r3, #1 800e2c4: d149 bne.n 800e35a { #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) 800e2c6: 4b2c ldr r3, [pc, #176] @ (800e378 ) 800e2c8: 789b ldrb r3, [r3, #2] 800e2ca: 2b01 cmp r3, #1 800e2cc: d117 bne.n 800e2fe { ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr; 800e2ce: 4b2a ldr r3, [pc, #168] @ (800e378 ) 800e2d0: 881a ldrh r2, [r3, #0] 800e2d2: 4b29 ldr r3, [pc, #164] @ (800e378 ) 800e2d4: 8a1b ldrh r3, [r3, #16] 800e2d6: 1ad3 subs r3, r2, r3 800e2d8: b29a uxth r2, r3 800e2da: 4b27 ldr r3, [pc, #156] @ (800e378 ) 800e2dc: 829a strh r2, [r3, #20] ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; 800e2de: 4b26 ldr r3, [pc, #152] @ (800e378 ) 800e2e0: 2202 movs r2, #2 800e2e2: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.unchunk_enabled = 0; 800e2e4: 4b24 ldr r3, [pc, #144] @ (800e378 ) 800e2e6: 2200 movs r2, #0 800e2e8: 801a strh r2, [r3, #0] UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); if(0u == ADV_TRACE_Ctx.TraceSentSize) 800e2ea: 4b23 ldr r3, [pc, #140] @ (800e378 ) 800e2ec: 8a9b ldrh r3, [r3, #20] 800e2ee: 2b00 cmp r3, #0 800e2f0: d105 bne.n 800e2fe { /* this case occurs when an ongoing write aligned the Rd position with chunk position */ /* in that case the unchunk is forgot */ ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; 800e2f2: 4b21 ldr r3, [pc, #132] @ (800e378 ) 800e2f4: 2200 movs r2, #0 800e2f6: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.TraceRdPtr = 0; 800e2f8: 4b1f ldr r3, [pc, #124] @ (800e378 ) 800e2fa: 2200 movs r2, #0 800e2fc: 821a strh r2, [r3, #16] } } if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) 800e2fe: 4b1e ldr r3, [pc, #120] @ (800e378 ) 800e300: 789b ldrb r3, [r3, #2] 800e302: 2b00 cmp r3, #0 800e304: d115 bne.n 800e332 { #endif if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) 800e306: 4b1c ldr r3, [pc, #112] @ (800e378 ) 800e308: 8a5a ldrh r2, [r3, #18] 800e30a: 4b1b ldr r3, [pc, #108] @ (800e378 ) 800e30c: 8a1b ldrh r3, [r3, #16] 800e30e: 429a cmp r2, r3 800e310: d908 bls.n 800e324 { ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; 800e312: 4b19 ldr r3, [pc, #100] @ (800e378 ) 800e314: 8a5a ldrh r2, [r3, #18] 800e316: 4b18 ldr r3, [pc, #96] @ (800e378 ) 800e318: 8a1b ldrh r3, [r3, #16] 800e31a: 1ad3 subs r3, r2, r3 800e31c: b29a uxth r2, r3 800e31e: 4b16 ldr r3, [pc, #88] @ (800e378 ) 800e320: 829a strh r2, [r3, #20] 800e322: e006 b.n 800e332 } else /* TraceRdPtr > TraceWrPtr */ { ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; 800e324: 4b14 ldr r3, [pc, #80] @ (800e378 ) 800e326: 8a1b ldrh r3, [r3, #16] 800e328: f5c3 7300 rsb r3, r3, #512 @ 0x200 800e32c: b29a uxth r2, r3 800e32e: 4b12 ldr r3, [pc, #72] @ (800e378 ) 800e330: 829a strh r2, [r3, #20] } #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE } #endif ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; 800e332: 4b11 ldr r3, [pc, #68] @ (800e378 ) 800e334: 8a1b ldrh r3, [r3, #16] 800e336: 461a mov r2, r3 800e338: 4b10 ldr r3, [pc, #64] @ (800e37c ) 800e33a: 4413 add r3, r2 800e33c: 61fb str r3, [r7, #28] 800e33e: 69bb ldr r3, [r7, #24] 800e340: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e342: 693b ldr r3, [r7, #16] 800e344: f383 8810 msr PRIMASK, r3 } 800e348: bf00 nop UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); 800e34a: 4b0d ldr r3, [pc, #52] @ (800e380 ) 800e34c: 68db ldr r3, [r3, #12] 800e34e: 4a0a ldr r2, [pc, #40] @ (800e378 ) 800e350: 8a92 ldrh r2, [r2, #20] 800e352: 4611 mov r1, r2 800e354: 69f8 ldr r0, [r7, #28] 800e356: 4798 blx r3 800e358: e00a b.n 800e370 800e35a: 69bb ldr r3, [r7, #24] 800e35c: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e35e: 68fb ldr r3, [r7, #12] 800e360: f383 8810 msr PRIMASK, r3 } 800e364: bf00 nop } else { UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); UTIL_ADV_TRACE_PostSendHook(); 800e366: f7f2 fc47 bl 8000bf8 TRACE_UnLock(); 800e36a: f000 f8a7 bl 800e4bc } } 800e36e: bf00 nop 800e370: bf00 nop 800e372: 3720 adds r7, #32 800e374: 46bd mov sp, r7 800e376: bd80 pop {r7, pc} 800e378: 20000c08 .word 0x20000c08 800e37c: 20000c20 .word 0x20000c20 800e380: 0800fb44 .word 0x0800fb44 0800e384 : * @param Size to allocate within fifo * @param Pos position within the fifo * @retval write position inside the buffer is -1 no space available. */ static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos) { 800e384: b480 push {r7} 800e386: b087 sub sp, #28 800e388: af00 add r7, sp, #0 800e38a: 4603 mov r3, r0 800e38c: 6039 str r1, [r7, #0] 800e38e: 80fb strh r3, [r7, #6] uint16_t freesize; int16_t ret = -1; 800e390: f64f 73ff movw r3, #65535 @ 0xffff 800e394: 82bb strh r3, [r7, #20] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800e396: f3ef 8310 mrs r3, PRIMASK 800e39a: 60fb str r3, [r7, #12] return(result); 800e39c: 68fb ldr r3, [r7, #12] UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); 800e39e: 613b str r3, [r7, #16] __ASM volatile ("cpsid i" : : : "memory"); 800e3a0: b672 cpsid i } 800e3a2: bf00 nop if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr) 800e3a4: 4b35 ldr r3, [pc, #212] @ (800e47c ) 800e3a6: 8a5a ldrh r2, [r3, #18] 800e3a8: 4b34 ldr r3, [pc, #208] @ (800e47c ) 800e3aa: 8a1b ldrh r3, [r3, #16] 800e3ac: 429a cmp r2, r3 800e3ae: d11b bne.n 800e3e8 { #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); 800e3b0: 4b32 ldr r3, [pc, #200] @ (800e47c ) 800e3b2: 8a5b ldrh r3, [r3, #18] 800e3b4: f5c3 7300 rsb r3, r3, #512 @ 0x200 800e3b8: 82fb strh r3, [r7, #22] if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) 800e3ba: 88fa ldrh r2, [r7, #6] 800e3bc: 8afb ldrh r3, [r7, #22] 800e3be: 429a cmp r2, r3 800e3c0: d33a bcc.n 800e438 800e3c2: 4b2e ldr r3, [pc, #184] @ (800e47c ) 800e3c4: 8a1b ldrh r3, [r3, #16] 800e3c6: 88fa ldrh r2, [r7, #6] 800e3c8: 429a cmp r2, r3 800e3ca: d235 bcs.n 800e438 { ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; 800e3cc: 4b2b ldr r3, [pc, #172] @ (800e47c ) 800e3ce: 2201 movs r2, #1 800e3d0: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; 800e3d2: 4b2a ldr r3, [pc, #168] @ (800e47c ) 800e3d4: 8a5a ldrh r2, [r3, #18] 800e3d6: 4b29 ldr r3, [pc, #164] @ (800e47c ) 800e3d8: 801a strh r2, [r3, #0] freesize = ADV_TRACE_Ctx.TraceRdPtr; 800e3da: 4b28 ldr r3, [pc, #160] @ (800e47c ) 800e3dc: 8a1b ldrh r3, [r3, #16] 800e3de: 82fb strh r3, [r7, #22] ADV_TRACE_Ctx.TraceWrPtr = 0; 800e3e0: 4b26 ldr r3, [pc, #152] @ (800e47c ) 800e3e2: 2200 movs r2, #0 800e3e4: 825a strh r2, [r3, #18] 800e3e6: e027 b.n 800e438 #endif } else { #ifdef UTIL_ADV_TRACE_UNCHUNK_MODE if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) 800e3e8: 4b24 ldr r3, [pc, #144] @ (800e47c ) 800e3ea: 8a5a ldrh r2, [r3, #18] 800e3ec: 4b23 ldr r3, [pc, #140] @ (800e47c ) 800e3ee: 8a1b ldrh r3, [r3, #16] 800e3f0: 429a cmp r2, r3 800e3f2: d91b bls.n 800e42c { freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); 800e3f4: 4b21 ldr r3, [pc, #132] @ (800e47c ) 800e3f6: 8a5b ldrh r3, [r3, #18] 800e3f8: f5c3 7300 rsb r3, r3, #512 @ 0x200 800e3fc: 82fb strh r3, [r7, #22] if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) 800e3fe: 88fa ldrh r2, [r7, #6] 800e400: 8afb ldrh r3, [r7, #22] 800e402: 429a cmp r2, r3 800e404: d318 bcc.n 800e438 800e406: 4b1d ldr r3, [pc, #116] @ (800e47c ) 800e408: 8a1b ldrh r3, [r3, #16] 800e40a: 88fa ldrh r2, [r7, #6] 800e40c: 429a cmp r2, r3 800e40e: d213 bcs.n 800e438 { ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; 800e410: 4b1a ldr r3, [pc, #104] @ (800e47c ) 800e412: 2201 movs r2, #1 800e414: 709a strb r2, [r3, #2] ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; 800e416: 4b19 ldr r3, [pc, #100] @ (800e47c ) 800e418: 8a5a ldrh r2, [r3, #18] 800e41a: 4b18 ldr r3, [pc, #96] @ (800e47c ) 800e41c: 801a strh r2, [r3, #0] freesize = ADV_TRACE_Ctx.TraceRdPtr; 800e41e: 4b17 ldr r3, [pc, #92] @ (800e47c ) 800e420: 8a1b ldrh r3, [r3, #16] 800e422: 82fb strh r3, [r7, #22] ADV_TRACE_Ctx.TraceWrPtr = 0; 800e424: 4b15 ldr r3, [pc, #84] @ (800e47c ) 800e426: 2200 movs r2, #0 800e428: 825a strh r2, [r3, #18] 800e42a: e005 b.n 800e438 } } else { freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr); 800e42c: 4b13 ldr r3, [pc, #76] @ (800e47c ) 800e42e: 8a1a ldrh r2, [r3, #16] 800e430: 4b12 ldr r3, [pc, #72] @ (800e47c ) 800e432: 8a5b ldrh r3, [r3, #18] 800e434: 1ad3 subs r3, r2, r3 800e436: 82fb strh r3, [r7, #22] freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr; } #endif } if(freesize > Size) 800e438: 8afa ldrh r2, [r7, #22] 800e43a: 88fb ldrh r3, [r7, #6] 800e43c: 429a cmp r2, r3 800e43e: d90f bls.n 800e460 { *Pos = ADV_TRACE_Ctx.TraceWrPtr; 800e440: 4b0e ldr r3, [pc, #56] @ (800e47c ) 800e442: 8a5a ldrh r2, [r3, #18] 800e444: 683b ldr r3, [r7, #0] 800e446: 801a strh r2, [r3, #0] ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE; 800e448: 4b0c ldr r3, [pc, #48] @ (800e47c ) 800e44a: 8a5a ldrh r2, [r3, #18] 800e44c: 88fb ldrh r3, [r7, #6] 800e44e: 4413 add r3, r2 800e450: b29b uxth r3, r3 800e452: f3c3 0308 ubfx r3, r3, #0, #9 800e456: b29a uxth r2, r3 800e458: 4b08 ldr r3, [pc, #32] @ (800e47c ) 800e45a: 825a strh r2, [r3, #18] ret = 0; 800e45c: 2300 movs r3, #0 800e45e: 82bb strh r3, [r7, #20] 800e460: 693b ldr r3, [r7, #16] 800e462: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e464: 68bb ldr r3, [r7, #8] 800e466: f383 8810 msr PRIMASK, r3 } 800e46a: bf00 nop } } #endif UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); return ret; 800e46c: f9b7 3014 ldrsh.w r3, [r7, #20] } 800e470: 4618 mov r0, r3 800e472: 371c adds r7, #28 800e474: 46bd mov sp, r7 800e476: bc80 pop {r7} 800e478: 4770 bx lr 800e47a: bf00 nop 800e47c: 20000c08 .word 0x20000c08 0800e480 : /** * @brief Lock the trace buffer. * @retval None. */ static void TRACE_Lock(void) { 800e480: b480 push {r7} 800e482: b085 sub sp, #20 800e484: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800e486: f3ef 8310 mrs r3, PRIMASK 800e48a: 607b str r3, [r7, #4] return(result); 800e48c: 687b ldr r3, [r7, #4] UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); 800e48e: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 800e490: b672 cpsid i } 800e492: bf00 nop ADV_TRACE_Ctx.TraceLock++; 800e494: 4b08 ldr r3, [pc, #32] @ (800e4b8 ) 800e496: 8adb ldrh r3, [r3, #22] 800e498: 3301 adds r3, #1 800e49a: b29a uxth r2, r3 800e49c: 4b06 ldr r3, [pc, #24] @ (800e4b8 ) 800e49e: 82da strh r2, [r3, #22] 800e4a0: 68fb ldr r3, [r7, #12] 800e4a2: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e4a4: 68bb ldr r3, [r7, #8] 800e4a6: f383 8810 msr PRIMASK, r3 } 800e4aa: bf00 nop UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); } 800e4ac: bf00 nop 800e4ae: 3714 adds r7, #20 800e4b0: 46bd mov sp, r7 800e4b2: bc80 pop {r7} 800e4b4: 4770 bx lr 800e4b6: bf00 nop 800e4b8: 20000c08 .word 0x20000c08 0800e4bc : /** * @brief UnLock the trace buffer. * @retval None. */ static void TRACE_UnLock(void) { 800e4bc: b480 push {r7} 800e4be: b085 sub sp, #20 800e4c0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800e4c2: f3ef 8310 mrs r3, PRIMASK 800e4c6: 607b str r3, [r7, #4] return(result); 800e4c8: 687b ldr r3, [r7, #4] UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); 800e4ca: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 800e4cc: b672 cpsid i } 800e4ce: bf00 nop ADV_TRACE_Ctx.TraceLock--; 800e4d0: 4b08 ldr r3, [pc, #32] @ (800e4f4 ) 800e4d2: 8adb ldrh r3, [r3, #22] 800e4d4: 3b01 subs r3, #1 800e4d6: b29a uxth r2, r3 800e4d8: 4b06 ldr r3, [pc, #24] @ (800e4f4 ) 800e4da: 82da strh r2, [r3, #22] 800e4dc: 68fb ldr r3, [r7, #12] 800e4de: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800e4e0: 68bb ldr r3, [r7, #8] 800e4e2: f383 8810 msr PRIMASK, r3 } 800e4e6: bf00 nop UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); } 800e4e8: bf00 nop 800e4ea: 3714 adds r7, #20 800e4ec: 46bd mov sp, r7 800e4ee: bc80 pop {r7} 800e4f0: 4770 bx lr 800e4f2: bf00 nop 800e4f4: 20000c08 .word 0x20000c08 0800e4f8 : /** * @brief UnLock the trace buffer. * @retval None. */ static uint32_t TRACE_IsLocked(void) { 800e4f8: b480 push {r7} 800e4fa: af00 add r7, sp, #0 return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u); 800e4fc: 4b05 ldr r3, [pc, #20] @ (800e514 ) 800e4fe: 8adb ldrh r3, [r3, #22] 800e500: 2b00 cmp r3, #0 800e502: bf14 ite ne 800e504: 2301 movne r3, #1 800e506: 2300 moveq r3, #0 800e508: b2db uxtb r3, r3 } 800e50a: 4618 mov r0, r3 800e50c: 46bd mov sp, r7 800e50e: bc80 pop {r7} 800e510: 4770 bx lr 800e512: bf00 nop 800e514: 20000c08 .word 0x20000c08 0800e518 <_strtol_l.isra.0>: 800e518: 2b24 cmp r3, #36 @ 0x24 800e51a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800e51e: 4686 mov lr, r0 800e520: 4690 mov r8, r2 800e522: d801 bhi.n 800e528 <_strtol_l.isra.0+0x10> 800e524: 2b01 cmp r3, #1 800e526: d106 bne.n 800e536 <_strtol_l.isra.0+0x1e> 800e528: f000 f948 bl 800e7bc <__errno> 800e52c: 2316 movs r3, #22 800e52e: 6003 str r3, [r0, #0] 800e530: 2000 movs r0, #0 800e532: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800e536: 4834 ldr r0, [pc, #208] @ (800e608 <_strtol_l.isra.0+0xf0>) 800e538: 460d mov r5, r1 800e53a: 462a mov r2, r5 800e53c: f815 4b01 ldrb.w r4, [r5], #1 800e540: 5d06 ldrb r6, [r0, r4] 800e542: f016 0608 ands.w r6, r6, #8 800e546: d1f8 bne.n 800e53a <_strtol_l.isra.0+0x22> 800e548: 2c2d cmp r4, #45 @ 0x2d 800e54a: d110 bne.n 800e56e <_strtol_l.isra.0+0x56> 800e54c: 782c ldrb r4, [r5, #0] 800e54e: 2601 movs r6, #1 800e550: 1c95 adds r5, r2, #2 800e552: f033 0210 bics.w r2, r3, #16 800e556: d115 bne.n 800e584 <_strtol_l.isra.0+0x6c> 800e558: 2c30 cmp r4, #48 @ 0x30 800e55a: d10d bne.n 800e578 <_strtol_l.isra.0+0x60> 800e55c: 782a ldrb r2, [r5, #0] 800e55e: f002 02df and.w r2, r2, #223 @ 0xdf 800e562: 2a58 cmp r2, #88 @ 0x58 800e564: d108 bne.n 800e578 <_strtol_l.isra.0+0x60> 800e566: 786c ldrb r4, [r5, #1] 800e568: 3502 adds r5, #2 800e56a: 2310 movs r3, #16 800e56c: e00a b.n 800e584 <_strtol_l.isra.0+0x6c> 800e56e: 2c2b cmp r4, #43 @ 0x2b 800e570: bf04 itt eq 800e572: 782c ldrbeq r4, [r5, #0] 800e574: 1c95 addeq r5, r2, #2 800e576: e7ec b.n 800e552 <_strtol_l.isra.0+0x3a> 800e578: 2b00 cmp r3, #0 800e57a: d1f6 bne.n 800e56a <_strtol_l.isra.0+0x52> 800e57c: 2c30 cmp r4, #48 @ 0x30 800e57e: bf14 ite ne 800e580: 230a movne r3, #10 800e582: 2308 moveq r3, #8 800e584: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 800e588: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff 800e58c: 2200 movs r2, #0 800e58e: fbbc f9f3 udiv r9, ip, r3 800e592: 4610 mov r0, r2 800e594: fb03 ca19 mls sl, r3, r9, ip 800e598: f1a4 0730 sub.w r7, r4, #48 @ 0x30 800e59c: 2f09 cmp r7, #9 800e59e: d80f bhi.n 800e5c0 <_strtol_l.isra.0+0xa8> 800e5a0: 463c mov r4, r7 800e5a2: 42a3 cmp r3, r4 800e5a4: dd1b ble.n 800e5de <_strtol_l.isra.0+0xc6> 800e5a6: 1c57 adds r7, r2, #1 800e5a8: d007 beq.n 800e5ba <_strtol_l.isra.0+0xa2> 800e5aa: 4581 cmp r9, r0 800e5ac: d314 bcc.n 800e5d8 <_strtol_l.isra.0+0xc0> 800e5ae: d101 bne.n 800e5b4 <_strtol_l.isra.0+0x9c> 800e5b0: 45a2 cmp sl, r4 800e5b2: db11 blt.n 800e5d8 <_strtol_l.isra.0+0xc0> 800e5b4: fb00 4003 mla r0, r0, r3, r4 800e5b8: 2201 movs r2, #1 800e5ba: f815 4b01 ldrb.w r4, [r5], #1 800e5be: e7eb b.n 800e598 <_strtol_l.isra.0+0x80> 800e5c0: f1a4 0741 sub.w r7, r4, #65 @ 0x41 800e5c4: 2f19 cmp r7, #25 800e5c6: d801 bhi.n 800e5cc <_strtol_l.isra.0+0xb4> 800e5c8: 3c37 subs r4, #55 @ 0x37 800e5ca: e7ea b.n 800e5a2 <_strtol_l.isra.0+0x8a> 800e5cc: f1a4 0761 sub.w r7, r4, #97 @ 0x61 800e5d0: 2f19 cmp r7, #25 800e5d2: d804 bhi.n 800e5de <_strtol_l.isra.0+0xc6> 800e5d4: 3c57 subs r4, #87 @ 0x57 800e5d6: e7e4 b.n 800e5a2 <_strtol_l.isra.0+0x8a> 800e5d8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800e5dc: e7ed b.n 800e5ba <_strtol_l.isra.0+0xa2> 800e5de: 1c53 adds r3, r2, #1 800e5e0: d108 bne.n 800e5f4 <_strtol_l.isra.0+0xdc> 800e5e2: 2322 movs r3, #34 @ 0x22 800e5e4: f8ce 3000 str.w r3, [lr] 800e5e8: 4660 mov r0, ip 800e5ea: f1b8 0f00 cmp.w r8, #0 800e5ee: d0a0 beq.n 800e532 <_strtol_l.isra.0+0x1a> 800e5f0: 1e69 subs r1, r5, #1 800e5f2: e006 b.n 800e602 <_strtol_l.isra.0+0xea> 800e5f4: b106 cbz r6, 800e5f8 <_strtol_l.isra.0+0xe0> 800e5f6: 4240 negs r0, r0 800e5f8: f1b8 0f00 cmp.w r8, #0 800e5fc: d099 beq.n 800e532 <_strtol_l.isra.0+0x1a> 800e5fe: 2a00 cmp r2, #0 800e600: d1f6 bne.n 800e5f0 <_strtol_l.isra.0+0xd8> 800e602: f8c8 1000 str.w r1, [r8] 800e606: e794 b.n 800e532 <_strtol_l.isra.0+0x1a> 800e608: 0800fccd .word 0x0800fccd 0800e60c : 800e60c: 4613 mov r3, r2 800e60e: 460a mov r2, r1 800e610: 4601 mov r1, r0 800e612: 4802 ldr r0, [pc, #8] @ (800e61c ) 800e614: 6800 ldr r0, [r0, #0] 800e616: f7ff bf7f b.w 800e518 <_strtol_l.isra.0> 800e61a: bf00 nop 800e61c: 2000003c .word 0x2000003c 0800e620 <_strtoul_l.isra.0>: 800e620: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800e624: 4e34 ldr r6, [pc, #208] @ (800e6f8 <_strtoul_l.isra.0+0xd8>) 800e626: 4686 mov lr, r0 800e628: 460d mov r5, r1 800e62a: 4628 mov r0, r5 800e62c: f815 4b01 ldrb.w r4, [r5], #1 800e630: 5d37 ldrb r7, [r6, r4] 800e632: f017 0708 ands.w r7, r7, #8 800e636: d1f8 bne.n 800e62a <_strtoul_l.isra.0+0xa> 800e638: 2c2d cmp r4, #45 @ 0x2d 800e63a: d110 bne.n 800e65e <_strtoul_l.isra.0+0x3e> 800e63c: 782c ldrb r4, [r5, #0] 800e63e: 2701 movs r7, #1 800e640: 1c85 adds r5, r0, #2 800e642: f033 0010 bics.w r0, r3, #16 800e646: d115 bne.n 800e674 <_strtoul_l.isra.0+0x54> 800e648: 2c30 cmp r4, #48 @ 0x30 800e64a: d10d bne.n 800e668 <_strtoul_l.isra.0+0x48> 800e64c: 7828 ldrb r0, [r5, #0] 800e64e: f000 00df and.w r0, r0, #223 @ 0xdf 800e652: 2858 cmp r0, #88 @ 0x58 800e654: d108 bne.n 800e668 <_strtoul_l.isra.0+0x48> 800e656: 786c ldrb r4, [r5, #1] 800e658: 3502 adds r5, #2 800e65a: 2310 movs r3, #16 800e65c: e00a b.n 800e674 <_strtoul_l.isra.0+0x54> 800e65e: 2c2b cmp r4, #43 @ 0x2b 800e660: bf04 itt eq 800e662: 782c ldrbeq r4, [r5, #0] 800e664: 1c85 addeq r5, r0, #2 800e666: e7ec b.n 800e642 <_strtoul_l.isra.0+0x22> 800e668: 2b00 cmp r3, #0 800e66a: d1f6 bne.n 800e65a <_strtoul_l.isra.0+0x3a> 800e66c: 2c30 cmp r4, #48 @ 0x30 800e66e: bf14 ite ne 800e670: 230a movne r3, #10 800e672: 2308 moveq r3, #8 800e674: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 800e678: 2600 movs r6, #0 800e67a: fbb8 f8f3 udiv r8, r8, r3 800e67e: fb03 f908 mul.w r9, r3, r8 800e682: ea6f 0909 mvn.w r9, r9 800e686: 4630 mov r0, r6 800e688: f1a4 0c30 sub.w ip, r4, #48 @ 0x30 800e68c: f1bc 0f09 cmp.w ip, #9 800e690: d810 bhi.n 800e6b4 <_strtoul_l.isra.0+0x94> 800e692: 4664 mov r4, ip 800e694: 42a3 cmp r3, r4 800e696: dd1e ble.n 800e6d6 <_strtoul_l.isra.0+0xb6> 800e698: f1b6 3fff cmp.w r6, #4294967295 @ 0xffffffff 800e69c: d007 beq.n 800e6ae <_strtoul_l.isra.0+0x8e> 800e69e: 4580 cmp r8, r0 800e6a0: d316 bcc.n 800e6d0 <_strtoul_l.isra.0+0xb0> 800e6a2: d101 bne.n 800e6a8 <_strtoul_l.isra.0+0x88> 800e6a4: 45a1 cmp r9, r4 800e6a6: db13 blt.n 800e6d0 <_strtoul_l.isra.0+0xb0> 800e6a8: fb00 4003 mla r0, r0, r3, r4 800e6ac: 2601 movs r6, #1 800e6ae: f815 4b01 ldrb.w r4, [r5], #1 800e6b2: e7e9 b.n 800e688 <_strtoul_l.isra.0+0x68> 800e6b4: f1a4 0c41 sub.w ip, r4, #65 @ 0x41 800e6b8: f1bc 0f19 cmp.w ip, #25 800e6bc: d801 bhi.n 800e6c2 <_strtoul_l.isra.0+0xa2> 800e6be: 3c37 subs r4, #55 @ 0x37 800e6c0: e7e8 b.n 800e694 <_strtoul_l.isra.0+0x74> 800e6c2: f1a4 0c61 sub.w ip, r4, #97 @ 0x61 800e6c6: f1bc 0f19 cmp.w ip, #25 800e6ca: d804 bhi.n 800e6d6 <_strtoul_l.isra.0+0xb6> 800e6cc: 3c57 subs r4, #87 @ 0x57 800e6ce: e7e1 b.n 800e694 <_strtoul_l.isra.0+0x74> 800e6d0: f04f 36ff mov.w r6, #4294967295 @ 0xffffffff 800e6d4: e7eb b.n 800e6ae <_strtoul_l.isra.0+0x8e> 800e6d6: 1c73 adds r3, r6, #1 800e6d8: d106 bne.n 800e6e8 <_strtoul_l.isra.0+0xc8> 800e6da: 2322 movs r3, #34 @ 0x22 800e6dc: f8ce 3000 str.w r3, [lr] 800e6e0: 4630 mov r0, r6 800e6e2: b932 cbnz r2, 800e6f2 <_strtoul_l.isra.0+0xd2> 800e6e4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800e6e8: b107 cbz r7, 800e6ec <_strtoul_l.isra.0+0xcc> 800e6ea: 4240 negs r0, r0 800e6ec: 2a00 cmp r2, #0 800e6ee: d0f9 beq.n 800e6e4 <_strtoul_l.isra.0+0xc4> 800e6f0: b106 cbz r6, 800e6f4 <_strtoul_l.isra.0+0xd4> 800e6f2: 1e69 subs r1, r5, #1 800e6f4: 6011 str r1, [r2, #0] 800e6f6: e7f5 b.n 800e6e4 <_strtoul_l.isra.0+0xc4> 800e6f8: 0800fccd .word 0x0800fccd 0800e6fc : 800e6fc: 4613 mov r3, r2 800e6fe: 460a mov r2, r1 800e700: 4601 mov r1, r0 800e702: 4802 ldr r0, [pc, #8] @ (800e70c ) 800e704: 6800 ldr r0, [r0, #0] 800e706: f7ff bf8b b.w 800e620 <_strtoul_l.isra.0> 800e70a: bf00 nop 800e70c: 2000003c .word 0x2000003c 0800e710 <_vsniprintf_r>: 800e710: b530 push {r4, r5, lr} 800e712: 4614 mov r4, r2 800e714: 2c00 cmp r4, #0 800e716: b09b sub sp, #108 @ 0x6c 800e718: 4605 mov r5, r0 800e71a: 461a mov r2, r3 800e71c: da05 bge.n 800e72a <_vsniprintf_r+0x1a> 800e71e: 238b movs r3, #139 @ 0x8b 800e720: 6003 str r3, [r0, #0] 800e722: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800e726: b01b add sp, #108 @ 0x6c 800e728: bd30 pop {r4, r5, pc} 800e72a: f44f 7302 mov.w r3, #520 @ 0x208 800e72e: f8ad 300c strh.w r3, [sp, #12] 800e732: f04f 0300 mov.w r3, #0 800e736: 9319 str r3, [sp, #100] @ 0x64 800e738: bf14 ite ne 800e73a: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 800e73e: 4623 moveq r3, r4 800e740: 9302 str r3, [sp, #8] 800e742: 9305 str r3, [sp, #20] 800e744: f64f 73ff movw r3, #65535 @ 0xffff 800e748: 9100 str r1, [sp, #0] 800e74a: 9104 str r1, [sp, #16] 800e74c: f8ad 300e strh.w r3, [sp, #14] 800e750: 4669 mov r1, sp 800e752: 9b1e ldr r3, [sp, #120] @ 0x78 800e754: f000 f9c0 bl 800ead8 <_svfiprintf_r> 800e758: 1c43 adds r3, r0, #1 800e75a: bfbc itt lt 800e75c: 238b movlt r3, #139 @ 0x8b 800e75e: 602b strlt r3, [r5, #0] 800e760: 2c00 cmp r4, #0 800e762: d0e0 beq.n 800e726 <_vsniprintf_r+0x16> 800e764: 9b00 ldr r3, [sp, #0] 800e766: 2200 movs r2, #0 800e768: 701a strb r2, [r3, #0] 800e76a: e7dc b.n 800e726 <_vsniprintf_r+0x16> 0800e76c : 800e76c: b507 push {r0, r1, r2, lr} 800e76e: 9300 str r3, [sp, #0] 800e770: 4613 mov r3, r2 800e772: 460a mov r2, r1 800e774: 4601 mov r1, r0 800e776: 4803 ldr r0, [pc, #12] @ (800e784 ) 800e778: 6800 ldr r0, [r0, #0] 800e77a: f7ff ffc9 bl 800e710 <_vsniprintf_r> 800e77e: b003 add sp, #12 800e780: f85d fb04 ldr.w pc, [sp], #4 800e784: 2000003c .word 0x2000003c 0800e788 : 800e788: 4402 add r2, r0 800e78a: 4603 mov r3, r0 800e78c: 4293 cmp r3, r2 800e78e: d100 bne.n 800e792 800e790: 4770 bx lr 800e792: f803 1b01 strb.w r1, [r3], #1 800e796: e7f9 b.n 800e78c 0800e798 : 800e798: b510 push {r4, lr} 800e79a: b16a cbz r2, 800e7b8 800e79c: 3901 subs r1, #1 800e79e: 1884 adds r4, r0, r2 800e7a0: f810 2b01 ldrb.w r2, [r0], #1 800e7a4: f811 3f01 ldrb.w r3, [r1, #1]! 800e7a8: 429a cmp r2, r3 800e7aa: d103 bne.n 800e7b4 800e7ac: 42a0 cmp r0, r4 800e7ae: d001 beq.n 800e7b4 800e7b0: 2a00 cmp r2, #0 800e7b2: d1f5 bne.n 800e7a0 800e7b4: 1ad0 subs r0, r2, r3 800e7b6: bd10 pop {r4, pc} 800e7b8: 4610 mov r0, r2 800e7ba: e7fc b.n 800e7b6 0800e7bc <__errno>: 800e7bc: 4b01 ldr r3, [pc, #4] @ (800e7c4 <__errno+0x8>) 800e7be: 6818 ldr r0, [r3, #0] 800e7c0: 4770 bx lr 800e7c2: bf00 nop 800e7c4: 2000003c .word 0x2000003c 0800e7c8 <__libc_init_array>: 800e7c8: b570 push {r4, r5, r6, lr} 800e7ca: 4d0d ldr r5, [pc, #52] @ (800e800 <__libc_init_array+0x38>) 800e7cc: 4c0d ldr r4, [pc, #52] @ (800e804 <__libc_init_array+0x3c>) 800e7ce: 1b64 subs r4, r4, r5 800e7d0: 10a4 asrs r4, r4, #2 800e7d2: 2600 movs r6, #0 800e7d4: 42a6 cmp r6, r4 800e7d6: d109 bne.n 800e7ec <__libc_init_array+0x24> 800e7d8: 4d0b ldr r5, [pc, #44] @ (800e808 <__libc_init_array+0x40>) 800e7da: 4c0c ldr r4, [pc, #48] @ (800e80c <__libc_init_array+0x44>) 800e7dc: f000 fc64 bl 800f0a8 <_init> 800e7e0: 1b64 subs r4, r4, r5 800e7e2: 10a4 asrs r4, r4, #2 800e7e4: 2600 movs r6, #0 800e7e6: 42a6 cmp r6, r4 800e7e8: d105 bne.n 800e7f6 <__libc_init_array+0x2e> 800e7ea: bd70 pop {r4, r5, r6, pc} 800e7ec: f855 3b04 ldr.w r3, [r5], #4 800e7f0: 4798 blx r3 800e7f2: 3601 adds r6, #1 800e7f4: e7ee b.n 800e7d4 <__libc_init_array+0xc> 800e7f6: f855 3b04 ldr.w r3, [r5], #4 800e7fa: 4798 blx r3 800e7fc: 3601 adds r6, #1 800e7fe: e7f2 b.n 800e7e6 <__libc_init_array+0x1e> 800e800: 0800fe08 .word 0x0800fe08 800e804: 0800fe08 .word 0x0800fe08 800e808: 0800fe08 .word 0x0800fe08 800e80c: 0800fe0c .word 0x0800fe0c 0800e810 <__retarget_lock_acquire_recursive>: 800e810: 4770 bx lr 0800e812 <__retarget_lock_release_recursive>: 800e812: 4770 bx lr 0800e814 : 800e814: 440a add r2, r1 800e816: 4291 cmp r1, r2 800e818: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800e81c: d100 bne.n 800e820 800e81e: 4770 bx lr 800e820: b510 push {r4, lr} 800e822: f811 4b01 ldrb.w r4, [r1], #1 800e826: f803 4f01 strb.w r4, [r3, #1]! 800e82a: 4291 cmp r1, r2 800e82c: d1f9 bne.n 800e822 800e82e: bd10 pop {r4, pc} 0800e830 <_free_r>: 800e830: b538 push {r3, r4, r5, lr} 800e832: 4605 mov r5, r0 800e834: 2900 cmp r1, #0 800e836: d041 beq.n 800e8bc <_free_r+0x8c> 800e838: f851 3c04 ldr.w r3, [r1, #-4] 800e83c: 1f0c subs r4, r1, #4 800e83e: 2b00 cmp r3, #0 800e840: bfb8 it lt 800e842: 18e4 addlt r4, r4, r3 800e844: f000 f8e0 bl 800ea08 <__malloc_lock> 800e848: 4a1d ldr r2, [pc, #116] @ (800e8c0 <_free_r+0x90>) 800e84a: 6813 ldr r3, [r2, #0] 800e84c: b933 cbnz r3, 800e85c <_free_r+0x2c> 800e84e: 6063 str r3, [r4, #4] 800e850: 6014 str r4, [r2, #0] 800e852: 4628 mov r0, r5 800e854: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800e858: f000 b8dc b.w 800ea14 <__malloc_unlock> 800e85c: 42a3 cmp r3, r4 800e85e: d908 bls.n 800e872 <_free_r+0x42> 800e860: 6820 ldr r0, [r4, #0] 800e862: 1821 adds r1, r4, r0 800e864: 428b cmp r3, r1 800e866: bf01 itttt eq 800e868: 6819 ldreq r1, [r3, #0] 800e86a: 685b ldreq r3, [r3, #4] 800e86c: 1809 addeq r1, r1, r0 800e86e: 6021 streq r1, [r4, #0] 800e870: e7ed b.n 800e84e <_free_r+0x1e> 800e872: 461a mov r2, r3 800e874: 685b ldr r3, [r3, #4] 800e876: b10b cbz r3, 800e87c <_free_r+0x4c> 800e878: 42a3 cmp r3, r4 800e87a: d9fa bls.n 800e872 <_free_r+0x42> 800e87c: 6811 ldr r1, [r2, #0] 800e87e: 1850 adds r0, r2, r1 800e880: 42a0 cmp r0, r4 800e882: d10b bne.n 800e89c <_free_r+0x6c> 800e884: 6820 ldr r0, [r4, #0] 800e886: 4401 add r1, r0 800e888: 1850 adds r0, r2, r1 800e88a: 4283 cmp r3, r0 800e88c: 6011 str r1, [r2, #0] 800e88e: d1e0 bne.n 800e852 <_free_r+0x22> 800e890: 6818 ldr r0, [r3, #0] 800e892: 685b ldr r3, [r3, #4] 800e894: 6053 str r3, [r2, #4] 800e896: 4408 add r0, r1 800e898: 6010 str r0, [r2, #0] 800e89a: e7da b.n 800e852 <_free_r+0x22> 800e89c: d902 bls.n 800e8a4 <_free_r+0x74> 800e89e: 230c movs r3, #12 800e8a0: 602b str r3, [r5, #0] 800e8a2: e7d6 b.n 800e852 <_free_r+0x22> 800e8a4: 6820 ldr r0, [r4, #0] 800e8a6: 1821 adds r1, r4, r0 800e8a8: 428b cmp r3, r1 800e8aa: bf04 itt eq 800e8ac: 6819 ldreq r1, [r3, #0] 800e8ae: 685b ldreq r3, [r3, #4] 800e8b0: 6063 str r3, [r4, #4] 800e8b2: bf04 itt eq 800e8b4: 1809 addeq r1, r1, r0 800e8b6: 6021 streq r1, [r4, #0] 800e8b8: 6054 str r4, [r2, #4] 800e8ba: e7ca b.n 800e852 <_free_r+0x22> 800e8bc: bd38 pop {r3, r4, r5, pc} 800e8be: bf00 nop 800e8c0: 20001064 .word 0x20001064 0800e8c4 : 800e8c4: b570 push {r4, r5, r6, lr} 800e8c6: 4e0f ldr r6, [pc, #60] @ (800e904 ) 800e8c8: 460c mov r4, r1 800e8ca: 6831 ldr r1, [r6, #0] 800e8cc: 4605 mov r5, r0 800e8ce: b911 cbnz r1, 800e8d6 800e8d0: f000 fba4 bl 800f01c <_sbrk_r> 800e8d4: 6030 str r0, [r6, #0] 800e8d6: 4621 mov r1, r4 800e8d8: 4628 mov r0, r5 800e8da: f000 fb9f bl 800f01c <_sbrk_r> 800e8de: 1c43 adds r3, r0, #1 800e8e0: d103 bne.n 800e8ea 800e8e2: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 800e8e6: 4620 mov r0, r4 800e8e8: bd70 pop {r4, r5, r6, pc} 800e8ea: 1cc4 adds r4, r0, #3 800e8ec: f024 0403 bic.w r4, r4, #3 800e8f0: 42a0 cmp r0, r4 800e8f2: d0f8 beq.n 800e8e6 800e8f4: 1a21 subs r1, r4, r0 800e8f6: 4628 mov r0, r5 800e8f8: f000 fb90 bl 800f01c <_sbrk_r> 800e8fc: 3001 adds r0, #1 800e8fe: d1f2 bne.n 800e8e6 800e900: e7ef b.n 800e8e2 800e902: bf00 nop 800e904: 20001060 .word 0x20001060 0800e908 <_malloc_r>: 800e908: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800e90c: 1ccd adds r5, r1, #3 800e90e: f025 0503 bic.w r5, r5, #3 800e912: 3508 adds r5, #8 800e914: 2d0c cmp r5, #12 800e916: bf38 it cc 800e918: 250c movcc r5, #12 800e91a: 2d00 cmp r5, #0 800e91c: 4606 mov r6, r0 800e91e: db01 blt.n 800e924 <_malloc_r+0x1c> 800e920: 42a9 cmp r1, r5 800e922: d904 bls.n 800e92e <_malloc_r+0x26> 800e924: 230c movs r3, #12 800e926: 6033 str r3, [r6, #0] 800e928: 2000 movs r0, #0 800e92a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800e92e: f8df 80d4 ldr.w r8, [pc, #212] @ 800ea04 <_malloc_r+0xfc> 800e932: f000 f869 bl 800ea08 <__malloc_lock> 800e936: f8d8 3000 ldr.w r3, [r8] 800e93a: 461c mov r4, r3 800e93c: bb44 cbnz r4, 800e990 <_malloc_r+0x88> 800e93e: 4629 mov r1, r5 800e940: 4630 mov r0, r6 800e942: f7ff ffbf bl 800e8c4 800e946: 1c43 adds r3, r0, #1 800e948: 4604 mov r4, r0 800e94a: d158 bne.n 800e9fe <_malloc_r+0xf6> 800e94c: f8d8 4000 ldr.w r4, [r8] 800e950: 4627 mov r7, r4 800e952: 2f00 cmp r7, #0 800e954: d143 bne.n 800e9de <_malloc_r+0xd6> 800e956: 2c00 cmp r4, #0 800e958: d04b beq.n 800e9f2 <_malloc_r+0xea> 800e95a: 6823 ldr r3, [r4, #0] 800e95c: 4639 mov r1, r7 800e95e: 4630 mov r0, r6 800e960: eb04 0903 add.w r9, r4, r3 800e964: f000 fb5a bl 800f01c <_sbrk_r> 800e968: 4581 cmp r9, r0 800e96a: d142 bne.n 800e9f2 <_malloc_r+0xea> 800e96c: 6821 ldr r1, [r4, #0] 800e96e: 1a6d subs r5, r5, r1 800e970: 4629 mov r1, r5 800e972: 4630 mov r0, r6 800e974: f7ff ffa6 bl 800e8c4 800e978: 3001 adds r0, #1 800e97a: d03a beq.n 800e9f2 <_malloc_r+0xea> 800e97c: 6823 ldr r3, [r4, #0] 800e97e: 442b add r3, r5 800e980: 6023 str r3, [r4, #0] 800e982: f8d8 3000 ldr.w r3, [r8] 800e986: 685a ldr r2, [r3, #4] 800e988: bb62 cbnz r2, 800e9e4 <_malloc_r+0xdc> 800e98a: f8c8 7000 str.w r7, [r8] 800e98e: e00f b.n 800e9b0 <_malloc_r+0xa8> 800e990: 6822 ldr r2, [r4, #0] 800e992: 1b52 subs r2, r2, r5 800e994: d420 bmi.n 800e9d8 <_malloc_r+0xd0> 800e996: 2a0b cmp r2, #11 800e998: d917 bls.n 800e9ca <_malloc_r+0xc2> 800e99a: 1961 adds r1, r4, r5 800e99c: 42a3 cmp r3, r4 800e99e: 6025 str r5, [r4, #0] 800e9a0: bf18 it ne 800e9a2: 6059 strne r1, [r3, #4] 800e9a4: 6863 ldr r3, [r4, #4] 800e9a6: bf08 it eq 800e9a8: f8c8 1000 streq.w r1, [r8] 800e9ac: 5162 str r2, [r4, r5] 800e9ae: 604b str r3, [r1, #4] 800e9b0: 4630 mov r0, r6 800e9b2: f000 f82f bl 800ea14 <__malloc_unlock> 800e9b6: f104 000b add.w r0, r4, #11 800e9ba: 1d23 adds r3, r4, #4 800e9bc: f020 0007 bic.w r0, r0, #7 800e9c0: 1ac2 subs r2, r0, r3 800e9c2: bf1c itt ne 800e9c4: 1a1b subne r3, r3, r0 800e9c6: 50a3 strne r3, [r4, r2] 800e9c8: e7af b.n 800e92a <_malloc_r+0x22> 800e9ca: 6862 ldr r2, [r4, #4] 800e9cc: 42a3 cmp r3, r4 800e9ce: bf0c ite eq 800e9d0: f8c8 2000 streq.w r2, [r8] 800e9d4: 605a strne r2, [r3, #4] 800e9d6: e7eb b.n 800e9b0 <_malloc_r+0xa8> 800e9d8: 4623 mov r3, r4 800e9da: 6864 ldr r4, [r4, #4] 800e9dc: e7ae b.n 800e93c <_malloc_r+0x34> 800e9de: 463c mov r4, r7 800e9e0: 687f ldr r7, [r7, #4] 800e9e2: e7b6 b.n 800e952 <_malloc_r+0x4a> 800e9e4: 461a mov r2, r3 800e9e6: 685b ldr r3, [r3, #4] 800e9e8: 42a3 cmp r3, r4 800e9ea: d1fb bne.n 800e9e4 <_malloc_r+0xdc> 800e9ec: 2300 movs r3, #0 800e9ee: 6053 str r3, [r2, #4] 800e9f0: e7de b.n 800e9b0 <_malloc_r+0xa8> 800e9f2: 230c movs r3, #12 800e9f4: 6033 str r3, [r6, #0] 800e9f6: 4630 mov r0, r6 800e9f8: f000 f80c bl 800ea14 <__malloc_unlock> 800e9fc: e794 b.n 800e928 <_malloc_r+0x20> 800e9fe: 6005 str r5, [r0, #0] 800ea00: e7d6 b.n 800e9b0 <_malloc_r+0xa8> 800ea02: bf00 nop 800ea04: 20001064 .word 0x20001064 0800ea08 <__malloc_lock>: 800ea08: 4801 ldr r0, [pc, #4] @ (800ea10 <__malloc_lock+0x8>) 800ea0a: f7ff bf01 b.w 800e810 <__retarget_lock_acquire_recursive> 800ea0e: bf00 nop 800ea10: 2000105c .word 0x2000105c 0800ea14 <__malloc_unlock>: 800ea14: 4801 ldr r0, [pc, #4] @ (800ea1c <__malloc_unlock+0x8>) 800ea16: f7ff befc b.w 800e812 <__retarget_lock_release_recursive> 800ea1a: bf00 nop 800ea1c: 2000105c .word 0x2000105c 0800ea20 <__ssputs_r>: 800ea20: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800ea24: 688e ldr r6, [r1, #8] 800ea26: 461f mov r7, r3 800ea28: 42be cmp r6, r7 800ea2a: 680b ldr r3, [r1, #0] 800ea2c: 4682 mov sl, r0 800ea2e: 460c mov r4, r1 800ea30: 4690 mov r8, r2 800ea32: d82d bhi.n 800ea90 <__ssputs_r+0x70> 800ea34: f9b1 200c ldrsh.w r2, [r1, #12] 800ea38: f412 6f90 tst.w r2, #1152 @ 0x480 800ea3c: d026 beq.n 800ea8c <__ssputs_r+0x6c> 800ea3e: 6965 ldr r5, [r4, #20] 800ea40: 6909 ldr r1, [r1, #16] 800ea42: eb05 0545 add.w r5, r5, r5, lsl #1 800ea46: eba3 0901 sub.w r9, r3, r1 800ea4a: eb05 75d5 add.w r5, r5, r5, lsr #31 800ea4e: 1c7b adds r3, r7, #1 800ea50: 444b add r3, r9 800ea52: 106d asrs r5, r5, #1 800ea54: 429d cmp r5, r3 800ea56: bf38 it cc 800ea58: 461d movcc r5, r3 800ea5a: 0553 lsls r3, r2, #21 800ea5c: d527 bpl.n 800eaae <__ssputs_r+0x8e> 800ea5e: 4629 mov r1, r5 800ea60: f7ff ff52 bl 800e908 <_malloc_r> 800ea64: 4606 mov r6, r0 800ea66: b360 cbz r0, 800eac2 <__ssputs_r+0xa2> 800ea68: 6921 ldr r1, [r4, #16] 800ea6a: 464a mov r2, r9 800ea6c: f7ff fed2 bl 800e814 800ea70: 89a3 ldrh r3, [r4, #12] 800ea72: f423 6390 bic.w r3, r3, #1152 @ 0x480 800ea76: f043 0380 orr.w r3, r3, #128 @ 0x80 800ea7a: 81a3 strh r3, [r4, #12] 800ea7c: 6126 str r6, [r4, #16] 800ea7e: 6165 str r5, [r4, #20] 800ea80: 444e add r6, r9 800ea82: eba5 0509 sub.w r5, r5, r9 800ea86: 6026 str r6, [r4, #0] 800ea88: 60a5 str r5, [r4, #8] 800ea8a: 463e mov r6, r7 800ea8c: 42be cmp r6, r7 800ea8e: d900 bls.n 800ea92 <__ssputs_r+0x72> 800ea90: 463e mov r6, r7 800ea92: 6820 ldr r0, [r4, #0] 800ea94: 4632 mov r2, r6 800ea96: 4641 mov r1, r8 800ea98: f000 faa6 bl 800efe8 800ea9c: 68a3 ldr r3, [r4, #8] 800ea9e: 1b9b subs r3, r3, r6 800eaa0: 60a3 str r3, [r4, #8] 800eaa2: 6823 ldr r3, [r4, #0] 800eaa4: 4433 add r3, r6 800eaa6: 6023 str r3, [r4, #0] 800eaa8: 2000 movs r0, #0 800eaaa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800eaae: 462a mov r2, r5 800eab0: f000 fac4 bl 800f03c <_realloc_r> 800eab4: 4606 mov r6, r0 800eab6: 2800 cmp r0, #0 800eab8: d1e0 bne.n 800ea7c <__ssputs_r+0x5c> 800eaba: 6921 ldr r1, [r4, #16] 800eabc: 4650 mov r0, sl 800eabe: f7ff feb7 bl 800e830 <_free_r> 800eac2: 230c movs r3, #12 800eac4: f8ca 3000 str.w r3, [sl] 800eac8: 89a3 ldrh r3, [r4, #12] 800eaca: f043 0340 orr.w r3, r3, #64 @ 0x40 800eace: 81a3 strh r3, [r4, #12] 800ead0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800ead4: e7e9 b.n 800eaaa <__ssputs_r+0x8a> ... 0800ead8 <_svfiprintf_r>: 800ead8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800eadc: 4698 mov r8, r3 800eade: 898b ldrh r3, [r1, #12] 800eae0: 061b lsls r3, r3, #24 800eae2: b09d sub sp, #116 @ 0x74 800eae4: 4607 mov r7, r0 800eae6: 460d mov r5, r1 800eae8: 4614 mov r4, r2 800eaea: d510 bpl.n 800eb0e <_svfiprintf_r+0x36> 800eaec: 690b ldr r3, [r1, #16] 800eaee: b973 cbnz r3, 800eb0e <_svfiprintf_r+0x36> 800eaf0: 2140 movs r1, #64 @ 0x40 800eaf2: f7ff ff09 bl 800e908 <_malloc_r> 800eaf6: 6028 str r0, [r5, #0] 800eaf8: 6128 str r0, [r5, #16] 800eafa: b930 cbnz r0, 800eb0a <_svfiprintf_r+0x32> 800eafc: 230c movs r3, #12 800eafe: 603b str r3, [r7, #0] 800eb00: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800eb04: b01d add sp, #116 @ 0x74 800eb06: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800eb0a: 2340 movs r3, #64 @ 0x40 800eb0c: 616b str r3, [r5, #20] 800eb0e: 2300 movs r3, #0 800eb10: 9309 str r3, [sp, #36] @ 0x24 800eb12: 2320 movs r3, #32 800eb14: f88d 3029 strb.w r3, [sp, #41] @ 0x29 800eb18: f8cd 800c str.w r8, [sp, #12] 800eb1c: 2330 movs r3, #48 @ 0x30 800eb1e: f8df 819c ldr.w r8, [pc, #412] @ 800ecbc <_svfiprintf_r+0x1e4> 800eb22: f88d 302a strb.w r3, [sp, #42] @ 0x2a 800eb26: f04f 0901 mov.w r9, #1 800eb2a: 4623 mov r3, r4 800eb2c: 469a mov sl, r3 800eb2e: f813 2b01 ldrb.w r2, [r3], #1 800eb32: b10a cbz r2, 800eb38 <_svfiprintf_r+0x60> 800eb34: 2a25 cmp r2, #37 @ 0x25 800eb36: d1f9 bne.n 800eb2c <_svfiprintf_r+0x54> 800eb38: ebba 0b04 subs.w fp, sl, r4 800eb3c: d00b beq.n 800eb56 <_svfiprintf_r+0x7e> 800eb3e: 465b mov r3, fp 800eb40: 4622 mov r2, r4 800eb42: 4629 mov r1, r5 800eb44: 4638 mov r0, r7 800eb46: f7ff ff6b bl 800ea20 <__ssputs_r> 800eb4a: 3001 adds r0, #1 800eb4c: f000 80a7 beq.w 800ec9e <_svfiprintf_r+0x1c6> 800eb50: 9a09 ldr r2, [sp, #36] @ 0x24 800eb52: 445a add r2, fp 800eb54: 9209 str r2, [sp, #36] @ 0x24 800eb56: f89a 3000 ldrb.w r3, [sl] 800eb5a: 2b00 cmp r3, #0 800eb5c: f000 809f beq.w 800ec9e <_svfiprintf_r+0x1c6> 800eb60: 2300 movs r3, #0 800eb62: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800eb66: e9cd 2305 strd r2, r3, [sp, #20] 800eb6a: f10a 0a01 add.w sl, sl, #1 800eb6e: 9304 str r3, [sp, #16] 800eb70: 9307 str r3, [sp, #28] 800eb72: f88d 3053 strb.w r3, [sp, #83] @ 0x53 800eb76: 931a str r3, [sp, #104] @ 0x68 800eb78: 4654 mov r4, sl 800eb7a: 2205 movs r2, #5 800eb7c: f814 1b01 ldrb.w r1, [r4], #1 800eb80: 484e ldr r0, [pc, #312] @ (800ecbc <_svfiprintf_r+0x1e4>) 800eb82: f7f1 fb15 bl 80001b0 800eb86: 9a04 ldr r2, [sp, #16] 800eb88: b9d8 cbnz r0, 800ebc2 <_svfiprintf_r+0xea> 800eb8a: 06d0 lsls r0, r2, #27 800eb8c: bf44 itt mi 800eb8e: 2320 movmi r3, #32 800eb90: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800eb94: 0711 lsls r1, r2, #28 800eb96: bf44 itt mi 800eb98: 232b movmi r3, #43 @ 0x2b 800eb9a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800eb9e: f89a 3000 ldrb.w r3, [sl] 800eba2: 2b2a cmp r3, #42 @ 0x2a 800eba4: d015 beq.n 800ebd2 <_svfiprintf_r+0xfa> 800eba6: 9a07 ldr r2, [sp, #28] 800eba8: 4654 mov r4, sl 800ebaa: 2000 movs r0, #0 800ebac: f04f 0c0a mov.w ip, #10 800ebb0: 4621 mov r1, r4 800ebb2: f811 3b01 ldrb.w r3, [r1], #1 800ebb6: 3b30 subs r3, #48 @ 0x30 800ebb8: 2b09 cmp r3, #9 800ebba: d94b bls.n 800ec54 <_svfiprintf_r+0x17c> 800ebbc: b1b0 cbz r0, 800ebec <_svfiprintf_r+0x114> 800ebbe: 9207 str r2, [sp, #28] 800ebc0: e014 b.n 800ebec <_svfiprintf_r+0x114> 800ebc2: eba0 0308 sub.w r3, r0, r8 800ebc6: fa09 f303 lsl.w r3, r9, r3 800ebca: 4313 orrs r3, r2 800ebcc: 9304 str r3, [sp, #16] 800ebce: 46a2 mov sl, r4 800ebd0: e7d2 b.n 800eb78 <_svfiprintf_r+0xa0> 800ebd2: 9b03 ldr r3, [sp, #12] 800ebd4: 1d19 adds r1, r3, #4 800ebd6: 681b ldr r3, [r3, #0] 800ebd8: 9103 str r1, [sp, #12] 800ebda: 2b00 cmp r3, #0 800ebdc: bfbb ittet lt 800ebde: 425b neglt r3, r3 800ebe0: f042 0202 orrlt.w r2, r2, #2 800ebe4: 9307 strge r3, [sp, #28] 800ebe6: 9307 strlt r3, [sp, #28] 800ebe8: bfb8 it lt 800ebea: 9204 strlt r2, [sp, #16] 800ebec: 7823 ldrb r3, [r4, #0] 800ebee: 2b2e cmp r3, #46 @ 0x2e 800ebf0: d10a bne.n 800ec08 <_svfiprintf_r+0x130> 800ebf2: 7863 ldrb r3, [r4, #1] 800ebf4: 2b2a cmp r3, #42 @ 0x2a 800ebf6: d132 bne.n 800ec5e <_svfiprintf_r+0x186> 800ebf8: 9b03 ldr r3, [sp, #12] 800ebfa: 1d1a adds r2, r3, #4 800ebfc: 681b ldr r3, [r3, #0] 800ebfe: 9203 str r2, [sp, #12] 800ec00: ea43 73e3 orr.w r3, r3, r3, asr #31 800ec04: 3402 adds r4, #2 800ec06: 9305 str r3, [sp, #20] 800ec08: f8df a0b4 ldr.w sl, [pc, #180] @ 800ecc0 <_svfiprintf_r+0x1e8> 800ec0c: 7821 ldrb r1, [r4, #0] 800ec0e: 2203 movs r2, #3 800ec10: 4650 mov r0, sl 800ec12: f7f1 facd bl 80001b0 800ec16: b138 cbz r0, 800ec28 <_svfiprintf_r+0x150> 800ec18: 9b04 ldr r3, [sp, #16] 800ec1a: eba0 000a sub.w r0, r0, sl 800ec1e: 2240 movs r2, #64 @ 0x40 800ec20: 4082 lsls r2, r0 800ec22: 4313 orrs r3, r2 800ec24: 3401 adds r4, #1 800ec26: 9304 str r3, [sp, #16] 800ec28: f814 1b01 ldrb.w r1, [r4], #1 800ec2c: 4825 ldr r0, [pc, #148] @ (800ecc4 <_svfiprintf_r+0x1ec>) 800ec2e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 800ec32: 2206 movs r2, #6 800ec34: f7f1 fabc bl 80001b0 800ec38: 2800 cmp r0, #0 800ec3a: d036 beq.n 800ecaa <_svfiprintf_r+0x1d2> 800ec3c: 4b22 ldr r3, [pc, #136] @ (800ecc8 <_svfiprintf_r+0x1f0>) 800ec3e: bb1b cbnz r3, 800ec88 <_svfiprintf_r+0x1b0> 800ec40: 9b03 ldr r3, [sp, #12] 800ec42: 3307 adds r3, #7 800ec44: f023 0307 bic.w r3, r3, #7 800ec48: 3308 adds r3, #8 800ec4a: 9303 str r3, [sp, #12] 800ec4c: 9b09 ldr r3, [sp, #36] @ 0x24 800ec4e: 4433 add r3, r6 800ec50: 9309 str r3, [sp, #36] @ 0x24 800ec52: e76a b.n 800eb2a <_svfiprintf_r+0x52> 800ec54: fb0c 3202 mla r2, ip, r2, r3 800ec58: 460c mov r4, r1 800ec5a: 2001 movs r0, #1 800ec5c: e7a8 b.n 800ebb0 <_svfiprintf_r+0xd8> 800ec5e: 2300 movs r3, #0 800ec60: 3401 adds r4, #1 800ec62: 9305 str r3, [sp, #20] 800ec64: 4619 mov r1, r3 800ec66: f04f 0c0a mov.w ip, #10 800ec6a: 4620 mov r0, r4 800ec6c: f810 2b01 ldrb.w r2, [r0], #1 800ec70: 3a30 subs r2, #48 @ 0x30 800ec72: 2a09 cmp r2, #9 800ec74: d903 bls.n 800ec7e <_svfiprintf_r+0x1a6> 800ec76: 2b00 cmp r3, #0 800ec78: d0c6 beq.n 800ec08 <_svfiprintf_r+0x130> 800ec7a: 9105 str r1, [sp, #20] 800ec7c: e7c4 b.n 800ec08 <_svfiprintf_r+0x130> 800ec7e: fb0c 2101 mla r1, ip, r1, r2 800ec82: 4604 mov r4, r0 800ec84: 2301 movs r3, #1 800ec86: e7f0 b.n 800ec6a <_svfiprintf_r+0x192> 800ec88: ab03 add r3, sp, #12 800ec8a: 9300 str r3, [sp, #0] 800ec8c: 462a mov r2, r5 800ec8e: 4b0f ldr r3, [pc, #60] @ (800eccc <_svfiprintf_r+0x1f4>) 800ec90: a904 add r1, sp, #16 800ec92: 4638 mov r0, r7 800ec94: f3af 8000 nop.w 800ec98: 1c42 adds r2, r0, #1 800ec9a: 4606 mov r6, r0 800ec9c: d1d6 bne.n 800ec4c <_svfiprintf_r+0x174> 800ec9e: 89ab ldrh r3, [r5, #12] 800eca0: 065b lsls r3, r3, #25 800eca2: f53f af2d bmi.w 800eb00 <_svfiprintf_r+0x28> 800eca6: 9809 ldr r0, [sp, #36] @ 0x24 800eca8: e72c b.n 800eb04 <_svfiprintf_r+0x2c> 800ecaa: ab03 add r3, sp, #12 800ecac: 9300 str r3, [sp, #0] 800ecae: 462a mov r2, r5 800ecb0: 4b06 ldr r3, [pc, #24] @ (800eccc <_svfiprintf_r+0x1f4>) 800ecb2: a904 add r1, sp, #16 800ecb4: 4638 mov r0, r7 800ecb6: f000 f879 bl 800edac <_printf_i> 800ecba: e7ed b.n 800ec98 <_svfiprintf_r+0x1c0> 800ecbc: 0800fdcd .word 0x0800fdcd 800ecc0: 0800fdd3 .word 0x0800fdd3 800ecc4: 0800fdd7 .word 0x0800fdd7 800ecc8: 00000000 .word 0x00000000 800eccc: 0800ea21 .word 0x0800ea21 0800ecd0 <_printf_common>: 800ecd0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800ecd4: 4616 mov r6, r2 800ecd6: 4698 mov r8, r3 800ecd8: 688a ldr r2, [r1, #8] 800ecda: 690b ldr r3, [r1, #16] 800ecdc: f8dd 9020 ldr.w r9, [sp, #32] 800ece0: 4293 cmp r3, r2 800ece2: bfb8 it lt 800ece4: 4613 movlt r3, r2 800ece6: 6033 str r3, [r6, #0] 800ece8: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 800ecec: 4607 mov r7, r0 800ecee: 460c mov r4, r1 800ecf0: b10a cbz r2, 800ecf6 <_printf_common+0x26> 800ecf2: 3301 adds r3, #1 800ecf4: 6033 str r3, [r6, #0] 800ecf6: 6823 ldr r3, [r4, #0] 800ecf8: 0699 lsls r1, r3, #26 800ecfa: bf42 ittt mi 800ecfc: 6833 ldrmi r3, [r6, #0] 800ecfe: 3302 addmi r3, #2 800ed00: 6033 strmi r3, [r6, #0] 800ed02: 6825 ldr r5, [r4, #0] 800ed04: f015 0506 ands.w r5, r5, #6 800ed08: d106 bne.n 800ed18 <_printf_common+0x48> 800ed0a: f104 0a19 add.w sl, r4, #25 800ed0e: 68e3 ldr r3, [r4, #12] 800ed10: 6832 ldr r2, [r6, #0] 800ed12: 1a9b subs r3, r3, r2 800ed14: 42ab cmp r3, r5 800ed16: dc26 bgt.n 800ed66 <_printf_common+0x96> 800ed18: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 800ed1c: 6822 ldr r2, [r4, #0] 800ed1e: 3b00 subs r3, #0 800ed20: bf18 it ne 800ed22: 2301 movne r3, #1 800ed24: 0692 lsls r2, r2, #26 800ed26: d42b bmi.n 800ed80 <_printf_common+0xb0> 800ed28: f104 0243 add.w r2, r4, #67 @ 0x43 800ed2c: 4641 mov r1, r8 800ed2e: 4638 mov r0, r7 800ed30: 47c8 blx r9 800ed32: 3001 adds r0, #1 800ed34: d01e beq.n 800ed74 <_printf_common+0xa4> 800ed36: 6823 ldr r3, [r4, #0] 800ed38: 6922 ldr r2, [r4, #16] 800ed3a: f003 0306 and.w r3, r3, #6 800ed3e: 2b04 cmp r3, #4 800ed40: bf02 ittt eq 800ed42: 68e5 ldreq r5, [r4, #12] 800ed44: 6833 ldreq r3, [r6, #0] 800ed46: 1aed subeq r5, r5, r3 800ed48: 68a3 ldr r3, [r4, #8] 800ed4a: bf0c ite eq 800ed4c: ea25 75e5 biceq.w r5, r5, r5, asr #31 800ed50: 2500 movne r5, #0 800ed52: 4293 cmp r3, r2 800ed54: bfc4 itt gt 800ed56: 1a9b subgt r3, r3, r2 800ed58: 18ed addgt r5, r5, r3 800ed5a: 2600 movs r6, #0 800ed5c: 341a adds r4, #26 800ed5e: 42b5 cmp r5, r6 800ed60: d11a bne.n 800ed98 <_printf_common+0xc8> 800ed62: 2000 movs r0, #0 800ed64: e008 b.n 800ed78 <_printf_common+0xa8> 800ed66: 2301 movs r3, #1 800ed68: 4652 mov r2, sl 800ed6a: 4641 mov r1, r8 800ed6c: 4638 mov r0, r7 800ed6e: 47c8 blx r9 800ed70: 3001 adds r0, #1 800ed72: d103 bne.n 800ed7c <_printf_common+0xac> 800ed74: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800ed78: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800ed7c: 3501 adds r5, #1 800ed7e: e7c6 b.n 800ed0e <_printf_common+0x3e> 800ed80: 18e1 adds r1, r4, r3 800ed82: 1c5a adds r2, r3, #1 800ed84: 2030 movs r0, #48 @ 0x30 800ed86: f881 0043 strb.w r0, [r1, #67] @ 0x43 800ed8a: 4422 add r2, r4 800ed8c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 800ed90: f882 1043 strb.w r1, [r2, #67] @ 0x43 800ed94: 3302 adds r3, #2 800ed96: e7c7 b.n 800ed28 <_printf_common+0x58> 800ed98: 2301 movs r3, #1 800ed9a: 4622 mov r2, r4 800ed9c: 4641 mov r1, r8 800ed9e: 4638 mov r0, r7 800eda0: 47c8 blx r9 800eda2: 3001 adds r0, #1 800eda4: d0e6 beq.n 800ed74 <_printf_common+0xa4> 800eda6: 3601 adds r6, #1 800eda8: e7d9 b.n 800ed5e <_printf_common+0x8e> ... 0800edac <_printf_i>: 800edac: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 800edb0: 7e0f ldrb r7, [r1, #24] 800edb2: 9e0c ldr r6, [sp, #48] @ 0x30 800edb4: 2f78 cmp r7, #120 @ 0x78 800edb6: 4691 mov r9, r2 800edb8: 4680 mov r8, r0 800edba: 460c mov r4, r1 800edbc: 469a mov sl, r3 800edbe: f101 0243 add.w r2, r1, #67 @ 0x43 800edc2: d807 bhi.n 800edd4 <_printf_i+0x28> 800edc4: 2f62 cmp r7, #98 @ 0x62 800edc6: d80a bhi.n 800edde <_printf_i+0x32> 800edc8: 2f00 cmp r7, #0 800edca: f000 80d1 beq.w 800ef70 <_printf_i+0x1c4> 800edce: 2f58 cmp r7, #88 @ 0x58 800edd0: f000 80b8 beq.w 800ef44 <_printf_i+0x198> 800edd4: f104 0642 add.w r6, r4, #66 @ 0x42 800edd8: f884 7042 strb.w r7, [r4, #66] @ 0x42 800eddc: e03a b.n 800ee54 <_printf_i+0xa8> 800edde: f1a7 0363 sub.w r3, r7, #99 @ 0x63 800ede2: 2b15 cmp r3, #21 800ede4: d8f6 bhi.n 800edd4 <_printf_i+0x28> 800ede6: a101 add r1, pc, #4 @ (adr r1, 800edec <_printf_i+0x40>) 800ede8: f851 f023 ldr.w pc, [r1, r3, lsl #2] 800edec: 0800ee45 .word 0x0800ee45 800edf0: 0800ee59 .word 0x0800ee59 800edf4: 0800edd5 .word 0x0800edd5 800edf8: 0800edd5 .word 0x0800edd5 800edfc: 0800edd5 .word 0x0800edd5 800ee00: 0800edd5 .word 0x0800edd5 800ee04: 0800ee59 .word 0x0800ee59 800ee08: 0800edd5 .word 0x0800edd5 800ee0c: 0800edd5 .word 0x0800edd5 800ee10: 0800edd5 .word 0x0800edd5 800ee14: 0800edd5 .word 0x0800edd5 800ee18: 0800ef57 .word 0x0800ef57 800ee1c: 0800ee83 .word 0x0800ee83 800ee20: 0800ef11 .word 0x0800ef11 800ee24: 0800edd5 .word 0x0800edd5 800ee28: 0800edd5 .word 0x0800edd5 800ee2c: 0800ef79 .word 0x0800ef79 800ee30: 0800edd5 .word 0x0800edd5 800ee34: 0800ee83 .word 0x0800ee83 800ee38: 0800edd5 .word 0x0800edd5 800ee3c: 0800edd5 .word 0x0800edd5 800ee40: 0800ef19 .word 0x0800ef19 800ee44: 6833 ldr r3, [r6, #0] 800ee46: 1d1a adds r2, r3, #4 800ee48: 681b ldr r3, [r3, #0] 800ee4a: 6032 str r2, [r6, #0] 800ee4c: f104 0642 add.w r6, r4, #66 @ 0x42 800ee50: f884 3042 strb.w r3, [r4, #66] @ 0x42 800ee54: 2301 movs r3, #1 800ee56: e09c b.n 800ef92 <_printf_i+0x1e6> 800ee58: 6833 ldr r3, [r6, #0] 800ee5a: 6820 ldr r0, [r4, #0] 800ee5c: 1d19 adds r1, r3, #4 800ee5e: 6031 str r1, [r6, #0] 800ee60: 0606 lsls r6, r0, #24 800ee62: d501 bpl.n 800ee68 <_printf_i+0xbc> 800ee64: 681d ldr r5, [r3, #0] 800ee66: e003 b.n 800ee70 <_printf_i+0xc4> 800ee68: 0645 lsls r5, r0, #25 800ee6a: d5fb bpl.n 800ee64 <_printf_i+0xb8> 800ee6c: f9b3 5000 ldrsh.w r5, [r3] 800ee70: 2d00 cmp r5, #0 800ee72: da03 bge.n 800ee7c <_printf_i+0xd0> 800ee74: 232d movs r3, #45 @ 0x2d 800ee76: 426d negs r5, r5 800ee78: f884 3043 strb.w r3, [r4, #67] @ 0x43 800ee7c: 4858 ldr r0, [pc, #352] @ (800efe0 <_printf_i+0x234>) 800ee7e: 230a movs r3, #10 800ee80: e011 b.n 800eea6 <_printf_i+0xfa> 800ee82: 6821 ldr r1, [r4, #0] 800ee84: 6833 ldr r3, [r6, #0] 800ee86: 0608 lsls r0, r1, #24 800ee88: f853 5b04 ldr.w r5, [r3], #4 800ee8c: d402 bmi.n 800ee94 <_printf_i+0xe8> 800ee8e: 0649 lsls r1, r1, #25 800ee90: bf48 it mi 800ee92: b2ad uxthmi r5, r5 800ee94: 2f6f cmp r7, #111 @ 0x6f 800ee96: 4852 ldr r0, [pc, #328] @ (800efe0 <_printf_i+0x234>) 800ee98: 6033 str r3, [r6, #0] 800ee9a: bf14 ite ne 800ee9c: 230a movne r3, #10 800ee9e: 2308 moveq r3, #8 800eea0: 2100 movs r1, #0 800eea2: f884 1043 strb.w r1, [r4, #67] @ 0x43 800eea6: 6866 ldr r6, [r4, #4] 800eea8: 60a6 str r6, [r4, #8] 800eeaa: 2e00 cmp r6, #0 800eeac: db05 blt.n 800eeba <_printf_i+0x10e> 800eeae: 6821 ldr r1, [r4, #0] 800eeb0: 432e orrs r6, r5 800eeb2: f021 0104 bic.w r1, r1, #4 800eeb6: 6021 str r1, [r4, #0] 800eeb8: d04b beq.n 800ef52 <_printf_i+0x1a6> 800eeba: 4616 mov r6, r2 800eebc: fbb5 f1f3 udiv r1, r5, r3 800eec0: fb03 5711 mls r7, r3, r1, r5 800eec4: 5dc7 ldrb r7, [r0, r7] 800eec6: f806 7d01 strb.w r7, [r6, #-1]! 800eeca: 462f mov r7, r5 800eecc: 42bb cmp r3, r7 800eece: 460d mov r5, r1 800eed0: d9f4 bls.n 800eebc <_printf_i+0x110> 800eed2: 2b08 cmp r3, #8 800eed4: d10b bne.n 800eeee <_printf_i+0x142> 800eed6: 6823 ldr r3, [r4, #0] 800eed8: 07df lsls r7, r3, #31 800eeda: d508 bpl.n 800eeee <_printf_i+0x142> 800eedc: 6923 ldr r3, [r4, #16] 800eede: 6861 ldr r1, [r4, #4] 800eee0: 4299 cmp r1, r3 800eee2: bfde ittt le 800eee4: 2330 movle r3, #48 @ 0x30 800eee6: f806 3c01 strble.w r3, [r6, #-1] 800eeea: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 800eeee: 1b92 subs r2, r2, r6 800eef0: 6122 str r2, [r4, #16] 800eef2: f8cd a000 str.w sl, [sp] 800eef6: 464b mov r3, r9 800eef8: aa03 add r2, sp, #12 800eefa: 4621 mov r1, r4 800eefc: 4640 mov r0, r8 800eefe: f7ff fee7 bl 800ecd0 <_printf_common> 800ef02: 3001 adds r0, #1 800ef04: d14a bne.n 800ef9c <_printf_i+0x1f0> 800ef06: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800ef0a: b004 add sp, #16 800ef0c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800ef10: 6823 ldr r3, [r4, #0] 800ef12: f043 0320 orr.w r3, r3, #32 800ef16: 6023 str r3, [r4, #0] 800ef18: 4832 ldr r0, [pc, #200] @ (800efe4 <_printf_i+0x238>) 800ef1a: 2778 movs r7, #120 @ 0x78 800ef1c: f884 7045 strb.w r7, [r4, #69] @ 0x45 800ef20: 6823 ldr r3, [r4, #0] 800ef22: 6831 ldr r1, [r6, #0] 800ef24: 061f lsls r7, r3, #24 800ef26: f851 5b04 ldr.w r5, [r1], #4 800ef2a: d402 bmi.n 800ef32 <_printf_i+0x186> 800ef2c: 065f lsls r7, r3, #25 800ef2e: bf48 it mi 800ef30: b2ad uxthmi r5, r5 800ef32: 6031 str r1, [r6, #0] 800ef34: 07d9 lsls r1, r3, #31 800ef36: bf44 itt mi 800ef38: f043 0320 orrmi.w r3, r3, #32 800ef3c: 6023 strmi r3, [r4, #0] 800ef3e: b11d cbz r5, 800ef48 <_printf_i+0x19c> 800ef40: 2310 movs r3, #16 800ef42: e7ad b.n 800eea0 <_printf_i+0xf4> 800ef44: 4826 ldr r0, [pc, #152] @ (800efe0 <_printf_i+0x234>) 800ef46: e7e9 b.n 800ef1c <_printf_i+0x170> 800ef48: 6823 ldr r3, [r4, #0] 800ef4a: f023 0320 bic.w r3, r3, #32 800ef4e: 6023 str r3, [r4, #0] 800ef50: e7f6 b.n 800ef40 <_printf_i+0x194> 800ef52: 4616 mov r6, r2 800ef54: e7bd b.n 800eed2 <_printf_i+0x126> 800ef56: 6833 ldr r3, [r6, #0] 800ef58: 6825 ldr r5, [r4, #0] 800ef5a: 6961 ldr r1, [r4, #20] 800ef5c: 1d18 adds r0, r3, #4 800ef5e: 6030 str r0, [r6, #0] 800ef60: 062e lsls r6, r5, #24 800ef62: 681b ldr r3, [r3, #0] 800ef64: d501 bpl.n 800ef6a <_printf_i+0x1be> 800ef66: 6019 str r1, [r3, #0] 800ef68: e002 b.n 800ef70 <_printf_i+0x1c4> 800ef6a: 0668 lsls r0, r5, #25 800ef6c: d5fb bpl.n 800ef66 <_printf_i+0x1ba> 800ef6e: 8019 strh r1, [r3, #0] 800ef70: 2300 movs r3, #0 800ef72: 6123 str r3, [r4, #16] 800ef74: 4616 mov r6, r2 800ef76: e7bc b.n 800eef2 <_printf_i+0x146> 800ef78: 6833 ldr r3, [r6, #0] 800ef7a: 1d1a adds r2, r3, #4 800ef7c: 6032 str r2, [r6, #0] 800ef7e: 681e ldr r6, [r3, #0] 800ef80: 6862 ldr r2, [r4, #4] 800ef82: 2100 movs r1, #0 800ef84: 4630 mov r0, r6 800ef86: f7f1 f913 bl 80001b0 800ef8a: b108 cbz r0, 800ef90 <_printf_i+0x1e4> 800ef8c: 1b80 subs r0, r0, r6 800ef8e: 6060 str r0, [r4, #4] 800ef90: 6863 ldr r3, [r4, #4] 800ef92: 6123 str r3, [r4, #16] 800ef94: 2300 movs r3, #0 800ef96: f884 3043 strb.w r3, [r4, #67] @ 0x43 800ef9a: e7aa b.n 800eef2 <_printf_i+0x146> 800ef9c: 6923 ldr r3, [r4, #16] 800ef9e: 4632 mov r2, r6 800efa0: 4649 mov r1, r9 800efa2: 4640 mov r0, r8 800efa4: 47d0 blx sl 800efa6: 3001 adds r0, #1 800efa8: d0ad beq.n 800ef06 <_printf_i+0x15a> 800efaa: 6823 ldr r3, [r4, #0] 800efac: 079b lsls r3, r3, #30 800efae: d413 bmi.n 800efd8 <_printf_i+0x22c> 800efb0: 68e0 ldr r0, [r4, #12] 800efb2: 9b03 ldr r3, [sp, #12] 800efb4: 4298 cmp r0, r3 800efb6: bfb8 it lt 800efb8: 4618 movlt r0, r3 800efba: e7a6 b.n 800ef0a <_printf_i+0x15e> 800efbc: 2301 movs r3, #1 800efbe: 4632 mov r2, r6 800efc0: 4649 mov r1, r9 800efc2: 4640 mov r0, r8 800efc4: 47d0 blx sl 800efc6: 3001 adds r0, #1 800efc8: d09d beq.n 800ef06 <_printf_i+0x15a> 800efca: 3501 adds r5, #1 800efcc: 68e3 ldr r3, [r4, #12] 800efce: 9903 ldr r1, [sp, #12] 800efd0: 1a5b subs r3, r3, r1 800efd2: 42ab cmp r3, r5 800efd4: dcf2 bgt.n 800efbc <_printf_i+0x210> 800efd6: e7eb b.n 800efb0 <_printf_i+0x204> 800efd8: 2500 movs r5, #0 800efda: f104 0619 add.w r6, r4, #25 800efde: e7f5 b.n 800efcc <_printf_i+0x220> 800efe0: 0800fdde .word 0x0800fdde 800efe4: 0800fdef .word 0x0800fdef 0800efe8 : 800efe8: 4288 cmp r0, r1 800efea: b510 push {r4, lr} 800efec: eb01 0402 add.w r4, r1, r2 800eff0: d902 bls.n 800eff8 800eff2: 4284 cmp r4, r0 800eff4: 4623 mov r3, r4 800eff6: d807 bhi.n 800f008 800eff8: 1e43 subs r3, r0, #1 800effa: 42a1 cmp r1, r4 800effc: d008 beq.n 800f010 800effe: f811 2b01 ldrb.w r2, [r1], #1 800f002: f803 2f01 strb.w r2, [r3, #1]! 800f006: e7f8 b.n 800effa 800f008: 4402 add r2, r0 800f00a: 4601 mov r1, r0 800f00c: 428a cmp r2, r1 800f00e: d100 bne.n 800f012 800f010: bd10 pop {r4, pc} 800f012: f813 4d01 ldrb.w r4, [r3, #-1]! 800f016: f802 4d01 strb.w r4, [r2, #-1]! 800f01a: e7f7 b.n 800f00c 0800f01c <_sbrk_r>: 800f01c: b538 push {r3, r4, r5, lr} 800f01e: 4d06 ldr r5, [pc, #24] @ (800f038 <_sbrk_r+0x1c>) 800f020: 2300 movs r3, #0 800f022: 4604 mov r4, r0 800f024: 4608 mov r0, r1 800f026: 602b str r3, [r5, #0] 800f028: f7f1 fe9c bl 8000d64 <_sbrk> 800f02c: 1c43 adds r3, r0, #1 800f02e: d102 bne.n 800f036 <_sbrk_r+0x1a> 800f030: 682b ldr r3, [r5, #0] 800f032: b103 cbz r3, 800f036 <_sbrk_r+0x1a> 800f034: 6023 str r3, [r4, #0] 800f036: bd38 pop {r3, r4, r5, pc} 800f038: 20001058 .word 0x20001058 0800f03c <_realloc_r>: 800f03c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800f040: 4607 mov r7, r0 800f042: 4614 mov r4, r2 800f044: 460d mov r5, r1 800f046: b921 cbnz r1, 800f052 <_realloc_r+0x16> 800f048: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800f04c: 4611 mov r1, r2 800f04e: f7ff bc5b b.w 800e908 <_malloc_r> 800f052: b92a cbnz r2, 800f060 <_realloc_r+0x24> 800f054: f7ff fbec bl 800e830 <_free_r> 800f058: 4625 mov r5, r4 800f05a: 4628 mov r0, r5 800f05c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800f060: f000 f81a bl 800f098 <_malloc_usable_size_r> 800f064: 4284 cmp r4, r0 800f066: 4606 mov r6, r0 800f068: d802 bhi.n 800f070 <_realloc_r+0x34> 800f06a: ebb4 0f50 cmp.w r4, r0, lsr #1 800f06e: d8f4 bhi.n 800f05a <_realloc_r+0x1e> 800f070: 4621 mov r1, r4 800f072: 4638 mov r0, r7 800f074: f7ff fc48 bl 800e908 <_malloc_r> 800f078: 4680 mov r8, r0 800f07a: b908 cbnz r0, 800f080 <_realloc_r+0x44> 800f07c: 4645 mov r5, r8 800f07e: e7ec b.n 800f05a <_realloc_r+0x1e> 800f080: 42b4 cmp r4, r6 800f082: 4622 mov r2, r4 800f084: 4629 mov r1, r5 800f086: bf28 it cs 800f088: 4632 movcs r2, r6 800f08a: f7ff fbc3 bl 800e814 800f08e: 4629 mov r1, r5 800f090: 4638 mov r0, r7 800f092: f7ff fbcd bl 800e830 <_free_r> 800f096: e7f1 b.n 800f07c <_realloc_r+0x40> 0800f098 <_malloc_usable_size_r>: 800f098: f851 3c04 ldr.w r3, [r1, #-4] 800f09c: 1f18 subs r0, r3, #4 800f09e: 2b00 cmp r3, #0 800f0a0: bfbc itt lt 800f0a2: 580b ldrlt r3, [r1, r0] 800f0a4: 18c0 addlt r0, r0, r3 800f0a6: 4770 bx lr 0800f0a8 <_init>: 800f0a8: b5f8 push {r3, r4, r5, r6, r7, lr} 800f0aa: bf00 nop 800f0ac: bcf8 pop {r3, r4, r5, r6, r7} 800f0ae: bc08 pop {r3} 800f0b0: 469e mov lr, r3 800f0b2: 4770 bx lr 0800f0b4 <_fini>: 800f0b4: b5f8 push {r3, r4, r5, r6, r7, lr} 800f0b6: bf00 nop 800f0b8: bcf8 pop {r3, r4, r5, r6, r7} 800f0ba: bc08 pop {r3} 800f0bc: 469e mov lr, r3 800f0be: 4770 bx lr